compiler/utils/x86/assembler_x86.cc

/*
 * Copyright (C) 2011 The Android Open Source Project
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include "assembler_x86.h"

#include "base/casts.h"
#include "base/memory_region.h"
#include "entrypoints/quick/quick_entrypoints.h"
#include "thread.h"

namespace art {
namespace x86 {

std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) {
  return os << "XMM" << static_cast<int>(reg);
}

std::ostream& operator<<(std::ostream& os, const X87Register& reg) {
  return os << "ST" << static_cast<int>(reg);
}

std::ostream& operator<<(std::ostream& os, const Address& addr) {
  switch (addr.mod()) {
    case 0:
      if (addr.rm() != ESP || addr.index() == ESP) {
        return os << "(%" << addr.rm() << ")";
      } else if (addr.base() == EBP) {
        return os << static_cast<int>(addr.disp32()) << "(,%" << addr.index()
                  << "," << (1 << addr.scale()) << ")";
      }
      return os << "(%" << addr.base() << ",%" << addr.index() << "," << (1 << addr.scale()) << ")";
    case 1:
      if (addr.rm() != ESP || addr.index() == ESP) {
        return os << static_cast<int>(addr.disp8()) << "(%" << addr.rm() << ")";
      }
      return os << static_cast<int>(addr.disp8()) << "(%" << addr.base() << ",%"
                << addr.index() << "," << (1 << addr.scale()) << ")";
    case 2:
      if (addr.rm() != ESP || addr.index() == ESP) {
        return os << static_cast<int>(addr.disp32()) << "(%" << addr.rm() << ")";
      }
      return os << static_cast<int>(addr.disp32()) << "(%" << addr.base() << ",%"
                << addr.index() << "," << (1 << addr.scale()) << ")";
    default:
      return os << "<address?>";
  }
}

bool X86Assembler::CpuHasAVXorAVX2FeatureFlag() {
  if (has_AVX_ || has_AVX2_) {
    return true;
  }
  return false;
}

void X86Assembler::call(Register reg) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xFF);
  EmitRegisterOperand(2, reg);
}


void X86Assembler::call(const Address& address) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xFF);
  EmitOperand(2, address);
}


void X86Assembler::call(Label* label) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xE8);
  static const int kSize = 5;
  // Offset by one because we already have emitted the opcode.
  EmitLabel(label, kSize - 1);
}


void X86Assembler::call(const ExternalLabel& label) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  intptr_t call_start = buffer_.GetPosition();
  EmitUint8(0xE8);
  EmitInt32(label.address());
  static const intptr_t kCallExternalLabelSize = 5;
  DCHECK_EQ((buffer_.GetPosition() - call_start), kCallExternalLabelSize);
}


void X86Assembler::pushl(Register reg) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x50 + reg);
}


void X86Assembler::pushl(const Address& address) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xFF);
  EmitOperand(6, address);
}


void X86Assembler::pushl(const Immediate& imm) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  if (imm.is_int8()) {
    EmitUint8(0x6A);
    EmitUint8(imm.value() & 0xFF);
  } else {
    EmitUint8(0x68);
    EmitImmediate(imm);
  }
}


void X86Assembler::popl(Register reg) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x58 + reg);
}


void X86Assembler::popl(const Address& address) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x8F);
  EmitOperand(0, address);
}


void X86Assembler::movl(Register dst, const Immediate& imm) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xB8 + dst);
  EmitImmediate(imm);
}


void X86Assembler::movl(Register dst, Register src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x89);
  EmitRegisterOperand(src, dst);
}


void X86Assembler::movl(Register dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x8B);
  EmitOperand(dst, src);
}


void X86Assembler::movl(const Address& dst, Register src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x89);
  EmitOperand(src, dst);
}


void X86Assembler::movl(const Address& dst, const Immediate& imm) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xC7);
  EmitOperand(0, dst);
  EmitImmediate(imm);
}

void X86Assembler::movl(const Address& dst, Label* lbl) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xC7);
  EmitOperand(0, dst);
  EmitLabel(lbl, dst.length_ + 5);
}

void X86Assembler::movntl(const Address& dst, Register src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0xC3);
  EmitOperand(src, dst);
}

void X86Assembler::blsi(Register dst, Register src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ false);
  uint8_t byte_one  = EmitVexPrefixByteOne(false, false, false, SET_VEX_M_0F_38);
  uint8_t byte_two  = EmitVexPrefixByteTwo(false,
                                           X86ManagedRegister::FromCpuRegister(dst),
                                            SET_VEX_L_128, SET_VEX_PP_NONE);
  EmitUint8(byte_zero);
  EmitUint8(byte_one);
  EmitUint8(byte_two);
  EmitUint8(0xF3);
  EmitRegisterOperand(3, src);
}

void X86Assembler::blsmsk(Register dst, Register src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ false);
  uint8_t byte_one = EmitVexPrefixByteOne(false, false, false, SET_VEX_M_0F_38);
  uint8_t byte_two = EmitVexPrefixByteTwo(false,
                                         X86ManagedRegister::FromCpuRegister(dst),
                                         SET_VEX_L_128, SET_VEX_PP_NONE);
  EmitUint8(byte_zero);
  EmitUint8(byte_one);
  EmitUint8(byte_two);
  EmitUint8(0xF3);
  EmitRegisterOperand(2, src);
}

void X86Assembler::blsr(Register dst, Register src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ false);
  uint8_t byte_one = EmitVexPrefixByteOne(false, false, false,  SET_VEX_M_0F_38);
  uint8_t byte_two = EmitVexPrefixByteTwo(false,
                                          X86ManagedRegister::FromCpuRegister(dst),
                                          SET_VEX_L_128, SET_VEX_PP_NONE);
  EmitUint8(byte_zero);
  EmitUint8(byte_one);
  EmitUint8(byte_two);
  EmitUint8(0xF3);
  EmitRegisterOperand(1, src);
}

void X86Assembler::bswapl(Register dst) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0xC8 + dst);
}

void X86Assembler::bsfl(Register dst, Register src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0xBC);
  EmitRegisterOperand(dst, src);
}

void X86Assembler::bsfl(Register dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0xBC);
  EmitOperand(dst, src);
}

void X86Assembler::bsrl(Register dst, Register src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0xBD);
  EmitRegisterOperand(dst, src);
}

void X86Assembler::bsrl(Register dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0xBD);
  EmitOperand(dst, src);
}

void X86Assembler::popcntl(Register dst, Register src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0xB8);
  EmitRegisterOperand(dst, src);
}

void X86Assembler::popcntl(Register dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0xB8);
  EmitOperand(dst, src);
}

void X86Assembler::movzxb(Register dst, ByteRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0xB6);
  EmitRegisterOperand(dst, src);
}


void X86Assembler::movzxb(Register dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0xB6);
  EmitOperand(dst, src);
}


void X86Assembler::movsxb(Register dst, ByteRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0xBE);
  EmitRegisterOperand(dst, src);
}


void X86Assembler::movsxb(Register dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0xBE);
  EmitOperand(dst, src);
}


void X86Assembler::movb(Register /*dst*/, const Address& /*src*/) {
  LOG(FATAL) << "Use movzxb or movsxb instead.";
}


void X86Assembler::movb(const Address& dst, ByteRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x88);
  EmitOperand(src, dst);
}


void X86Assembler::movb(const Address& dst, const Immediate& imm) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xC6);
  EmitOperand(EAX, dst);
  CHECK(imm.is_int8());
  EmitUint8(imm.value() & 0xFF);
}


void X86Assembler::movzxw(Register dst, Register src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0xB7);
  EmitRegisterOperand(dst, src);
}


void X86Assembler::movzxw(Register dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0xB7);
  EmitOperand(dst, src);
}


void X86Assembler::movsxw(Register dst, Register src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0xBF);
  EmitRegisterOperand(dst, src);
}


void X86Assembler::movsxw(Register dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0xBF);
  EmitOperand(dst, src);
}


void X86Assembler::movw(Register /*dst*/, const Address& /*src*/) {
  LOG(FATAL) << "Use movzxw or movsxw instead.";
}


void X86Assembler::movw(const Address& dst, Register src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitOperandSizeOverride();
  EmitUint8(0x89);
  EmitOperand(src, dst);
}


void X86Assembler::movw(const Address& dst, const Immediate& imm) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitOperandSizeOverride();
  EmitUint8(0xC7);
  EmitOperand(0, dst);
  CHECK(imm.is_uint16() || imm.is_int16());
  EmitUint8(imm.value() & 0xFF);
  EmitUint8(imm.value() >> 8);
}


void X86Assembler::leal(Register dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x8D);
  EmitOperand(dst, src);
}


void X86Assembler::cmovl(Condition condition, Register dst, Register src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x40 + condition);
  EmitRegisterOperand(dst, src);
}


void X86Assembler::cmovl(Condition condition, Register dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x40 + condition);
  EmitOperand(dst, src);
}


void X86Assembler::setb(Condition condition, Register dst) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x90 + condition);
  EmitOperand(0, Operand(dst));
}


void X86Assembler::movaps(XmmRegister dst, XmmRegister src) {
  if (CpuHasAVXorAVX2FeatureFlag()) {
    vmovaps(dst, src);
    return;
  }
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x28);
  EmitXmmRegisterOperand(dst, src);
}

/**VEX.128.0F.WIG 28 /r VMOVAPS xmm1, xmm2*/
void X86Assembler::vmovaps(XmmRegister dst, XmmRegister src) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  /**Instruction VEX Prefix*/
  uint8_t byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
  /**a REX prefix is necessary only if an instruction references one of the
  extended registers or uses a 64-bit operand.*/
  uint8_t byte_one = EmitVexPrefixByteOne(/*R=*/ false,
                                          vvvv_reg,
                                          SET_VEX_L_128,
                                          SET_VEX_PP_NONE);
  EmitUint8(byte_zero);
  EmitUint8(byte_one);
  /**Instruction Opcode*/
  EmitUint8(0x28);
  /**Instruction Operands*/
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::movaps(XmmRegister dst, const Address& src) {
  if (CpuHasAVXorAVX2FeatureFlag()) {
    vmovaps(dst, src);
    return;
  }
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x28);
  EmitOperand(dst, src);
}

/**VEX.128.0F.WIG 28 /r VMOVAPS xmm1, m128*/
void X86Assembler::vmovaps(XmmRegister dst, const Address& src) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  /**Instruction VEX Prefix*/
  uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
  /**a REX prefix is necessary only if an instruction references one of the
  extended registers or uses a 64-bit operand.*/
  uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                         vvvv_reg,
                                         SET_VEX_L_128,
                                         SET_VEX_PP_NONE);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  /**Instruction Opcode*/
  EmitUint8(0x28);
  /**Instruction Operands*/
  EmitOperand(dst, src);
}

void X86Assembler::movups(XmmRegister dst, const Address& src) {
  if (CpuHasAVXorAVX2FeatureFlag()) {
    vmovups(dst, src);
    return;
  }
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x10);
  EmitOperand(dst, src);
}

/**VEX.128.0F.WIG 10 /r VMOVUPS xmm1, m128*/
void X86Assembler::vmovups(XmmRegister dst, const Address& src) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  /**Instruction VEX Prefix*/
  uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
  /**a REX prefix is necessary only if an instruction references one of the
  extended registers or uses a 64-bit operand.*/
  uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                         vvvv_reg,
                                         SET_VEX_L_128,
                                         SET_VEX_PP_NONE);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  /*Instruction Opcode*/
  EmitUint8(0x10);
  /*Instruction Operands*/
  EmitOperand(dst, src);
}

void X86Assembler::movaps(const Address& dst, XmmRegister src) {
  if (CpuHasAVXorAVX2FeatureFlag()) {
    vmovaps(dst, src);
    return;
  }
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x29);
  EmitOperand(src, dst);
}

/**VEX.128.0F.WIG 29 /r VMOVAPS m128, xmm1*/
void X86Assembler::vmovaps(const Address& dst, XmmRegister src) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  /**Instruction VEX Prefix*/
  uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
  /**a REX prefix is necessary only if an instruction references one of the
  extended registers or uses a 64-bit operand.*/
  uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                         vvvv_reg,
                                         SET_VEX_L_128,
                                         SET_VEX_PP_NONE);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  /**Instruction Opcode*/
  EmitUint8(0x29);
  /**Instruction Operands*/
  EmitOperand(src, dst);
}

void X86Assembler::movups(const Address& dst, XmmRegister src) {
  if (CpuHasAVXorAVX2FeatureFlag()) {
    vmovups(dst, src);
    return;
  }
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x11);
  EmitOperand(src, dst);
}

/**VEX.128.0F.WIG 11 /r VMOVUPS m128, xmm1*/
void X86Assembler::vmovups(const Address& dst, XmmRegister src) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  /**Instruction VEX Prefix*/
  uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
  /**a REX prefix is necessary only if an instruction references one of the
  extended registers or uses a 64-bit operand.*/
  uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                         vvvv_reg,
                                         SET_VEX_L_128,
                                         SET_VEX_PP_NONE);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x11);
  // Instruction Operands
  EmitOperand(src, dst);
}


void X86Assembler::movss(XmmRegister dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x10);
  EmitOperand(dst, src);
}


void X86Assembler::movss(const Address& dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x11);
  EmitOperand(src, dst);
}


void X86Assembler::movss(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x11);
  EmitXmmRegisterOperand(src, dst);
}


void X86Assembler::movd(XmmRegister dst, Register src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x6E);
  EmitOperand(dst, Operand(src));
}


void X86Assembler::movd(Register dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x7E);
  EmitOperand(src, Operand(dst));
}


void X86Assembler::addss(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x58);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::addss(XmmRegister dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x58);
  EmitOperand(dst, src);
}


void X86Assembler::subss(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x5C);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::subss(XmmRegister dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x5C);
  EmitOperand(dst, src);
}


void X86Assembler::mulss(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x59);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::mulss(XmmRegister dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x59);
  EmitOperand(dst, src);
}


void X86Assembler::divss(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x5E);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::divss(XmmRegister dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x5E);
  EmitOperand(dst, src);
}


void X86Assembler::addps(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x58);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::vaddps(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(add_left),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_NONE);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(0x58);
  EmitXmmRegisterOperand(dst, add_right);
}

void X86Assembler::subps(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x5C);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::vsubps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t byte_zero = 0x00, byte_one = 0x00;
  byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(src1);
  byte_one = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_NONE);
  EmitUint8(byte_zero);
  EmitUint8(byte_one);
  EmitUint8(0x5C);
  EmitXmmRegisterOperand(dst, src2);
}

void X86Assembler::mulps(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x59);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::vmulps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_NONE);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(0x59);
  EmitXmmRegisterOperand(dst, src2);
}

void X86Assembler::divps(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x5E);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::vdivps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_NONE);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(0x5E);
  EmitXmmRegisterOperand(dst, src2);
}


void X86Assembler::movapd(XmmRegister dst, XmmRegister src) {
  if (CpuHasAVXorAVX2FeatureFlag()) {
    vmovapd(dst, src);
    return;
  }
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x28);
  EmitXmmRegisterOperand(dst, src);
}

/**VEX.128.66.0F.WIG 28 /r VMOVAPD xmm1, xmm2*/
void X86Assembler::vmovapd(XmmRegister dst, XmmRegister src) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  /**Instruction VEX Prefix*/
  uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
  /**a REX prefix is necessary only if an instruction references one of the
  extended registers or uses a 64-bit operand.*/
  uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                         vvvv_reg ,
                                         SET_VEX_L_128,
                                         SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x28);
  // Instruction Operands
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::movapd(XmmRegister dst, const Address& src) {
  if (CpuHasAVXorAVX2FeatureFlag()) {
    vmovapd(dst, src);
    return;
  }
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x28);
  EmitOperand(dst, src);
}

/**VEX.128.66.0F.WIG 28 /r VMOVAPD xmm1, m128*/
void X86Assembler::vmovapd(XmmRegister dst, const Address& src) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  /**Instruction VEX Prefix*/
  uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
  /**a REX prefix is necessary only if an instruction references one of the
  extended registers or uses a 64-bit operand.*/
  uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                         vvvv_reg,
                                         SET_VEX_L_128,
                                         SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x28);
  // Instruction Operands
  EmitOperand(dst, src);
}

void X86Assembler::movupd(XmmRegister dst, const Address& src) {
  if (CpuHasAVXorAVX2FeatureFlag()) {
    vmovupd(dst, src);
    return;
  }
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x10);
  EmitOperand(dst, src);
}

/**VEX.128.66.0F.WIG 10 /r VMOVUPD xmm1, m128*/
void X86Assembler::vmovupd(XmmRegister dst, const Address& src) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  /**Instruction VEX Prefix*/
  uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
  /**a REX prefix is necessary only if an instruction references one of the
  extended registers or uses a 64-bit operand.*/
  uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                         vvvv_reg,
                                         SET_VEX_L_128,
                                         SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x10);
  // Instruction Operands
  EmitOperand(dst, src);
}


void X86Assembler::movapd(const Address& dst, XmmRegister src) {
  if (CpuHasAVXorAVX2FeatureFlag()) {
    vmovapd(dst, src);
    return;
  }
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x29);
  EmitOperand(src, dst);
}

/**VEX.128.66.0F.WIG 29 /r VMOVAPD m128, xmm1 */
void X86Assembler::vmovapd(const Address& dst, XmmRegister src) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  /**Instruction VEX Prefix */
  uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
  /**a REX prefix is necessary only if an instruction references one of the
  extended registers or uses a 64-bit operand.*/
  uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                         vvvv_reg,
                                         SET_VEX_L_128,
                                         SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x29);
  // Instruction Operands
  EmitOperand(src, dst);
}

void X86Assembler::movupd(const Address& dst, XmmRegister src) {
  if (CpuHasAVXorAVX2FeatureFlag()) {
    vmovupd(dst, src);
    return;
  }
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x11);
  EmitOperand(src, dst);
}

/**VEX.128.66.0F.WIG 11 /r VMOVUPD m128, xmm1 */
void X86Assembler::vmovupd(const Address& dst, XmmRegister src) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  /**Instruction VEX Prefix */
  uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
  /**a REX prefix is necessary only if an instruction references one of the
  extended registers or uses a 64-bit operand.**/
  uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                         vvvv_reg,
                                         SET_VEX_L_128,
                                         SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x11);
  // Instruction Operands
  EmitOperand(src, dst);
}

void X86Assembler::flds(const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xD9);
  EmitOperand(0, src);
}


void X86Assembler::fsts(const Address& dst) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xD9);
  EmitOperand(2, dst);
}


void X86Assembler::fstps(const Address& dst) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xD9);
  EmitOperand(3, dst);
}


void X86Assembler::movsd(XmmRegister dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x10);
  EmitOperand(dst, src);
}


void X86Assembler::movsd(const Address& dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x11);
  EmitOperand(src, dst);
}


void X86Assembler::movsd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x11);
  EmitXmmRegisterOperand(src, dst);
}


void X86Assembler::movhpd(XmmRegister dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x16);
  EmitOperand(dst, src);
}


void X86Assembler::movhpd(const Address& dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x17);
  EmitOperand(src, dst);
}


void X86Assembler::addsd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x58);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::addsd(XmmRegister dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x58);
  EmitOperand(dst, src);
}


void X86Assembler::subsd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x5C);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::subsd(XmmRegister dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x5C);
  EmitOperand(dst, src);
}


void X86Assembler::mulsd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x59);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::mulsd(XmmRegister dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x59);
  EmitOperand(dst, src);
}


void X86Assembler::divsd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x5E);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::divsd(XmmRegister dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x5E);
  EmitOperand(dst, src);
}


void X86Assembler::addpd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x58);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::vaddpd(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(add_left),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(0x58);
  EmitXmmRegisterOperand(dst, add_right);
}


void X86Assembler::subpd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x5C);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::vsubpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form*/ true);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(0x5C);
  EmitXmmRegisterOperand(dst, src2);
}

void X86Assembler::mulpd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x59);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::vmulpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(0x59);
  EmitXmmRegisterOperand(dst, src2);
}

void X86Assembler::divpd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x5E);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::vdivpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(0x5E);
  EmitXmmRegisterOperand(dst, src2);
}

void X86Assembler::movdqa(XmmRegister dst, XmmRegister src) {
  if (CpuHasAVXorAVX2FeatureFlag()) {
    vmovdqa(dst, src);
    return;
  }
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x6F);
  EmitXmmRegisterOperand(dst, src);
}

/**VEX.128.66.0F.WIG 6F /r VMOVDQA xmm1, xmm2 */
void X86Assembler::vmovdqa(XmmRegister dst, XmmRegister src) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  /**Instruction VEX Prefix */
  uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
  uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                         vvvv_reg,
                                         SET_VEX_L_128,
                                         SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x6F);
  // Instruction Operands
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::movdqa(XmmRegister dst, const Address& src) {
  if (CpuHasAVXorAVX2FeatureFlag()) {
    vmovdqa(dst, src);
    return;
  }
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x6F);
  EmitOperand(dst, src);
}

/**VEX.128.66.0F.WIG 6F /r VMOVDQA xmm1, m128 */
void X86Assembler::vmovdqa(XmmRegister dst, const Address& src) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  /**Instruction VEX Prefix */
  uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
  uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                         vvvv_reg,
                                         SET_VEX_L_128,
                                         SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x6F);
  // Instruction Operands
  EmitOperand(dst, src);
}

void X86Assembler::movdqu(XmmRegister dst, const Address& src) {
  if (CpuHasAVXorAVX2FeatureFlag()) {
    vmovdqu(dst, src);
    return;
  }
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x6F);
  EmitOperand(dst, src);
}

/**VEX.128.F3.0F.WIG 6F /r VMOVDQU xmm1, m128 */
void X86Assembler::vmovdqu(XmmRegister dst, const Address& src) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  /**Instruction VEX Prefix */
  uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
  uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                         vvvv_reg,
                                         SET_VEX_L_128,
                                         SET_VEX_PP_F3);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x6F);
  // Instruction Operands
  EmitOperand(dst, src);
}

void X86Assembler::movdqa(const Address& dst, XmmRegister src) {
  if (CpuHasAVXorAVX2FeatureFlag()) {
    vmovdqa(dst, src);
    return;
  }
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x7F);
  EmitOperand(src, dst);
}

/**VEX.128.66.0F.WIG 7F /r VMOVDQA m128, xmm1 */
void X86Assembler::vmovdqa(const Address& dst, XmmRegister src) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  /**Instruction VEX Prefix */
  uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
  uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                         vvvv_reg,
                                         SET_VEX_L_128,
                                         SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x7F);
  // Instruction Operands
  EmitOperand(src, dst);
}


void X86Assembler::movdqu(const Address& dst, XmmRegister src) {
  if (CpuHasAVXorAVX2FeatureFlag()) {
    vmovdqu(dst, src);
    return;
  }
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x7F);
  EmitOperand(src, dst);
}

/**VEX.128.F3.0F.WIG 7F /r VMOVDQU m128, xmm1 */
void X86Assembler::vmovdqu(const Address& dst, XmmRegister src) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  // Instruction VEX Prefix
  uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
  uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                         vvvv_reg,
                                         SET_VEX_L_128,
                                         SET_VEX_PP_F3);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x7F);
  // Instruction Operands
  EmitOperand(src, dst);
}

void X86Assembler::paddb(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xFC);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::vpaddb(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteOne = 0x00, ByteZero = 0x00;
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(0xFC);
  EmitXmmRegisterOperand(dst, add_right);
}

void X86Assembler::psubb(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xF8);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::vpsubb(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(0xF8);
  EmitXmmRegisterOperand(dst, add_right);
}

void X86Assembler::paddw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xFD);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::vpaddw(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(0xFD);
  EmitXmmRegisterOperand(dst, add_right);
}

void X86Assembler::psubw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xF9);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::vpsubw(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(0xF9);
  EmitXmmRegisterOperand(dst, add_right);
}

void X86Assembler::pmullw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xD5);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::paddd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xFE);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::vpaddd(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(0xFE);
  EmitXmmRegisterOperand(dst, add_right);
}

void X86Assembler::psubd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xFA);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::vpsubd(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(0xFA);
  EmitXmmRegisterOperand(dst, add_right);
}


void X86Assembler::pmulld(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x38);
  EmitUint8(0x40);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::vpmulld(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00, ByteTwo = 0x00;
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ false);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 /*X=*/ false,
                                 /*B=*/ false,
                                 SET_VEX_M_0F_38);
  ByteTwo = EmitVexPrefixByteTwo(/*W=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(ByteTwo);
  EmitUint8(0x40);
  EmitRegisterOperand(dst, src2);
}

void X86Assembler::vpmullw(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(0xD5);
  EmitRegisterOperand(dst, src2);
}

void X86Assembler::paddq(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xD4);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::vpaddq(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(0xD4);
  EmitXmmRegisterOperand(dst, add_right);
}


void X86Assembler::psubq(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xFB);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::vpsubq(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(0xFB);
  EmitXmmRegisterOperand(dst, add_right);
}

void X86Assembler::paddusb(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xDC);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::paddsb(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xEC);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::paddusw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xDD);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::paddsw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xED);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::psubusb(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xD8);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::psubsb(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xE8);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::psubusw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xD9);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::psubsw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xE9);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::cvtsi2ss(XmmRegister dst, Register src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x2A);
  EmitOperand(dst, Operand(src));
}


void X86Assembler::cvtsi2sd(XmmRegister dst, Register src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x2A);
  EmitOperand(dst, Operand(src));
}


void X86Assembler::cvtss2si(Register dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x2D);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x5A);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::cvtsd2si(Register dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x2D);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::cvttss2si(Register dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x2C);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::cvttsd2si(Register dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x2C);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x5A);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::cvtdq2ps(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x5B);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0xE6);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::comiss(XmmRegister a, XmmRegister b) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x2F);
  EmitXmmRegisterOperand(a, b);
}


void X86Assembler::comiss(XmmRegister a, const Address& b) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x2F);
  EmitOperand(a, b);
}


void X86Assembler::comisd(XmmRegister a, XmmRegister b) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x2F);
  EmitXmmRegisterOperand(a, b);
}


void X86Assembler::comisd(XmmRegister a, const Address& b) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x2F);
  EmitOperand(a, b);
}


void X86Assembler::ucomiss(XmmRegister a, XmmRegister b) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x2E);
  EmitXmmRegisterOperand(a, b);
}


void X86Assembler::ucomiss(XmmRegister a, const Address& b) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x2E);
  EmitOperand(a, b);
}


void X86Assembler::ucomisd(XmmRegister a, XmmRegister b) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x2E);
  EmitXmmRegisterOperand(a, b);
}


void X86Assembler::ucomisd(XmmRegister a, const Address& b) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x2E);
  EmitOperand(a, b);
}


void X86Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x3A);
  EmitUint8(0x0B);
  EmitXmmRegisterOperand(dst, src);
  EmitUint8(imm.value());
}


void X86Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x3A);
  EmitUint8(0x0A);
  EmitXmmRegisterOperand(dst, src);
  EmitUint8(imm.value());
}


void X86Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x51);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF3);
  EmitUint8(0x0F);
  EmitUint8(0x51);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::xorpd(XmmRegister dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x57);
  EmitOperand(dst, src);
}


void X86Assembler::xorpd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x57);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::xorps(XmmRegister dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x57);
  EmitOperand(dst, src);
}


void X86Assembler::xorps(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x57);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::pxor(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xEF);
  EmitXmmRegisterOperand(dst, src);
}

/* VEX.128.66.0F.WIG EF /r VPXOR xmm1, xmm2, xmm3/m128 */
void X86Assembler::vpxor(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  /* Instruction VEX Prefix */
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  /* REX prefix is necessary only if an instruction references one of extended
  registers or uses a 64-bit operand. */
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0xEF);
  // Instruction Operands
  EmitXmmRegisterOperand(dst, src2);
}

/* VEX.128.0F.WIG 57 /r VXORPS xmm1,xmm2, xmm3/m128 */
void X86Assembler::vxorps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  /* Instruction VEX Prefix */
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  /* REX prefix is necessary only if an instruction references one of extended
  registers or uses a 64-bit operand. */
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_NONE);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x57);
  // Instruction Operands
  EmitXmmRegisterOperand(dst, src2);
}

/* VEX.128.66.0F.WIG 57 /r VXORPD xmm1,xmm2, xmm3/m128 */
void X86Assembler::vxorpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  /* Instruction VEX Prefix */
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  /* REX prefix is necessary only if an instruction references one of extended
  registers or uses a 64-bit operand. */
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x57);
  // Instruction Operands
  EmitXmmRegisterOperand(dst, src2);
}

void X86Assembler::andpd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x54);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::andpd(XmmRegister dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x54);
  EmitOperand(dst, src);
}


void X86Assembler::andps(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x54);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::andps(XmmRegister dst, const Address& src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x54);
  EmitOperand(dst, src);
}


void X86Assembler::pand(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xDB);
  EmitXmmRegisterOperand(dst, src);
}

/* VEX.128.66.0F.WIG DB /r VPAND xmm1, xmm2, xmm3/m128 */
void X86Assembler::vpand(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  /* Instruction VEX Prefix */
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  /* REX prefix is necessary only if an instruction references one of extended
  registers or uses a 64-bit operand. */
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0xDB);
  // Instruction Operands
  EmitXmmRegisterOperand(dst, src2);
}

/* VEX.128.0F 54 /r VANDPS xmm1,xmm2, xmm3/m128 */
void X86Assembler::vandps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  /* Instruction VEX Prefix */
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_NONE);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x54);
  // Instruction Operands
  EmitXmmRegisterOperand(dst, src2);
}

/* VEX.128.66.0F 54 /r VANDPD xmm1, xmm2, xmm3/m128 */
void X86Assembler::vandpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  /* Instruction VEX Prefix */
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  /* REX prefix is necessary only if an instruction references one of extended
  registers or uses a 64-bit operand. */
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x54);
  // Instruction Operands
  EmitXmmRegisterOperand(dst, src2);
}

void X86Assembler::andnpd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x55);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::andnps(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x55);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::pandn(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xDF);
  EmitXmmRegisterOperand(dst, src);
}

/* VEX.128.66.0F.WIG DF /r VPANDN xmm1, xmm2, xmm3/m128 */
void X86Assembler::vpandn(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  /* Instruction VEX Prefix */
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  /* REX prefix is necessary only if an instruction references one of extended
  registers or uses a 64-bit operand. */
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0xDF);
  // Instruction Operands
  EmitXmmRegisterOperand(dst, src2);
}

/* VEX.128.0F 55 /r VANDNPS xmm1, xmm2, xmm3/m128 */
void X86Assembler::vandnps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  /* Instruction VEX Prefix */
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  /* REX prefix is necessary only if an instruction references one of extended
  registers or uses a 64-bit operand. */
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_NONE);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x55);
  // Instruction Operands
  EmitXmmRegisterOperand(dst, src2);
}

/* VEX.128.66.0F 55 /r VANDNPD xmm1, xmm2, xmm3/m128 */
void X86Assembler::vandnpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  /* Instruction VEX Prefix */
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  /* REX prefix is necessary only if an instruction references one of extended
  registers or uses a 64-bit operand. */
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x55);
  // Instruction Operands
  EmitXmmRegisterOperand(dst, src2);
}

void X86Assembler::orpd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x56);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::orps(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x56);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::andn(Register dst, Register src1, Register src2) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ false);
  uint8_t byte_one = EmitVexPrefixByteOne(/*R=*/ false,
                                          /*X=*/ false,
                                          /*B=*/ false,
                                          SET_VEX_M_0F_38);
  uint8_t byte_two = EmitVexPrefixByteTwo(/*W=*/ false,
                                          X86ManagedRegister::FromCpuRegister(src1),
                                          SET_VEX_L_128,
                                          SET_VEX_PP_NONE);
  EmitUint8(byte_zero);
  EmitUint8(byte_one);
  EmitUint8(byte_two);
  // Opcode field
  EmitUint8(0xF2);
  EmitRegisterOperand(dst, src2);
}

void X86Assembler::por(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xEB);
  EmitXmmRegisterOperand(dst, src);
}

/* VEX.128.66.0F.WIG EB /r VPOR xmm1, xmm2, xmm3/m128 */
void X86Assembler::vpor(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  /* Instruction VEX Prefix */
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  /* REX prefix is necessary only if an instruction references one of extended
  registers or uses a 64-bit operand. */
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0xEB);
  // Instruction Operands
  EmitXmmRegisterOperand(dst, src2);
}

/* VEX.128.0F 56 /r VORPS xmm1,xmm2, xmm3/m128 */
void X86Assembler::vorps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  /* Instruction VEX Prefix */
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  /* REX prefix is necessary only if an instruction references one of extended
  registers or uses a 64-bit operand. */
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_NONE);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x56);
  // Instruction Operands
  EmitXmmRegisterOperand(dst, src2);
}

/* VEX.128.66.0F 56 /r VORPD xmm1,xmm2, xmm3/m128 */
void X86Assembler::vorpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  /* Instruction VEX Prefix */
  ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
  /* REX prefix is necessary only if an instruction references one of extended
  registers or uses a 64-bit operand. */
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
                                 X86ManagedRegister::FromXmmRegister(src1),
                                 SET_VEX_L_128,
                                 SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  // Instruction Opcode
  EmitUint8(0x56);
  // Instruction Operands
  EmitXmmRegisterOperand(dst, src2);
}

void X86Assembler::pavgb(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xE0);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::pavgw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xE3);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::psadbw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xF6);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::pmaddwd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xF5);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::vpmaddwd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
  DCHECK(CpuHasAVXorAVX2FeatureFlag());
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  uint8_t ByteZero = 0x00, ByteOne = 0x00;
  ByteZero = EmitVexPrefixByteZero(/* is_twobyte_form=*/ true);
  X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(src1);
  ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
  EmitUint8(ByteZero);
  EmitUint8(ByteOne);
  EmitUint8(0xF5);
  EmitXmmRegisterOperand(dst, src2);
}


void X86Assembler::phaddw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x38);
  EmitUint8(0x01);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::phaddd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x38);
  EmitUint8(0x02);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::haddps(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x7C);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::haddpd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x7C);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::phsubw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x38);
  EmitUint8(0x05);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::phsubd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x38);
  EmitUint8(0x06);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::hsubps(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0xF2);
  EmitUint8(0x0F);
  EmitUint8(0x7D);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::hsubpd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x7D);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::pminsb(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x38);
  EmitUint8(0x38);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::pmaxsb(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x38);
  EmitUint8(0x3C);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::pminsw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xEA);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::pmaxsw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xEE);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::pminsd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x38);
  EmitUint8(0x39);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::pmaxsd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x38);
  EmitUint8(0x3D);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::pminub(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xDA);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::pmaxub(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xDE);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::pminuw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x38);
  EmitUint8(0x3A);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::pmaxuw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x38);
  EmitUint8(0x3E);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::pminud(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x38);
  EmitUint8(0x3B);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::pmaxud(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x38);
  EmitUint8(0x3F);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::minps(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x5D);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::maxps(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0x5F);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::minpd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x5D);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::maxpd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x5F);
  EmitXmmRegisterOperand(dst, src);
}

void X86Assembler::pcmpeqb(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x74);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::pcmpeqw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x75);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::pcmpeqd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x76);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::pcmpeqq(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x38);
  EmitUint8(0x29);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::pcmpgtb(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x64);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::pcmpgtw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x65);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::pcmpgtd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x66);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::pcmpgtq(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x38);
  EmitUint8(0x37);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0xC6);
  EmitXmmRegisterOperand(dst, src);
  EmitUint8(imm.value());
}


void X86Assembler::shufps(XmmRegister dst, XmmRegister src, const Immediate& imm) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x0F);
  EmitUint8(0xC6);
  EmitXmmRegisterOperand(dst, src);
  EmitUint8(imm.value());
}


void X86Assembler::pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x70);
  EmitXmmRegisterOperand(dst, src);
  EmitUint8(imm.value());
}


void X86Assembler::punpcklbw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x60);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::punpcklwd(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x61);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::punpckldq(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x62);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::punpcklqdq(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x6C);
  EmitXmmRegisterOperand(dst, src);
}


void X86Assembler::punpckhbw(XmmRegister dst, XmmRegister src) {
  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
  EmitUint8(0x66);
  EmitUint8(0x0F);
  EmitUint8(0x68);
  EmitXmmRegisterOperand(dst, src);
}