tree 46f8727c0009978e1c15f94ea353a9fc92d2fe42
parent 7a59a24987beb52877b72b4e3f841e406413bb6d
author Yixin Shou <yixin.shou@intel.com> 1404236897 -0400
committer Yixin Shou <yixin.shou@intel.com> 1404297612 -0400

Load 64 bit constant into GPR by single instruction for 64bit mode

This patch load 64 bit constant into a register by a single movabsq
instruction on 64 bit bit instead of previous mov, shift, add
instruction sequences.

Change-Id: I9d013c4f6c0b5c2e43bd125f91436263c7e6028c
Signed-off-by: Yixin Shou <yixin.shou@intel.com>