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/*
* Copyright (C) 2014 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "assembler_mips64.h"
#include "base/bit_utils.h"
#include "base/casts.h"
#include "base/memory_region.h"
#include "entrypoints/quick/quick_entrypoints.h"
#include "entrypoints/quick/quick_entrypoints_enum.h"
#include "thread.h"
namespace art {
namespace mips64 {
static_assert(static_cast<size_t>(kMips64PointerSize) == kMips64DoublewordSize,
"Unexpected Mips64 pointer size.");
static_assert(kMips64PointerSize == PointerSize::k64, "Unexpected Mips64 pointer size.");
void Mips64Assembler::FinalizeCode() {
for (auto& exception_block : exception_blocks_) {
EmitExceptionPoll(&exception_block);
}
ReserveJumpTableSpace();
EmitLiterals();
PromoteBranches();
}
void Mips64Assembler::FinalizeInstructions(const MemoryRegion& region) {
EmitBranches();
EmitJumpTables();
Assembler::FinalizeInstructions(region);
PatchCFI();
}
void Mips64Assembler::PatchCFI() {
if (cfi().NumberOfDelayedAdvancePCs() == 0u) {
return;
}
using DelayedAdvancePC = DebugFrameOpCodeWriterForAssembler::DelayedAdvancePC;
const auto data = cfi().ReleaseStreamAndPrepareForDelayedAdvancePC();
const std::vector<uint8_t>& old_stream = data.first;
const std::vector<DelayedAdvancePC>& advances = data.second;
// Refill our data buffer with patched opcodes.
cfi().ReserveCFIStream(old_stream.size() + advances.size() + 16);
size_t stream_pos = 0;
for (const DelayedAdvancePC& advance : advances) {
DCHECK_GE(advance.stream_pos, stream_pos);
// Copy old data up to the point where advance was issued.
cfi().AppendRawData(old_stream, stream_pos, advance.stream_pos);
stream_pos = advance.stream_pos;
// Insert the advance command with its final offset.
size_t final_pc = GetAdjustedPosition(advance.pc);
cfi().AdvancePC(final_pc);
}
// Copy the final segment if any.
cfi().AppendRawData(old_stream, stream_pos, old_stream.size());
}
void Mips64Assembler::EmitBranches() {
CHECK(!overwriting_);
// Switch from appending instructions at the end of the buffer to overwriting
// existing instructions (branch placeholders) in the buffer.
overwriting_ = true;
for (auto& branch : branches_) {
EmitBranch(&branch);
}
overwriting_ = false;
}
void Mips64Assembler::Emit(uint32_t value) {
if (overwriting_) {
// Branches to labels are emitted into their placeholders here.
buffer_.Store<uint32_t>(overwrite_location_, value);
overwrite_location_ += sizeof(uint32_t);
} else {
// Other instructions are simply appended at the end here.
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
buffer_.Emit<uint32_t>(value);
}
}
void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd,
int shamt, int funct) {
CHECK_NE(rs, kNoGpuRegister);
CHECK_NE(rt, kNoGpuRegister);
CHECK_NE(rd, kNoGpuRegister);
uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
static_cast<uint32_t>(rs) << kRsShift |
static_cast<uint32_t>(rt) << kRtShift |
static_cast<uint32_t>(rd) << kRdShift |
shamt << kShamtShift |
funct;
Emit(encoding);
}
void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd,
int shamt, int funct) {
CHECK_NE(rs, kNoGpuRegister);
CHECK_NE(rd, kNoGpuRegister);
uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
static_cast<uint32_t>(rs) << kRsShift |
static_cast<uint32_t>(ZERO) << kRtShift |
static_cast<uint32_t>(rd) << kRdShift |
shamt << kShamtShift |
funct;
Emit(encoding);
}
void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd,
int shamt, int funct) {
CHECK_NE(rt, kNoGpuRegister);
CHECK_NE(rd, kNoGpuRegister);
uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
static_cast<uint32_t>(ZERO) << kRsShift |
static_cast<uint32_t>(rt) << kRtShift |
static_cast<uint32_t>(rd) << kRdShift |
shamt << kShamtShift |
funct;
Emit(encoding);
}
void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) {
CHECK_NE(rs, kNoGpuRegister);
CHECK_NE(rt, kNoGpuRegister);
uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
static_cast<uint32_t>(rs) << kRsShift |
static_cast<uint32_t>(rt) << kRtShift |
imm;
Emit(encoding);
}
void Mips64Assembler::EmitI21(int opcode, GpuRegister rs, uint32_t imm21) {
CHECK_NE(rs, kNoGpuRegister);
CHECK(IsUint<21>(imm21)) << imm21;
uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
static_cast<uint32_t>(rs) << kRsShift |
imm21;
Emit(encoding);
}
void Mips64Assembler::EmitI26(int opcode, uint32_t imm26) {
CHECK(IsUint<26>(imm26)) << imm26;
uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift | imm26;
Emit(encoding);
}
void Mips64Assembler::EmitFR(int opcode, int fmt, FpuRegister ft, FpuRegister fs, FpuRegister fd,
int funct) {
CHECK_NE(ft, kNoFpuRegister);
CHECK_NE(fs, kNoFpuRegister);
CHECK_NE(fd, kNoFpuRegister);
uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
fmt << kFmtShift |
static_cast<uint32_t>(ft) << kFtShift |
static_cast<uint32_t>(fs) << kFsShift |
static_cast<uint32_t>(fd) << kFdShift |
funct;
Emit(encoding);
}
void Mips64Assembler::EmitFI(int opcode, int fmt, FpuRegister ft, uint16_t imm) {
CHECK_NE(ft, kNoFpuRegister);
uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
fmt << kFmtShift |
static_cast<uint32_t>(ft) << kFtShift |
imm;
Emit(encoding);
}
void Mips64Assembler::EmitMsa3R(int operation,
int df,
VectorRegister wt,
VectorRegister ws,
VectorRegister wd,
int minor_opcode) {
CHECK_NE(wt, kNoVectorRegister);
CHECK_NE(ws, kNoVectorRegister);
CHECK_NE(wd, kNoVectorRegister);
uint32_t encoding = static_cast<uint32_t>(kMsaMajorOpcode) << kOpcodeShift |
operation << kMsaOperationShift |
df << kDfShift |
static_cast<uint32_t>(wt) << kWtShift |
static_cast<uint32_t>(ws) << kWsShift |
static_cast<uint32_t>(wd) << kWdShift |
minor_opcode;
Emit(encoding);
}
void Mips64Assembler::EmitMsaBIT(int operation,
int df_m,
VectorRegister ws,
VectorRegister wd,
int minor_opcode) {
CHECK_NE(ws, kNoVectorRegister);
CHECK_NE(wd, kNoVectorRegister);
uint32_t encoding = static_cast<uint32_t>(kMsaMajorOpcode) << kOpcodeShift |
operation << kMsaOperationShift |
df_m << kDfMShift |
static_cast<uint32_t>(ws) << kWsShift |
static_cast<uint32_t>(wd) << kWdShift |
minor_opcode;
Emit(encoding);
}
void Mips64Assembler::EmitMsaELM(int operation,
int df_n,
VectorRegister ws,
VectorRegister wd,
int minor_opcode) {
CHECK_NE(ws, kNoVectorRegister);
CHECK_NE(wd, kNoVectorRegister);
uint32_t encoding = static_cast<uint32_t>(kMsaMajorOpcode) << kOpcodeShift |
operation << kMsaELMOperationShift |
df_n << kDfNShift |
static_cast<uint32_t>(ws) << kWsShift |
static_cast<uint32_t>(wd) << kWdShift |
minor_opcode;
Emit(encoding);
}
void Mips64Assembler::EmitMsaMI10(int s10,
GpuRegister rs,
VectorRegister wd,
int minor_opcode,
int df) {
CHECK_NE(rs, kNoGpuRegister);
CHECK_NE(wd, kNoVectorRegister);
CHECK(IsUint<10>(s10)) << s10;
uint32_t encoding = static_cast<uint32_t>(kMsaMajorOpcode) << kOpcodeShift |
s10 << kS10Shift |
static_cast<uint32_t>(rs) << kWsShift |
static_cast<uint32_t>(wd) << kWdShift |
minor_opcode << kS10MinorShift |
df;
Emit(encoding);
}
void Mips64Assembler::EmitMsaI10(int operation,
int df,
int i10,
VectorRegister wd,
int minor_opcode) {
CHECK_NE(wd, kNoVectorRegister);
CHECK(IsUint<10>(i10)) << i10;
uint32_t encoding = static_cast<uint32_t>(kMsaMajorOpcode) << kOpcodeShift |
operation << kMsaOperationShift |
df << kDfShift |
i10 << kI10Shift |
static_cast<uint32_t>(wd) << kWdShift |
minor_opcode;
Emit(encoding);
}
void Mips64Assembler::EmitMsa2R(int operation,
int df,
VectorRegister ws,
VectorRegister wd,
int minor_opcode) {
CHECK_NE(ws, kNoVectorRegister);
CHECK_NE(wd, kNoVectorRegister);
uint32_t encoding = static_cast<uint32_t>(kMsaMajorOpcode) << kOpcodeShift |
operation << kMsa2ROperationShift |
df << kDf2RShift |
static_cast<uint32_t>(ws) << kWsShift |
static_cast<uint32_t>(wd) << kWdShift |
minor_opcode;
Emit(encoding);
}
void Mips64Assembler::EmitMsa2RF(int operation,
int df,
VectorRegister ws,
VectorRegister wd,
int minor_opcode) {
CHECK_NE(ws, kNoVectorRegister);
CHECK_NE(wd, kNoVectorRegister);
uint32_t encoding = static_cast<uint32_t>(kMsaMajorOpcode) << kOpcodeShift |
operation << kMsa2RFOperationShift |
df << kDf2RShift |
static_cast<uint32_t>(ws) << kWsShift |
static_cast<uint32_t>(wd) << kWdShift |
minor_opcode;
Emit(encoding);
}
void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 0, 0x21);
}
void Mips64Assembler::Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0x9, rs, rt, imm16);
}
void Mips64Assembler::Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 0, 0x2d);
}
void Mips64Assembler::Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0x19, rs, rt, imm16);
}
void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 0, 0x23);
}
void Mips64Assembler::Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 0, 0x2f);
}
void Mips64Assembler::MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 2, 0x18);
}
void Mips64Assembler::MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 3, 0x18);
}
void Mips64Assembler::DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 2, 0x1a);
}
void Mips64Assembler::ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 3, 0x1a);
}
void Mips64Assembler::DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 2, 0x1b);
}
void Mips64Assembler::ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 3, 0x1b);
}
void Mips64Assembler::Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 2, 0x1c);
}
void Mips64Assembler::Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 3, 0x1c);
}
void Mips64Assembler::Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 2, 0x1e);
}
void Mips64Assembler::Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 3, 0x1e);
}
void Mips64Assembler::Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 2, 0x1f);
}
void Mips64Assembler::Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 3, 0x1f);
}
void Mips64Assembler::And(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 0, 0x24);
}
void Mips64Assembler::Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0xc, rs, rt, imm16);
}
void Mips64Assembler::Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 0, 0x25);
}
void Mips64Assembler::Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0xd, rs, rt, imm16);
}
void Mips64Assembler::Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 0, 0x26);
}
void Mips64Assembler::Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0xe, rs, rt, imm16);
}
void Mips64Assembler::Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 0, 0x27);
}
void Mips64Assembler::Bitswap(GpuRegister rd, GpuRegister rt) {
EmitRtd(0x1f, rt, rd, 0x0, 0x20);
}
void Mips64Assembler::Dbitswap(GpuRegister rd, GpuRegister rt) {
EmitRtd(0x1f, rt, rd, 0x0, 0x24);
}
void Mips64Assembler::Seb(GpuRegister rd, GpuRegister rt) {
EmitR(0x1f, static_cast<GpuRegister>(0), rt, rd, 0x10, 0x20);
}
void Mips64Assembler::Seh(GpuRegister rd, GpuRegister rt) {
EmitR(0x1f, static_cast<GpuRegister>(0), rt, rd, 0x18, 0x20);
}
void Mips64Assembler::Dsbh(GpuRegister rd, GpuRegister rt) {
EmitRtd(0x1f, rt, rd, 0x2, 0x24);
}
void Mips64Assembler::Dshd(GpuRegister rd, GpuRegister rt) {
EmitRtd(0x1f, rt, rd, 0x5, 0x24);
}
void Mips64Assembler::Dext(GpuRegister rt, GpuRegister rs, int pos, int size) {
CHECK(IsUint<5>(pos)) << pos;
CHECK(IsUint<5>(size - 1)) << size;
EmitR(0x1f, rs, rt, static_cast<GpuRegister>(size - 1), pos, 0x3);
}
void Mips64Assembler::Ins(GpuRegister rd, GpuRegister rt, int pos, int size) {
CHECK(IsUint<5>(pos)) << pos;
CHECK(IsUint<5>(size - 1)) << size;
CHECK(IsUint<5>(pos + size - 1)) << pos << " + " << size;
EmitR(0x1f, rt, rd, static_cast<GpuRegister>(pos + size - 1), pos, 0x04);
}
void Mips64Assembler::Dinsm(GpuRegister rt, GpuRegister rs, int pos, int size) {
CHECK(IsUint<5>(pos)) << pos;
CHECK(2 <= size && size <= 64) << size;
CHECK(IsUint<5>(pos + size - 33)) << pos << " + " << size;
EmitR(0x1f, rs, rt, static_cast<GpuRegister>(pos + size - 33), pos, 0x5);
}
void Mips64Assembler::Dinsu(GpuRegister rt, GpuRegister rs, int pos, int size) {
CHECK(IsUint<5>(pos - 32)) << pos;
CHECK(IsUint<5>(size - 1)) << size;
CHECK(IsUint<5>(pos + size - 33)) << pos << " + " << size;
EmitR(0x1f, rs, rt, static_cast<GpuRegister>(pos + size - 33), pos - 32, 0x6);
}
void Mips64Assembler::Dins(GpuRegister rt, GpuRegister rs, int pos, int size) {
CHECK(IsUint<5>(pos)) << pos;
CHECK(IsUint<5>(size - 1)) << size;
CHECK(IsUint<5>(pos + size - 1)) << pos << " + " << size;
EmitR(0x1f, rs, rt, static_cast<GpuRegister>(pos + size - 1), pos, 0x7);
}
void Mips64Assembler::DblIns(GpuRegister rt, GpuRegister rs, int pos, int size) {
if (pos >= 32) {
Dinsu(rt, rs, pos, size);
} else if ((static_cast<int64_t>(pos) + size - 1) >= 32) {
Dinsm(rt, rs, pos, size);
} else {
Dins(rt, rs, pos, size);
}
}
void Mips64Assembler::Lsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne) {
CHECK(1 <= saPlusOne && saPlusOne <= 4) << saPlusOne;
int sa = saPlusOne - 1;
EmitR(0x0, rs, rt, rd, sa, 0x05);
}
void Mips64Assembler::Dlsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne) {
CHECK(1 <= saPlusOne && saPlusOne <= 4) << saPlusOne;
int sa = saPlusOne - 1;
EmitR(0x0, rs, rt, rd, sa, 0x15);
}
void Mips64Assembler::Wsbh(GpuRegister rd, GpuRegister rt) {
EmitRtd(0x1f, rt, rd, 2, 0x20);
}
void Mips64Assembler::Sc(GpuRegister rt, GpuRegister base, int16_t imm9) {
CHECK(IsInt<9>(imm9));
EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x26);
}
void Mips64Assembler::Scd(GpuRegister rt, GpuRegister base, int16_t imm9) {
CHECK(IsInt<9>(imm9));
EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x27);
}
void Mips64Assembler::Ll(GpuRegister rt, GpuRegister base, int16_t imm9) {
CHECK(IsInt<9>(imm9));
EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x36);
}
void Mips64Assembler::Lld(GpuRegister rt, GpuRegister base, int16_t imm9) {
CHECK(IsInt<9>(imm9));
EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x37);
}
void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) {
EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x00);
}
void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) {
EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x02);
}
void Mips64Assembler::Rotr(GpuRegister rd, GpuRegister rt, int shamt) {
EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x02);
}
void Mips64Assembler::Sra(GpuRegister rd, GpuRegister rt, int shamt) {
EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x03);
}
void Mips64Assembler::Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
EmitR(0, rs, rt, rd, 0, 0x04);
}
void Mips64Assembler::Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
EmitR(0, rs, rt, rd, 1, 0x06);
}
void Mips64Assembler::Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
EmitR(0, rs, rt, rd, 0, 0x06);
}
void Mips64Assembler::Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
EmitR(0, rs, rt, rd, 0, 0x07);
}
void Mips64Assembler::Dsll(GpuRegister rd, GpuRegister rt, int shamt) {
EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x38);
}
void Mips64Assembler::Dsrl(GpuRegister rd, GpuRegister rt, int shamt) {
EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3a);
}
void Mips64Assembler::Drotr(GpuRegister rd, GpuRegister rt, int shamt) {
EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x3a);
}
void Mips64Assembler::Dsra(GpuRegister rd, GpuRegister rt, int shamt) {
EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3b);
}
void Mips64Assembler::Dsll32(GpuRegister rd, GpuRegister rt, int shamt) {
EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3c);
}
void Mips64Assembler::Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) {
EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3e);
}
void Mips64Assembler::Drotr32(GpuRegister rd, GpuRegister rt, int shamt) {
EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x3e);
}
void Mips64Assembler::Dsra32(GpuRegister rd, GpuRegister rt, int shamt) {
EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3f);
}
void Mips64Assembler::Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
EmitR(0, rs, rt, rd, 0, 0x14);
}
void Mips64Assembler::Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
EmitR(0, rs, rt, rd, 0, 0x16);
}
void Mips64Assembler::Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
EmitR(0, rs, rt, rd, 1, 0x16);
}
void Mips64Assembler::Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
EmitR(0, rs, rt, rd, 0, 0x17);
}
void Mips64Assembler::Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0x20, rs, rt, imm16);
}
void Mips64Assembler::Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0x21, rs, rt, imm16);
}
void Mips64Assembler::Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0x23, rs, rt, imm16);
}
void Mips64Assembler::Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0x37, rs, rt, imm16);
}
void Mips64Assembler::Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0x24, rs, rt, imm16);
}
void Mips64Assembler::Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0x25, rs, rt, imm16);
}
void Mips64Assembler::Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0x27, rs, rt, imm16);
}
void Mips64Assembler::Lwpc(GpuRegister rs, uint32_t imm19) {
CHECK(IsUint<19>(imm19)) << imm19;
EmitI21(0x3B, rs, (0x01 << 19) | imm19);
}
void Mips64Assembler::Lwupc(GpuRegister rs, uint32_t imm19) {
CHECK(IsUint<19>(imm19)) << imm19;
EmitI21(0x3B, rs, (0x02 << 19) | imm19);
}
void Mips64Assembler::Ldpc(GpuRegister rs, uint32_t imm18) {
CHECK(IsUint<18>(imm18)) << imm18;
EmitI21(0x3B, rs, (0x06 << 18) | imm18);
}
void Mips64Assembler::Lui(GpuRegister rt, uint16_t imm16) {
EmitI(0xf, static_cast<GpuRegister>(0), rt, imm16);
}
void Mips64Assembler::Aui(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0xf, rs, rt, imm16);
}
void Mips64Assembler::Daui(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
CHECK_NE(rs, ZERO);
EmitI(0x1d, rs, rt, imm16);
}
void Mips64Assembler::Dahi(GpuRegister rs, uint16_t imm16) {
EmitI(1, rs, static_cast<GpuRegister>(6), imm16);
}
void Mips64Assembler::Dati(GpuRegister rs, uint16_t imm16) {
EmitI(1, rs, static_cast<GpuRegister>(0x1e), imm16);
}
void Mips64Assembler::Sync(uint32_t stype) {
EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0),
static_cast<GpuRegister>(0), stype & 0x1f, 0xf);
}
void Mips64Assembler::Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0x28, rs, rt, imm16);
}
void Mips64Assembler::Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0x29, rs, rt, imm16);
}
void Mips64Assembler::Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0x2b, rs, rt, imm16);
}
void Mips64Assembler::Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0x3f, rs, rt, imm16);
}
void Mips64Assembler::Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 0, 0x2a);
}
void Mips64Assembler::Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 0, 0x2b);
}
void Mips64Assembler::Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0xa, rs, rt, imm16);
}
void Mips64Assembler::Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0xb, rs, rt, imm16);
}
void Mips64Assembler::Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 0, 0x35);
}
void Mips64Assembler::Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 0, 0x37);
}
void Mips64Assembler::Clz(GpuRegister rd, GpuRegister rs) {
EmitRsd(0, rs, rd, 0x01, 0x10);
}
void Mips64Assembler::Clo(GpuRegister rd, GpuRegister rs) {
EmitRsd(0, rs, rd, 0x01, 0x11);
}
void Mips64Assembler::Dclz(GpuRegister rd, GpuRegister rs) {
EmitRsd(0, rs, rd, 0x01, 0x12);
}
void Mips64Assembler::Dclo(GpuRegister rd, GpuRegister rs) {
EmitRsd(0, rs, rd, 0x01, 0x13);
}
void Mips64Assembler::Jalr(GpuRegister rd, GpuRegister rs) {
EmitR(0, rs, static_cast<GpuRegister>(0), rd, 0, 0x09);
}
void Mips64Assembler::Jalr(GpuRegister rs) {
Jalr(RA, rs);
}
void Mips64Assembler::Jr(GpuRegister rs) {
Jalr(ZERO, rs);
}
void Mips64Assembler::Auipc(GpuRegister rs, uint16_t imm16) {
EmitI(0x3B, rs, static_cast<GpuRegister>(0x1E), imm16);
}
void Mips64Assembler::Addiupc(GpuRegister rs, uint32_t imm19) {
CHECK(IsUint<19>(imm19)) << imm19;
EmitI21(0x3B, rs, imm19);
}
void Mips64Assembler::Bc(uint32_t imm26) {
EmitI26(0x32, imm26);
}
void Mips64Assembler::Balc(uint32_t imm26) {
EmitI26(0x3A, imm26);
}
void Mips64Assembler::Jic(GpuRegister rt, uint16_t imm16) {
EmitI(0x36, static_cast<GpuRegister>(0), rt, imm16);
}
void Mips64Assembler::Jialc(GpuRegister rt, uint16_t imm16) {
EmitI(0x3E, static_cast<GpuRegister>(0), rt, imm16);
}
void Mips64Assembler::Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16) {
CHECK_NE(rs, ZERO);
CHECK_NE(rt, ZERO);
CHECK_NE(rs, rt);
EmitI(0x17, rs, rt, imm16);
}
void Mips64Assembler::Bltzc(GpuRegister rt, uint16_t imm16) {
CHECK_NE(rt, ZERO);
EmitI(0x17, rt, rt, imm16);
}
void Mips64Assembler::Bgtzc(GpuRegister rt, uint16_t imm16) {
CHECK_NE(rt, ZERO);
EmitI(0x17, static_cast<GpuRegister>(0), rt, imm16);
}
void Mips64Assembler::Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16) {
CHECK_NE(rs, ZERO);
CHECK_NE(rt, ZERO);
CHECK_NE(rs, rt);
EmitI(0x16, rs, rt, imm16);
}
void Mips64Assembler::Bgezc(GpuRegister rt, uint16_t imm16) {
CHECK_NE(rt, ZERO);
EmitI(0x16, rt, rt, imm16);
}
void Mips64Assembler::Blezc(GpuRegister rt, uint16_t imm16) {
CHECK_NE(rt, ZERO);
EmitI(0x16, static_cast<GpuRegister>(0), rt, imm16);
}
void Mips64Assembler::Bltuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) {
CHECK_NE(rs, ZERO);
CHECK_NE(rt, ZERO);
CHECK_NE(rs, rt);
EmitI(0x7, rs, rt, imm16);
}
void Mips64Assembler::Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) {
CHECK_NE(rs, ZERO);
CHECK_NE(rt, ZERO);
CHECK_NE(rs, rt);
EmitI(0x6, rs, rt, imm16);
}
void Mips64Assembler::Beqc(GpuRegister rs, GpuRegister rt, uint16_t imm16) {
CHECK_NE(rs, ZERO);
CHECK_NE(rt, ZERO);
CHECK_NE(rs, rt);
EmitI(0x8, std::min(rs, rt), std::max(rs, rt), imm16);
}
void Mips64Assembler::Bnec(GpuRegister rs, GpuRegister rt, uint16_t imm16) {
CHECK_NE(rs, ZERO);
CHECK_NE(rt, ZERO);
CHECK_NE(rs, rt);
EmitI(0x18, std::min(rs, rt), std::max(rs, rt), imm16);
}
void Mips64Assembler::Beqzc(GpuRegister rs, uint32_t imm21) {
CHECK_NE(rs, ZERO);
EmitI21(0x36, rs, imm21);
}
void Mips64Assembler::Bnezc(GpuRegister rs, uint32_t imm21) {
CHECK_NE(rs, ZERO);
EmitI21(0x3E, rs, imm21);
}
void Mips64Assembler::Bc1eqz(FpuRegister ft, uint16_t imm16) {
EmitFI(0x11, 0x9, ft, imm16);
}
void Mips64Assembler::Bc1nez(FpuRegister ft, uint16_t imm16) {
EmitFI(0x11, 0xD, ft, imm16);
}
void Mips64Assembler::Beq(GpuRegister rs, GpuRegister rt, uint16_t imm16) {
EmitI(0x4, rs, rt, imm16);
}
void Mips64Assembler::Bne(GpuRegister rs, GpuRegister rt, uint16_t imm16) {
EmitI(0x5, rs, rt, imm16);
}
void Mips64Assembler::Beqz(GpuRegister rt, uint16_t imm16) {
Beq(rt, ZERO, imm16);
}
void Mips64Assembler::Bnez(GpuRegister rt, uint16_t imm16) {
Bne(rt, ZERO, imm16);
}
void Mips64Assembler::Bltz(GpuRegister rt, uint16_t imm16) {
EmitI(0x1, rt, static_cast<GpuRegister>(0), imm16);
}
void Mips64Assembler::Bgez(GpuRegister rt, uint16_t imm16) {
EmitI(0x1, rt, static_cast<GpuRegister>(0x1), imm16);
}
void Mips64Assembler::Blez(GpuRegister rt, uint16_t imm16) {
EmitI(0x6, rt, static_cast<GpuRegister>(0), imm16);
}
void Mips64Assembler::Bgtz(GpuRegister rt, uint16_t imm16) {
EmitI(0x7, rt, static_cast<GpuRegister>(0), imm16);
}
void Mips64Assembler::EmitBcondR6(BranchCondition cond,
GpuRegister rs,
GpuRegister rt,
uint32_t imm16_21) {
switch (cond) {
case kCondLT:
Bltc(rs, rt, imm16_21);
break;
case kCondGE:
Bgec(rs, rt, imm16_21);
break;
case kCondLE:
Bgec(rt, rs, imm16_21);
break;
case kCondGT:
Bltc(rt, rs, imm16_21);
break;
case kCondLTZ:
CHECK_EQ(rt, ZERO);
Bltzc(rs, imm16_21);
break;
case kCondGEZ:
CHECK_EQ(rt, ZERO);
Bgezc(rs, imm16_21);
break;
case kCondLEZ:
CHECK_EQ(rt, ZERO);
Blezc(rs, imm16_21);
break;
case kCondGTZ:
CHECK_EQ(rt, ZERO);
Bgtzc(rs, imm16_21);
break;
case kCondEQ:
Beqc(rs, rt, imm16_21);
break;
case kCondNE:
Bnec(rs, rt, imm16_21);
break;
case kCondEQZ:
CHECK_EQ(rt, ZERO);
Beqzc(rs, imm16_21);
break;
case kCondNEZ:
CHECK_EQ(rt, ZERO);
Bnezc(rs, imm16_21);
break;
case kCondLTU:
Bltuc(rs, rt, imm16_21);
break;
case kCondGEU:
Bgeuc(rs, rt, imm16_21);
break;
case kCondF:
CHECK_EQ(rt, ZERO);
Bc1eqz(static_cast<FpuRegister>(rs), imm16_21);
break;
case kCondT:
CHECK_EQ(rt, ZERO);
Bc1nez(static_cast<FpuRegister>(rs), imm16_21);
break;
case kUncond:
LOG(FATAL) << "Unexpected branch condition " << cond;
UNREACHABLE();
}
}
void Mips64Assembler::EmitBcondR2(BranchCondition cond,
GpuRegister rs,
GpuRegister rt,
uint16_t imm16) {
switch (cond) {
case kCondLTZ:
CHECK_EQ(rt, ZERO);
Bltz(rs, imm16);
break;
case kCondGEZ:
CHECK_EQ(rt, ZERO);
Bgez(rs, imm16);
break;
case kCondLEZ:
CHECK_EQ(rt, ZERO);
Blez(rs, imm16);
break;
case kCondGTZ:
CHECK_EQ(rt, ZERO);
Bgtz(rs, imm16);
break;
case kCondEQ:
Beq(rs, rt, imm16);
break;
case kCondNE:
Bne(rs, rt, imm16);
break;
case kCondEQZ:
CHECK_EQ(rt, ZERO);
Beqz(rs, imm16);
break;
case kCondNEZ:
CHECK_EQ(rt, ZERO);
Bnez(rs, imm16);
break;
case kCondF:
case kCondT:
case kCondLT:
case kCondGE:
case kCondLE:
case kCondGT:
case kCondLTU:
case kCondGEU:
case kUncond:
LOG(FATAL) << "Unexpected branch condition " << cond;
UNREACHABLE();
}
}
void Mips64Assembler::AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x10, ft, fs, fd, 0x0);
}
void Mips64Assembler::SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x10, ft, fs, fd, 0x1);
}
void Mips64Assembler::MulS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x10, ft, fs, fd, 0x2);
}
void Mips64Assembler::DivS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x10, ft, fs, fd, 0x3);
}
void Mips64Assembler::AddD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x11, ft, fs, fd, 0x0);
}
void Mips64Assembler::SubD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x11, ft, fs, fd, 0x1);
}
void Mips64Assembler::MulD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x11, ft, fs, fd, 0x2);
}
void Mips64Assembler::DivD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x11, ft, fs, fd, 0x3);
}
void Mips64Assembler::SqrtS(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x4);
}
void Mips64Assembler::SqrtD(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x4);
}
void Mips64Assembler::AbsS(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x5);
}
void Mips64Assembler::AbsD(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x5);
}
void Mips64Assembler::MovS(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x6);
}
void Mips64Assembler::MovD(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x6);
}
void Mips64Assembler::NegS(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x7);
}
void Mips64Assembler::NegD(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x7);
}
void Mips64Assembler::RoundLS(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x8);
}
void Mips64Assembler::RoundLD(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x8);
}
void Mips64Assembler::RoundWS(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xc);
}
void Mips64Assembler::RoundWD(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xc);
}
void Mips64Assembler::TruncLS(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x9);
}
void Mips64Assembler::TruncLD(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x9);
}
void Mips64Assembler::TruncWS(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xd);
}
void Mips64Assembler::TruncWD(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xd);
}
void Mips64Assembler::CeilLS(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xa);
}
void Mips64Assembler::CeilLD(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xa);
}
void Mips64Assembler::CeilWS(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xe);
}
void Mips64Assembler::CeilWD(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xe);
}
void Mips64Assembler::FloorLS(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xb);
}
void Mips64Assembler::FloorLD(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xb);
}
void Mips64Assembler::FloorWS(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xf);
}
void Mips64Assembler::FloorWD(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xf);
}
void Mips64Assembler::SelS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x10, ft, fs, fd, 0x10);
}
void Mips64Assembler::SelD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x11, ft, fs, fd, 0x10);
}
void Mips64Assembler::SeleqzS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x10, ft, fs, fd, 0x14);
}
void Mips64Assembler::SeleqzD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x11, ft, fs, fd, 0x14);
}
void Mips64Assembler::SelnezS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x10, ft, fs, fd, 0x17);
}
void Mips64Assembler::SelnezD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x11, ft, fs, fd, 0x17);
}
void Mips64Assembler::RintS(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x1a);
}
void Mips64Assembler::RintD(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x1a);
}
void Mips64Assembler::ClassS(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x1b);
}
void Mips64Assembler::ClassD(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x1b);
}
void Mips64Assembler::MinS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x10, ft, fs, fd, 0x1c);
}
void Mips64Assembler::MinD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x11, ft, fs, fd, 0x1c);
}
void Mips64Assembler::MaxS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x10, ft, fs, fd, 0x1e);
}
void Mips64Assembler::MaxD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x11, ft, fs, fd, 0x1e);
}
void Mips64Assembler::CmpUnS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x14, ft, fs, fd, 0x01);
}
void Mips64Assembler::CmpEqS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x14, ft, fs, fd, 0x02);
}
void Mips64Assembler::CmpUeqS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x14, ft, fs, fd, 0x03);
}
void Mips64Assembler::CmpLtS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x14, ft, fs, fd, 0x04);
}
void Mips64Assembler::CmpUltS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x14, ft, fs, fd, 0x05);
}
void Mips64Assembler::CmpLeS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x14, ft, fs, fd, 0x06);
}
void Mips64Assembler::CmpUleS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x14, ft, fs, fd, 0x07);
}
void Mips64Assembler::CmpOrS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x14, ft, fs, fd, 0x11);
}
void Mips64Assembler::CmpUneS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x14, ft, fs, fd, 0x12);
}
void Mips64Assembler::CmpNeS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x14, ft, fs, fd, 0x13);
}
void Mips64Assembler::CmpUnD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x15, ft, fs, fd, 0x01);
}
void Mips64Assembler::CmpEqD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x15, ft, fs, fd, 0x02);
}
void Mips64Assembler::CmpUeqD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x15, ft, fs, fd, 0x03);
}
void Mips64Assembler::CmpLtD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x15, ft, fs, fd, 0x04);
}
void Mips64Assembler::CmpUltD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x15, ft, fs, fd, 0x05);
}
void Mips64Assembler::CmpLeD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x15, ft, fs, fd, 0x06);
}
void Mips64Assembler::CmpUleD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x15, ft, fs, fd, 0x07);
}
void Mips64Assembler::CmpOrD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x15, ft, fs, fd, 0x11);
}
void Mips64Assembler::CmpUneD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x15, ft, fs, fd, 0x12);
}
void Mips64Assembler::CmpNeD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x15, ft, fs, fd, 0x13);
}
void Mips64Assembler::Cvtsw(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x14, static_cast<FpuRegister>(0), fs, fd, 0x20);
}
void Mips64Assembler::Cvtdw(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x14, static_cast<FpuRegister>(0), fs, fd, 0x21);
}
void Mips64Assembler::Cvtsd(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x20);
}
void Mips64Assembler::Cvtds(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x21);
}
void Mips64Assembler::Cvtsl(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x15, static_cast<FpuRegister>(0), fs, fd, 0x20);
}
void Mips64Assembler::Cvtdl(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x15, static_cast<FpuRegister>(0), fs, fd, 0x21);
}
void Mips64Assembler::Mfc1(GpuRegister rt, FpuRegister fs) {
EmitFR(0x11, 0x00, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
}
void Mips64Assembler::Mfhc1(GpuRegister rt, FpuRegister fs) {
EmitFR(0x11, 0x03, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
}
void Mips64Assembler::Mtc1(GpuRegister rt, FpuRegister fs) {
EmitFR(0x11, 0x04, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
}
void Mips64Assembler::Mthc1(GpuRegister rt, FpuRegister fs) {
EmitFR(0x11, 0x07, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
}
void Mips64Assembler::Dmfc1(GpuRegister rt, FpuRegister fs) {
EmitFR(0x11, 0x01, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
}
void Mips64Assembler::Dmtc1(GpuRegister rt, FpuRegister fs) {
EmitFR(0x11, 0x05, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
}
void Mips64Assembler::Lwc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) {
EmitI(0x31, rs, static_cast<GpuRegister>(ft), imm16);
}
void Mips64Assembler::Ldc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) {
EmitI(0x35, rs, static_cast<GpuRegister>(ft), imm16);
}
void Mips64Assembler::Swc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) {
EmitI(0x39, rs, static_cast<GpuRegister>(ft), imm16);
}
void Mips64Assembler::Sdc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) {
EmitI(0x3d, rs, static_cast<GpuRegister>(ft), imm16);
}
void Mips64Assembler::Break() {
EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0),
static_cast<GpuRegister>(0), 0, 0xD);
}
void Mips64Assembler::Nop() {
EmitR(0x0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0),
static_cast<GpuRegister>(0), 0, 0x0);
}
void Mips64Assembler::Move(GpuRegister rd, GpuRegister rs) {
Or(rd, rs, ZERO);
}
void Mips64Assembler::Clear(GpuRegister rd) {
Move(rd, ZERO);
}
void Mips64Assembler::Not(GpuRegister rd, GpuRegister rs) {
Nor(rd, rs, ZERO);
}
void Mips64Assembler::AndV(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x0, wt, ws, wd, 0x1e);
}
void Mips64Assembler::OrV(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x1, wt, ws, wd, 0x1e);
}
void Mips64Assembler::NorV(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x2, wt, ws, wd, 0x1e);
}
void Mips64Assembler::XorV(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x3, wt, ws, wd, 0x1e);
}
void Mips64Assembler::AddvB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x0, wt, ws, wd, 0xe);
}
void Mips64Assembler::AddvH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x1, wt, ws, wd, 0xe);
}
void Mips64Assembler::AddvW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x2, wt, ws, wd, 0xe);
}
void Mips64Assembler::AddvD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x3, wt, ws, wd, 0xe);
}
void Mips64Assembler::SubvB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x1, 0x0, wt, ws, wd, 0xe);
}
void Mips64Assembler::SubvH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x1, 0x1, wt, ws, wd, 0xe);
}
void Mips64Assembler::SubvW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x1, 0x2, wt, ws, wd, 0xe);
}
void Mips64Assembler::SubvD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x1, 0x3, wt, ws, wd, 0xe);
}
void Mips64Assembler::Asub_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x0, wt, ws, wd, 0x11);
}
void Mips64Assembler::Asub_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x1, wt, ws, wd, 0x11);
}
void Mips64Assembler::Asub_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x2, wt, ws, wd, 0x11);
}
void Mips64Assembler::Asub_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x3, wt, ws, wd, 0x11);
}
void Mips64Assembler::Asub_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x0, wt, ws, wd, 0x11);
}
void Mips64Assembler::Asub_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x1, wt, ws, wd, 0x11);
}
void Mips64Assembler::Asub_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x2, wt, ws, wd, 0x11);
}
void Mips64Assembler::Asub_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x3, wt, ws, wd, 0x11);
}
void Mips64Assembler::MulvB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x0, wt, ws, wd, 0x12);
}
void Mips64Assembler::MulvH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x1, wt, ws, wd, 0x12);
}
void Mips64Assembler::MulvW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x2, wt, ws, wd, 0x12);
}
void Mips64Assembler::MulvD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x3, wt, ws, wd, 0x12);
}
void Mips64Assembler::Div_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x0, wt, ws, wd, 0x12);
}
void Mips64Assembler::Div_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x1, wt, ws, wd, 0x12);
}
void Mips64Assembler::Div_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x2, wt, ws, wd, 0x12);
}
void Mips64Assembler::Div_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x3, wt, ws, wd, 0x12);
}
void Mips64Assembler::Div_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x0, wt, ws, wd, 0x12);
}
void Mips64Assembler::Div_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x1, wt, ws, wd, 0x12);
}
void Mips64Assembler::Div_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x2, wt, ws, wd, 0x12);
}
void Mips64Assembler::Div_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x3, wt, ws, wd, 0x12);
}
void Mips64Assembler::Mod_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x6, 0x0, wt, ws, wd, 0x12);
}
void Mips64Assembler::Mod_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x6, 0x1, wt, ws, wd, 0x12);
}
void Mips64Assembler::Mod_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x6, 0x2, wt, ws, wd, 0x12);
}
void Mips64Assembler::Mod_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x6, 0x3, wt, ws, wd, 0x12);
}
void Mips64Assembler::Mod_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x7, 0x0, wt, ws, wd, 0x12);
}
void Mips64Assembler::Mod_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x7, 0x1, wt, ws, wd, 0x12);
}
void Mips64Assembler::Mod_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x7, 0x2, wt, ws, wd, 0x12);
}
void Mips64Assembler::Mod_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x7, 0x3, wt, ws, wd, 0x12);
}
void Mips64Assembler::Add_aB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x0, wt, ws, wd, 0x10);
}
void Mips64Assembler::Add_aH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x1, wt, ws, wd, 0x10);
}
void Mips64Assembler::Add_aW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x2, wt, ws, wd, 0x10);
}
void Mips64Assembler::Add_aD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x3, wt, ws, wd, 0x10);
}
void Mips64Assembler::Ave_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x0, wt, ws, wd, 0x10);
}
void Mips64Assembler::Ave_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x1, wt, ws, wd, 0x10);
}
void Mips64Assembler::Ave_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x2, wt, ws, wd, 0x10);
}
void Mips64Assembler::Ave_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x3, wt, ws, wd, 0x10);
}
void Mips64Assembler::Ave_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x0, wt, ws, wd, 0x10);
}
void Mips64Assembler::Ave_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x1, wt, ws, wd, 0x10);
}
void Mips64Assembler::Ave_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x2, wt, ws, wd, 0x10);
}
void Mips64Assembler::Ave_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x3, wt, ws, wd, 0x10);
}
void Mips64Assembler::Aver_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x6, 0x0, wt, ws, wd, 0x10);
}
void Mips64Assembler::Aver_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x6, 0x1, wt, ws, wd, 0x10);
}
void Mips64Assembler::Aver_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x6, 0x2, wt, ws, wd, 0x10);
}
void Mips64Assembler::Aver_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x6, 0x3, wt, ws, wd, 0x10);
}
void Mips64Assembler::Aver_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x7, 0x0, wt, ws, wd, 0x10);
}
void Mips64Assembler::Aver_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x7, 0x1, wt, ws, wd, 0x10);
}
void Mips64Assembler::Aver_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x7, 0x2, wt, ws, wd, 0x10);
}
void Mips64Assembler::Aver_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x7, 0x3, wt, ws, wd, 0x10);
}
void Mips64Assembler::Max_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x2, 0x0, wt, ws, wd, 0xe);
}
void Mips64Assembler::Max_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x2, 0x1, wt, ws, wd, 0xe);
}
void Mips64Assembler::Max_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x2, 0x2, wt, ws, wd, 0xe);
}
void Mips64Assembler::Max_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x2, 0x3, wt, ws, wd, 0xe);
}
void Mips64Assembler::Max_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x3, 0x0, wt, ws, wd, 0xe);
}
void Mips64Assembler::Max_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x3, 0x1, wt, ws, wd, 0xe);
}
void Mips64Assembler::Max_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x3, 0x2, wt, ws, wd, 0xe);
}
void Mips64Assembler::Max_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x3, 0x3, wt, ws, wd, 0xe);
}
void Mips64Assembler::Min_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x0, wt, ws, wd, 0xe);
}
void Mips64Assembler::Min_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x1, wt, ws, wd, 0xe);
}
void Mips64Assembler::Min_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x2, wt, ws, wd, 0xe);
}
void Mips64Assembler::Min_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x3, wt, ws, wd, 0xe);
}
void Mips64Assembler::Min_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x0, wt, ws, wd, 0xe);
}
void Mips64Assembler::Min_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x1, wt, ws, wd, 0xe);
}
void Mips64Assembler::Min_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x2, wt, ws, wd, 0xe);
}
void Mips64Assembler::Min_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x3, wt, ws, wd, 0xe);
}
void Mips64Assembler::FaddW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x0, wt, ws, wd, 0x1b);
}
void Mips64Assembler::FaddD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x1, wt, ws, wd, 0x1b);
}
void Mips64Assembler::FsubW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x2, wt, ws, wd, 0x1b);
}
void Mips64Assembler::FsubD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x3, wt, ws, wd, 0x1b);
}
void Mips64Assembler::FmulW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x1, 0x0, wt, ws, wd, 0x1b);
}
void Mips64Assembler::FmulD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x1, 0x1, wt, ws, wd, 0x1b);
}
void Mips64Assembler::FdivW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x1, 0x2, wt, ws, wd, 0x1b);
}
void Mips64Assembler::FdivD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x1, 0x3, wt, ws, wd, 0x1b);
}
void Mips64Assembler::FmaxW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x7, 0x0, wt, ws, wd, 0x1b);
}
void Mips64Assembler::FmaxD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x7, 0x1, wt, ws, wd, 0x1b);
}
void Mips64Assembler::FminW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x6, 0x0, wt, ws, wd, 0x1b);
}
void Mips64Assembler::FminD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x6, 0x1, wt, ws, wd, 0x1b);
}
void Mips64Assembler::Ffint_sW(VectorRegister wd, VectorRegister ws) {
CHECK(HasMsa());
EmitMsa2RF(0x19e, 0x0, ws, wd, 0x1e);
}
void Mips64Assembler::Ffint_sD(VectorRegister wd, VectorRegister ws) {
CHECK(HasMsa());
EmitMsa2RF(0x19e, 0x1, ws, wd, 0x1e);
}
void Mips64Assembler::Ftint_sW(VectorRegister wd, VectorRegister ws) {
CHECK(HasMsa());
EmitMsa2RF(0x19c, 0x0, ws, wd, 0x1e);
}
void Mips64Assembler::Ftint_sD(VectorRegister wd, VectorRegister ws) {
CHECK(HasMsa());
EmitMsa2RF(0x19c, 0x1, ws, wd, 0x1e);
}
void Mips64Assembler::SllB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x0, wt, ws, wd, 0xd);
}
void Mips64Assembler::SllH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x1, wt, ws, wd, 0xd);
}
void Mips64Assembler::SllW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x2, wt, ws, wd, 0xd);
}
void Mips64Assembler::SllD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x0, 0x3, wt, ws, wd, 0xd);
}
void Mips64Assembler::SraB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x1, 0x0, wt, ws, wd, 0xd);
}
void Mips64Assembler::SraH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x1, 0x1, wt, ws, wd, 0xd);
}
void Mips64Assembler::SraW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x1, 0x2, wt, ws, wd, 0xd);
}
void Mips64Assembler::SraD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x1, 0x3, wt, ws, wd, 0xd);
}
void Mips64Assembler::SrlB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x2, 0x0, wt, ws, wd, 0xd);
}
void Mips64Assembler::SrlH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x2, 0x1, wt, ws, wd, 0xd);
}
void Mips64Assembler::SrlW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x2, 0x2, wt, ws, wd, 0xd);
}
void Mips64Assembler::SrlD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x2, 0x3, wt, ws, wd, 0xd);
}
void Mips64Assembler::SlliB(VectorRegister wd, VectorRegister ws, int shamt3) {
CHECK(HasMsa());
CHECK(IsUint<3>(shamt3)) << shamt3;
EmitMsaBIT(0x0, shamt3 | kMsaDfMByteMask, ws, wd, 0x9);
}
void Mips64Assembler::SlliH(VectorRegister wd, VectorRegister ws, int shamt4) {
CHECK(HasMsa());
CHECK(IsUint<4>(shamt4)) << shamt4;
EmitMsaBIT(0x0, shamt4 | kMsaDfMHalfwordMask, ws, wd, 0x9);
}
void Mips64Assembler::SlliW(VectorRegister wd, VectorRegister ws, int shamt5) {
CHECK(HasMsa());
CHECK(IsUint<5>(shamt5)) << shamt5;
EmitMsaBIT(0x0, shamt5 | kMsaDfMWordMask, ws, wd, 0x9);
}
void Mips64Assembler::SlliD(VectorRegister wd, VectorRegister ws, int shamt6) {
CHECK(HasMsa());
CHECK(IsUint<6>(shamt6)) << shamt6;
EmitMsaBIT(0x0, shamt6 | kMsaDfMDoublewordMask, ws, wd, 0x9);
}
void Mips64Assembler::SraiB(VectorRegister wd, VectorRegister ws, int shamt3) {
CHECK(HasMsa());
CHECK(IsUint<3>(shamt3)) << shamt3;
EmitMsaBIT(0x1, shamt3 | kMsaDfMByteMask, ws, wd, 0x9);
}
void Mips64Assembler::SraiH(VectorRegister wd, VectorRegister ws, int shamt4) {
CHECK(HasMsa());
CHECK(IsUint<4>(shamt4)) << shamt4;
EmitMsaBIT(0x1, shamt4 | kMsaDfMHalfwordMask, ws, wd, 0x9);
}
void Mips64Assembler::SraiW(VectorRegister wd, VectorRegister ws, int shamt5) {
CHECK(HasMsa());
CHECK(IsUint<5>(shamt5)) << shamt5;
EmitMsaBIT(0x1, shamt5 | kMsaDfMWordMask, ws, wd, 0x9);
}
void Mips64Assembler::SraiD(VectorRegister wd, VectorRegister ws, int shamt6) {
CHECK(HasMsa());
CHECK(IsUint<6>(shamt6)) << shamt6;
EmitMsaBIT(0x1, shamt6 | kMsaDfMDoublewordMask, ws, wd, 0x9);
}
void Mips64Assembler::SrliB(VectorRegister wd, VectorRegister ws, int shamt3) {
CHECK(HasMsa());
CHECK(IsUint<3>(shamt3)) << shamt3;
EmitMsaBIT(0x2, shamt3 | kMsaDfMByteMask, ws, wd, 0x9);
}
void Mips64Assembler::SrliH(VectorRegister wd, VectorRegister ws, int shamt4) {
CHECK(HasMsa());
CHECK(IsUint<4>(shamt4)) << shamt4;
EmitMsaBIT(0x2, shamt4 | kMsaDfMHalfwordMask, ws, wd, 0x9);
}
void Mips64Assembler::SrliW(VectorRegister wd, VectorRegister ws, int shamt5) {
CHECK(HasMsa());
CHECK(IsUint<5>(shamt5)) << shamt5;
EmitMsaBIT(0x2, shamt5 | kMsaDfMWordMask, ws, wd, 0x9);
}
void Mips64Assembler::SrliD(VectorRegister wd, VectorRegister ws, int shamt6) {
CHECK(HasMsa());
CHECK(IsUint<6>(shamt6)) << shamt6;
EmitMsaBIT(0x2, shamt6 | kMsaDfMDoublewordMask, ws, wd, 0x9);
}
void Mips64Assembler::MoveV(VectorRegister wd, VectorRegister ws) {
CHECK(HasMsa());
EmitMsaBIT(0x1, 0x3e, ws, wd, 0x19);
}
void Mips64Assembler::SplatiB(VectorRegister wd, VectorRegister ws, int n4) {
CHECK(HasMsa());
CHECK(IsUint<4>(n4)) << n4;
EmitMsaELM(0x1, n4 | kMsaDfNByteMask, ws, wd, 0x19);
}
void Mips64Assembler::SplatiH(VectorRegister wd, VectorRegister ws, int n3) {
CHECK(HasMsa());
CHECK(IsUint<3>(n3)) << n3;
EmitMsaELM(0x1, n3 | kMsaDfNHalfwordMask, ws, wd, 0x19);
}
void Mips64Assembler::SplatiW(VectorRegister wd, VectorRegister ws, int n2) {
CHECK(HasMsa());
CHECK(IsUint<2>(n2)) << n2;
EmitMsaELM(0x1, n2 | kMsaDfNWordMask, ws, wd, 0x19);
}
void Mips64Assembler::SplatiD(VectorRegister wd, VectorRegister ws, int n1) {
CHECK(HasMsa());
CHECK(IsUint<1>(n1)) << n1;
EmitMsaELM(0x1, n1 | kMsaDfNDoublewordMask, ws, wd, 0x19);
}
void Mips64Assembler::Copy_sB(GpuRegister rd, VectorRegister ws, int n4) {
CHECK(HasMsa());
CHECK(IsUint<4>(n4)) << n4;
EmitMsaELM(0x2, n4 | kMsaDfNByteMask, ws, static_cast<VectorRegister>(rd), 0x19);
}
void Mips64Assembler::Copy_sH(GpuRegister rd, VectorRegister ws, int n3) {
CHECK(HasMsa());
CHECK(IsUint<3>(n3)) << n3;
EmitMsaELM(0x2, n3 | kMsaDfNHalfwordMask, ws, static_cast<VectorRegister>(rd), 0x19);
}
void Mips64Assembler::Copy_sW(GpuRegister rd, VectorRegister ws, int n2) {
CHECK(HasMsa());
CHECK(IsUint<2>(n2)) << n2;
EmitMsaELM(0x2, n2 | kMsaDfNWordMask, ws, static_cast<VectorRegister>(rd), 0x19);
}
void Mips64Assembler::Copy_sD(GpuRegister rd, VectorRegister ws, int n1) {
CHECK(HasMsa());
CHECK(IsUint<1>(n1)) << n1;
EmitMsaELM(0x2, n1 | kMsaDfNDoublewordMask, ws, static_cast<VectorRegister>(rd), 0x19);
}
void Mips64Assembler::Copy_uB(GpuRegister rd, VectorRegister ws, int n4) {
CHECK(HasMsa());
CHECK(IsUint<4>(n4)) << n4;
EmitMsaELM(0x3, n4 | kMsaDfNByteMask, ws, static_cast<VectorRegister>(rd), 0x19);
}
void Mips64Assembler::Copy_uH(GpuRegister rd, VectorRegister ws, int n3) {
CHECK(HasMsa());
CHECK(IsUint<3>(n3)) << n3;
EmitMsaELM(0x3, n3 | kMsaDfNHalfwordMask, ws, static_cast<VectorRegister>(rd), 0x19);
}
void Mips64Assembler::Copy_uW(GpuRegister rd, VectorRegister ws, int n2) {
CHECK(HasMsa());
CHECK(IsUint<2>(n2)) << n2;
EmitMsaELM(0x3, n2 | kMsaDfNWordMask, ws, static_cast<VectorRegister>(rd), 0x19);
}
void Mips64Assembler::InsertB(VectorRegister wd, GpuRegister rs, int n4) {
CHECK(HasMsa());
CHECK(IsUint<4>(n4)) << n4;
EmitMsaELM(0x4, n4 | kMsaDfNByteMask, static_cast<VectorRegister>(rs), wd, 0x19);
}
void Mips64Assembler::InsertH(VectorRegister wd, GpuRegister rs, int n3) {
CHECK(HasMsa());
CHECK(IsUint<3>(n3)) << n3;
EmitMsaELM(0x4, n3 | kMsaDfNHalfwordMask, static_cast<VectorRegister>(rs), wd, 0x19);
}
void Mips64Assembler::InsertW(VectorRegister wd, GpuRegister rs, int n2) {
CHECK(HasMsa());
CHECK(IsUint<2>(n2)) << n2;
EmitMsaELM(0x4, n2 | kMsaDfNWordMask, static_cast<VectorRegister>(rs), wd, 0x19);
}
void Mips64Assembler::InsertD(VectorRegister wd, GpuRegister rs, int n1) {
CHECK(HasMsa());
CHECK(IsUint<1>(n1)) << n1;
EmitMsaELM(0x4, n1 | kMsaDfNDoublewordMask, static_cast<VectorRegister>(rs), wd, 0x19);
}
void Mips64Assembler::FillB(VectorRegister wd, GpuRegister rs) {
CHECK(HasMsa());
EmitMsa2R(0xc0, 0x0, static_cast<VectorRegister>(rs), wd, 0x1e);
}
void Mips64Assembler::FillH(VectorRegister wd, GpuRegister rs) {
CHECK(HasMsa());
EmitMsa2R(0xc0, 0x1, static_cast<VectorRegister>(rs), wd, 0x1e);
}
void Mips64Assembler::FillW(VectorRegister wd, GpuRegister rs) {
CHECK(HasMsa());
EmitMsa2R(0xc0, 0x2, static_cast<VectorRegister>(rs), wd, 0x1e);
}
void Mips64Assembler::FillD(VectorRegister wd, GpuRegister rs) {
CHECK(HasMsa());
EmitMsa2R(0xc0, 0x3, static_cast<VectorRegister>(rs), wd, 0x1e);
}
void Mips64Assembler::LdiB(VectorRegister wd, int imm8) {
CHECK(HasMsa());
CHECK(IsInt<8>(imm8)) << imm8;
EmitMsaI10(0x6, 0x0, imm8 & kMsaS10Mask, wd, 0x7);
}
void Mips64Assembler::LdiH(VectorRegister wd, int imm10) {
CHECK(HasMsa());
CHECK(IsInt<10>(imm10)) << imm10;
EmitMsaI10(0x6, 0x1, imm10 & kMsaS10Mask, wd, 0x7);
}
void Mips64Assembler::LdiW(VectorRegister wd, int imm10) {
CHECK(HasMsa());
CHECK(IsInt<10>(imm10)) << imm10;
EmitMsaI10(0x6, 0x2, imm10 & kMsaS10Mask, wd, 0x7);
}
void Mips64Assembler::LdiD(VectorRegister wd, int imm10) {
CHECK(HasMsa());
CHECK(IsInt<10>(imm10)) << imm10;
EmitMsaI10(0x6, 0x3, imm10 & kMsaS10Mask, wd, 0x7);
}
void Mips64Assembler::LdB(VectorRegister wd, GpuRegister rs, int offset) {
CHECK(HasMsa());
CHECK(IsInt<10>(offset)) << offset;
EmitMsaMI10(offset & kMsaS10Mask, rs, wd, 0x8, 0x0);
}
void Mips64Assembler::LdH(VectorRegister wd, GpuRegister rs, int offset) {
CHECK(HasMsa());
CHECK(IsInt<11>(offset)) << offset;
CHECK_ALIGNED(offset, kMips64HalfwordSize);
EmitMsaMI10((offset >> TIMES_2) & kMsaS10Mask, rs, wd, 0x8, 0x1);
}
void Mips64Assembler::LdW(VectorRegister wd, GpuRegister rs, int offset) {
CHECK(HasMsa());
CHECK(IsInt<12>(offset)) << offset;
CHECK_ALIGNED(offset, kMips64WordSize);
EmitMsaMI10((offset >> TIMES_4) & kMsaS10Mask, rs, wd, 0x8, 0x2);
}
void Mips64Assembler::LdD(VectorRegister wd, GpuRegister rs, int offset) {
CHECK(HasMsa());
CHECK(IsInt<13>(offset)) << offset;
CHECK_ALIGNED(offset, kMips64DoublewordSize);
EmitMsaMI10((offset >> TIMES_8) & kMsaS10Mask, rs, wd, 0x8, 0x3);
}
void Mips64Assembler::StB(VectorRegister wd, GpuRegister rs, int offset) {
CHECK(HasMsa());
CHECK(IsInt<10>(offset)) << offset;
EmitMsaMI10(offset & kMsaS10Mask, rs, wd, 0x9, 0x0);
}
void Mips64Assembler::StH(VectorRegister wd, GpuRegister rs, int offset) {
CHECK(HasMsa());
CHECK(IsInt<11>(offset)) << offset;
CHECK_ALIGNED(offset, kMips64HalfwordSize);
EmitMsaMI10((offset >> TIMES_2) & kMsaS10Mask, rs, wd, 0x9, 0x1);
}
void Mips64Assembler::StW(VectorRegister wd, GpuRegister rs, int offset) {
CHECK(HasMsa());
CHECK(IsInt<12>(offset)) << offset;
CHECK_ALIGNED(offset, kMips64WordSize);
EmitMsaMI10((offset >> TIMES_4) & kMsaS10Mask, rs, wd, 0x9, 0x2);
}
void Mips64Assembler::StD(VectorRegister wd, GpuRegister rs, int offset) {
CHECK(HasMsa());
CHECK(IsInt<13>(offset)) << offset;
CHECK_ALIGNED(offset, kMips64DoublewordSize);
EmitMsaMI10((offset >> TIMES_8) & kMsaS10Mask, rs, wd, 0x9, 0x3);
}
void Mips64Assembler::IlvlB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x0, wt, ws, wd, 0x14);
}
void Mips64Assembler::IlvlH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x1, wt, ws, wd, 0x14);
}
void Mips64Assembler::IlvlW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x2, wt, ws, wd, 0x14);
}
void Mips64Assembler::IlvlD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x3, wt, ws, wd, 0x14);
}
void Mips64Assembler::IlvrB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x0, wt, ws, wd, 0x14);
}
void Mips64Assembler::IlvrH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x1, wt, ws, wd, 0x14);
}
void Mips64Assembler::IlvrW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x2, wt, ws, wd, 0x14);
}
void Mips64Assembler::IlvrD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x3, wt, ws, wd, 0x14);
}
void Mips64Assembler::IlvevB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x6, 0x0, wt, ws, wd, 0x14);
}
void Mips64Assembler::IlvevH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x6, 0x1, wt, ws, wd, 0x14);
}
void Mips64Assembler::IlvevW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x6, 0x2, wt, ws, wd, 0x14);
}
void Mips64Assembler::IlvevD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x6, 0x3, wt, ws, wd, 0x14);
}
void Mips64Assembler::IlvodB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x7, 0x0, wt, ws, wd, 0x14);
}
void Mips64Assembler::IlvodH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x7, 0x1, wt, ws, wd, 0x14);
}
void Mips64Assembler::IlvodW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x7, 0x2, wt, ws, wd, 0x14);
}
void Mips64Assembler::IlvodD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x7, 0x3, wt, ws, wd, 0x14);
}
void Mips64Assembler::MaddvB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x1, 0x0, wt, ws, wd, 0x12);
}
void Mips64Assembler::MaddvH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x1, 0x1, wt, ws, wd, 0x12);
}
void Mips64Assembler::MaddvW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x1, 0x2, wt, ws, wd, 0x12);
}
void Mips64Assembler::MaddvD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x1, 0x3, wt, ws, wd, 0x12);
}
void Mips64Assembler::MsubvB(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x2, 0x0, wt, ws, wd, 0x12);
}
void Mips64Assembler::MsubvH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x2, 0x1, wt, ws, wd, 0x12);
}
void Mips64Assembler::MsubvW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x2, 0x2, wt, ws, wd, 0x12);
}
void Mips64Assembler::MsubvD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x2, 0x3, wt, ws, wd, 0x12);
}
void Mips64Assembler::FmaddW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x2, 0x0, wt, ws, wd, 0x1b);
}
void Mips64Assembler::FmaddD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x2, 0x1, wt, ws, wd, 0x1b);
}
void Mips64Assembler::FmsubW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x2, 0x2, wt, ws, wd, 0x1b);
}
void Mips64Assembler::FmsubD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x2, 0x3, wt, ws, wd, 0x1b);
}
void Mips64Assembler::Hadd_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x1, wt, ws, wd, 0x15);
}
void Mips64Assembler::Hadd_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x2, wt, ws, wd, 0x15);
}
void Mips64Assembler::Hadd_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x4, 0x3, wt, ws, wd, 0x15);
}
void Mips64Assembler::Hadd_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt) {
CHECK(HasMsa());
EmitMsa3R(0x5, 0x1, wt, ws, wd, 0x15);
}
void Mips64Assembler::Hadd_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt) {