commit 3a0831507637028a439712dedaaddd7cd0893995
author Jeff Hao <jeffhao@google.com> Wed Sep 11 18:04:26 2013 -0700
committer Jeff Hao <jeffhao@google.com> Thu Sep 12 01:35:24 2013 +0000
tree bc64f05af01521fb9636b05e564e3ada08fdd033
parent 226476bd6067864b860b48ed5b88982e131c20d9

Fix CAS intrinsic to clear exclusive if values don't match.

The LDREX has a matching STREX if the values match, but it needed
a CLREX for the case where they didn't.

Bug: 10530407
Change-Id: I46b474cca326a251536e7f214c80486694431386
(cherry picked from commit 78765e84a3654357a03f84b76985556cf7d9731a)

compiler/dex/quick/arm/int_arm.cc

diff --git a/compiler/dex/quick/arm/int_arm.cc b/compiler/dex/quick/arm/int_arm.cc
index f2ff58e..103dec6 100644
--- a/compiler/dex/quick/arm/int_arm.cc
+++ b/compiler/dex/quick/arm/int_arm.cc
@@ -549,10 +549,11 @@
   OpRegReg(kOpCmp, r_old_value, rl_expected.low_reg);
   FreeTemp(r_old_value);  // Now unneeded.
   RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
-  OpIT(kCondEq, "TE");
+  OpIT(kCondEq, "TEE");
   NewLIR4(kThumb2Strex, rl_result.low_reg, rl_new_value.low_reg, r_ptr, 0);
   FreeTemp(r_ptr);  // Now unneeded.
   OpRegImm(kOpXor, rl_result.low_reg, 1);
+  NewLIR0(kThumb2Clrex);
   OpRegReg(kOpXor, rl_result.low_reg, rl_result.low_reg);
 
   StoreValue(rl_dest, rl_result);