diff --git a/Android.mk b/Android.mk
index 5a28723..4e4928c 100644
--- a/Android.mk
+++ b/Android.mk
@@ -334,7 +334,7 @@
 .PHONY: cpplint-art
 cpplint-art:
 	./art/tools/cpplint.py \
-	    --filter=-,+build/header_guard, \
+	    --filter=-,+build/header_guard,+whitespace/braces \
 	    $(shell find art -name *.h -o -name *$(ART_CPP_EXTENSION))
 
 # "mm cpplint-art-aspirational" to see warnings we would like to fix
diff --git a/compiler/dex/arena_allocator.h b/compiler/dex/arena_allocator.h
index 23d6b9f..cc81e50 100644
--- a/compiler/dex/arena_allocator.h
+++ b/compiler/dex/arena_allocator.h
@@ -86,7 +86,7 @@
      void Dump(std::ostream& os) const {
        arena_.DumpMemStats(os);
      }
-     MemStats(const ArenaAllocator &arena) : arena_(arena){};
+     MemStats(const ArenaAllocator &arena) : arena_(arena) {};
   private:
     const ArenaAllocator &arena_;
 }; // MemStats
diff --git a/compiler/dex/arena_bit_vector.cc b/compiler/dex/arena_bit_vector.cc
index 1fbf774..724fdf8 100644
--- a/compiler/dex/arena_bit_vector.cc
+++ b/compiler/dex/arena_bit_vector.cc
@@ -114,8 +114,7 @@
 }
 
 // Count the number of bits that are set.
-int ArenaBitVector::NumSetBits()
-{
+int ArenaBitVector::NumSetBits() {
   unsigned int count = 0;
 
   for (unsigned int word = 0; word < storage_size_; word++) {
@@ -129,8 +128,7 @@
  * since there might be unused bits - setting those to one will confuse the
  * iterator.
  */
-void ArenaBitVector::SetInitialBits(unsigned int num_bits)
-{
+void ArenaBitVector::SetInitialBits(unsigned int num_bits) {
   DCHECK_LE(((num_bits + 31) >> 5), storage_size_);
   unsigned int idx;
   for (idx = 0; idx < (num_bits >> 5); idx++) {
diff --git a/compiler/dex/dataflow_iterator.h b/compiler/dex/dataflow_iterator.h
index 4c112f9..1946869 100644
--- a/compiler/dex/dataflow_iterator.h
+++ b/compiler/dex/dataflow_iterator.h
@@ -42,7 +42,7 @@
   class DataflowIterator {
     public:
 
-      virtual ~DataflowIterator(){}
+      virtual ~DataflowIterator() {}
 
       // Return the next BasicBlock* to visit.
       BasicBlock* Next() {
diff --git a/compiler/dex/frontend.cc b/compiler/dex/frontend.cc
index 746d475..2d7c973 100644
--- a/compiler/dex/frontend.cc
+++ b/compiler/dex/frontend.cc
@@ -220,7 +220,7 @@
                                        llvm_compilation_unit));
   } else
 #endif
-  {
+  { // NOLINT(whitespace/braces)
     switch (compiler.GetInstructionSet()) {
       case kThumb2:
         cu->cg.reset(ArmCodeGenerator(cu.get(), cu->mir_graph.get(), &cu->arena)); break;
diff --git a/compiler/dex/local_value_numbering.cc b/compiler/dex/local_value_numbering.cc
index ec5ab5d..b783f3e 100644
--- a/compiler/dex/local_value_numbering.cc
+++ b/compiler/dex/local_value_numbering.cc
@@ -19,8 +19,7 @@
 namespace art {
 
 
-uint16_t LocalValueNumbering::GetValueNumber(MIR* mir)
-{
+uint16_t LocalValueNumbering::GetValueNumber(MIR* mir) {
   uint16_t res = NO_VALUE;
   uint16_t opcode = mir->dalvikInsn.opcode;
   switch (opcode) {
diff --git a/compiler/dex/mir_dataflow.cc b/compiler/dex/mir_dataflow.cc
index 6c152d2..9632388 100644
--- a/compiler/dex/mir_dataflow.cc
+++ b/compiler/dex/mir_dataflow.cc
@@ -849,8 +849,7 @@
 
 /* Any register that is used before being defined is considered live-in */
 void MIRGraph::HandleLiveInUse(ArenaBitVector* use_v, ArenaBitVector* def_v,
-                            ArenaBitVector* live_in_v, int dalvik_reg_id)
-{
+                            ArenaBitVector* live_in_v, int dalvik_reg_id) {
   use_v->SetBit(dalvik_reg_id);
   if (!def_v->IsBitSet(dalvik_reg_id)) {
     live_in_v->SetBit(dalvik_reg_id);
@@ -858,8 +857,7 @@
 }
 
 /* Mark a reg as being defined */
-void MIRGraph::HandleDef(ArenaBitVector* def_v, int dalvik_reg_id)
-{
+void MIRGraph::HandleDef(ArenaBitVector* def_v, int dalvik_reg_id) {
   def_v->SetBit(dalvik_reg_id);
 }
 
@@ -867,8 +865,7 @@
  * Find out live-in variables for natural loops. Variables that are live-in in
  * the main loop body are considered to be defined in the entry block.
  */
-bool MIRGraph::FindLocalLiveIn(BasicBlock* bb)
-{
+bool MIRGraph::FindLocalLiveIn(BasicBlock* bb) {
   MIR* mir;
   ArenaBitVector *use_v, *def_v, *live_in_v;
 
@@ -925,8 +922,7 @@
   return true;
 }
 
-int MIRGraph::AddNewSReg(int v_reg)
-{
+int MIRGraph::AddNewSReg(int v_reg) {
   // Compiler temps always have a subscript of 0
   int subscript = (v_reg < 0) ? 0 : ++ssa_last_defs_[v_reg];
   int ssa_reg = GetNumSSARegs();
@@ -938,15 +934,13 @@
 }
 
 /* Find out the latest SSA register for a given Dalvik register */
-void MIRGraph::HandleSSAUse(int* uses, int dalvik_reg, int reg_index)
-{
+void MIRGraph::HandleSSAUse(int* uses, int dalvik_reg, int reg_index) {
   DCHECK((dalvik_reg >= 0) && (dalvik_reg < cu_->num_dalvik_registers));
   uses[reg_index] = vreg_to_ssa_map_[dalvik_reg];
 }
 
 /* Setup a new SSA register for a given Dalvik register */
-void MIRGraph::HandleSSADef(int* defs, int dalvik_reg, int reg_index)
-{
+void MIRGraph::HandleSSADef(int* defs, int dalvik_reg, int reg_index) {
   DCHECK((dalvik_reg >= 0) && (dalvik_reg < cu_->num_dalvik_registers));
   int ssa_reg = AddNewSReg(dalvik_reg);
   vreg_to_ssa_map_[dalvik_reg] = ssa_reg;
@@ -954,8 +948,7 @@
 }
 
 /* Look up new SSA names for format_35c instructions */
-void MIRGraph::DataFlowSSAFormat35C(MIR* mir)
-{
+void MIRGraph::DataFlowSSAFormat35C(MIR* mir) {
   DecodedInstruction *d_insn = &mir->dalvikInsn;
   int num_uses = d_insn->vA;
   int i;
@@ -973,8 +966,7 @@
 }
 
 /* Look up new SSA names for format_3rc instructions */
-void MIRGraph::DataFlowSSAFormat3RC(MIR* mir)
-{
+void MIRGraph::DataFlowSSAFormat3RC(MIR* mir) {
   DecodedInstruction *d_insn = &mir->dalvikInsn;
   int num_uses = d_insn->vA;
   int i;
@@ -992,8 +984,7 @@
 }
 
 /* Entry function to convert a block into SSA representation */
-bool MIRGraph::DoSSAConversion(BasicBlock* bb)
-{
+bool MIRGraph::DoSSAConversion(BasicBlock* bb) {
   MIR* mir;
 
   if (bb->data_flow_info == NULL) return false;
@@ -1127,8 +1118,7 @@
 }
 
 /* Setup the basic data structures for SSA conversion */
-void MIRGraph::CompilerInitializeSSAConversion()
-{
+void MIRGraph::CompilerInitializeSSAConversion() {
   size_t num_dalvik_reg = cu_->num_dalvik_registers;
 
   ssa_base_vregs_ = new (arena_) GrowableArray<int>(arena_, num_dalvik_reg + GetDefCount() + 128,
@@ -1196,8 +1186,7 @@
  * and attempting to do would involve more complexity than it's
  * worth.
  */
-bool MIRGraph::InvokeUsesMethodStar(MIR* mir)
-{
+bool MIRGraph::InvokeUsesMethodStar(MIR* mir) {
   InvokeType type;
   Instruction::Code opcode = mir->dalvikInsn.opcode;
   switch (opcode) {
@@ -1246,8 +1235,7 @@
  * counts explicitly used s_regs.  A later phase will add implicit
  * counts for things such as Method*, null-checked references, etc.
  */
-bool MIRGraph::CountUses(struct BasicBlock* bb)
-{
+bool MIRGraph::CountUses(struct BasicBlock* bb) {
   if (bb->block_type != kDalvikByteCode) {
     return false;
   }
@@ -1286,8 +1274,7 @@
   return false;
 }
 
-void MIRGraph::MethodUseCount()
-{
+void MIRGraph::MethodUseCount() {
   // Now that we know, resize the lists.
   int num_ssa_regs = GetNumSSARegs();
   use_counts_.Resize(num_ssa_regs + 32);
@@ -1307,8 +1294,7 @@
 }
 
 /* Verify if all the successor is connected with all the claimed predecessors */
-bool MIRGraph::VerifyPredInfo(BasicBlock* bb)
-{
+bool MIRGraph::VerifyPredInfo(BasicBlock* bb) {
   GrowableArray<BasicBlock*>::Iterator iter(bb->predecessors);
 
   while (true) {
@@ -1343,8 +1329,7 @@
   return true;
 }
 
-void MIRGraph::VerifyDataflow()
-{
+void MIRGraph::VerifyDataflow() {
     /* Verify if all blocks are connected as claimed */
   AllNodesIterator iter(this, false /* not iterative */);
   for (BasicBlock* bb = iter.Next(); bb != NULL; bb = iter.Next()) {
diff --git a/compiler/dex/mir_graph.cc b/compiler/dex/mir_graph.cc
index 11e100d..ef9955e 100644
--- a/compiler/dex/mir_graph.cc
+++ b/compiler/dex/mir_graph.cc
@@ -107,8 +107,7 @@
       method_sreg_(0),
       attributes_(METHOD_IS_LEAF),  // Start with leaf assumption, change on encountering invoke.
       checkstats_(NULL),
-      arena_(arena)
-      {
+      arena_(arena) {
   try_block_addr_ = new (arena_) ArenaBitVector(arena_, 0, true /* expandable */);
 }
 
@@ -129,8 +128,7 @@
 /*
  * Parse an instruction, return the length of the instruction
  */
-int MIRGraph::ParseInsn(const uint16_t* code_ptr, DecodedInstruction* decoded_instruction)
-{
+int MIRGraph::ParseInsn(const uint16_t* code_ptr, DecodedInstruction* decoded_instruction) {
   // Don't parse instruction data
   if (!ContentIsInsn(code_ptr)) {
     return 0;
@@ -145,8 +143,7 @@
 
 /* Split an existing block from the specified code offset into two */
 BasicBlock* MIRGraph::SplitBlock(unsigned int code_offset,
-                                 BasicBlock* orig_block, BasicBlock** immed_pred_block_p)
-{
+                                 BasicBlock* orig_block, BasicBlock** immed_pred_block_p) {
   MIR* insn = orig_block->first_mir_insn;
   while (insn) {
     if (insn->offset == code_offset) break;
@@ -224,8 +221,7 @@
  * Utilizes a map for fast lookup of the typical cases.
  */
 BasicBlock* MIRGraph::FindBlock(unsigned int code_offset, bool split, bool create,
-                                BasicBlock** immed_pred_block_p)
-{
+                                BasicBlock** immed_pred_block_p) {
   BasicBlock* bb;
   unsigned int i;
   SafeMap<unsigned int, BasicBlock*>::iterator it;
@@ -260,8 +256,7 @@
 }
 
 /* Identify code range in try blocks and set up the empty catch blocks */
-void MIRGraph::ProcessTryCatchBlocks()
-{
+void MIRGraph::ProcessTryCatchBlocks() {
   int tries_size = current_code_item_->tries_size_;
   int offset;
 
@@ -296,8 +291,7 @@
 /* Process instructions with the kBranch flag */
 BasicBlock* MIRGraph::ProcessCanBranch(BasicBlock* cur_block, MIR* insn, int cur_offset, int width,
                                        int flags, const uint16_t* code_ptr,
-                                       const uint16_t* code_end)
-{
+                                       const uint16_t* code_end) {
   int target = cur_offset;
   switch (insn->dalvikInsn.opcode) {
     case Instruction::GOTO:
@@ -365,8 +359,7 @@
 
 /* Process instructions with the kSwitch flag */
 void MIRGraph::ProcessCanSwitch(BasicBlock* cur_block, MIR* insn, int cur_offset, int width,
-                                int flags)
-{
+                                int flags) {
   const uint16_t* switch_data =
       reinterpret_cast<const uint16_t*>(GetCurrentInsns() + cur_offset + insn->dalvikInsn.vB);
   int size;
@@ -443,8 +436,7 @@
 /* Process instructions with the kThrow flag */
 BasicBlock* MIRGraph::ProcessCanThrow(BasicBlock* cur_block, MIR* insn, int cur_offset, int width,
                                       int flags, ArenaBitVector* try_block_addr,
-                                      const uint16_t* code_ptr, const uint16_t* code_end)
-{
+                                      const uint16_t* code_ptr, const uint16_t* code_end) {
   bool in_try_block = try_block_addr->IsBitSet(cur_offset);
 
   /* In try block */
@@ -483,7 +475,7 @@
     eh_block->predecessors->Insert(cur_block);
   }
 
-  if (insn->dalvikInsn.opcode == Instruction::THROW){
+  if (insn->dalvikInsn.opcode == Instruction::THROW) {
     cur_block->explicit_throw = true;
     if ((code_ptr < code_end) && ContentIsInsn(code_ptr)) {
       // Force creation of new block following THROW via side-effect
@@ -529,8 +521,7 @@
 /* Parse a Dex method and insert it into the MIRGraph at the current insert point. */
 void MIRGraph::InlineMethod(const DexFile::CodeItem* code_item, uint32_t access_flags,
                            InvokeType invoke_type, uint32_t class_def_idx,
-                           uint32_t method_idx, jobject class_loader, const DexFile& dex_file)
-{
+                           uint32_t method_idx, jobject class_loader, const DexFile& dex_file) {
   current_code_item_ = code_item;
   method_stack_.push_back(std::make_pair(current_method_, current_offset_));
   current_method_ = m_units_.size();
@@ -705,8 +696,7 @@
   }
 }
 
-void MIRGraph::ShowOpcodeStats()
-{
+void MIRGraph::ShowOpcodeStats() {
   DCHECK(opcode_count_ != NULL);
   LOG(INFO) << "Opcode Count";
   for (int i = 0; i < kNumPackedOpcodes; i++) {
@@ -719,8 +709,7 @@
 
 // TODO: use a configurable base prefix, and adjust callers to supply pass name.
 /* Dump the CFG into a DOT graph */
-void MIRGraph::DumpCFG(const char* dir_prefix, bool all_blocks)
-{
+void MIRGraph::DumpCFG(const char* dir_prefix, bool all_blocks) {
   FILE* file;
   std::string fname(PrettyMethod(cu_->method_idx, *cu_->dex_file));
   ReplaceSpecialChars(fname);
@@ -849,8 +838,7 @@
 }
 
 /* Insert an MIR instruction to the end of a basic block */
-void MIRGraph::AppendMIR(BasicBlock* bb, MIR* mir)
-{
+void MIRGraph::AppendMIR(BasicBlock* bb, MIR* mir) {
   if (bb->first_mir_insn == NULL) {
     DCHECK(bb->last_mir_insn == NULL);
     bb->last_mir_insn = bb->first_mir_insn = mir;
@@ -864,8 +852,7 @@
 }
 
 /* Insert an MIR instruction to the head of a basic block */
-void MIRGraph::PrependMIR(BasicBlock* bb, MIR* mir)
-{
+void MIRGraph::PrependMIR(BasicBlock* bb, MIR* mir) {
   if (bb->first_mir_insn == NULL) {
     DCHECK(bb->last_mir_insn == NULL);
     bb->last_mir_insn = bb->first_mir_insn = mir;
@@ -879,8 +866,7 @@
 }
 
 /* Insert a MIR instruction after the specified MIR */
-void MIRGraph::InsertMIRAfter(BasicBlock* bb, MIR* current_mir, MIR* new_mir)
-{
+void MIRGraph::InsertMIRAfter(BasicBlock* bb, MIR* current_mir, MIR* new_mir) {
   new_mir->prev = current_mir;
   new_mir->next = current_mir->next;
   current_mir->next = new_mir;
@@ -894,8 +880,7 @@
   }
 }
 
-char* MIRGraph::GetDalvikDisassembly(const MIR* mir)
-{
+char* MIRGraph::GetDalvikDisassembly(const MIR* mir) {
   DecodedInstruction insn = mir->dalvikInsn;
   std::string str;
   int flags = 0;
@@ -1024,8 +1009,7 @@
 }
 
 /* Turn method name into a legal Linux file name */
-void MIRGraph::ReplaceSpecialChars(std::string& str)
-{
+void MIRGraph::ReplaceSpecialChars(std::string& str) {
   static const struct { const char before; const char after; } match[] =
       {{'/','-'}, {';','#'}, {' ','#'}, {'$','+'},
        {'(','@'}, {')','@'}, {'<','='}, {'>','='}};
@@ -1034,8 +1018,7 @@
   }
 }
 
-std::string MIRGraph::GetSSAName(int ssa_reg)
-{
+std::string MIRGraph::GetSSAName(int ssa_reg) {
   // TODO: This value is needed for LLVM and debugging. Currently, we compute this and then copy to
   //       the arena. We should be smarter and just place straight into the arena, or compute the
   //       value more lazily.
@@ -1043,8 +1026,7 @@
 }
 
 // Similar to GetSSAName, but if ssa name represents an immediate show that as well.
-std::string MIRGraph::GetSSANameWithConst(int ssa_reg, bool singles_only)
-{
+std::string MIRGraph::GetSSANameWithConst(int ssa_reg, bool singles_only) {
   if (reg_location_ == NULL) {
     // Pre-SSA - just use the standard name
     return GetSSAName(ssa_reg);
@@ -1062,8 +1044,7 @@
   }
 }
 
-void MIRGraph::GetBlockName(BasicBlock* bb, char* name)
-{
+void MIRGraph::GetBlockName(BasicBlock* bb, char* name) {
   switch (bb->block_type) {
     case kEntryBlock:
       snprintf(name, BLOCK_NAME_LEN, "entry_%d", bb->id);
@@ -1084,16 +1065,14 @@
   }
 }
 
-const char* MIRGraph::GetShortyFromTargetIdx(int target_idx)
-{
+const char* MIRGraph::GetShortyFromTargetIdx(int target_idx) {
   // FIXME: use current code unit for inline support.
   const DexFile::MethodId& method_id = cu_->dex_file->GetMethodId(target_idx);
   return cu_->dex_file->GetShorty(method_id.proto_idx_);
 }
 
 /* Debug Utility - dump a compilation unit */
-void MIRGraph::DumpMIRGraph()
-{
+void MIRGraph::DumpMIRGraph() {
   BasicBlock* bb;
   const char* block_type_names[] = {
     "Entry Block",
@@ -1135,8 +1114,7 @@
  * MOVE_RESULT and incorporate it into the invoke.
  */
 CallInfo* MIRGraph::NewMemCallInfo(BasicBlock* bb, MIR* mir, InvokeType type,
-                                  bool is_range)
-{
+                                  bool is_range) {
   CallInfo* info = static_cast<CallInfo*>(arena_->NewMem(sizeof(CallInfo), true,
                                                          ArenaAllocator::kAllocMisc));
   MIR* move_result_mir = FindMoveResult(bb, mir);
@@ -1163,8 +1141,7 @@
 }
 
 // Allocate a new basic block.
-BasicBlock* MIRGraph::NewMemBB(BBType block_type, int block_id)
-{
+BasicBlock* MIRGraph::NewMemBB(BBType block_type, int block_id) {
   BasicBlock* bb = static_cast<BasicBlock*>(arena_->NewMem(sizeof(BasicBlock), true,
                                                            ArenaAllocator::kAllocBB));
   bb->block_type = block_type;
diff --git a/compiler/dex/mir_graph.h b/compiler/dex/mir_graph.h
index a40fa97..f86e130 100644
--- a/compiler/dex/mir_graph.h
+++ b/compiler/dex/mir_graph.h
@@ -452,43 +452,37 @@
     return ssa_subscripts_->Get(ssa_reg);
   }
 
-  RegLocation GetRawSrc(MIR* mir, int num)
-  {
+  RegLocation GetRawSrc(MIR* mir, int num) {
     DCHECK(num < mir->ssa_rep->num_uses);
     RegLocation res = reg_location_[mir->ssa_rep->uses[num]];
     return res;
   }
 
-  RegLocation GetRawDest(MIR* mir)
-  {
+  RegLocation GetRawDest(MIR* mir) {
     DCHECK_GT(mir->ssa_rep->num_defs, 0);
     RegLocation res = reg_location_[mir->ssa_rep->defs[0]];
     return res;
   }
 
-  RegLocation GetDest(MIR* mir)
-  {
+  RegLocation GetDest(MIR* mir) {
     RegLocation res = GetRawDest(mir);
     DCHECK(!res.wide);
     return res;
   }
 
-  RegLocation GetSrc(MIR* mir, int num)
-  {
+  RegLocation GetSrc(MIR* mir, int num) {
     RegLocation res = GetRawSrc(mir, num);
     DCHECK(!res.wide);
     return res;
   }
 
-  RegLocation GetDestWide(MIR* mir)
-  {
+  RegLocation GetDestWide(MIR* mir) {
     RegLocation res = GetRawDest(mir);
     DCHECK(res.wide);
     return res;
   }
 
-  RegLocation GetSrcWide(MIR* mir, int low)
-  {
+  RegLocation GetSrcWide(MIR* mir, int low) {
     RegLocation res = GetRawSrc(mir, low);
     DCHECK(res.wide);
     return res;
diff --git a/compiler/dex/mir_optimization.cc b/compiler/dex/mir_optimization.cc
index 6b8f3f0..306dbc7 100644
--- a/compiler/dex/mir_optimization.cc
+++ b/compiler/dex/mir_optimization.cc
@@ -20,27 +20,23 @@
 
 namespace art {
 
-static unsigned int Predecessors(BasicBlock* bb)
-{
+static unsigned int Predecessors(BasicBlock* bb) {
   return bb->predecessors->Size();
 }
 
 /* Setup a constant value for opcodes thare have the DF_SETS_CONST attribute */
-void MIRGraph::SetConstant(int32_t ssa_reg, int value)
-{
+void MIRGraph::SetConstant(int32_t ssa_reg, int value) {
   is_constant_v_->SetBit(ssa_reg);
   constant_values_[ssa_reg] = value;
 }
 
-void MIRGraph::SetConstantWide(int ssa_reg, int64_t value)
-{
+void MIRGraph::SetConstantWide(int ssa_reg, int64_t value) {
   is_constant_v_->SetBit(ssa_reg);
   constant_values_[ssa_reg] = Low32Bits(value);
   constant_values_[ssa_reg + 1] = High32Bits(value);
 }
 
-void MIRGraph::DoConstantPropogation(BasicBlock* bb)
-{
+void MIRGraph::DoConstantPropogation(BasicBlock* bb) {
   MIR* mir;
 
   for (mir = bb->first_mir_insn; mir != NULL; mir = mir->next) {
@@ -96,8 +92,7 @@
   /* TODO: implement code to handle arithmetic operations */
 }
 
-void MIRGraph::PropagateConstants()
-{
+void MIRGraph::PropagateConstants() {
   is_constant_v_ = new (arena_) ArenaBitVector(arena_, GetNumSSARegs(), false);
   constant_values_ = static_cast<int*>(arena_->NewMem(sizeof(int) * GetNumSSARegs(), true,
                                                       ArenaAllocator::kAllocDFInfo));
@@ -108,8 +103,7 @@
 }
 
 /* Advance to next strictly dominated MIR node in an extended basic block */
-static MIR* AdvanceMIR(BasicBlock** p_bb, MIR* mir)
-{
+static MIR* AdvanceMIR(BasicBlock** p_bb, MIR* mir) {
   BasicBlock* bb = *p_bb;
   if (mir != NULL) {
     mir = mir->next;
@@ -133,8 +127,7 @@
  * opcodes or incoming arcs.  However, if the result of the invoke is not
  * used, a move-result may not be present.
  */
-MIR* MIRGraph::FindMoveResult(BasicBlock* bb, MIR* mir)
-{
+MIR* MIRGraph::FindMoveResult(BasicBlock* bb, MIR* mir) {
   BasicBlock* tbb = bb;
   mir = AdvanceMIR(&tbb, mir);
   while (mir != NULL) {
@@ -154,8 +147,7 @@
   return mir;
 }
 
-static BasicBlock* NextDominatedBlock(BasicBlock* bb)
-{
+static BasicBlock* NextDominatedBlock(BasicBlock* bb) {
   if (bb->block_type == kDead) {
     return NULL;
   }
@@ -169,8 +161,7 @@
   return bb;
 }
 
-static MIR* FindPhi(BasicBlock* bb, int ssa_name)
-{
+static MIR* FindPhi(BasicBlock* bb, int ssa_name) {
   for (MIR* mir = bb->first_mir_insn; mir != NULL; mir = mir->next) {
     if (static_cast<int>(mir->dalvikInsn.opcode) == kMirOpPhi) {
       for (int i = 0; i < mir->ssa_rep->num_uses; i++) {
@@ -183,8 +174,7 @@
   return NULL;
 }
 
-static SelectInstructionKind SelectKind(MIR* mir)
-{
+static SelectInstructionKind SelectKind(MIR* mir) {
   switch (mir->dalvikInsn.opcode) {
     case Instruction::MOVE:
     case Instruction::MOVE_OBJECT:
@@ -206,15 +196,13 @@
   return kSelectNone;
 }
 
-int MIRGraph::GetSSAUseCount(int s_reg)
-{
+int MIRGraph::GetSSAUseCount(int s_reg) {
   return raw_use_counts_.Get(s_reg);
 }
 
 
 /* Do some MIR-level extended basic block optimizations */
-bool MIRGraph::BasicBlockOpt(BasicBlock* bb)
-{
+bool MIRGraph::BasicBlockOpt(BasicBlock* bb) {
   if (bb->block_type == kDead) {
     return true;
   }
@@ -474,8 +462,7 @@
   return true;
 }
 
-void MIRGraph::NullCheckEliminationInit(struct BasicBlock* bb)
-{
+void MIRGraph::NullCheckEliminationInit(struct BasicBlock* bb) {
   if (bb->data_flow_info != NULL) {
     bb->data_flow_info->ending_null_check_v =
         new (arena_) ArenaBitVector(arena_, GetNumSSARegs(), false, kBitMapNullCheck);
@@ -483,8 +470,7 @@
 }
 
 /* Collect stats on number of checks removed */
-void MIRGraph::CountChecks(struct BasicBlock* bb)
-{
+void MIRGraph::CountChecks(struct BasicBlock* bb) {
   if (bb->data_flow_info != NULL) {
     for (MIR* mir = bb->first_mir_insn; mir != NULL; mir = mir->next) {
       if (mir->ssa_rep == NULL) {
@@ -508,8 +494,7 @@
 }
 
 /* Try to make common case the fallthrough path */
-static bool LayoutBlocks(struct BasicBlock* bb)
-{
+static bool LayoutBlocks(struct BasicBlock* bb) {
   // TODO: For now, just looking for direct throws.  Consider generalizing for profile feedback
   if (!bb->explicit_throw) {
     return false;
@@ -556,8 +541,7 @@
 }
 
 /* Combine any basic blocks terminated by instructions that we now know can't throw */
-bool MIRGraph::CombineBlocks(struct BasicBlock* bb)
-{
+bool MIRGraph::CombineBlocks(struct BasicBlock* bb) {
   // Loop here to allow combining a sequence of blocks
   while (true) {
     // Check termination conditions
@@ -625,8 +609,7 @@
 }
 
 /* Eliminate unnecessary null checks for a basic block. */
-bool MIRGraph::EliminateNullChecks(struct BasicBlock* bb)
-{
+bool MIRGraph::EliminateNullChecks(struct BasicBlock* bb) {
   if (bb->data_flow_info == NULL) return false;
 
   /*
@@ -770,8 +753,7 @@
   return changed;
 }
 
-void MIRGraph::NullCheckElimination()
-{
+void MIRGraph::NullCheckElimination() {
   if (!(cu_->disable_opt & (1 << kNullCheckElimination))) {
     DCHECK(temp_ssa_register_v_ != NULL);
     AllNodesIterator iter(this, false /* not iterative */);
@@ -789,8 +771,7 @@
   }
 }
 
-void MIRGraph::BasicBlockCombine()
-{
+void MIRGraph::BasicBlockCombine() {
   PreOrderDfsIterator iter(this, false /* not iterative */);
   for (BasicBlock* bb = iter.Next(); bb != NULL; bb = iter.Next()) {
     CombineBlocks(bb);
@@ -800,8 +781,7 @@
   }
 }
 
-void MIRGraph::CodeLayout()
-{
+void MIRGraph::CodeLayout() {
   if (cu_->enable_debug & (1 << kDebugVerifyDataflow)) {
     VerifyDataflow();
   }
@@ -814,8 +794,7 @@
   }
 }
 
-void MIRGraph::DumpCheckStats()
-{
+void MIRGraph::DumpCheckStats() {
   Checkstats* stats =
       static_cast<Checkstats*>(arena_->NewMem(sizeof(Checkstats), true,
                                               ArenaAllocator::kAllocDFInfo));
@@ -840,8 +819,7 @@
   }
 }
 
-bool MIRGraph::BuildExtendedBBList(struct BasicBlock* bb)
-{
+bool MIRGraph::BuildExtendedBBList(struct BasicBlock* bb) {
   if (bb->visited) return false;
   if (!((bb->block_type == kEntryBlock) || (bb->block_type == kDalvikByteCode)
       || (bb->block_type == kExitBlock))) {
@@ -871,8 +849,7 @@
 }
 
 
-void MIRGraph::BasicBlockOptimization()
-{
+void MIRGraph::BasicBlockOptimization() {
   if (!(cu_->disable_opt & (1 << kBBOpt))) {
     DCHECK_EQ(cu_->num_compiler_temps, 0);
     ClearAllVisitedFlags();
diff --git a/compiler/dex/portable/mir_to_gbc.cc b/compiler/dex/portable/mir_to_gbc.cc
index 2be1ef4..4317d1e 100644
--- a/compiler/dex/portable/mir_to_gbc.cc
+++ b/compiler/dex/portable/mir_to_gbc.cc
@@ -42,18 +42,15 @@
 
 namespace art {
 
-::llvm::BasicBlock* MirConverter::GetLLVMBlock(int id)
-{
+::llvm::BasicBlock* MirConverter::GetLLVMBlock(int id) {
   return id_to_block_map_.Get(id);
 }
 
-::llvm::Value* MirConverter::GetLLVMValue(int s_reg)
-{
+::llvm::Value* MirConverter::GetLLVMValue(int s_reg) {
   return llvm_values_.Get(s_reg);
 }
 
-void MirConverter::SetVregOnValue(::llvm::Value* val, int s_reg)
-{
+void MirConverter::SetVregOnValue(::llvm::Value* val, int s_reg) {
   // Set vreg for debugging
   art::llvm::IntrinsicHelper::IntrinsicId id = art::llvm::IntrinsicHelper::SetVReg;
   ::llvm::Function* func = intrinsic_helper_->GetIntrinsicFunction(id);
@@ -64,8 +61,7 @@
 }
 
 // Replace the placeholder value with the real definition
-void MirConverter::DefineValueOnly(::llvm::Value* val, int s_reg)
-{
+void MirConverter::DefineValueOnly(::llvm::Value* val, int s_reg) {
   ::llvm::Value* placeholder = GetLLVMValue(s_reg);
   if (placeholder == NULL) {
     // This can happen on instruction rewrite on verification failure
@@ -81,14 +77,12 @@
 
 }
 
-void MirConverter::DefineValue(::llvm::Value* val, int s_reg)
-{
+void MirConverter::DefineValue(::llvm::Value* val, int s_reg) {
   DefineValueOnly(val, s_reg);
   SetVregOnValue(val, s_reg);
 }
 
-::llvm::Type* MirConverter::LlvmTypeFromLocRec(RegLocation loc)
-{
+::llvm::Type* MirConverter::LlvmTypeFromLocRec(RegLocation loc) {
   ::llvm::Type* res = NULL;
   if (loc.wide) {
     if (loc.fp)
@@ -108,8 +102,7 @@
   return res;
 }
 
-void MirConverter::InitIR()
-{
+void MirConverter::InitIR() {
   if (llvm_info_ == NULL) {
     CompilerTls* tls = cu_->compiler_driver->GetTls();
     CHECK(tls != NULL);
@@ -125,16 +118,14 @@
   irb_ = llvm_info_->GetIRBuilder();
 }
 
-::llvm::BasicBlock* MirConverter::FindCaseTarget(uint32_t vaddr)
-{
+::llvm::BasicBlock* MirConverter::FindCaseTarget(uint32_t vaddr) {
   BasicBlock* bb = mir_graph_->FindBlock(vaddr);
   DCHECK(bb != NULL);
   return GetLLVMBlock(bb->id);
 }
 
 void MirConverter::ConvertPackedSwitch(BasicBlock* bb,
-                                int32_t table_offset, RegLocation rl_src)
-{
+                                int32_t table_offset, RegLocation rl_src) {
   const Instruction::PackedSwitchPayload* payload =
       reinterpret_cast<const Instruction::PackedSwitchPayload*>(
       cu_->insns + current_dalvik_offset_ + table_offset);
@@ -158,8 +149,7 @@
 }
 
 void MirConverter::ConvertSparseSwitch(BasicBlock* bb,
-                                int32_t table_offset, RegLocation rl_src)
-{
+                                int32_t table_offset, RegLocation rl_src) {
   const Instruction::SparseSwitchPayload* payload =
       reinterpret_cast<const Instruction::SparseSwitchPayload*>(
       cu_->insns + current_dalvik_offset_ + table_offset);
@@ -186,8 +176,7 @@
 }
 
 void MirConverter::ConvertSget(int32_t field_index,
-                        art::llvm::IntrinsicHelper::IntrinsicId id, RegLocation rl_dest)
-{
+                        art::llvm::IntrinsicHelper::IntrinsicId id, RegLocation rl_dest) {
   ::llvm::Constant* field_idx = irb_->getInt32(field_index);
   ::llvm::Function* intr = intrinsic_helper_->GetIntrinsicFunction(id);
   ::llvm::Value* res = irb_->CreateCall(intr, field_idx);
@@ -195,8 +184,7 @@
 }
 
 void MirConverter::ConvertSput(int32_t field_index,
-                        art::llvm::IntrinsicHelper::IntrinsicId id, RegLocation rl_src)
-{
+                        art::llvm::IntrinsicHelper::IntrinsicId id, RegLocation rl_src) {
   ::llvm::SmallVector< ::llvm::Value*, 2> args;
   args.push_back(irb_->getInt32(field_index));
   args.push_back(GetLLVMValue(rl_src.orig_sreg));
@@ -204,8 +192,7 @@
   irb_->CreateCall(intr, args);
 }
 
-void MirConverter::ConvertFillArrayData(int32_t offset, RegLocation rl_array)
-{
+void MirConverter::ConvertFillArrayData(int32_t offset, RegLocation rl_array) {
   art::llvm::IntrinsicHelper::IntrinsicId id;
   id = art::llvm::IntrinsicHelper::HLFillArrayData;
   ::llvm::SmallVector< ::llvm::Value*, 2> args;
@@ -216,8 +203,7 @@
 }
 
 ::llvm::Value* MirConverter::EmitConst(::llvm::ArrayRef< ::llvm::Value*> src,
-                              RegLocation loc)
-{
+                              RegLocation loc) {
   art::llvm::IntrinsicHelper::IntrinsicId id;
   if (loc.wide) {
     if (loc.fp) {
@@ -238,16 +224,14 @@
   return irb_->CreateCall(intr, src);
 }
 
-void MirConverter::EmitPopShadowFrame()
-{
+void MirConverter::EmitPopShadowFrame() {
   ::llvm::Function* intr = intrinsic_helper_->GetIntrinsicFunction(
       art::llvm::IntrinsicHelper::PopShadowFrame);
   irb_->CreateCall(intr);
 }
 
 ::llvm::Value* MirConverter::EmitCopy(::llvm::ArrayRef< ::llvm::Value*> src,
-                             RegLocation loc)
-{
+                             RegLocation loc) {
   art::llvm::IntrinsicHelper::IntrinsicId id;
   if (loc.wide) {
     if (loc.fp) {
@@ -268,16 +252,14 @@
   return irb_->CreateCall(intr, src);
 }
 
-void MirConverter::ConvertMoveException(RegLocation rl_dest)
-{
+void MirConverter::ConvertMoveException(RegLocation rl_dest) {
   ::llvm::Function* func = intrinsic_helper_->GetIntrinsicFunction(
       art::llvm::IntrinsicHelper::GetException);
   ::llvm::Value* res = irb_->CreateCall(func);
   DefineValue(res, rl_dest.orig_sreg);
 }
 
-void MirConverter::ConvertThrow(RegLocation rl_src)
-{
+void MirConverter::ConvertThrow(RegLocation rl_src) {
   ::llvm::Value* src = GetLLVMValue(rl_src.orig_sreg);
   ::llvm::Function* func = intrinsic_helper_->GetIntrinsicFunction(
       art::llvm::IntrinsicHelper::HLThrowException);
@@ -286,8 +268,7 @@
 
 void MirConverter::ConvertMonitorEnterExit(int opt_flags,
                                     art::llvm::IntrinsicHelper::IntrinsicId id,
-                                    RegLocation rl_src)
-{
+                                    RegLocation rl_src) {
   ::llvm::SmallVector< ::llvm::Value*, 2> args;
   args.push_back(irb_->getInt32(opt_flags));
   args.push_back(GetLLVMValue(rl_src.orig_sreg));
@@ -296,8 +277,7 @@
 }
 
 void MirConverter::ConvertArrayLength(int opt_flags,
-                               RegLocation rl_dest, RegLocation rl_src)
-{
+                               RegLocation rl_dest, RegLocation rl_src) {
   ::llvm::SmallVector< ::llvm::Value*, 2> args;
   args.push_back(irb_->getInt32(opt_flags));
   args.push_back(GetLLVMValue(rl_src.orig_sreg));
@@ -307,8 +287,7 @@
   DefineValue(res, rl_dest.orig_sreg);
 }
 
-void MirConverter::EmitSuspendCheck()
-{
+void MirConverter::EmitSuspendCheck() {
   art::llvm::IntrinsicHelper::IntrinsicId id =
       art::llvm::IntrinsicHelper::CheckSuspend;
   ::llvm::Function* intr = intrinsic_helper_->GetIntrinsicFunction(id);
@@ -316,8 +295,7 @@
 }
 
 ::llvm::Value* MirConverter::ConvertCompare(ConditionCode cc,
-                                   ::llvm::Value* src1, ::llvm::Value* src2)
-{
+                                   ::llvm::Value* src1, ::llvm::Value* src2) {
   ::llvm::Value* res = NULL;
   DCHECK_EQ(src1->getType(), src2->getType());
   switch(cc) {
@@ -333,8 +311,7 @@
 }
 
 void MirConverter::ConvertCompareAndBranch(BasicBlock* bb, MIR* mir,
-                                    ConditionCode cc, RegLocation rl_src1, RegLocation rl_src2)
-{
+                                    ConditionCode cc, RegLocation rl_src1, RegLocation rl_src2) {
   if (bb->taken->start_offset <= mir->offset) {
     EmitSuspendCheck();
   }
@@ -349,8 +326,7 @@
 }
 
 void MirConverter::ConvertCompareZeroAndBranch(BasicBlock* bb,
-                                        MIR* mir, ConditionCode cc, RegLocation rl_src1)
-{
+                                        MIR* mir, ConditionCode cc, RegLocation rl_src1) {
   if (bb->taken->start_offset <= mir->offset) {
     EmitSuspendCheck();
   }
@@ -369,8 +345,7 @@
 }
 
 ::llvm::Value* MirConverter::GenDivModOp(bool is_div, bool is_long,
-                                ::llvm::Value* src1, ::llvm::Value* src2)
-{
+                                ::llvm::Value* src1, ::llvm::Value* src2) {
   art::llvm::IntrinsicHelper::IntrinsicId id;
   if (is_long) {
     if (is_div) {
@@ -393,8 +368,7 @@
 }
 
 ::llvm::Value* MirConverter::GenArithOp(OpKind op, bool is_long,
-                               ::llvm::Value* src1, ::llvm::Value* src2)
-{
+                               ::llvm::Value* src1, ::llvm::Value* src2) {
   ::llvm::Value* res = NULL;
   switch(op) {
     case kOpAdd: res = irb_->CreateAdd(src1, src2); break;
@@ -416,8 +390,7 @@
 }
 
 void MirConverter::ConvertFPArithOp(OpKind op, RegLocation rl_dest,
-                             RegLocation rl_src1, RegLocation rl_src2)
-{
+                             RegLocation rl_src1, RegLocation rl_src2) {
   ::llvm::Value* src1 = GetLLVMValue(rl_src1.orig_sreg);
   ::llvm::Value* src2 = GetLLVMValue(rl_src2.orig_sreg);
   ::llvm::Value* res = NULL;
@@ -434,8 +407,7 @@
 }
 
 void MirConverter::ConvertShift(art::llvm::IntrinsicHelper::IntrinsicId id,
-                         RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
-{
+                         RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
   ::llvm::Function* intr = intrinsic_helper_->GetIntrinsicFunction(id);
   ::llvm::SmallVector< ::llvm::Value*, 2>args;
   args.push_back(GetLLVMValue(rl_src1.orig_sreg));
@@ -445,8 +417,7 @@
 }
 
 void MirConverter::ConvertShiftLit(art::llvm::IntrinsicHelper::IntrinsicId id,
-                            RegLocation rl_dest, RegLocation rl_src, int shift_amount)
-{
+                            RegLocation rl_dest, RegLocation rl_src, int shift_amount) {
   ::llvm::Function* intr = intrinsic_helper_->GetIntrinsicFunction(id);
   ::llvm::SmallVector< ::llvm::Value*, 2>args;
   args.push_back(GetLLVMValue(rl_src.orig_sreg));
@@ -456,8 +427,7 @@
 }
 
 void MirConverter::ConvertArithOp(OpKind op, RegLocation rl_dest,
-                           RegLocation rl_src1, RegLocation rl_src2)
-{
+                           RegLocation rl_src1, RegLocation rl_src2) {
   ::llvm::Value* src1 = GetLLVMValue(rl_src1.orig_sreg);
   ::llvm::Value* src2 = GetLLVMValue(rl_src2.orig_sreg);
   DCHECK_EQ(src1->getType(), src2->getType());
@@ -466,8 +436,7 @@
 }
 
 void MirConverter::ConvertArithOpLit(OpKind op, RegLocation rl_dest,
-                              RegLocation rl_src1, int32_t imm)
-{
+                              RegLocation rl_src1, int32_t imm) {
   ::llvm::Value* src1 = GetLLVMValue(rl_src1.orig_sreg);
   ::llvm::Value* src2 = irb_->getInt32(imm);
   ::llvm::Value* res = GenArithOp(op, rl_dest.wide, src1, src2);
@@ -480,8 +449,7 @@
  * The requirements are similar.
  */
 void MirConverter::ConvertInvoke(BasicBlock* bb, MIR* mir,
-                          InvokeType invoke_type, bool is_range, bool is_filled_new_array)
-{
+                          InvokeType invoke_type, bool is_range, bool is_filled_new_array) {
   CallInfo* info = mir_graph_->NewMemCallInfo(bb, mir, invoke_type, is_range);
   ::llvm::SmallVector< ::llvm::Value*, 10> args;
   // Insert the invoke_type
@@ -529,16 +497,14 @@
 }
 
 void MirConverter::ConvertConstObject(uint32_t idx,
-                               art::llvm::IntrinsicHelper::IntrinsicId id, RegLocation rl_dest)
-{
+                               art::llvm::IntrinsicHelper::IntrinsicId id, RegLocation rl_dest) {
   ::llvm::Function* intr = intrinsic_helper_->GetIntrinsicFunction(id);
   ::llvm::Value* index = irb_->getInt32(idx);
   ::llvm::Value* res = irb_->CreateCall(intr, index);
   DefineValue(res, rl_dest.orig_sreg);
 }
 
-void MirConverter::ConvertCheckCast(uint32_t type_idx, RegLocation rl_src)
-{
+void MirConverter::ConvertCheckCast(uint32_t type_idx, RegLocation rl_src) {
   art::llvm::IntrinsicHelper::IntrinsicId id;
   id = art::llvm::IntrinsicHelper::HLCheckCast;
   ::llvm::Function* intr = intrinsic_helper_->GetIntrinsicFunction(id);
@@ -548,8 +514,7 @@
   irb_->CreateCall(intr, args);
 }
 
-void MirConverter::ConvertNewInstance(uint32_t type_idx, RegLocation rl_dest)
-{
+void MirConverter::ConvertNewInstance(uint32_t type_idx, RegLocation rl_dest) {
   art::llvm::IntrinsicHelper::IntrinsicId id;
   id = art::llvm::IntrinsicHelper::NewInstance;
   ::llvm::Function* intr = intrinsic_helper_->GetIntrinsicFunction(id);
@@ -559,8 +524,7 @@
 }
 
 void MirConverter::ConvertNewArray(uint32_t type_idx,
-                            RegLocation rl_dest, RegLocation rl_src)
-{
+                            RegLocation rl_dest, RegLocation rl_src) {
   art::llvm::IntrinsicHelper::IntrinsicId id;
   id = art::llvm::IntrinsicHelper::NewArray;
   ::llvm::Function* intr = intrinsic_helper_->GetIntrinsicFunction(id);
@@ -573,8 +537,7 @@
 
 void MirConverter::ConvertAget(int opt_flags,
                         art::llvm::IntrinsicHelper::IntrinsicId id,
-                        RegLocation rl_dest, RegLocation rl_array, RegLocation rl_index)
-{
+                        RegLocation rl_dest, RegLocation rl_array, RegLocation rl_index) {
   ::llvm::SmallVector< ::llvm::Value*, 3> args;
   args.push_back(irb_->getInt32(opt_flags));
   args.push_back(GetLLVMValue(rl_array.orig_sreg));
@@ -586,8 +549,7 @@
 
 void MirConverter::ConvertAput(int opt_flags,
                         art::llvm::IntrinsicHelper::IntrinsicId id,
-                        RegLocation rl_src, RegLocation rl_array, RegLocation rl_index)
-{
+                        RegLocation rl_src, RegLocation rl_array, RegLocation rl_index) {
   ::llvm::SmallVector< ::llvm::Value*, 4> args;
   args.push_back(irb_->getInt32(opt_flags));
   args.push_back(GetLLVMValue(rl_src.orig_sreg));
@@ -599,8 +561,7 @@
 
 void MirConverter::ConvertIget(int opt_flags,
                         art::llvm::IntrinsicHelper::IntrinsicId id,
-                        RegLocation rl_dest, RegLocation rl_obj, int field_index)
-{
+                        RegLocation rl_dest, RegLocation rl_obj, int field_index) {
   ::llvm::SmallVector< ::llvm::Value*, 3> args;
   args.push_back(irb_->getInt32(opt_flags));
   args.push_back(GetLLVMValue(rl_obj.orig_sreg));
@@ -612,8 +573,7 @@
 
 void MirConverter::ConvertIput(int opt_flags,
                         art::llvm::IntrinsicHelper::IntrinsicId id,
-                        RegLocation rl_src, RegLocation rl_obj, int field_index)
-{
+                        RegLocation rl_src, RegLocation rl_obj, int field_index) {
   ::llvm::SmallVector< ::llvm::Value*, 4> args;
   args.push_back(irb_->getInt32(opt_flags));
   args.push_back(GetLLVMValue(rl_src.orig_sreg));
@@ -624,8 +584,7 @@
 }
 
 void MirConverter::ConvertInstanceOf(uint32_t type_idx,
-                              RegLocation rl_dest, RegLocation rl_src)
-{
+                              RegLocation rl_dest, RegLocation rl_src) {
   art::llvm::IntrinsicHelper::IntrinsicId id;
   id = art::llvm::IntrinsicHelper::InstanceOf;
   ::llvm::Function* intr = intrinsic_helper_->GetIntrinsicFunction(id);
@@ -636,29 +595,25 @@
   DefineValue(res, rl_dest.orig_sreg);
 }
 
-void MirConverter::ConvertIntToLong(RegLocation rl_dest, RegLocation rl_src)
-{
+void MirConverter::ConvertIntToLong(RegLocation rl_dest, RegLocation rl_src) {
   ::llvm::Value* res = irb_->CreateSExt(GetLLVMValue(rl_src.orig_sreg),
                                             irb_->getInt64Ty());
   DefineValue(res, rl_dest.orig_sreg);
 }
 
-void MirConverter::ConvertLongToInt(RegLocation rl_dest, RegLocation rl_src)
-{
+void MirConverter::ConvertLongToInt(RegLocation rl_dest, RegLocation rl_src) {
   ::llvm::Value* src = GetLLVMValue(rl_src.orig_sreg);
   ::llvm::Value* res = irb_->CreateTrunc(src, irb_->getInt32Ty());
   DefineValue(res, rl_dest.orig_sreg);
 }
 
-void MirConverter::ConvertFloatToDouble(RegLocation rl_dest, RegLocation rl_src)
-{
+void MirConverter::ConvertFloatToDouble(RegLocation rl_dest, RegLocation rl_src) {
   ::llvm::Value* src = GetLLVMValue(rl_src.orig_sreg);
   ::llvm::Value* res = irb_->CreateFPExt(src, irb_->getDoubleTy());
   DefineValue(res, rl_dest.orig_sreg);
 }
 
-void MirConverter::ConvertDoubleToFloat(RegLocation rl_dest, RegLocation rl_src)
-{
+void MirConverter::ConvertDoubleToFloat(RegLocation rl_dest, RegLocation rl_src) {
   ::llvm::Value* src = GetLLVMValue(rl_src.orig_sreg);
   ::llvm::Value* res = irb_->CreateFPTrunc(src, irb_->getFloatTy());
   DefineValue(res, rl_dest.orig_sreg);
@@ -666,8 +621,7 @@
 
 void MirConverter::ConvertWideComparison(art::llvm::IntrinsicHelper::IntrinsicId id,
                                          RegLocation rl_dest, RegLocation rl_src1,
-                                         RegLocation rl_src2)
-{
+                                         RegLocation rl_src2) {
   DCHECK_EQ(rl_src1.fp, rl_src2.fp);
   DCHECK_EQ(rl_src1.wide, rl_src2.wide);
   ::llvm::Function* intr = intrinsic_helper_->GetIntrinsicFunction(id);
@@ -679,23 +633,20 @@
 }
 
 void MirConverter::ConvertIntNarrowing(RegLocation rl_dest, RegLocation rl_src,
-                                art::llvm::IntrinsicHelper::IntrinsicId id)
-{
+                                art::llvm::IntrinsicHelper::IntrinsicId id) {
   ::llvm::Function* intr = intrinsic_helper_->GetIntrinsicFunction(id);
   ::llvm::Value* res =
       irb_->CreateCall(intr, GetLLVMValue(rl_src.orig_sreg));
   DefineValue(res, rl_dest.orig_sreg);
 }
 
-void MirConverter::ConvertNeg(RegLocation rl_dest, RegLocation rl_src)
-{
+void MirConverter::ConvertNeg(RegLocation rl_dest, RegLocation rl_src) {
   ::llvm::Value* res = irb_->CreateNeg(GetLLVMValue(rl_src.orig_sreg));
   DefineValue(res, rl_dest.orig_sreg);
 }
 
 void MirConverter::ConvertIntToFP(::llvm::Type* ty, RegLocation rl_dest,
-                           RegLocation rl_src)
-{
+                           RegLocation rl_src) {
   ::llvm::Value* res =
       irb_->CreateSIToFP(GetLLVMValue(rl_src.orig_sreg), ty);
   DefineValue(res, rl_dest.orig_sreg);
@@ -703,23 +654,20 @@
 
 void MirConverter::ConvertFPToInt(art::llvm::IntrinsicHelper::IntrinsicId id,
                            RegLocation rl_dest,
-                    RegLocation rl_src)
-{
+                    RegLocation rl_src) {
   ::llvm::Function* intr = intrinsic_helper_->GetIntrinsicFunction(id);
   ::llvm::Value* res = irb_->CreateCall(intr, GetLLVMValue(rl_src.orig_sreg));
   DefineValue(res, rl_dest.orig_sreg);
 }
 
 
-void MirConverter::ConvertNegFP(RegLocation rl_dest, RegLocation rl_src)
-{
+void MirConverter::ConvertNegFP(RegLocation rl_dest, RegLocation rl_src) {
   ::llvm::Value* res =
       irb_->CreateFNeg(GetLLVMValue(rl_src.orig_sreg));
   DefineValue(res, rl_dest.orig_sreg);
 }
 
-void MirConverter::ConvertNot(RegLocation rl_dest, RegLocation rl_src)
-{
+void MirConverter::ConvertNot(RegLocation rl_dest, RegLocation rl_src) {
   ::llvm::Value* src = GetLLVMValue(rl_src.orig_sreg);
   ::llvm::Value* res = irb_->CreateXor(src, static_cast<uint64_t>(-1));
   DefineValue(res, rl_dest.orig_sreg);
@@ -737,8 +685,7 @@
  * when necessary.
  */
 bool MirConverter::ConvertMIRNode(MIR* mir, BasicBlock* bb,
-                           ::llvm::BasicBlock* llvm_bb)
-{
+                           ::llvm::BasicBlock* llvm_bb) {
   bool res = false;   // Assume success
   RegLocation rl_src[3];
   RegLocation rl_dest = mir_graph_->GetBadLoc();
@@ -1556,8 +1503,7 @@
   return res;
 }
 
-void MirConverter::SetDexOffset(int32_t offset)
-{
+void MirConverter::SetDexOffset(int32_t offset) {
   current_dalvik_offset_ = offset;
   ::llvm::SmallVector< ::llvm::Value*, 1> array_ref;
   array_ref.push_back(irb_->getInt32(offset));
@@ -1566,8 +1512,7 @@
 }
 
 // Attach method info as metadata to special intrinsic
-void MirConverter::SetMethodInfo()
-{
+void MirConverter::SetMethodInfo() {
   // We don't want dex offset on this
   irb_->SetDexOffset(NULL);
   art::llvm::IntrinsicHelper::IntrinsicId id;
@@ -1585,8 +1530,7 @@
   SetDexOffset(current_dalvik_offset_);
 }
 
-void MirConverter::HandlePhiNodes(BasicBlock* bb, ::llvm::BasicBlock* llvm_bb)
-{
+void MirConverter::HandlePhiNodes(BasicBlock* bb, ::llvm::BasicBlock* llvm_bb) {
   SetDexOffset(bb->start_offset);
   for (MIR* mir = bb->first_mir_insn; mir != NULL; mir = mir->next) {
     int opcode = mir->dalvikInsn.opcode;
@@ -1636,8 +1580,7 @@
 
 /* Extended MIR instructions like PHI */
 void MirConverter::ConvertExtendedMIR(BasicBlock* bb, MIR* mir,
-                               ::llvm::BasicBlock* llvm_bb)
-{
+                               ::llvm::BasicBlock* llvm_bb) {
 
   switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) {
     case kMirOpPhi: {
@@ -1684,8 +1627,7 @@
 }
 
 /* Handle the content in each basic block */
-bool MirConverter::BlockBitcodeConversion(BasicBlock* bb)
-{
+bool MirConverter::BlockBitcodeConversion(BasicBlock* bb) {
   if (bb->block_type == kDead) return false;
   ::llvm::BasicBlock* llvm_bb = GetLLVMBlock(bb->id);
   if (llvm_bb == NULL) {
@@ -1901,8 +1843,7 @@
   return true;
 }
 
-bool MirConverter::CreateLLVMBasicBlock(BasicBlock* bb)
-{
+bool MirConverter::CreateLLVMBasicBlock(BasicBlock* bb) {
   // Skip the exit block
   if ((bb->block_type == kDead) ||(bb->block_type == kExitBlock)) {
     id_to_block_map_.Put(bb->id, NULL);
@@ -1933,8 +1874,7 @@
  *  o Iterate through the MIR a basic block at a time, setting arguments
  *    to recovered ssa name.
  */
-void MirConverter::MethodMIR2Bitcode()
-{
+void MirConverter::MethodMIR2Bitcode() {
   InitIR();
 
   // Create the function
diff --git a/compiler/dex/quick/arm/assemble_arm.cc b/compiler/dex/quick/arm/assemble_arm.cc
index e804215..9e14457 100644
--- a/compiler/dex/quick/arm/assemble_arm.cc
+++ b/compiler/dex/quick/arm/assemble_arm.cc
@@ -1002,8 +1002,7 @@
  * discover that pc-relative displacements may not fit the selected
  * instruction.
  */
-AssemblerStatus ArmMir2Lir::AssembleInstructions(uintptr_t start_addr)
-{
+AssemblerStatus ArmMir2Lir::AssembleInstructions(uintptr_t start_addr) {
   LIR* lir;
   AssemblerStatus res = kSuccess;  // Assume success
 
@@ -1389,8 +1388,7 @@
   return res;
 }
 
-int ArmMir2Lir::GetInsnSize(LIR* lir)
-{
+int ArmMir2Lir::GetInsnSize(LIR* lir) {
   return EncodingMap[lir->opcode].size;
 }
 
diff --git a/compiler/dex/quick/arm/call_arm.cc b/compiler/dex/quick/arm/call_arm.cc
index a6720ce..0e81324 100644
--- a/compiler/dex/quick/arm/call_arm.cc
+++ b/compiler/dex/quick/arm/call_arm.cc
@@ -25,8 +25,7 @@
 
 
 /* Return the position of an ssa name within the argument list */
-int ArmMir2Lir::InPosition(int s_reg)
-{
+int ArmMir2Lir::InPosition(int s_reg) {
   int v_reg = mir_graph_->SRegToVReg(s_reg);
   return v_reg - cu_->num_regs;
 }
@@ -36,8 +35,7 @@
  * there.  NOTE: all live arg registers must be locked prior to this call
  * to avoid having them allocated as a temp by downstream utilities.
  */
-RegLocation ArmMir2Lir::ArgLoc(RegLocation loc)
-{
+RegLocation ArmMir2Lir::ArgLoc(RegLocation loc) {
   int arg_num = InPosition(loc.s_reg_low);
   if (loc.wide) {
     if (arg_num == 2) {
@@ -66,8 +64,7 @@
  * the frame, we can't use the normal LoadValue() because it assumed
  * a proper frame - and we're frameless.
  */
-RegLocation ArmMir2Lir::LoadArg(RegLocation loc)
-{
+RegLocation ArmMir2Lir::LoadArg(RegLocation loc) {
   if (loc.location == kLocDalvikFrame) {
     int start = (InPosition(loc.s_reg_low) + 1) * sizeof(uint32_t);
     loc.low_reg = AllocTemp();
@@ -82,8 +79,7 @@
 }
 
 /* Lock any referenced arguments that arrive in registers */
-void ArmMir2Lir::LockLiveArgs(MIR* mir)
-{
+void ArmMir2Lir::LockLiveArgs(MIR* mir) {
   int first_in = cu_->num_regs;
   const int num_arg_regs = 3;  // TODO: generalize & move to RegUtil.cc
   for (int i = 0; i < mir->ssa_rep->num_uses; i++) {
@@ -97,8 +93,7 @@
 
 /* Find the next MIR, which may be in a following basic block */
 // TODO: should this be a utility in mir_graph?
-MIR* ArmMir2Lir::GetNextMir(BasicBlock** p_bb, MIR* mir)
-{
+MIR* ArmMir2Lir::GetNextMir(BasicBlock** p_bb, MIR* mir) {
   BasicBlock* bb = *p_bb;
   MIR* orig_mir = mir;
   while (bb != NULL) {
@@ -123,8 +118,7 @@
 
 /* Used for the "verbose" listing */
 //TODO:  move to common code
-void ArmMir2Lir::GenPrintLabel(MIR* mir)
-{
+void ArmMir2Lir::GenPrintLabel(MIR* mir) {
   /* Mark the beginning of a Dalvik instruction for line tracking */
   char* inst_str = cu_->verbose ?
      mir_graph_->GetDalvikDisassembly(mir) : NULL;
@@ -132,8 +126,7 @@
 }
 
 MIR* ArmMir2Lir::SpecialIGet(BasicBlock** bb, MIR* mir,
-                             OpSize size, bool long_or_double, bool is_object)
-{
+                             OpSize size, bool long_or_double, bool is_object) {
   int field_offset;
   bool is_volatile;
   uint32_t field_idx = mir->dalvikInsn.vC;
@@ -158,8 +151,7 @@
 }
 
 MIR* ArmMir2Lir::SpecialIPut(BasicBlock** bb, MIR* mir,
-                             OpSize size, bool long_or_double, bool is_object)
-{
+                             OpSize size, bool long_or_double, bool is_object) {
   int field_offset;
   bool is_volatile;
   uint32_t field_idx = mir->dalvikInsn.vC;
@@ -192,8 +184,7 @@
   return GetNextMir(bb, mir);
 }
 
-MIR* ArmMir2Lir::SpecialIdentity(MIR* mir)
-{
+MIR* ArmMir2Lir::SpecialIdentity(MIR* mir) {
   RegLocation rl_src;
   RegLocation rl_dest;
   bool wide = (mir->ssa_rep->num_uses == 2);
@@ -225,8 +216,7 @@
  * Special-case code genration for simple non-throwing leaf methods.
  */
 void ArmMir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir,
-                                SpecialCaseHandler special_case)
-{
+                                SpecialCaseHandler special_case) {
    current_dalvik_offset_ = mir->offset;
    MIR* next_mir = NULL;
    switch (special_case) {
@@ -319,8 +309,7 @@
  *   cbnz  r_idx, lp
  */
 void ArmMir2Lir::GenSparseSwitch(MIR* mir, uint32_t table_offset,
-                                 RegLocation rl_src)
-{
+                                 RegLocation rl_src) {
   const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
   if (cu_->verbose) {
     DumpSparseSwitchTable(table);
@@ -369,8 +358,7 @@
 
 
 void ArmMir2Lir::GenPackedSwitch(MIR* mir, uint32_t table_offset,
-                                 RegLocation rl_src)
-{
+                                 RegLocation rl_src) {
   const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
   if (cu_->verbose) {
     DumpPackedSwitchTable(table);
@@ -427,8 +415,7 @@
  *
  * Total size is 4+(width * size + 1)/2 16-bit code units.
  */
-void ArmMir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src)
-{
+void ArmMir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src) {
   const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
   // Add the table to the list - we'll process it later
   FillArrayData *tab_rec =
@@ -480,8 +467,7 @@
  * preserved.
  *
  */
-void ArmMir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src)
-{
+void ArmMir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) {
   FlushAllRegs();
   DCHECK_EQ(LW_SHAPE_THIN, 0);
   LoadValueDirectFixed(rl_src, r0);  // Get obj
@@ -515,8 +501,7 @@
  * a zero recursion count, it's safe to punch it back to the
  * initial, unlock thin state with a store word.
  */
-void ArmMir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src)
-{
+void ArmMir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) {
   DCHECK_EQ(LW_SHAPE_THIN, 0);
   FlushAllRegs();
   LoadValueDirectFixed(rl_src, r0);  // Get obj
@@ -541,8 +526,7 @@
   GenMemBarrier(kStoreLoad);
 }
 
-void ArmMir2Lir::GenMoveException(RegLocation rl_dest)
-{
+void ArmMir2Lir::GenMoveException(RegLocation rl_dest) {
   int ex_offset = Thread::ExceptionOffset().Int32Value();
   RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
   int reset_reg = AllocTemp();
@@ -556,8 +540,7 @@
 /*
  * Mark garbage collection card. Skip if the value we're storing is null.
  */
-void ArmMir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg)
-{
+void ArmMir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg) {
   int reg_card_base = AllocTemp();
   int reg_card_no = AllocTemp();
   LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL);
@@ -571,8 +554,7 @@
   FreeTemp(reg_card_no);
 }
 
-void ArmMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method)
-{
+void ArmMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) {
   int spill_count = num_core_spills_ + num_fp_spills_;
   /*
    * On entry, r0, r1, r2 & r3 are live.  Let the register allocation
@@ -624,8 +606,7 @@
   FreeTemp(r3);
 }
 
-void ArmMir2Lir::GenExitSequence()
-{
+void ArmMir2Lir::GenExitSequence() {
   int spill_count = num_core_spills_ + num_fp_spills_;
   /*
    * In the exit path, r0/r1 are live - make sure they aren't
diff --git a/compiler/dex/quick/arm/fp_arm.cc b/compiler/dex/quick/arm/fp_arm.cc
index 53a5e1a..2c626a0 100644
--- a/compiler/dex/quick/arm/fp_arm.cc
+++ b/compiler/dex/quick/arm/fp_arm.cc
@@ -21,8 +21,7 @@
 namespace art {
 
 void ArmMir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
-                                 RegLocation rl_src1, RegLocation rl_src2)
-{
+                                 RegLocation rl_src1, RegLocation rl_src2) {
   int op = kThumbBkpt;
   RegLocation rl_result;
 
@@ -68,8 +67,7 @@
 }
 
 void ArmMir2Lir::GenArithOpDouble(Instruction::Code opcode,
-                                  RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
-{
+                                  RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
   int op = kThumbBkpt;
   RegLocation rl_result;
 
@@ -117,8 +115,7 @@
 }
 
 void ArmMir2Lir::GenConversion(Instruction::Code opcode,
-                               RegLocation rl_dest, RegLocation rl_src)
-{
+                               RegLocation rl_dest, RegLocation rl_src) {
   int op = kThumbBkpt;
   int src_reg;
   RegLocation rl_result;
@@ -176,8 +173,7 @@
 }
 
 void ArmMir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias,
-                                     bool is_double)
-{
+                                     bool is_double) {
   LIR* target = &block_label_list_[bb->taken->id];
   RegLocation rl_src1;
   RegLocation rl_src2;
@@ -229,8 +225,7 @@
 
 
 void ArmMir2Lir::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest,
-                          RegLocation rl_src1, RegLocation rl_src2)
-{
+                          RegLocation rl_src1, RegLocation rl_src2) {
   bool is_double = false;
   int default_result = -1;
   RegLocation rl_result;
@@ -288,8 +283,7 @@
   StoreValue(rl_dest, rl_result);
 }
 
-void ArmMir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src)
-{
+void ArmMir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src) {
   RegLocation rl_result;
   rl_src = LoadValue(rl_src, kFPReg);
   rl_result = EvalLoc(rl_dest, kFPReg, true);
@@ -297,8 +291,7 @@
   StoreValue(rl_dest, rl_result);
 }
 
-void ArmMir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src)
-{
+void ArmMir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src) {
   RegLocation rl_result;
   rl_src = LoadValueWide(rl_src, kFPReg);
   rl_result = EvalLoc(rl_dest, kFPReg, true);
diff --git a/compiler/dex/quick/arm/int_arm.cc b/compiler/dex/quick/arm/int_arm.cc
index feea896..ee2d76c 100644
--- a/compiler/dex/quick/arm/int_arm.cc
+++ b/compiler/dex/quick/arm/int_arm.cc
@@ -25,8 +25,7 @@
 namespace art {
 
 LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, int src1,
-         int src2, LIR* target)
-{
+         int src2, LIR* target) {
   OpRegReg(kOpCmp, src1, src2);
   return OpCondBranch(cond, target);
 }
@@ -41,8 +40,7 @@
  * met, and an "E" means the instruction is executed if the condition
  * is not met.
  */
-LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide)
-{
+LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide) {
   int mask;
   int mask3 = 0;
   int mask2 = 0;
@@ -86,8 +84,7 @@
  * done:
  */
 void ArmMir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1,
-                            RegLocation rl_src2)
-{
+                            RegLocation rl_src2) {
   LIR* target1;
   LIR* target2;
   rl_src1 = LoadValueWide(rl_src1, kCoreReg);
@@ -121,8 +118,7 @@
 }
 
 void ArmMir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1,
-                                          int64_t val, ConditionCode ccode)
-{
+                                          int64_t val, ConditionCode ccode) {
   int32_t val_lo = Low32Bits(val);
   int32_t val_hi = High32Bits(val);
   DCHECK(ModifiedImmediate(val_lo) >= 0);
@@ -180,8 +176,7 @@
   OpCmpImmBranch(ccode, low_reg, val_lo, taken);
 }
 
-void ArmMir2Lir::GenSelect(BasicBlock* bb, MIR* mir)
-{
+void ArmMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) {
   RegLocation rl_result;
   RegLocation rl_src = mir_graph_->GetSrc(mir, 0);
   // Temporary debugging code
@@ -249,8 +244,7 @@
   StoreValue(rl_dest, rl_result);
 }
 
-void ArmMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir)
-{
+void ArmMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) {
   RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0);
   RegLocation rl_src2 = mir_graph_->GetSrcWide(mir, 2);
   // Normalize such that if either operand is constant, src2 will be constant.
@@ -315,8 +309,7 @@
  * is responsible for setting branch target field.
  */
 LIR* ArmMir2Lir::OpCmpImmBranch(ConditionCode cond, int reg, int check_value,
-                                LIR* target)
-{
+                                LIR* target) {
   LIR* branch;
   int mod_imm;
   ArmConditionCode arm_cond = ArmConditionEncoding(cond);
@@ -341,8 +334,7 @@
   return branch;
 }
 
-LIR* ArmMir2Lir::OpRegCopyNoInsert(int r_dest, int r_src)
-{
+LIR* ArmMir2Lir::OpRegCopyNoInsert(int r_dest, int r_src) {
   LIR* res;
   int opcode;
   if (ARM_FPREG(r_dest) || ARM_FPREG(r_src))
@@ -362,16 +354,14 @@
   return res;
 }
 
-LIR* ArmMir2Lir::OpRegCopy(int r_dest, int r_src)
-{
+LIR* ArmMir2Lir::OpRegCopy(int r_dest, int r_src) {
   LIR* res = OpRegCopyNoInsert(r_dest, r_src);
   AppendLIR(res);
   return res;
 }
 
 void ArmMir2Lir::OpRegCopyWide(int dest_lo, int dest_hi, int src_lo,
-                               int src_hi)
-{
+                               int src_hi) {
   bool dest_fp = ARM_FPREG(dest_lo) && ARM_FPREG(dest_hi);
   bool src_fp = ARM_FPREG(src_lo) && ARM_FPREG(src_hi);
   DCHECK_EQ(ARM_FPREG(src_lo), ARM_FPREG(src_hi));
@@ -426,8 +416,7 @@
 
 // Integer division by constant via reciprocal multiply (Hacker's Delight, 10-4)
 bool ArmMir2Lir::SmallLiteralDivide(Instruction::Code dalvik_opcode,
-                                    RegLocation rl_src, RegLocation rl_dest, int lit)
-{
+                                    RegLocation rl_src, RegLocation rl_dest, int lit) {
   if ((lit < 0) || (lit >= static_cast<int>(sizeof(magic_table)/sizeof(magic_table[0])))) {
     return false;
   }
@@ -471,28 +460,24 @@
 }
 
 LIR* ArmMir2Lir::GenRegMemCheck(ConditionCode c_code,
-                    int reg1, int base, int offset, ThrowKind kind)
-{
+                    int reg1, int base, int offset, ThrowKind kind) {
   LOG(FATAL) << "Unexpected use of GenRegMemCheck for Arm";
   return NULL;
 }
 
 RegLocation ArmMir2Lir::GenDivRemLit(RegLocation rl_dest, int reg1, int lit,
-                                     bool is_div)
-{
+                                     bool is_div) {
   LOG(FATAL) << "Unexpected use of GenDivRemLit for Arm";
   return rl_dest;
 }
 
 RegLocation ArmMir2Lir::GenDivRem(RegLocation rl_dest, int reg1, int reg2,
-                                  bool is_div)
-{
+                                  bool is_div) {
   LOG(FATAL) << "Unexpected use of GenDivRem for Arm";
   return rl_dest;
 }
 
-bool ArmMir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min)
-{
+bool ArmMir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min) {
   DCHECK_EQ(cu_->instruction_set, kThumb2);
   RegLocation rl_src1 = info->args[0];
   RegLocation rl_src2 = info->args[1];
@@ -509,13 +494,11 @@
   return true;
 }
 
-void ArmMir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset)
-{
+void ArmMir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) {
   LOG(FATAL) << "Unexpected use of OpLea for Arm";
 }
 
-void ArmMir2Lir::OpTlsCmp(int offset, int val)
-{
+void ArmMir2Lir::OpTlsCmp(int offset, int val) {
   LOG(FATAL) << "Unexpected use of OpTlsCmp for Arm";
 }
 
@@ -577,25 +560,21 @@
   return true;
 }
 
-LIR* ArmMir2Lir::OpPcRelLoad(int reg, LIR* target)
-{
+LIR* ArmMir2Lir::OpPcRelLoad(int reg, LIR* target) {
   return RawLIR(current_dalvik_offset_, kThumb2LdrPcRel12, reg, 0, 0, 0, 0, target);
 }
 
-LIR* ArmMir2Lir::OpVldm(int rBase, int count)
-{
+LIR* ArmMir2Lir::OpVldm(int rBase, int count) {
   return NewLIR3(kThumb2Vldms, rBase, fr0, count);
 }
 
-LIR* ArmMir2Lir::OpVstm(int rBase, int count)
-{
+LIR* ArmMir2Lir::OpVstm(int rBase, int count) {
   return NewLIR3(kThumb2Vstms, rBase, fr0, count);
 }
 
 void ArmMir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src,
                                                RegLocation rl_result, int lit,
-                                               int first_bit, int second_bit)
-{
+                                               int first_bit, int second_bit) {
   OpRegRegRegShift(kOpAdd, rl_result.low_reg, rl_src.low_reg, rl_src.low_reg,
                    EncodeShift(kArmLsl, second_bit - first_bit));
   if (first_bit != 0) {
@@ -603,8 +582,7 @@
   }
 }
 
-void ArmMir2Lir::GenDivZeroCheck(int reg_lo, int reg_hi)
-{
+void ArmMir2Lir::GenDivZeroCheck(int reg_lo, int reg_hi) {
   int t_reg = AllocTemp();
   NewLIR4(kThumb2OrrRRRs, t_reg, reg_lo, reg_hi, 0);
   FreeTemp(t_reg);
@@ -612,22 +590,19 @@
 }
 
 // Test suspend flag, return target of taken suspend branch
-LIR* ArmMir2Lir::OpTestSuspend(LIR* target)
-{
+LIR* ArmMir2Lir::OpTestSuspend(LIR* target) {
   NewLIR2(kThumbSubRI8, rARM_SUSPEND, 1);
   return OpCondBranch((target == NULL) ? kCondEq : kCondNe, target);
 }
 
 // Decrement register and branch on condition
-LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target)
-{
+LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) {
   // Combine sub & test using sub setflags encoding here
   NewLIR3(kThumb2SubsRRI12, reg, reg, 1);
   return OpCondBranch(c_code, target);
 }
 
-void ArmMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind)
-{
+void ArmMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) {
 #if ANDROID_SMP != 0
   int dmb_flavor;
   // TODO: revisit Arm barrier kinds
@@ -646,8 +621,7 @@
 #endif
 }
 
-void ArmMir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src)
-{
+void ArmMir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) {
   rl_src = LoadValueWide(rl_src, kCoreReg);
   RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
   int z_reg = AllocTemp();
@@ -672,16 +646,14 @@
   * is not usual for dx to generate, but it is legal (for now).  In a future rev of
   * dex, we'll want to make this case illegal.
   */
-bool ArmMir2Lir::BadOverlap(RegLocation rl_src, RegLocation rl_dest)
-{
+bool ArmMir2Lir::BadOverlap(RegLocation rl_src, RegLocation rl_dest) {
   DCHECK(rl_src.wide);
   DCHECK(rl_dest.wide);
   return (abs(mir_graph_->SRegToVReg(rl_src.s_reg_low) - mir_graph_->SRegToVReg(rl_dest.s_reg_low)) == 1);
 }
 
 void ArmMir2Lir::GenMulLong(RegLocation rl_dest, RegLocation rl_src1,
-                            RegLocation rl_src2)
-{
+                            RegLocation rl_src2) {
     /*
      * To pull off inline multiply, we have a worst-case requirement of 8 temporary
      * registers.  Normally for Arm, we get 5.  We can get to 6 by including
@@ -754,32 +726,27 @@
 }
 
 void ArmMir2Lir::GenAddLong(RegLocation rl_dest, RegLocation rl_src1,
-                            RegLocation rl_src2)
-{
+                            RegLocation rl_src2) {
   LOG(FATAL) << "Unexpected use of GenAddLong for Arm";
 }
 
 void ArmMir2Lir::GenSubLong(RegLocation rl_dest, RegLocation rl_src1,
-                            RegLocation rl_src2)
-{
+                            RegLocation rl_src2) {
   LOG(FATAL) << "Unexpected use of GenSubLong for Arm";
 }
 
 void ArmMir2Lir::GenAndLong(RegLocation rl_dest, RegLocation rl_src1,
-                            RegLocation rl_src2)
-{
+                            RegLocation rl_src2) {
   LOG(FATAL) << "Unexpected use of GenAndLong for Arm";
 }
 
 void ArmMir2Lir::GenOrLong(RegLocation rl_dest, RegLocation rl_src1,
-                           RegLocation rl_src2)
-{
+                           RegLocation rl_src2) {
   LOG(FATAL) << "Unexpected use of GenOrLong for Arm";
 }
 
 void ArmMir2Lir::GenXorLong(RegLocation rl_dest, RegLocation rl_src1,
-                            RegLocation rl_src2)
-{
+                            RegLocation rl_src2) {
   LOG(FATAL) << "Unexpected use of genXoLong for Arm";
 }
 
@@ -787,8 +754,7 @@
  * Generate array load
  */
 void ArmMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
-                          RegLocation rl_index, RegLocation rl_dest, int scale)
-{
+                          RegLocation rl_index, RegLocation rl_dest, int scale) {
   RegisterClass reg_class = oat_reg_class_by_size(size);
   int len_offset = mirror::Array::LengthOffset().Int32Value();
   int data_offset;
@@ -878,8 +844,7 @@
  *
  */
 void ArmMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
-                          RegLocation rl_index, RegLocation rl_src, int scale)
-{
+                          RegLocation rl_index, RegLocation rl_src, int scale) {
   RegisterClass reg_class = oat_reg_class_by_size(size);
   int len_offset = mirror::Array::LengthOffset().Int32Value();
   int data_offset;
@@ -968,8 +933,7 @@
  *
  */
 void ArmMir2Lir::GenArrayObjPut(int opt_flags, RegLocation rl_array,
-                             RegLocation rl_index, RegLocation rl_src, int scale)
-{
+                             RegLocation rl_index, RegLocation rl_src, int scale) {
   int len_offset = mirror::Array::LengthOffset().Int32Value();
   int data_offset = mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value();
 
@@ -1025,8 +989,7 @@
 }
 
 void ArmMir2Lir::GenShiftImmOpLong(Instruction::Code opcode,
-                                   RegLocation rl_dest, RegLocation rl_src, RegLocation rl_shift)
-{
+                                   RegLocation rl_dest, RegLocation rl_src, RegLocation rl_shift) {
   rl_src = LoadValueWide(rl_src, kCoreReg);
   // Per spec, we only care about low 6 bits of shift amount.
   int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f;
@@ -1099,8 +1062,7 @@
 }
 
 void ArmMir2Lir::GenArithImmOpLong(Instruction::Code opcode,
-                                   RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
-{
+                                   RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
   if ((opcode == Instruction::SUB_LONG_2ADDR) || (opcode == Instruction::SUB_LONG)) {
     if (!rl_src2.is_const) {
       // Don't bother with special handling for subtract from immediate.
diff --git a/compiler/dex/quick/arm/target_arm.cc b/compiler/dex/quick/arm/target_arm.cc
index 4bece13..7021593 100644
--- a/compiler/dex/quick/arm/target_arm.cc
+++ b/compiler/dex/quick/arm/target_arm.cc
@@ -34,26 +34,22 @@
 static int fp_temps[] = {fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
                         fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15};
 
-RegLocation ArmMir2Lir::LocCReturn()
-{
+RegLocation ArmMir2Lir::LocCReturn() {
   RegLocation res = ARM_LOC_C_RETURN;
   return res;
 }
 
-RegLocation ArmMir2Lir::LocCReturnWide()
-{
+RegLocation ArmMir2Lir::LocCReturnWide() {
   RegLocation res = ARM_LOC_C_RETURN_WIDE;
   return res;
 }
 
-RegLocation ArmMir2Lir::LocCReturnFloat()
-{
+RegLocation ArmMir2Lir::LocCReturnFloat() {
   RegLocation res = ARM_LOC_C_RETURN_FLOAT;
   return res;
 }
 
-RegLocation ArmMir2Lir::LocCReturnDouble()
-{
+RegLocation ArmMir2Lir::LocCReturnDouble() {
   RegLocation res = ARM_LOC_C_RETURN_DOUBLE;
   return res;
 }
@@ -85,28 +81,24 @@
 
 
 // Create a double from a pair of singles.
-int ArmMir2Lir::S2d(int low_reg, int high_reg)
-{
+int ArmMir2Lir::S2d(int low_reg, int high_reg) {
   return ARM_S2D(low_reg, high_reg);
 }
 
 // Return mask to strip off fp reg flags and bias.
-uint32_t ArmMir2Lir::FpRegMask()
-{
+uint32_t ArmMir2Lir::FpRegMask() {
   return ARM_FP_REG_MASK;
 }
 
 // True if both regs single, both core or both double.
-bool ArmMir2Lir::SameRegType(int reg1, int reg2)
-{
+bool ArmMir2Lir::SameRegType(int reg1, int reg2) {
   return (ARM_REGTYPE(reg1) == ARM_REGTYPE(reg2));
 }
 
 /*
  * Decode the register id.
  */
-uint64_t ArmMir2Lir::GetRegMaskCommon(int reg)
-{
+uint64_t ArmMir2Lir::GetRegMaskCommon(int reg) {
   uint64_t seed;
   int shift;
   int reg_id;
@@ -122,13 +114,11 @@
   return (seed << shift);
 }
 
-uint64_t ArmMir2Lir::GetPCUseDefEncoding()
-{
+uint64_t ArmMir2Lir::GetPCUseDefEncoding() {
   return ENCODE_ARM_REG_PC;
 }
 
-void ArmMir2Lir::SetupTargetResourceMasks(LIR* lir)
-{
+void ArmMir2Lir::SetupTargetResourceMasks(LIR* lir) {
   DCHECK_EQ(cu_->instruction_set, kThumb2);
 
   // Thumb2 specific setup
@@ -203,8 +193,7 @@
   }
 }
 
-ArmConditionCode ArmMir2Lir::ArmConditionEncoding(ConditionCode ccode)
-{
+ArmConditionCode ArmMir2Lir::ArmConditionEncoding(ConditionCode ccode) {
   ArmConditionCode res;
   switch (ccode) {
     case kCondEq: res = kArmCondEq; break;
@@ -257,8 +246,7 @@
   "ror"};
 
 /* Decode and print a ARM register name */
-static char* DecodeRegList(int opcode, int vector, char* buf)
-{
+static char* DecodeRegList(int opcode, int vector, char* buf) {
   int i;
   bool printed = false;
   buf[0] = 0;
@@ -281,8 +269,7 @@
   return buf;
 }
 
-static char*  DecodeFPCSRegList(int count, int base, char* buf)
-{
+static char*  DecodeFPCSRegList(int count, int base, char* buf) {
   sprintf(buf, "s%d", base);
   for (int i = 1; i < count; i++) {
     sprintf(buf + strlen(buf), ", s%d",base + i);
@@ -290,8 +277,7 @@
   return buf;
 }
 
-static int ExpandImmediate(int value)
-{
+static int ExpandImmediate(int value) {
   int mode = (value & 0xf00) >> 8;
   uint32_t bits = value & 0xff;
   switch (mode) {
@@ -316,8 +302,7 @@
  * Interpret a format string and build a string no longer than size
  * See format key in Assemble.c.
  */
-std::string ArmMir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr)
-{
+std::string ArmMir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) {
   std::string buf;
   int i;
   const char* fmt_end = &fmt[strlen(fmt)];
@@ -455,8 +440,7 @@
   return buf;
 }
 
-void ArmMir2Lir::DumpResourceMask(LIR* arm_lir, uint64_t mask, const char* prefix)
-{
+void ArmMir2Lir::DumpResourceMask(LIR* arm_lir, uint64_t mask, const char* prefix) {
   char buf[256];
   buf[0] = 0;
 
@@ -501,8 +485,7 @@
   }
 }
 
-bool ArmMir2Lir::IsUnconditionalBranch(LIR* lir)
-{
+bool ArmMir2Lir::IsUnconditionalBranch(LIR* lir) {
   return ((lir->opcode == kThumbBUncond) || (lir->opcode == kThumb2BUncond));
 }
 
@@ -527,8 +510,7 @@
  * Alloc a pair of core registers, or a double.  Low reg in low byte,
  * high reg in next byte.
  */
-int ArmMir2Lir::AllocTypedTempPair(bool fp_hint, int reg_class)
-{
+int ArmMir2Lir::AllocTypedTempPair(bool fp_hint, int reg_class) {
   int high_reg;
   int low_reg;
   int res = 0;
@@ -544,15 +526,13 @@
   return res;
 }
 
-int ArmMir2Lir::AllocTypedTemp(bool fp_hint, int reg_class)
-{
+int ArmMir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) {
   if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg))
     return AllocTempFloat();
   return AllocTemp();
 }
 
-void ArmMir2Lir::CompilerInitializeRegAlloc()
-{
+void ArmMir2Lir::CompilerInitializeRegAlloc() {
   int num_regs = sizeof(core_regs)/sizeof(*core_regs);
   int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs);
   int num_temps = sizeof(core_temps)/sizeof(*core_temps);
@@ -591,8 +571,7 @@
 }
 
 void ArmMir2Lir::FreeRegLocTemps(RegLocation rl_keep,
-                     RegLocation rl_free)
-{
+                     RegLocation rl_free) {
   if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) &&
     (rl_free.high_reg != rl_keep.low_reg) && (rl_free.high_reg != rl_keep.high_reg)) {
     // No overlap, free both
@@ -606,8 +585,7 @@
  * machinery is in place, always spill lr.
  */
 
-void ArmMir2Lir::AdjustSpillMask()
-{
+void ArmMir2Lir::AdjustSpillMask() {
   core_spill_mask_ |= (1 << rARM_LR);
   num_core_spills_++;
 }
@@ -618,8 +596,7 @@
  * include any holes in the mask.  Associate holes with
  * Dalvik register INVALID_VREG (0xFFFFU).
  */
-void ArmMir2Lir::MarkPreservedSingle(int v_reg, int reg)
-{
+void ArmMir2Lir::MarkPreservedSingle(int v_reg, int reg) {
   DCHECK_GE(reg, ARM_FP_REG_MASK + ARM_FP_CALLEE_SAVE_BASE);
   reg = (reg & ARM_FP_REG_MASK) - ARM_FP_CALLEE_SAVE_BASE;
   // Ensure fp_vmap_table is large enough
@@ -634,8 +611,7 @@
   fp_spill_mask_ = ((1 << num_fp_spills_) - 1) << ARM_FP_CALLEE_SAVE_BASE;
 }
 
-void ArmMir2Lir::FlushRegWide(int reg1, int reg2)
-{
+void ArmMir2Lir::FlushRegWide(int reg1, int reg2) {
   RegisterInfo* info1 = GetRegInfo(reg1);
   RegisterInfo* info2 = GetRegInfo(reg2);
   DCHECK(info1 && info2 && info1->pair && info2->pair &&
@@ -657,8 +633,7 @@
   }
 }
 
-void ArmMir2Lir::FlushReg(int reg)
-{
+void ArmMir2Lir::FlushReg(int reg) {
   RegisterInfo* info = GetRegInfo(reg);
   if (info->live && info->dirty) {
     info->dirty = false;
@@ -673,8 +648,7 @@
 }
 
 /* Clobber all regs that might be used by an external C call */
-void ArmMir2Lir::ClobberCalleeSave()
-{
+void ArmMir2Lir::ClobberCalleeSave() {
   Clobber(r0);
   Clobber(r1);
   Clobber(r2);
@@ -699,8 +673,7 @@
   Clobber(fr15);
 }
 
-RegLocation ArmMir2Lir::GetReturnWideAlt()
-{
+RegLocation ArmMir2Lir::GetReturnWideAlt() {
   RegLocation res = LocCReturnWide();
   res.low_reg = r2;
   res.high_reg = r3;
@@ -712,8 +685,7 @@
   return res;
 }
 
-RegLocation ArmMir2Lir::GetReturnAlt()
-{
+RegLocation ArmMir2Lir::GetReturnAlt() {
   RegLocation res = LocCReturn();
   res.low_reg = r1;
   Clobber(r1);
@@ -721,15 +693,13 @@
   return res;
 }
 
-ArmMir2Lir::RegisterInfo* ArmMir2Lir::GetRegInfo(int reg)
-{
+ArmMir2Lir::RegisterInfo* ArmMir2Lir::GetRegInfo(int reg) {
   return ARM_FPREG(reg) ? &reg_pool_->FPRegs[reg & ARM_FP_REG_MASK]
       : &reg_pool_->core_regs[reg];
 }
 
 /* To be used when explicitly managing register use */
-void ArmMir2Lir::LockCallTemps()
-{
+void ArmMir2Lir::LockCallTemps() {
   LockTemp(r0);
   LockTemp(r1);
   LockTemp(r2);
@@ -737,32 +707,27 @@
 }
 
 /* To be used when explicitly managing register use */
-void ArmMir2Lir::FreeCallTemps()
-{
+void ArmMir2Lir::FreeCallTemps() {
   FreeTemp(r0);
   FreeTemp(r1);
   FreeTemp(r2);
   FreeTemp(r3);
 }
 
-int ArmMir2Lir::LoadHelper(int offset)
-{
+int ArmMir2Lir::LoadHelper(int offset) {
   LoadWordDisp(rARM_SELF, offset, rARM_LR);
   return rARM_LR;
 }
 
-uint64_t ArmMir2Lir::GetTargetInstFlags(int opcode)
-{
+uint64_t ArmMir2Lir::GetTargetInstFlags(int opcode) {
   return ArmMir2Lir::EncodingMap[opcode].flags;
 }
 
-const char* ArmMir2Lir::GetTargetInstName(int opcode)
-{
+const char* ArmMir2Lir::GetTargetInstName(int opcode) {
   return ArmMir2Lir::EncodingMap[opcode].name;
 }
 
-const char* ArmMir2Lir::GetTargetInstFmt(int opcode)
-{
+const char* ArmMir2Lir::GetTargetInstFmt(int opcode) {
   return ArmMir2Lir::EncodingMap[opcode].fmt;
 }
 
diff --git a/compiler/dex/quick/arm/utility_arm.cc b/compiler/dex/quick/arm/utility_arm.cc
index abf921f..80f597d 100644
--- a/compiler/dex/quick/arm/utility_arm.cc
+++ b/compiler/dex/quick/arm/utility_arm.cc
@@ -22,8 +22,7 @@
 
 /* This file contains codegen for the Thumb ISA. */
 
-static int EncodeImmSingle(int value)
-{
+static int EncodeImmSingle(int value) {
   int res;
   int bit_a =  (value & 0x80000000) >> 31;
   int not_bit_b = (value & 0x40000000) >> 30;
@@ -48,8 +47,7 @@
  * Determine whether value can be encoded as a Thumb2 floating point
  * immediate.  If not, return -1.  If so return encoded 8-bit value.
  */
-static int EncodeImmDouble(int64_t value)
-{
+static int EncodeImmDouble(int64_t value) {
   int res;
   int bit_a = (value & 0x8000000000000000ll) >> 63;
   int not_bit_b = (value & 0x4000000000000000ll) >> 62;
@@ -70,8 +68,7 @@
   return res;
 }
 
-LIR* ArmMir2Lir::LoadFPConstantValue(int r_dest, int value)
-{
+LIR* ArmMir2Lir::LoadFPConstantValue(int r_dest, int value) {
   DCHECK(ARM_SINGLEREG(r_dest));
   if (value == 0) {
     // TODO: we need better info about the target CPU.  a vector exclusive or
@@ -98,8 +95,7 @@
   return load_pc_rel;
 }
 
-static int LeadingZeros(uint32_t val)
-{
+static int LeadingZeros(uint32_t val) {
   uint32_t alt;
   int n;
   int count;
@@ -121,8 +117,7 @@
  * Determine whether value can be encoded as a Thumb2 modified
  * immediate.  If not, return -1.  If so, return i:imm3:a:bcdefgh form.
  */
-int ArmMir2Lir::ModifiedImmediate(uint32_t value)
-{
+int ArmMir2Lir::ModifiedImmediate(uint32_t value) {
    int z_leading;
    int z_trailing;
    uint32_t b0 = value & 0xff;
@@ -151,23 +146,19 @@
    return value | ((0x8 + z_leading) << 7); /* [01000..11111]:bcdefgh */
 }
 
-bool ArmMir2Lir::InexpensiveConstantInt(int32_t value)
-{
+bool ArmMir2Lir::InexpensiveConstantInt(int32_t value) {
   return (ModifiedImmediate(value) >= 0) || (ModifiedImmediate(~value) >= 0);
 }
 
-bool ArmMir2Lir::InexpensiveConstantFloat(int32_t value)
-{
+bool ArmMir2Lir::InexpensiveConstantFloat(int32_t value) {
   return EncodeImmSingle(value) >= 0;
 }
 
-bool ArmMir2Lir::InexpensiveConstantLong(int64_t value)
-{
+bool ArmMir2Lir::InexpensiveConstantLong(int64_t value) {
   return InexpensiveConstantInt(High32Bits(value)) && InexpensiveConstantInt(Low32Bits(value));
 }
 
-bool ArmMir2Lir::InexpensiveConstantDouble(int64_t value)
-{
+bool ArmMir2Lir::InexpensiveConstantDouble(int64_t value) {
   return EncodeImmDouble(value) >= 0;
 }
 
@@ -179,8 +170,7 @@
  * 1) r_dest is freshly returned from AllocTemp or
  * 2) The codegen is under fixed register usage
  */
-LIR* ArmMir2Lir::LoadConstantNoClobber(int r_dest, int value)
-{
+LIR* ArmMir2Lir::LoadConstantNoClobber(int r_dest, int value) {
   LIR* res;
   int mod_imm;
 
@@ -214,23 +204,20 @@
   return res;
 }
 
-LIR* ArmMir2Lir::OpUnconditionalBranch(LIR* target)
-{
+LIR* ArmMir2Lir::OpUnconditionalBranch(LIR* target) {
   LIR* res = NewLIR1(kThumbBUncond, 0 /* offset to be patched  during assembly*/);
   res->target = target;
   return res;
 }
 
-LIR* ArmMir2Lir::OpCondBranch(ConditionCode cc, LIR* target)
-{
+LIR* ArmMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) {
   LIR* branch = NewLIR2(kThumb2BCond, 0 /* offset to be patched */,
                         ArmConditionEncoding(cc));
   branch->target = target;
   return branch;
 }
 
-LIR* ArmMir2Lir::OpReg(OpKind op, int r_dest_src)
-{
+LIR* ArmMir2Lir::OpReg(OpKind op, int r_dest_src) {
   ArmOpcode opcode = kThumbBkpt;
   switch (op) {
     case kOpBlx:
@@ -243,8 +230,7 @@
 }
 
 LIR* ArmMir2Lir::OpRegRegShift(OpKind op, int r_dest_src1, int r_src2,
-                               int shift)
-{
+                               int shift) {
   bool thumb_form = ((shift == 0) && ARM_LOWREG(r_dest_src1) && ARM_LOWREG(r_src2));
   ArmOpcode opcode = kThumbBkpt;
   switch (op) {
@@ -358,14 +344,12 @@
   }
 }
 
-LIR* ArmMir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2)
-{
+LIR* ArmMir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2) {
   return OpRegRegShift(op, r_dest_src1, r_src2, 0);
 }
 
 LIR* ArmMir2Lir::OpRegRegRegShift(OpKind op, int r_dest, int r_src1,
-                                  int r_src2, int shift)
-{
+                                  int r_src2, int shift) {
   ArmOpcode opcode = kThumbBkpt;
   bool thumb_form = (shift == 0) && ARM_LOWREG(r_dest) && ARM_LOWREG(r_src1) &&
       ARM_LOWREG(r_src2);
@@ -430,13 +414,11 @@
   }
 }
 
-LIR* ArmMir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2)
-{
+LIR* ArmMir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2) {
   return OpRegRegRegShift(op, r_dest, r_src1, r_src2, 0);
 }
 
-LIR* ArmMir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src1, int value)
-{
+LIR* ArmMir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src1, int value) {
   LIR* res;
   bool neg = (value < 0);
   int abs_value = (neg) ? -value : value;
@@ -560,8 +542,7 @@
 }
 
 /* Handle Thumb-only variants here - otherwise punt to OpRegRegImm */
-LIR* ArmMir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value)
-{
+LIR* ArmMir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value) {
   bool neg = (value < 0);
   int abs_value = (neg) ? -value : value;
   bool short_form = (((abs_value & 0xff) == abs_value) && ARM_LOWREG(r_dest_src1));
@@ -605,8 +586,7 @@
   }
 }
 
-LIR* ArmMir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value)
-{
+LIR* ArmMir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) {
   LIR* res = NULL;
   int32_t val_lo = Low32Bits(value);
   int32_t val_hi = High32Bits(value);
@@ -656,8 +636,7 @@
 }
 
 LIR* ArmMir2Lir::LoadBaseIndexed(int rBase, int r_index, int r_dest,
-                                 int scale, OpSize size)
-{
+                                 int scale, OpSize size) {
   bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_dest);
   LIR* load;
   ArmOpcode opcode = kThumbBkpt;
@@ -721,8 +700,7 @@
 }
 
 LIR* ArmMir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src,
-                                  int scale, OpSize size)
-{
+                                  int scale, OpSize size) {
   bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_src);
   LIR* store = NULL;
   ArmOpcode opcode = kThumbBkpt;
@@ -787,8 +765,7 @@
  * performing null check, incoming MIR can be null.
  */
 LIR* ArmMir2Lir::LoadBaseDispBody(int rBase, int displacement, int r_dest,
-                                  int r_dest_hi, OpSize size, int s_reg)
-{
+                                  int r_dest_hi, OpSize size, int s_reg) {
   LIR* load = NULL;
   ArmOpcode opcode = kThumbBkpt;
   bool short_form = false;
@@ -908,14 +885,12 @@
 }
 
 LIR* ArmMir2Lir::LoadBaseDisp(int rBase, int displacement, int r_dest,
-                              OpSize size, int s_reg)
-{
+                              OpSize size, int s_reg) {
   return LoadBaseDispBody(rBase, displacement, r_dest, -1, size, s_reg);
 }
 
 LIR* ArmMir2Lir::LoadBaseDispWide(int rBase, int displacement, int r_dest_lo,
-                                  int r_dest_hi, int s_reg)
-{
+                                  int r_dest_hi, int s_reg) {
   return LoadBaseDispBody(rBase, displacement, r_dest_lo, r_dest_hi, kLong, s_reg);
 }
 
@@ -1024,19 +999,16 @@
 }
 
 LIR* ArmMir2Lir::StoreBaseDisp(int rBase, int displacement, int r_src,
-                               OpSize size)
-{
+                               OpSize size) {
   return StoreBaseDispBody(rBase, displacement, r_src, -1, size);
 }
 
 LIR* ArmMir2Lir::StoreBaseDispWide(int rBase, int displacement,
-                                   int r_src_lo, int r_src_hi)
-{
+                                   int r_src_lo, int r_src_hi) {
   return StoreBaseDispBody(rBase, displacement, r_src_lo, r_src_hi, kLong);
 }
 
-LIR* ArmMir2Lir::OpFpRegCopy(int r_dest, int r_src)
-{
+LIR* ArmMir2Lir::OpFpRegCopy(int r_dest, int r_src) {
   int opcode;
   DCHECK_EQ(ARM_DOUBLEREG(r_dest), ARM_DOUBLEREG(r_src));
   if (ARM_DOUBLEREG(r_dest)) {
@@ -1056,36 +1028,31 @@
   return res;
 }
 
-LIR* ArmMir2Lir::OpThreadMem(OpKind op, int thread_offset)
-{
+LIR* ArmMir2Lir::OpThreadMem(OpKind op, int thread_offset) {
   LOG(FATAL) << "Unexpected use of OpThreadMem for Arm";
   return NULL;
 }
 
-LIR* ArmMir2Lir::OpMem(OpKind op, int rBase, int disp)
-{
+LIR* ArmMir2Lir::OpMem(OpKind op, int rBase, int disp) {
   LOG(FATAL) << "Unexpected use of OpMem for Arm";
   return NULL;
 }
 
 LIR* ArmMir2Lir::StoreBaseIndexedDisp(int rBase, int r_index, int scale,
                                       int displacement, int r_src, int r_src_hi, OpSize size,
-                                      int s_reg)
-{
+                                      int s_reg) {
   LOG(FATAL) << "Unexpected use of StoreBaseIndexedDisp for Arm";
   return NULL;
 }
 
-LIR* ArmMir2Lir::OpRegMem(OpKind op, int r_dest, int rBase, int offset)
-{
+LIR* ArmMir2Lir::OpRegMem(OpKind op, int r_dest, int rBase, int offset) {
   LOG(FATAL) << "Unexpected use of OpRegMem for Arm";
   return NULL;
 }
 
 LIR* ArmMir2Lir::LoadBaseIndexedDisp(int rBase, int r_index, int scale,
                                      int displacement, int r_dest, int r_dest_hi, OpSize size,
-                                     int s_reg)
-{
+                                     int s_reg) {
   LOG(FATAL) << "Unexpected use of LoadBaseIndexedDisp for Arm";
   return NULL;
 }
diff --git a/compiler/dex/quick/codegen_util.cc b/compiler/dex/quick/codegen_util.cc
index 5c10c4c..e728d27 100644
--- a/compiler/dex/quick/codegen_util.cc
+++ b/compiler/dex/quick/codegen_util.cc
@@ -23,8 +23,7 @@
 
 namespace art {
 
-bool Mir2Lir::IsInexpensiveConstant(RegLocation rl_src)
-{
+bool Mir2Lir::IsInexpensiveConstant(RegLocation rl_src) {
   bool res = false;
   if (rl_src.is_const) {
     if (rl_src.wide) {
@@ -44,27 +43,23 @@
   return res;
 }
 
-void Mir2Lir::MarkSafepointPC(LIR* inst)
-{
+void Mir2Lir::MarkSafepointPC(LIR* inst) {
   inst->def_mask = ENCODE_ALL;
   LIR* safepoint_pc = NewLIR0(kPseudoSafepointPC);
   DCHECK_EQ(safepoint_pc->def_mask, ENCODE_ALL);
 }
 
-bool Mir2Lir::FastInstance(uint32_t field_idx, int& field_offset, bool& is_volatile, bool is_put)
-{
+bool Mir2Lir::FastInstance(uint32_t field_idx, int& field_offset, bool& is_volatile, bool is_put) {
   return cu_->compiler_driver->ComputeInstanceFieldInfo(
       field_idx, mir_graph_->GetCurrentDexCompilationUnit(), field_offset, is_volatile, is_put);
 }
 
 /* Convert an instruction to a NOP */
-void Mir2Lir::NopLIR( LIR* lir)
-{
+void Mir2Lir::NopLIR( LIR* lir) {
   lir->flags.is_nop = true;
 }
 
-void Mir2Lir::SetMemRefType(LIR* lir, bool is_load, int mem_type)
-{
+void Mir2Lir::SetMemRefType(LIR* lir, bool is_load, int mem_type) {
   uint64_t *mask_ptr;
   uint64_t mask = ENCODE_MEM;;
   DCHECK(GetTargetInstFlags(lir->opcode) & (IS_LOAD | IS_STORE));
@@ -101,8 +96,7 @@
  * Mark load/store instructions that access Dalvik registers through the stack.
  */
 void Mir2Lir::AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load,
-                                      bool is64bit)
-{
+                                      bool is64bit) {
   SetMemRefType(lir, is_load, kDalvikReg);
 
   /*
@@ -118,8 +112,7 @@
 #define DUMP_RESOURCE_MASK(X)
 
 /* Pretty-print a LIR instruction */
-void Mir2Lir::DumpLIRInsn(LIR* lir, unsigned char* base_addr)
-{
+void Mir2Lir::DumpLIRInsn(LIR* lir, unsigned char* base_addr) {
   int offset = lir->offset;
   int dest = lir->operands[0];
   const bool dump_nop = (cu_->enable_debug & (1 << kDebugShowNops));
@@ -204,8 +197,7 @@
   }
 }
 
-void Mir2Lir::DumpPromotionMap()
-{
+void Mir2Lir::DumpPromotionMap() {
   int num_regs = cu_->num_dalvik_registers + cu_->num_compiler_temps + 1;
   for (int i = 0; i < num_regs; i++) {
     PromotionMap v_reg_map = promotion_map_[i];
@@ -249,8 +241,7 @@
 }
 
 /* Dump instructions and constant pool contents */
-void Mir2Lir::CodegenDump()
-{
+void Mir2Lir::CodegenDump() {
   LOG(INFO) << "Dumping LIR insns for "
             << PrettyMethod(cu_->method_idx, *cu_->dex_file);
   LIR* lir_insn;
@@ -291,8 +282,7 @@
  * Search the existing constants in the literal pool for an exact or close match
  * within specified delta (greater or equal to 0).
  */
-LIR* Mir2Lir::ScanLiteralPool(LIR* data_target, int value, unsigned int delta)
-{
+LIR* Mir2Lir::ScanLiteralPool(LIR* data_target, int value, unsigned int delta) {
   while (data_target) {
     if ((static_cast<unsigned>(value - data_target->operands[0])) <= delta)
       return data_target;
@@ -302,8 +292,7 @@
 }
 
 /* Search the existing constants in the literal pool for an exact wide match */
-LIR* Mir2Lir::ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi)
-{
+LIR* Mir2Lir::ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi) {
   bool lo_match = false;
   LIR* lo_target = NULL;
   while (data_target) {
@@ -328,8 +317,7 @@
  */
 
 /* Add a 32-bit constant to the constant pool */
-LIR* Mir2Lir::AddWordData(LIR* *constant_list_p, int value)
-{
+LIR* Mir2Lir::AddWordData(LIR* *constant_list_p, int value) {
   /* Add the constant to the literal pool */
   if (constant_list_p) {
     LIR* new_value = static_cast<LIR*>(arena_->NewMem(sizeof(LIR), true, ArenaAllocator::kAllocData));
@@ -342,8 +330,7 @@
 }
 
 /* Add a 64-bit constant to the constant pool or mixed with code */
-LIR* Mir2Lir::AddWideData(LIR* *constant_list_p, int val_lo, int val_hi)
-{
+LIR* Mir2Lir::AddWideData(LIR* *constant_list_p, int val_lo, int val_hi) {
   AddWordData(constant_list_p, val_hi);
   return AddWordData(constant_list_p, val_lo);
 }
@@ -362,8 +349,7 @@
 }
 
 /* Write the literal pool to the output stream */
-void Mir2Lir::InstallLiteralPools()
-{
+void Mir2Lir::InstallLiteralPools() {
   AlignBuffer(code_buffer_, data_offset_);
   LIR* data_lir = literal_list_;
   while (data_lir != NULL) {
@@ -404,8 +390,7 @@
 }
 
 /* Write the switch tables to the output stream */
-void Mir2Lir::InstallSwitchTables()
-{
+void Mir2Lir::InstallSwitchTables() {
   GrowableArray<SwitchTable*>::Iterator iterator(&switch_tables_);
   while (true) {
     Mir2Lir::SwitchTable* tab_rec = iterator.Next();
@@ -462,8 +447,7 @@
 }
 
 /* Write the fill array dta to the output stream */
-void Mir2Lir::InstallFillArrayData()
-{
+void Mir2Lir::InstallFillArrayData() {
   GrowableArray<FillArrayData*>::Iterator iterator(&fill_array_data_);
   while (true) {
     Mir2Lir::FillArrayData *tab_rec = iterator.Next();
@@ -476,8 +460,7 @@
   }
 }
 
-static int AssignLiteralOffsetCommon(LIR* lir, int offset)
-{
+static int AssignLiteralOffsetCommon(LIR* lir, int offset) {
   for (;lir != NULL; lir = lir->next) {
     lir->offset = offset;
     offset += 4;
@@ -486,8 +469,7 @@
 }
 
 // Make sure we have a code address for every declared catch entry
-bool Mir2Lir::VerifyCatchEntries()
-{
+bool Mir2Lir::VerifyCatchEntries() {
   bool success = true;
   for (std::set<uint32_t>::const_iterator it = mir_graph_->catches_.begin();
        it != mir_graph_->catches_.end(); ++it) {
@@ -521,8 +503,7 @@
 }
 
 
-void Mir2Lir::CreateMappingTables()
-{
+void Mir2Lir::CreateMappingTables() {
   for (LIR* tgt_lir = first_lir_insn_; tgt_lir != NULL; tgt_lir = NEXT_LIR(tgt_lir)) {
     if (!tgt_lir->flags.is_nop && (tgt_lir->opcode == kPseudoSafepointPC)) {
       pc2dex_mapping_table_.push_back(tgt_lir->offset);
@@ -650,16 +631,14 @@
 }
 
 /* Determine the offset of each literal field */
-int Mir2Lir::AssignLiteralOffset(int offset)
-{
+int Mir2Lir::AssignLiteralOffset(int offset) {
   offset = AssignLiteralOffsetCommon(literal_list_, offset);
   offset = AssignLiteralOffsetCommon(code_literal_list_, offset);
   offset = AssignLiteralOffsetCommon(method_literal_list_, offset);
   return offset;
 }
 
-int Mir2Lir::AssignSwitchTablesOffset(int offset)
-{
+int Mir2Lir::AssignSwitchTablesOffset(int offset) {
   GrowableArray<SwitchTable*>::Iterator iterator(&switch_tables_);
   while (true) {
     Mir2Lir::SwitchTable *tab_rec = iterator.Next();
@@ -676,8 +655,7 @@
   return offset;
 }
 
-int Mir2Lir::AssignFillArrayDataOffset(int offset)
-{
+int Mir2Lir::AssignFillArrayDataOffset(int offset) {
   GrowableArray<FillArrayData*>::Iterator iterator(&fill_array_data_);
   while (true) {
     Mir2Lir::FillArrayData *tab_rec = iterator.Next();
@@ -691,8 +669,7 @@
 }
 
 // LIR offset assignment.
-int Mir2Lir::AssignInsnOffsets()
-{
+int Mir2Lir::AssignInsnOffsets() {
   LIR* lir;
   int offset = 0;
 
@@ -720,8 +697,7 @@
  * Walk the compilation unit and assign offsets to instructions
  * and literals and compute the total size of the compiled unit.
  */
-void Mir2Lir::AssignOffsets()
-{
+void Mir2Lir::AssignOffsets() {
   int offset = AssignInsnOffsets();
 
   /* Const values have to be word aligned */
@@ -744,8 +720,7 @@
  * before sending them off to the assembler. If out-of-range branch distance is
  * seen rearrange the instructions a bit to correct it.
  */
-void Mir2Lir::AssembleLIR()
-{
+void Mir2Lir::AssembleLIR() {
   AssignOffsets();
   int assembler_retries = 0;
   /*
@@ -791,8 +766,7 @@
  * all resource flags on this to prevent code motion across
  * target boundaries.  KeyVal is just there for debugging.
  */
-LIR* Mir2Lir::InsertCaseLabel(int vaddr, int keyVal)
-{
+LIR* Mir2Lir::InsertCaseLabel(int vaddr, int keyVal) {
   SafeMap<unsigned int, LIR*>::iterator it;
   it = boundary_map_.find(vaddr);
   if (it == boundary_map_.end()) {
@@ -806,8 +780,7 @@
   return new_label;
 }
 
-void Mir2Lir::MarkPackedCaseLabels(Mir2Lir::SwitchTable *tab_rec)
-{
+void Mir2Lir::MarkPackedCaseLabels(Mir2Lir::SwitchTable *tab_rec) {
   const uint16_t* table = tab_rec->table;
   int base_vaddr = tab_rec->vaddr;
   const int *targets = reinterpret_cast<const int*>(&table[4]);
@@ -818,8 +791,7 @@
   }
 }
 
-void Mir2Lir::MarkSparseCaseLabels(Mir2Lir::SwitchTable *tab_rec)
-{
+void Mir2Lir::MarkSparseCaseLabels(Mir2Lir::SwitchTable *tab_rec) {
   const uint16_t* table = tab_rec->table;
   int base_vaddr = tab_rec->vaddr;
   int entries = table[1];
@@ -830,8 +802,7 @@
   }
 }
 
-void Mir2Lir::ProcessSwitchTables()
-{
+void Mir2Lir::ProcessSwitchTables() {
   GrowableArray<SwitchTable*>::Iterator iterator(&switch_tables_);
   while (true) {
     Mir2Lir::SwitchTable *tab_rec = iterator.Next();
@@ -846,7 +817,7 @@
   }
 }
 
-void Mir2Lir::DumpSparseSwitchTable(const uint16_t* table)
+void Mir2Lir::DumpSparseSwitchTable(const uint16_t* table) {
   /*
    * Sparse switch data format:
    *  ushort ident = 0x0200   magic value
@@ -856,7 +827,6 @@
    *
    * Total size is (2+size*4) 16-bit code units.
    */
-{
   uint16_t ident = table[0];
   int entries = table[1];
   const int* keys = reinterpret_cast<const int*>(&table[2]);
@@ -868,7 +838,7 @@
   }
 }
 
-void Mir2Lir::DumpPackedSwitchTable(const uint16_t* table)
+void Mir2Lir::DumpPackedSwitchTable(const uint16_t* table) {
   /*
    * Packed switch data format:
    *  ushort ident = 0x0100   magic value
@@ -878,7 +848,6 @@
    *
    * Total size is (4+size*2) 16-bit code units.
    */
-{
   uint16_t ident = table[0];
   const int* targets = reinterpret_cast<const int*>(&table[4]);
   int entries = table[1];
@@ -897,8 +866,7 @@
  * which we split a single Dalvik instruction, only the first MIR op
  * associated with a Dalvik PC should be entered into the map.
  */
-LIR* Mir2Lir::MarkBoundary(int offset, const char* inst_str)
-{
+LIR* Mir2Lir::MarkBoundary(int offset, const char* inst_str) {
   LIR* res = NewLIR1(kPseudoDalvikByteCodeBoundary, reinterpret_cast<uintptr_t>(inst_str));
   if (boundary_map_.find(offset) == boundary_map_.end()) {
     boundary_map_.Put(offset, res);
@@ -906,8 +874,7 @@
   return res;
 }
 
-bool Mir2Lir::EvaluateBranch(Instruction::Code opcode, int32_t src1, int32_t src2)
-{
+bool Mir2Lir::EvaluateBranch(Instruction::Code opcode, int32_t src1, int32_t src2) {
   bool is_taken;
   switch (opcode) {
     case Instruction::IF_EQ: is_taken = (src1 == src2); break;
@@ -971,8 +938,7 @@
       core_spill_mask_(0),
       fp_spill_mask_(0),
       first_lir_insn_(NULL),
-      last_lir_insn_(NULL)
- {
+      last_lir_insn_(NULL) {
   promotion_map_ = static_cast<PromotionMap*>
       (arena_->NewMem((cu_->num_dalvik_registers  + cu_->num_compiler_temps + 1) *
                       sizeof(promotion_map_[0]), true, ArenaAllocator::kAllocRegAlloc));
@@ -1060,8 +1026,7 @@
  * Append an LIR instruction to the LIR list maintained by a compilation
  * unit
  */
-void Mir2Lir::AppendLIR(LIR* lir)
-{
+void Mir2Lir::AppendLIR(LIR* lir) {
   if (first_lir_insn_ == NULL) {
     DCHECK(last_lir_insn_ == NULL);
     last_lir_insn_ = first_lir_insn_ = lir;
@@ -1080,8 +1045,7 @@
  *
  * prev_lir <-> new_lir <-> current_lir
  */
-void Mir2Lir::InsertLIRBefore(LIR* current_lir, LIR* new_lir)
-{
+void Mir2Lir::InsertLIRBefore(LIR* current_lir, LIR* new_lir) {
   DCHECK(current_lir->prev != NULL);
   LIR *prev_lir = current_lir->prev;
 
@@ -1097,8 +1061,7 @@
  *
  * current_lir -> new_lir -> old_next
  */
-void Mir2Lir::InsertLIRAfter(LIR* current_lir, LIR* new_lir)
-{
+void Mir2Lir::InsertLIRAfter(LIR* current_lir, LIR* new_lir) {
   new_lir->prev = current_lir;
   new_lir->next = current_lir->next;
   current_lir->next = new_lir;
diff --git a/compiler/dex/quick/gen_common.cc b/compiler/dex/quick/gen_common.cc
index 865b9c5..a34d2a9 100644
--- a/compiler/dex/quick/gen_common.cc
+++ b/compiler/dex/quick/gen_common.cc
@@ -33,8 +33,7 @@
  * Generate an kPseudoBarrier marker to indicate the boundary of special
  * blocks.
  */
-void Mir2Lir::GenBarrier()
-{
+void Mir2Lir::GenBarrier() {
   LIR* barrier = NewLIR0(kPseudoBarrier);
   /* Mark all resources as being clobbered */
   barrier->def_mask = -1;
@@ -42,8 +41,7 @@
 
 // FIXME: need to do some work to split out targets with
 // condition codes and those without
-LIR* Mir2Lir::GenCheck(ConditionCode c_code, ThrowKind kind)
-{
+LIR* Mir2Lir::GenCheck(ConditionCode c_code, ThrowKind kind) {
   DCHECK_NE(cu_->instruction_set, kMips);
   LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind, current_dalvik_offset_);
   LIR* branch = OpCondBranch(c_code, tgt);
@@ -52,8 +50,7 @@
   return branch;
 }
 
-LIR* Mir2Lir::GenImmedCheck(ConditionCode c_code, int reg, int imm_val, ThrowKind kind)
-{
+LIR* Mir2Lir::GenImmedCheck(ConditionCode c_code, int reg, int imm_val, ThrowKind kind) {
   LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind, current_dalvik_offset_, reg, imm_val);
   LIR* branch;
   if (c_code == kCondAl) {
@@ -67,8 +64,7 @@
 }
 
 /* Perform null-check on a register.  */
-LIR* Mir2Lir::GenNullCheck(int s_reg, int m_reg, int opt_flags)
-{
+LIR* Mir2Lir::GenNullCheck(int s_reg, int m_reg, int opt_flags) {
   if (!(cu_->disable_opt & (1 << kNullCheckElimination)) &&
     opt_flags & MIR_IGNORE_NULL_CHECK) {
     return NULL;
@@ -78,8 +74,7 @@
 
 /* Perform check on two registers */
 LIR* Mir2Lir::GenRegRegCheck(ConditionCode c_code, int reg1, int reg2,
-                             ThrowKind kind)
-{
+                             ThrowKind kind) {
   LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind, current_dalvik_offset_, reg1, reg2);
   LIR* branch = OpCmpBranch(c_code, reg1, reg2, tgt);
   // Remember branch target - will process later
@@ -89,8 +84,7 @@
 
 void Mir2Lir::GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1,
                                   RegLocation rl_src2, LIR* taken,
-                                  LIR* fall_through)
-{
+                                  LIR* fall_through) {
   ConditionCode cond;
   switch (opcode) {
     case Instruction::IF_EQ:
@@ -143,8 +137,7 @@
 }
 
 void Mir2Lir::GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, LIR* taken,
-                                      LIR* fall_through)
-{
+                                      LIR* fall_through) {
   ConditionCode cond;
   rl_src = LoadValue(rl_src, kCoreReg);
   switch (opcode) {
@@ -174,8 +167,7 @@
   OpUnconditionalBranch(fall_through);
 }
 
-void Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src)
-{
+void Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) {
   RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
   if (rl_src.location == kLocPhysReg) {
     OpRegCopy(rl_result.low_reg, rl_src.low_reg);
@@ -187,8 +179,7 @@
 }
 
 void Mir2Lir::GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest,
-                              RegLocation rl_src)
-{
+                              RegLocation rl_src) {
    rl_src = LoadValue(rl_src, kCoreReg);
    RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
    OpKind op = kOpInvalid;
@@ -215,8 +206,7 @@
  * Note: AllocFromCode will handle checks for errNegativeArraySize.
  */
 void Mir2Lir::GenNewArray(uint32_t type_idx, RegLocation rl_dest,
-                          RegLocation rl_src)
-{
+                          RegLocation rl_src) {
   FlushAllRegs();  /* Everything to home location */
   int func_offset;
   if (cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, *cu_->dex_file,
@@ -236,8 +226,7 @@
  * code throws runtime exception "bad Filled array req" for 'D' and 'J'.
  * Current code also throws internal unimp if not 'L', '[' or 'I'.
  */
-void Mir2Lir::GenFilledNewArray(CallInfo* info)
-{
+void Mir2Lir::GenFilledNewArray(CallInfo* info) {
   int elems = info->num_arg_words;
   int type_idx = info->index;
   FlushAllRegs();  /* Everything to home location */
@@ -342,8 +331,7 @@
 }
 
 void Mir2Lir::GenSput(uint32_t field_idx, RegLocation rl_src, bool is_long_or_double,
-                      bool is_object)
-{
+                      bool is_object) {
   int field_offset;
   int ssb_index;
   bool is_volatile;
@@ -428,8 +416,7 @@
 }
 
 void Mir2Lir::GenSget(uint32_t field_idx, RegLocation rl_dest,
-                      bool is_long_or_double, bool is_object)
-{
+                      bool is_long_or_double, bool is_object) {
   int field_offset;
   int ssb_index;
   bool is_volatile;
@@ -510,8 +497,7 @@
   }
 }
 
-void Mir2Lir::HandleSuspendLaunchPads()
-{
+void Mir2Lir::HandleSuspendLaunchPads() {
   int num_elems = suspend_launchpads_.Size();
   int helper_offset = ENTRYPOINT_OFFSET(pTestSuspendFromCode);
   for (int i = 0; i < num_elems; i++) {
@@ -527,8 +513,7 @@
   }
 }
 
-void Mir2Lir::HandleIntrinsicLaunchPads()
-{
+void Mir2Lir::HandleIntrinsicLaunchPads() {
   int num_elems = intrinsic_launchpads_.Size();
   for (int i = 0; i < num_elems; i++) {
     ResetRegPool();
@@ -546,8 +531,7 @@
   }
 }
 
-void Mir2Lir::HandleThrowLaunchPads()
-{
+void Mir2Lir::HandleThrowLaunchPads() {
   int num_elems = throw_launchpads_.Size();
   for (int i = 0; i < num_elems; i++) {
     ResetRegPool();
@@ -636,8 +620,7 @@
 
 void Mir2Lir::GenIGet(uint32_t field_idx, int opt_flags, OpSize size,
                       RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double,
-                      bool is_object)
-{
+                      bool is_object) {
   int field_offset;
   bool is_volatile;
 
@@ -697,8 +680,7 @@
 
 void Mir2Lir::GenIPut(uint32_t field_idx, int opt_flags, OpSize size,
                       RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double,
-                      bool is_object)
-{
+                      bool is_object) {
   int field_offset;
   bool is_volatile;
 
@@ -744,8 +726,7 @@
   }
 }
 
-void Mir2Lir::GenConstClass(uint32_t type_idx, RegLocation rl_dest)
-{
+void Mir2Lir::GenConstClass(uint32_t type_idx, RegLocation rl_dest) {
   RegLocation rl_method = LoadCurrMethod();
   int res_reg = AllocTemp();
   RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
@@ -803,8 +784,7 @@
   }
 }
 
-void Mir2Lir::GenConstString(uint32_t string_idx, RegLocation rl_dest)
-{
+void Mir2Lir::GenConstString(uint32_t string_idx, RegLocation rl_dest) {
   /* NOTE: Most strings should be available at compile time */
   int32_t offset_of_string = mirror::Array::DataOffset(sizeof(mirror::String*)).Int32Value() +
                  (sizeof(mirror::String*) * string_idx);
@@ -860,8 +840,7 @@
  * Let helper function take care of everything.  Will
  * call Class::NewInstanceFromCode(type_idx, method);
  */
-void Mir2Lir::GenNewInstance(uint32_t type_idx, RegLocation rl_dest)
-{
+void Mir2Lir::GenNewInstance(uint32_t type_idx, RegLocation rl_dest) {
   FlushAllRegs();  /* Everything to home location */
   // alloc will always check for resolution, do we also need to verify
   // access because the verifier was unable to?
@@ -877,8 +856,7 @@
   StoreValue(rl_dest, rl_result);
 }
 
-void Mir2Lir::GenThrow(RegLocation rl_src)
-{
+void Mir2Lir::GenThrow(RegLocation rl_src) {
   FlushAllRegs();
   CallRuntimeHelperRegLocation(ENTRYPOINT_OFFSET(pDeliverException), rl_src, true);
 }
@@ -1065,8 +1043,7 @@
   }
 }
 
-void Mir2Lir::GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src)
-{
+void Mir2Lir::GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src) {
   bool type_known_final, type_known_abstract, use_declaring_class;
   bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx,
                                                                               *cu_->dex_file,
@@ -1142,8 +1119,7 @@
 }
 
 void Mir2Lir::GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest,
-                           RegLocation rl_src1, RegLocation rl_src2)
-{
+                           RegLocation rl_src1, RegLocation rl_src2) {
   RegLocation rl_result;
   if (cu_->instruction_set == kThumb2) {
     /*
@@ -1161,7 +1137,7 @@
   rl_src2 = LoadValueWide(rl_src2, kCoreReg);
   rl_result = EvalLoc(rl_dest, kCoreReg, true);
   // The longs may overlap - use intermediate temp if so
-  if ((rl_result.low_reg == rl_src1.high_reg) || (rl_result.low_reg == rl_src2.high_reg)){
+  if ((rl_result.low_reg == rl_src1.high_reg) || (rl_result.low_reg == rl_src2.high_reg)) {
     int t_reg = AllocTemp();
     OpRegRegReg(first_op, t_reg, rl_src1.low_reg, rl_src2.low_reg);
     OpRegRegReg(second_op, rl_result.high_reg, rl_src1.high_reg, rl_src2.high_reg);
@@ -1190,8 +1166,7 @@
 
 
 void Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest,
-                             RegLocation rl_src1, RegLocation rl_shift)
-{
+                             RegLocation rl_src1, RegLocation rl_shift) {
   int func_offset = -1; // Make gcc happy
 
   switch (opcode) {
@@ -1218,8 +1193,7 @@
 
 
 void Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest,
-                            RegLocation rl_src1, RegLocation rl_src2)
-{
+                            RegLocation rl_src1, RegLocation rl_src2) {
   OpKind op = kOpBkpt;
   bool is_div_rem = false;
   bool check_zero = false;
@@ -1353,14 +1327,12 @@
  * or produce corresponding Thumb instructions directly.
  */
 
-static bool IsPowerOfTwo(int x)
-{
+static bool IsPowerOfTwo(int x) {
   return (x & (x - 1)) == 0;
 }
 
 // Returns true if no more than two bits are set in 'x'.
-static bool IsPopCountLE2(unsigned int x)
-{
+static bool IsPopCountLE2(unsigned int x) {
   x &= x - 1;
   return (x & (x - 1)) == 0;
 }
@@ -1382,8 +1354,7 @@
 // Returns true if it added instructions to 'cu' to divide 'rl_src' by 'lit'
 // and store the result in 'rl_dest'.
 bool Mir2Lir::HandleEasyDivide(Instruction::Code dalvik_opcode,
-                               RegLocation rl_src, RegLocation rl_dest, int lit)
-{
+                               RegLocation rl_src, RegLocation rl_dest, int lit) {
   if ((lit < 2) || ((cu_->instruction_set != kThumb2) && !IsPowerOfTwo(lit))) {
     return false;
   }
@@ -1435,8 +1406,7 @@
 
 // Returns true if it added instructions to 'cu' to multiply 'rl_src' by 'lit'
 // and store the result in 'rl_dest'.
-bool Mir2Lir::HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit)
-{
+bool Mir2Lir::HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) {
   // Can we simplify this multiplication?
   bool power_of_two = false;
   bool pop_count_le2 = false;
@@ -1476,8 +1446,7 @@
 }
 
 void Mir2Lir::GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src,
-                               int lit)
-{
+                               int lit) {
   RegLocation rl_result;
   OpKind op = static_cast<OpKind>(0);    /* Make gcc happy */
   int shift_op = false;
@@ -1613,8 +1582,7 @@
 }
 
 void Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest,
-                             RegLocation rl_src1, RegLocation rl_src2)
-{
+                             RegLocation rl_src1, RegLocation rl_src2) {
   RegLocation rl_result;
   OpKind first_op = kOpBkpt;
   OpKind second_op = kOpBkpt;
@@ -1741,8 +1709,7 @@
 }
 
 void Mir2Lir::GenConversionCall(int func_offset,
-                                RegLocation rl_dest, RegLocation rl_src)
-{
+                                RegLocation rl_dest, RegLocation rl_src) {
   /*
    * Don't optimize the register usage since it calls out to support
    * functions
@@ -1767,8 +1734,7 @@
 }
 
 /* Check if we need to check for pending suspend request */
-void Mir2Lir::GenSuspendTest(int opt_flags)
-{
+void Mir2Lir::GenSuspendTest(int opt_flags) {
   if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) {
     return;
   }
@@ -1782,8 +1748,7 @@
 }
 
 /* Check if we need to check for pending suspend request */
-void Mir2Lir::GenSuspendTestAndBranch(int opt_flags, LIR* target)
-{
+void Mir2Lir::GenSuspendTestAndBranch(int opt_flags, LIR* target) {
   if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) {
     OpUnconditionalBranch(target);
     return;
diff --git a/compiler/dex/quick/gen_invoke.cc b/compiler/dex/quick/gen_invoke.cc
index e3993e0..14e395c 100644
--- a/compiler/dex/quick/gen_invoke.cc
+++ b/compiler/dex/quick/gen_invoke.cc
@@ -37,14 +37,12 @@
  * has a memory call operation, part 1 is a NOP for x86.  For other targets,
  * load arguments between the two parts.
  */
-int Mir2Lir::CallHelperSetup(int helper_offset)
-{
+int Mir2Lir::CallHelperSetup(int helper_offset) {
   return (cu_->instruction_set == kX86) ? 0 : LoadHelper(helper_offset);
 }
 
 /* NOTE: if r_tgt is a temp, it will be freed following use */
-LIR* Mir2Lir::CallHelper(int r_tgt, int helper_offset, bool safepoint_pc)
-{
+LIR* Mir2Lir::CallHelper(int r_tgt, int helper_offset, bool safepoint_pc) {
   LIR* call_inst;
   if (cu_->instruction_set == kX86) {
     call_inst = OpThreadMem(kOpBlx, helper_offset);
@@ -233,8 +231,7 @@
  * ArgLocs is an array of location records describing the incoming arguments
  * with one location record per word of argument.
  */
-void Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method)
-{
+void Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method) {
   /*
    * Dummy up a RegLocation for the incoming Method*
    * It will attempt to keep kArg0 live (or copy it to home location
@@ -316,8 +313,7 @@
                           int state, const MethodReference& target_method,
                           uint32_t unused,
                           uintptr_t direct_code, uintptr_t direct_method,
-                          InvokeType type)
-{
+                          InvokeType type) {
   Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get());
   if (cu->instruction_set != kThumb2) {
     // Disable sharpening
@@ -420,8 +416,7 @@
 static int NextVCallInsn(CompilationUnit* cu, CallInfo* info,
                          int state, const MethodReference& target_method,
                          uint32_t method_idx, uintptr_t unused, uintptr_t unused2,
-                         InvokeType unused3)
-{
+                         InvokeType unused3) {
   Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get());
   /*
    * This is the fast path in which the target virtual method is
@@ -469,8 +464,7 @@
 static int NextInterfaceCallInsn(CompilationUnit* cu, CallInfo* info, int state,
                                  const MethodReference& target_method,
                                  uint32_t unused, uintptr_t unused2,
-                                 uintptr_t direct_method, InvokeType unused4)
-{
+                                 uintptr_t direct_method, InvokeType unused4) {
   Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get());
   if (cu->instruction_set != kThumb2) {
     // Disable sharpening
@@ -536,8 +530,7 @@
 
 static int NextInvokeInsnSP(CompilationUnit* cu, CallInfo* info, int trampoline,
                             int state, const MethodReference& target_method,
-                            uint32_t method_idx)
-{
+                            uint32_t method_idx) {
   Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get());
   /*
    * This handles the case in which the base method is not fully
@@ -561,8 +554,7 @@
                                 const MethodReference& target_method,
                                 uint32_t method_idx,
                                 uintptr_t unused, uintptr_t unused2,
-                                InvokeType unused3)
-{
+                                InvokeType unused3) {
   int trampoline = ENTRYPOINT_OFFSET(pInvokeStaticTrampolineWithAccessCheck);
   return NextInvokeInsnSP(cu, info, trampoline, state, target_method, 0);
 }
@@ -570,8 +562,7 @@
 static int NextDirectCallInsnSP(CompilationUnit* cu, CallInfo* info, int state,
                                 const MethodReference& target_method,
                                 uint32_t method_idx, uintptr_t unused,
-                                uintptr_t unused2, InvokeType unused3)
-{
+                                uintptr_t unused2, InvokeType unused3) {
   int trampoline = ENTRYPOINT_OFFSET(pInvokeDirectTrampolineWithAccessCheck);
   return NextInvokeInsnSP(cu, info, trampoline, state, target_method, 0);
 }
@@ -579,8 +570,7 @@
 static int NextSuperCallInsnSP(CompilationUnit* cu, CallInfo* info, int state,
                                const MethodReference& target_method,
                                uint32_t method_idx, uintptr_t unused,
-                               uintptr_t unused2, InvokeType unused3)
-{
+                               uintptr_t unused2, InvokeType unused3) {
   int trampoline = ENTRYPOINT_OFFSET(pInvokeSuperTrampolineWithAccessCheck);
   return NextInvokeInsnSP(cu, info, trampoline, state, target_method, 0);
 }
@@ -588,8 +578,7 @@
 static int NextVCallInsnSP(CompilationUnit* cu, CallInfo* info, int state,
                            const MethodReference& target_method,
                            uint32_t method_idx, uintptr_t unused,
-                           uintptr_t unused2, InvokeType unused3)
-{
+                           uintptr_t unused2, InvokeType unused3) {
   int trampoline = ENTRYPOINT_OFFSET(pInvokeVirtualTrampolineWithAccessCheck);
   return NextInvokeInsnSP(cu, info, trampoline, state, target_method, 0);
 }
@@ -599,8 +588,7 @@
                                                 const MethodReference& target_method,
                                                 uint32_t unused,
                                                 uintptr_t unused2, uintptr_t unused3,
-                                                InvokeType unused4)
-{
+                                                InvokeType unused4) {
   int trampoline = ENTRYPOINT_OFFSET(pInvokeInterfaceTrampolineWithAccessCheck);
   return NextInvokeInsnSP(cu, info, trampoline, state, target_method, 0);
 }
@@ -609,8 +597,7 @@
                          NextCallInsn next_call_insn,
                          const MethodReference& target_method,
                          uint32_t vtable_idx, uintptr_t direct_code,
-                         uintptr_t direct_method, InvokeType type, bool skip_this)
-{
+                         uintptr_t direct_method, InvokeType type, bool skip_this) {
   int last_arg_reg = TargetReg(kArg3);
   int next_reg = TargetReg(kArg1);
   int next_arg = 0;
@@ -649,8 +636,7 @@
                                   int call_state, LIR** pcrLabel, NextCallInsn next_call_insn,
                                   const MethodReference& target_method,
                                   uint32_t vtable_idx, uintptr_t direct_code,
-                                  uintptr_t direct_method, InvokeType type, bool skip_this)
-{
+                                  uintptr_t direct_method, InvokeType type, bool skip_this) {
   RegLocation rl_arg;
 
   /* If no arguments, just return */
@@ -749,8 +735,7 @@
                                 LIR** pcrLabel, NextCallInsn next_call_insn,
                                 const MethodReference& target_method,
                                 uint32_t vtable_idx, uintptr_t direct_code, uintptr_t direct_method,
-                                InvokeType type, bool skip_this)
-{
+                                InvokeType type, bool skip_this) {
 
   // If we can treat it as non-range (Jumbo ops will use range form)
   if (info->num_arg_words <= 5)
@@ -833,8 +818,7 @@
   return call_state;
 }
 
-RegLocation Mir2Lir::InlineTarget(CallInfo* info)
-{
+RegLocation Mir2Lir::InlineTarget(CallInfo* info) {
   RegLocation res;
   if (info->result.location == kLocInvalid) {
     res = GetReturn(false);
@@ -844,8 +828,7 @@
   return res;
 }
 
-RegLocation Mir2Lir::InlineTargetWide(CallInfo* info)
-{
+RegLocation Mir2Lir::InlineTargetWide(CallInfo* info) {
   RegLocation res;
   if (info->result.location == kLocInvalid) {
     res = GetReturnWide(false);
@@ -855,8 +838,7 @@
   return res;
 }
 
-bool Mir2Lir::GenInlinedCharAt(CallInfo* info)
-{
+bool Mir2Lir::GenInlinedCharAt(CallInfo* info) {
   if (cu_->instruction_set == kMips) {
     // TODO - add Mips implementation
     return false;
@@ -932,8 +914,7 @@
 }
 
 // Generates an inlined String.is_empty or String.length.
-bool Mir2Lir::GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty)
-{
+bool Mir2Lir::GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty) {
   if (cu_->instruction_set == kMips) {
     // TODO - add Mips implementation
     return false;
@@ -961,8 +942,7 @@
   return true;
 }
 
-bool Mir2Lir::GenInlinedAbsInt(CallInfo* info)
-{
+bool Mir2Lir::GenInlinedAbsInt(CallInfo* info) {
   if (cu_->instruction_set == kMips) {
     // TODO - add Mips implementation
     return false;
@@ -980,8 +960,7 @@
   return true;
 }
 
-bool Mir2Lir::GenInlinedAbsLong(CallInfo* info)
-{
+bool Mir2Lir::GenInlinedAbsLong(CallInfo* info) {
   if (cu_->instruction_set == kMips) {
     // TODO - add Mips implementation
     return false;
@@ -1022,8 +1001,7 @@
   }
 }
 
-bool Mir2Lir::GenInlinedFloatCvt(CallInfo* info)
-{
+bool Mir2Lir::GenInlinedFloatCvt(CallInfo* info) {
   if (cu_->instruction_set == kMips) {
     // TODO - add Mips implementation
     return false;
@@ -1034,8 +1012,7 @@
   return true;
 }
 
-bool Mir2Lir::GenInlinedDoubleCvt(CallInfo* info)
-{
+bool Mir2Lir::GenInlinedDoubleCvt(CallInfo* info) {
   if (cu_->instruction_set == kMips) {
     // TODO - add Mips implementation
     return false;
@@ -1050,8 +1027,7 @@
  * Fast string.index_of(I) & (II).  Tests for simple case of char <= 0xffff,
  * otherwise bails to standard library code.
  */
-bool Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based)
-{
+bool Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) {
   if (cu_->instruction_set == kMips) {
     // TODO - add Mips implementation
     return false;
@@ -1094,8 +1070,7 @@
 }
 
 /* Fast string.compareTo(Ljava/lang/string;)I. */
-bool Mir2Lir::GenInlinedStringCompareTo(CallInfo* info)
-{
+bool Mir2Lir::GenInlinedStringCompareTo(CallInfo* info) {
   if (cu_->instruction_set == kMips) {
     // TODO - add Mips implementation
     return false;
@@ -1211,8 +1186,7 @@
   return true;
 }
 
-bool Mir2Lir::GenIntrinsic(CallInfo* info)
-{
+bool Mir2Lir::GenIntrinsic(CallInfo* info) {
   if (info->opt_flags & MIR_INLINED) {
     return false;
   }
@@ -1358,8 +1332,7 @@
   return false;
 }
 
-void Mir2Lir::GenInvoke(CallInfo* info)
-{
+void Mir2Lir::GenInvoke(CallInfo* info) {
   if (GenIntrinsic(info)) {
     return;
   }
diff --git a/compiler/dex/quick/gen_loadstore.cc b/compiler/dex/quick/gen_loadstore.cc
index 6a25c1d..3539106 100644
--- a/compiler/dex/quick/gen_loadstore.cc
+++ b/compiler/dex/quick/gen_loadstore.cc
@@ -27,8 +27,7 @@
  * Load an immediate value into a fixed or temp register.  Target
  * register is clobbered, and marked in_use.
  */
-LIR* Mir2Lir::LoadConstant(int r_dest, int value)
-{
+LIR* Mir2Lir::LoadConstant(int r_dest, int value) {
   if (IsTemp(r_dest)) {
     Clobber(r_dest);
     MarkInUse(r_dest);
@@ -41,8 +40,7 @@
  * promoted floating point register, also copy a zero into the int/ref identity of
  * that sreg.
  */
-void Mir2Lir::Workaround7250540(RegLocation rl_dest, int zero_reg)
-{
+void Mir2Lir::Workaround7250540(RegLocation rl_dest, int zero_reg) {
   if (rl_dest.fp) {
     int pmap_index = SRegToPMap(rl_dest.s_reg_low);
     if (promotion_map_[pmap_index].fp_location == kLocPhysReg) {
@@ -77,14 +75,12 @@
 }
 
 /* Load a word at base + displacement.  Displacement must be word multiple */
-LIR* Mir2Lir::LoadWordDisp(int rBase, int displacement, int r_dest)
-{
+LIR* Mir2Lir::LoadWordDisp(int rBase, int displacement, int r_dest) {
   return LoadBaseDisp(rBase, displacement, r_dest, kWord,
                       INVALID_SREG);
 }
 
-LIR* Mir2Lir::StoreWordDisp(int rBase, int displacement, int r_src)
-{
+LIR* Mir2Lir::StoreWordDisp(int rBase, int displacement, int r_src) {
   return StoreBaseDisp(rBase, displacement, r_src, kWord);
 }
 
@@ -93,8 +89,7 @@
  * using this routine, as it doesn't perform any bookkeeping regarding
  * register liveness.  That is the responsibility of the caller.
  */
-void Mir2Lir::LoadValueDirect(RegLocation rl_src, int r_dest)
-{
+void Mir2Lir::LoadValueDirect(RegLocation rl_src, int r_dest) {
   rl_src = UpdateLoc(rl_src);
   if (rl_src.location == kLocPhysReg) {
     OpRegCopy(r_dest, rl_src.low_reg);
@@ -112,8 +107,7 @@
  * register.  Should be used when loading to a fixed register (for example,
  * loading arguments to an out of line call.
  */
-void Mir2Lir::LoadValueDirectFixed(RegLocation rl_src, int r_dest)
-{
+void Mir2Lir::LoadValueDirectFixed(RegLocation rl_src, int r_dest) {
   Clobber(r_dest);
   MarkInUse(r_dest);
   LoadValueDirect(rl_src, r_dest);
@@ -125,8 +119,7 @@
  * register liveness.  That is the responsibility of the caller.
  */
 void Mir2Lir::LoadValueDirectWide(RegLocation rl_src, int reg_lo,
-             int reg_hi)
-{
+             int reg_hi) {
   rl_src = UpdateLocWide(rl_src);
   if (rl_src.location == kLocPhysReg) {
     OpRegCopyWide(reg_lo, reg_hi, rl_src.low_reg, rl_src.high_reg);
@@ -146,8 +139,7 @@
  * loading arguments to an out of line call.
  */
 void Mir2Lir::LoadValueDirectWideFixed(RegLocation rl_src, int reg_lo,
-                                       int reg_hi)
-{
+                                       int reg_hi) {
   Clobber(reg_lo);
   Clobber(reg_hi);
   MarkInUse(reg_lo);
@@ -155,8 +147,7 @@
   LoadValueDirectWide(rl_src, reg_lo, reg_hi);
 }
 
-RegLocation Mir2Lir::LoadValue(RegLocation rl_src, RegisterClass op_kind)
-{
+RegLocation Mir2Lir::LoadValue(RegLocation rl_src, RegisterClass op_kind) {
   rl_src = EvalLoc(rl_src, op_kind, false);
   if (IsInexpensiveConstant(rl_src) || rl_src.location != kLocPhysReg) {
     LoadValueDirect(rl_src, rl_src.low_reg);
@@ -166,8 +157,7 @@
   return rl_src;
 }
 
-void Mir2Lir::StoreValue(RegLocation rl_dest, RegLocation rl_src)
-{
+void Mir2Lir::StoreValue(RegLocation rl_dest, RegLocation rl_src) {
   /*
    * Sanity checking - should never try to store to the same
    * ssa name during the compilation of a single instruction
@@ -222,8 +212,7 @@
   }
 }
 
-RegLocation Mir2Lir::LoadValueWide(RegLocation rl_src, RegisterClass op_kind)
-{
+RegLocation Mir2Lir::LoadValueWide(RegLocation rl_src, RegisterClass op_kind) {
   DCHECK(rl_src.wide);
   rl_src = EvalLoc(rl_src, op_kind, false);
   if (IsInexpensiveConstant(rl_src) || rl_src.location != kLocPhysReg) {
@@ -235,8 +224,7 @@
   return rl_src;
 }
 
-void Mir2Lir::StoreValueWide(RegLocation rl_dest, RegLocation rl_src)
-{
+void Mir2Lir::StoreValueWide(RegLocation rl_dest, RegLocation rl_src) {
   /*
    * Sanity checking - should never try to store to the same
    * ssa name during the compilation of a single instruction
@@ -299,13 +287,11 @@
 }
 
 /* Utilities to load the current Method* */
-void Mir2Lir::LoadCurrMethodDirect(int r_tgt)
-{
+void Mir2Lir::LoadCurrMethodDirect(int r_tgt) {
   LoadValueDirectFixed(mir_graph_->GetMethodLoc(), r_tgt);
 }
 
-RegLocation Mir2Lir::LoadCurrMethod()
-{
+RegLocation Mir2Lir::LoadCurrMethod() {
   return LoadValue(mir_graph_->GetMethodLoc(), kCoreReg);
 }
 
diff --git a/compiler/dex/quick/local_optimizations.cc b/compiler/dex/quick/local_optimizations.cc
index ac654d8..eb27bf8 100644
--- a/compiler/dex/quick/local_optimizations.cc
+++ b/compiler/dex/quick/local_optimizations.cc
@@ -29,8 +29,7 @@
 #define LDLD_DISTANCE 4
 #define LD_LATENCY 2
 
-static bool IsDalvikRegisterClobbered(LIR* lir1, LIR* lir2)
-{
+static bool IsDalvikRegisterClobbered(LIR* lir1, LIR* lir2) {
   int reg1Lo = DECODE_ALIAS_INFO_REG(lir1->alias_info);
   int reg1Hi = reg1Lo + DECODE_ALIAS_INFO_WIDE(lir1->alias_info);
   int reg2Lo = DECODE_ALIAS_INFO_REG(lir2->alias_info);
@@ -40,8 +39,7 @@
 }
 
 /* Convert a more expensive instruction (ie load) into a move */
-void Mir2Lir::ConvertMemOpIntoMove(LIR* orig_lir, int dest, int src)
-{
+void Mir2Lir::ConvertMemOpIntoMove(LIR* orig_lir, int dest, int src) {
   /* Insert a move to replace the load */
   LIR* move_lir;
   move_lir = OpRegCopyNoInsert(dest, src);
@@ -72,8 +70,7 @@
  *   1) They are must-aliases
  *   2) The memory location is not written to in between
  */
-void Mir2Lir::ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir)
-{
+void Mir2Lir::ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir) {
   LIR* this_lir;
 
   if (head_lir == tail_lir) return;
@@ -268,8 +265,7 @@
  * Perform a pass of bottom-up walk, from the second instruction in the
  * superblock, to try to hoist loads to earlier slots.
  */
-void Mir2Lir::ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir)
-{
+void Mir2Lir::ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir) {
   LIR* this_lir, *check_lir;
   /*
    * Store the list of independent instructions that can be hoisted past.
@@ -447,8 +443,7 @@
   }
 }
 
-void Mir2Lir::ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir)
-{
+void Mir2Lir::ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir) {
   if (!(cu_->disable_opt & (1 << kLoadStoreElimination))) {
     ApplyLoadStoreElimination(head_lir, tail_lir);
   }
@@ -462,8 +457,7 @@
  * Note: new redundant branches may be inserted later, and we'll
  * use a check in final instruction assembly to nop those out.
  */
-void Mir2Lir::RemoveRedundantBranches()
-{
+void Mir2Lir::RemoveRedundantBranches() {
   LIR* this_lir;
 
   for (this_lir = first_lir_insn_; this_lir != last_lir_insn_; this_lir = NEXT_LIR(this_lir)) {
diff --git a/compiler/dex/quick/mips/assemble_mips.cc b/compiler/dex/quick/mips/assemble_mips.cc
index 2482aa4..dcfb13f 100644
--- a/compiler/dex/quick/mips/assemble_mips.cc
+++ b/compiler/dex/quick/mips/assemble_mips.cc
@@ -457,8 +457,7 @@
  * NOTE: An out-of-range bal isn't supported because it should
  * never happen with the current PIC model.
  */
-void MipsMir2Lir::ConvertShortToLongBranch(LIR* lir)
-{
+void MipsMir2Lir::ConvertShortToLongBranch(LIR* lir) {
   // For conditional branches we'll need to reverse the sense
   bool unconditional = false;
   int opcode = lir->opcode;
@@ -513,8 +512,7 @@
  * instruction.  In those cases we will try to substitute a new code
  * sequence or request that the trace be shortened and retried.
  */
-AssemblerStatus MipsMir2Lir::AssembleInstructions(uintptr_t start_addr)
-{
+AssemblerStatus MipsMir2Lir::AssembleInstructions(uintptr_t start_addr) {
   LIR *lir;
   AssemblerStatus res = kSuccess;  // Assume success
 
@@ -708,8 +706,7 @@
   return res;
 }
 
-int MipsMir2Lir::GetInsnSize(LIR* lir)
-{
+int MipsMir2Lir::GetInsnSize(LIR* lir) {
   return EncodingMap[lir->opcode].size;
 }
 
diff --git a/compiler/dex/quick/mips/call_mips.cc b/compiler/dex/quick/mips/call_mips.cc
index eb0302e..db57643 100644
--- a/compiler/dex/quick/mips/call_mips.cc
+++ b/compiler/dex/quick/mips/call_mips.cc
@@ -24,8 +24,7 @@
 namespace art {
 
 void MipsMir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir,
-                                 SpecialCaseHandler special_case)
-{
+                                 SpecialCaseHandler special_case) {
     // TODO
 }
 
@@ -61,8 +60,7 @@
  *
  */
 void MipsMir2Lir::GenSparseSwitch(MIR* mir, uint32_t table_offset,
-                                  RegLocation rl_src)
-{
+                                  RegLocation rl_src) {
   const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
   if (cu_->verbose) {
     DumpSparseSwitchTable(table);
@@ -142,8 +140,7 @@
  * done:
  */
 void MipsMir2Lir::GenPackedSwitch(MIR* mir, uint32_t table_offset,
-                                  RegLocation rl_src)
-{
+                                  RegLocation rl_src) {
   const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
   if (cu_->verbose) {
     DumpPackedSwitchTable(table);
@@ -227,8 +224,7 @@
  *
  * Total size is 4+(width * size + 1)/2 16-bit code units.
  */
-void MipsMir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src)
-{
+void MipsMir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src) {
   const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
   // Add the table to the list - we'll process it later
   FillArrayData *tab_rec =
@@ -270,8 +266,7 @@
 /*
  * TODO: implement fast path to short-circuit thin-lock case
  */
-void MipsMir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src)
-{
+void MipsMir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) {
   FlushAllRegs();
   LoadValueDirectFixed(rl_src, rMIPS_ARG0);  // Get obj
   LockCallTemps();  // Prepare for explicit register usage
@@ -286,8 +281,7 @@
 /*
  * TODO: implement fast path to short-circuit thin-lock case
  */
-void MipsMir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src)
-{
+void MipsMir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) {
   FlushAllRegs();
   LoadValueDirectFixed(rl_src, rMIPS_ARG0);  // Get obj
   LockCallTemps();  // Prepare for explicit register usage
@@ -299,8 +293,7 @@
   MarkSafepointPC(call_inst);
 }
 
-void MipsMir2Lir::GenMoveException(RegLocation rl_dest)
-{
+void MipsMir2Lir::GenMoveException(RegLocation rl_dest) {
   int ex_offset = Thread::ExceptionOffset().Int32Value();
   RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
   int reset_reg = AllocTemp();
@@ -314,8 +307,7 @@
 /*
  * Mark garbage collection card. Skip if the value we're storing is null.
  */
-void MipsMir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg)
-{
+void MipsMir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg) {
   int reg_card_base = AllocTemp();
   int reg_card_no = AllocTemp();
   LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL);
@@ -328,8 +320,7 @@
   FreeTemp(reg_card_base);
   FreeTemp(reg_card_no);
 }
-void MipsMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method)
-{
+void MipsMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) {
   int spill_count = num_core_spills_ + num_fp_spills_;
   /*
    * On entry, rMIPS_ARG0, rMIPS_ARG1, rMIPS_ARG2 & rMIPS_ARG3 are live.  Let the register
@@ -375,8 +366,7 @@
   FreeTemp(rMIPS_ARG3);
 }
 
-void MipsMir2Lir::GenExitSequence()
-{
+void MipsMir2Lir::GenExitSequence() {
   /*
    * In the exit path, rMIPS_RET0/rMIPS_RET1 are live - make sure they aren't
    * allocated by the register utilities as temps.
diff --git a/compiler/dex/quick/mips/fp_mips.cc b/compiler/dex/quick/mips/fp_mips.cc
index 8581d5b..2e744a2 100644
--- a/compiler/dex/quick/mips/fp_mips.cc
+++ b/compiler/dex/quick/mips/fp_mips.cc
@@ -22,8 +22,7 @@
 namespace art {
 
 void MipsMir2Lir::GenArithOpFloat(Instruction::Code opcode,
-                                  RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
-{
+                                  RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
   int op = kMipsNop;
   RegLocation rl_result;
 
@@ -69,8 +68,7 @@
 }
 
 void MipsMir2Lir::GenArithOpDouble(Instruction::Code opcode,
-                                   RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
-{
+                                   RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
   int op = kMipsNop;
   RegLocation rl_result;
 
@@ -117,8 +115,7 @@
 }
 
 void MipsMir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest,
-                                RegLocation rl_src)
-{
+                                RegLocation rl_src) {
   int op = kMipsNop;
   int src_reg;
   RegLocation rl_result;
@@ -175,8 +172,7 @@
 }
 
 void MipsMir2Lir::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest,
-                           RegLocation rl_src1, RegLocation rl_src2)
-{
+                           RegLocation rl_src1, RegLocation rl_src2) {
   bool wide = true;
   int offset = -1; // Make gcc happy.
 
@@ -215,13 +211,11 @@
 }
 
 void MipsMir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir,
-                                bool gt_bias, bool is_double)
-{
+                                bool gt_bias, bool is_double) {
   UNIMPLEMENTED(FATAL) << "Need codegen for fused fp cmp branch";
 }
 
-void MipsMir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src)
-{
+void MipsMir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src) {
   RegLocation rl_result;
   rl_src = LoadValue(rl_src, kCoreReg);
   rl_result = EvalLoc(rl_dest, kCoreReg, true);
@@ -229,8 +223,7 @@
   StoreValue(rl_dest, rl_result);
 }
 
-void MipsMir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src)
-{
+void MipsMir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src) {
   RegLocation rl_result;
   rl_src = LoadValueWide(rl_src, kCoreReg);
   rl_result = EvalLoc(rl_dest, kCoreReg, true);
@@ -239,8 +232,7 @@
   StoreValueWide(rl_dest, rl_result);
 }
 
-bool MipsMir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min)
-{
+bool MipsMir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min) {
   // TODO: need Mips implementation
   return false;
 }
diff --git a/compiler/dex/quick/mips/int_mips.cc b/compiler/dex/quick/mips/int_mips.cc
index 8bfc4e1..03a58cc 100644
--- a/compiler/dex/quick/mips/int_mips.cc
+++ b/compiler/dex/quick/mips/int_mips.cc
@@ -41,8 +41,7 @@
  *
  */
 void MipsMir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1,
-                             RegLocation rl_src2)
-{
+                             RegLocation rl_src2) {
   rl_src1 = LoadValueWide(rl_src1, kCoreReg);
   rl_src2 = LoadValueWide(rl_src2, kCoreReg);
   int t0 = AllocTemp();
@@ -63,8 +62,7 @@
 }
 
 LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, int src1, int src2,
-                              LIR* target)
-{
+                              LIR* target) {
   LIR* branch;
   MipsOpCode slt_op;
   MipsOpCode br_op;
@@ -131,8 +129,7 @@
 }
 
 LIR* MipsMir2Lir::OpCmpImmBranch(ConditionCode cond, int reg,
-                                 int check_value, LIR* target)
-{
+                                 int check_value, LIR* target) {
   LIR* branch;
   if (check_value != 0) {
     // TUNING: handle s16 & kCondLt/Mi case using slti
@@ -164,8 +161,7 @@
   return branch;
 }
 
-LIR* MipsMir2Lir::OpRegCopyNoInsert(int r_dest, int r_src)
-{
+LIR* MipsMir2Lir::OpRegCopyNoInsert(int r_dest, int r_src) {
   if (MIPS_FPREG(r_dest) || MIPS_FPREG(r_src))
     return OpFpRegCopy(r_dest, r_src);
   LIR* res = RawLIR(current_dalvik_offset_, kMipsMove,
@@ -176,16 +172,14 @@
   return res;
 }
 
-LIR* MipsMir2Lir::OpRegCopy(int r_dest, int r_src)
-{
+LIR* MipsMir2Lir::OpRegCopy(int r_dest, int r_src) {
   LIR *res = OpRegCopyNoInsert(r_dest, r_src);
   AppendLIR(res);
   return res;
 }
 
 void MipsMir2Lir::OpRegCopyWide(int dest_lo, int dest_hi, int src_lo,
-                                int src_hi)
-{
+                                int src_hi) {
   bool dest_fp = MIPS_FPREG(dest_lo) && MIPS_FPREG(dest_hi);
   bool src_fp = MIPS_FPREG(src_lo) && MIPS_FPREG(src_hi);
   assert(MIPS_FPREG(src_lo) == MIPS_FPREG(src_hi));
@@ -215,26 +209,22 @@
   }
 }
 
-void MipsMir2Lir::GenSelect(BasicBlock* bb, MIR* mir)
-{
+void MipsMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) {
   UNIMPLEMENTED(FATAL) << "Need codegen for select";
 }
 
-void MipsMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir)
-{
+void MipsMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) {
   UNIMPLEMENTED(FATAL) << "Need codegen for fused long cmp branch";
 }
 
 LIR* MipsMir2Lir::GenRegMemCheck(ConditionCode c_code,
-                    int reg1, int base, int offset, ThrowKind kind)
-{
+                    int reg1, int base, int offset, ThrowKind kind) {
   LOG(FATAL) << "Unexpected use of GenRegMemCheck for Arm";
   return NULL;
 }
 
 RegLocation MipsMir2Lir::GenDivRem(RegLocation rl_dest, int reg1, int reg2,
-                                    bool is_div)
-{
+                                    bool is_div) {
   NewLIR4(kMipsDiv, r_HI, r_LO, reg1, reg2);
   RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
   if (is_div) {
@@ -246,8 +236,7 @@
 }
 
 RegLocation MipsMir2Lir::GenDivRemLit(RegLocation rl_dest, int reg1, int lit,
-                                       bool is_div)
-{
+                                       bool is_div) {
   int t_reg = AllocTemp();
   NewLIR3(kMipsAddiu, t_reg, r_ZERO, lit);
   NewLIR4(kMipsDiv, r_HI, r_LO, reg1, t_reg);
@@ -261,13 +250,11 @@
   return rl_result;
 }
 
-void MipsMir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset)
-{
+void MipsMir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) {
   LOG(FATAL) << "Unexpected use of OpLea for Arm";
 }
 
-void MipsMir2Lir::OpTlsCmp(int offset, int val)
-{
+void MipsMir2Lir::OpTlsCmp(int offset, int val) {
   LOG(FATAL) << "Unexpected use of OpTlsCmp for Arm";
 }
 
@@ -286,22 +273,19 @@
   return NULL;
 }
 
-LIR* MipsMir2Lir::OpVldm(int rBase, int count)
-{
+LIR* MipsMir2Lir::OpVldm(int rBase, int count) {
   LOG(FATAL) << "Unexpected use of OpVldm for Mips";
   return NULL;
 }
 
-LIR* MipsMir2Lir::OpVstm(int rBase, int count)
-{
+LIR* MipsMir2Lir::OpVstm(int rBase, int count) {
   LOG(FATAL) << "Unexpected use of OpVstm for Mips";
   return NULL;
 }
 
 void MipsMir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src,
                                                 RegLocation rl_result, int lit,
-                                                int first_bit, int second_bit)
-{
+                                                int first_bit, int second_bit) {
   int t_reg = AllocTemp();
   OpRegRegImm(kOpLsl, t_reg, rl_src.low_reg, second_bit - first_bit);
   OpRegRegReg(kOpAdd, rl_result.low_reg, rl_src.low_reg, t_reg);
@@ -311,8 +295,7 @@
   }
 }
 
-void MipsMir2Lir::GenDivZeroCheck(int reg_lo, int reg_hi)
-{
+void MipsMir2Lir::GenDivZeroCheck(int reg_lo, int reg_hi) {
   int t_reg = AllocTemp();
   OpRegRegReg(kOpOr, t_reg, reg_lo, reg_hi);
   GenImmedCheck(kCondEq, t_reg, 0, kThrowDivZero);
@@ -320,41 +303,35 @@
 }
 
 // Test suspend flag, return target of taken suspend branch
-LIR* MipsMir2Lir::OpTestSuspend(LIR* target)
-{
+LIR* MipsMir2Lir::OpTestSuspend(LIR* target) {
   OpRegImm(kOpSub, rMIPS_SUSPEND, 1);
   return OpCmpImmBranch((target == NULL) ? kCondEq : kCondNe, rMIPS_SUSPEND, 0, target);
 }
 
 // Decrement register and branch on condition
-LIR* MipsMir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target)
-{
+LIR* MipsMir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) {
   OpRegImm(kOpSub, reg, 1);
   return OpCmpImmBranch(c_code, reg, 0, target);
 }
 
 bool MipsMir2Lir::SmallLiteralDivide(Instruction::Code dalvik_opcode,
-                                     RegLocation rl_src, RegLocation rl_dest, int lit)
-{
+                                     RegLocation rl_src, RegLocation rl_dest, int lit) {
   LOG(FATAL) << "Unexpected use of smallLiteralDive in Mips";
   return false;
 }
 
-LIR* MipsMir2Lir::OpIT(ConditionCode cond, const char* guide)
-{
+LIR* MipsMir2Lir::OpIT(ConditionCode cond, const char* guide) {
   LOG(FATAL) << "Unexpected use of OpIT in Mips";
   return NULL;
 }
 
 void MipsMir2Lir::GenMulLong(RegLocation rl_dest, RegLocation rl_src1,
-                             RegLocation rl_src2)
-{
+                             RegLocation rl_src2) {
   LOG(FATAL) << "Unexpected use of GenMulLong for Mips";
 }
 
 void MipsMir2Lir::GenAddLong(RegLocation rl_dest, RegLocation rl_src1,
-                             RegLocation rl_src2)
-{
+                             RegLocation rl_src2) {
   rl_src1 = LoadValueWide(rl_src1, kCoreReg);
   rl_src2 = LoadValueWide(rl_src2, kCoreReg);
   RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
@@ -376,8 +353,7 @@
 }
 
 void MipsMir2Lir::GenSubLong(RegLocation rl_dest, RegLocation rl_src1,
-                             RegLocation rl_src2)
-{
+                             RegLocation rl_src2) {
   rl_src1 = LoadValueWide(rl_src1, kCoreReg);
   rl_src2 = LoadValueWide(rl_src2, kCoreReg);
   RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
@@ -398,8 +374,7 @@
   StoreValueWide(rl_dest, rl_result);
 }
 
-void MipsMir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src)
-{
+void MipsMir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) {
   rl_src = LoadValueWide(rl_src, kCoreReg);
   RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
   /*
@@ -420,20 +395,17 @@
 }
 
 void MipsMir2Lir::GenAndLong(RegLocation rl_dest, RegLocation rl_src1,
-                             RegLocation rl_src2)
-{
+                             RegLocation rl_src2) {
   LOG(FATAL) << "Unexpected use of GenAndLong for Mips";
 }
 
 void MipsMir2Lir::GenOrLong(RegLocation rl_dest, RegLocation rl_src1,
-                            RegLocation rl_src2)
-{
+                            RegLocation rl_src2) {
   LOG(FATAL) << "Unexpected use of GenOrLong for Mips";
 }
 
 void MipsMir2Lir::GenXorLong(RegLocation rl_dest, RegLocation rl_src1,
-                             RegLocation rl_src2)
-{
+                             RegLocation rl_src2) {
   LOG(FATAL) << "Unexpected use of GenXorLong for Mips";
 }
 
@@ -441,8 +413,7 @@
  * Generate array load
  */
 void MipsMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
-                          RegLocation rl_index, RegLocation rl_dest, int scale)
-{
+                          RegLocation rl_index, RegLocation rl_dest, int scale) {
   RegisterClass reg_class = oat_reg_class_by_size(size);
   int len_offset = mirror::Array::LengthOffset().Int32Value();
   int data_offset;
@@ -513,8 +484,7 @@
  *
  */
 void MipsMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
-                          RegLocation rl_index, RegLocation rl_src, int scale)
-{
+                          RegLocation rl_index, RegLocation rl_src, int scale) {
   RegisterClass reg_class = oat_reg_class_by_size(size);
   int len_offset = mirror::Array::LengthOffset().Int32Value();
   int data_offset;
@@ -586,8 +556,7 @@
  *
  */
 void MipsMir2Lir::GenArrayObjPut(int opt_flags, RegLocation rl_array,
-                             RegLocation rl_index, RegLocation rl_src, int scale)
-{
+                             RegLocation rl_index, RegLocation rl_src, int scale) {
   int len_offset = mirror::Array::LengthOffset().Int32Value();
   int data_offset = mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value();
 
@@ -643,15 +612,13 @@
 }
 
 void MipsMir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
-                                    RegLocation rl_src1, RegLocation rl_shift)
-{
+                                    RegLocation rl_src1, RegLocation rl_shift) {
   // Default implementation is just to ignore the constant case.
   GenShiftOpLong(opcode, rl_dest, rl_src1, rl_shift);
 }
 
 void MipsMir2Lir::GenArithImmOpLong(Instruction::Code opcode,
-                                    RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
-{
+                                    RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
   // Default - bail to non-const handler.
   GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2);
 }
diff --git a/compiler/dex/quick/mips/target_mips.cc b/compiler/dex/quick/mips/target_mips.cc
index cab2c1b..bd20e00 100644
--- a/compiler/dex/quick/mips/target_mips.cc
+++ b/compiler/dex/quick/mips/target_mips.cc
@@ -36,26 +36,22 @@
 static int fp_temps[] = {r_F0, r_F1, r_F2, r_F3, r_F4, r_F5, r_F6, r_F7,
                          r_F8, r_F9, r_F10, r_F11, r_F12, r_F13, r_F14, r_F15};
 
-RegLocation MipsMir2Lir::LocCReturn()
-{
+RegLocation MipsMir2Lir::LocCReturn() {
   RegLocation res = MIPS_LOC_C_RETURN;
   return res;
 }
 
-RegLocation MipsMir2Lir::LocCReturnWide()
-{
+RegLocation MipsMir2Lir::LocCReturnWide() {
   RegLocation res = MIPS_LOC_C_RETURN_WIDE;
   return res;
 }
 
-RegLocation MipsMir2Lir::LocCReturnFloat()
-{
+RegLocation MipsMir2Lir::LocCReturnFloat() {
   RegLocation res = MIPS_LOC_C_RETURN_FLOAT;
   return res;
 }
 
-RegLocation MipsMir2Lir::LocCReturnDouble()
-{
+RegLocation MipsMir2Lir::LocCReturnDouble() {
   RegLocation res = MIPS_LOC_C_RETURN_DOUBLE;
   return res;
 }
@@ -86,28 +82,24 @@
 }
 
 // Create a double from a pair of singles.
-int MipsMir2Lir::S2d(int low_reg, int high_reg)
-{
+int MipsMir2Lir::S2d(int low_reg, int high_reg) {
   return MIPS_S2D(low_reg, high_reg);
 }
 
 // Return mask to strip off fp reg flags and bias.
-uint32_t MipsMir2Lir::FpRegMask()
-{
+uint32_t MipsMir2Lir::FpRegMask() {
   return MIPS_FP_REG_MASK;
 }
 
 // True if both regs single, both core or both double.
-bool MipsMir2Lir::SameRegType(int reg1, int reg2)
-{
+bool MipsMir2Lir::SameRegType(int reg1, int reg2) {
   return (MIPS_REGTYPE(reg1) == MIPS_REGTYPE(reg2));
 }
 
 /*
  * Decode the register id.
  */
-uint64_t MipsMir2Lir::GetRegMaskCommon(int reg)
-{
+uint64_t MipsMir2Lir::GetRegMaskCommon(int reg) {
   uint64_t seed;
   int shift;
   int reg_id;
@@ -123,14 +115,12 @@
   return (seed << shift);
 }
 
-uint64_t MipsMir2Lir::GetPCUseDefEncoding()
-{
+uint64_t MipsMir2Lir::GetPCUseDefEncoding() {
   return ENCODE_MIPS_REG_PC;
 }
 
 
-void MipsMir2Lir::SetupTargetResourceMasks(LIR* lir)
-{
+void MipsMir2Lir::SetupTargetResourceMasks(LIR* lir) {
   DCHECK_EQ(cu_->instruction_set, kMips);
 
   // Mips-specific resource map setup here.
@@ -162,8 +152,7 @@
  * Interpret a format string and build a string no longer than size
  * See format key in Assemble.c.
  */
-std::string MipsMir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr)
-{
+std::string MipsMir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) {
   std::string buf;
   int i;
   const char *fmt_end = &fmt[strlen(fmt)];
@@ -255,8 +244,7 @@
 }
 
 // FIXME: need to redo resource maps for MIPS - fix this at that time
-void MipsMir2Lir::DumpResourceMask(LIR *mips_lir, uint64_t mask, const char *prefix)
-{
+void MipsMir2Lir::DumpResourceMask(LIR *mips_lir, uint64_t mask, const char *prefix) {
   char buf[256];
   buf[0] = 0;
 
@@ -306,8 +294,7 @@
  * machinery is in place, always spill lr.
  */
 
-void MipsMir2Lir::AdjustSpillMask()
-{
+void MipsMir2Lir::AdjustSpillMask() {
   core_spill_mask_ |= (1 << r_RA);
   num_core_spills_++;
 }
@@ -318,13 +305,11 @@
  * include any holes in the mask.  Associate holes with
  * Dalvik register INVALID_VREG (0xFFFFU).
  */
-void MipsMir2Lir::MarkPreservedSingle(int s_reg, int reg)
-{
+void MipsMir2Lir::MarkPreservedSingle(int s_reg, int reg) {
   LOG(FATAL) << "No support yet for promoted FP regs";
 }
 
-void MipsMir2Lir::FlushRegWide(int reg1, int reg2)
-{
+void MipsMir2Lir::FlushRegWide(int reg1, int reg2) {
   RegisterInfo* info1 = GetRegInfo(reg1);
   RegisterInfo* info2 = GetRegInfo(reg2);
   DCHECK(info1 && info2 && info1->pair && info2->pair &&
@@ -345,8 +330,7 @@
   }
 }
 
-void MipsMir2Lir::FlushReg(int reg)
-{
+void MipsMir2Lir::FlushReg(int reg) {
   RegisterInfo* info = GetRegInfo(reg);
   if (info->live && info->dirty) {
     info->dirty = false;
@@ -361,8 +345,7 @@
 }
 
 /* Clobber all regs that might be used by an external C call */
-void MipsMir2Lir::ClobberCalleeSave()
-{
+void MipsMir2Lir::ClobberCalleeSave() {
   Clobber(r_ZERO);
   Clobber(r_AT);
   Clobber(r_V0);
@@ -404,29 +387,25 @@
   Clobber(r_F15);
 }
 
-RegLocation MipsMir2Lir::GetReturnWideAlt()
-{
+RegLocation MipsMir2Lir::GetReturnWideAlt() {
   UNIMPLEMENTED(FATAL) << "No GetReturnWideAlt for MIPS";
   RegLocation res = LocCReturnWide();
   return res;
 }
 
-RegLocation MipsMir2Lir::GetReturnAlt()
-{
+RegLocation MipsMir2Lir::GetReturnAlt() {
   UNIMPLEMENTED(FATAL) << "No GetReturnAlt for MIPS";
   RegLocation res = LocCReturn();
   return res;
 }
 
-MipsMir2Lir::RegisterInfo* MipsMir2Lir::GetRegInfo(int reg)
-{
+MipsMir2Lir::RegisterInfo* MipsMir2Lir::GetRegInfo(int reg) {
   return MIPS_FPREG(reg) ? &reg_pool_->FPRegs[reg & MIPS_FP_REG_MASK]
             : &reg_pool_->core_regs[reg];
 }
 
 /* To be used when explicitly managing register use */
-void MipsMir2Lir::LockCallTemps()
-{
+void MipsMir2Lir::LockCallTemps() {
   LockTemp(rMIPS_ARG0);
   LockTemp(rMIPS_ARG1);
   LockTemp(rMIPS_ARG2);
@@ -434,16 +413,14 @@
 }
 
 /* To be used when explicitly managing register use */
-void MipsMir2Lir::FreeCallTemps()
-{
+void MipsMir2Lir::FreeCallTemps() {
   FreeTemp(rMIPS_ARG0);
   FreeTemp(rMIPS_ARG1);
   FreeTemp(rMIPS_ARG2);
   FreeTemp(rMIPS_ARG3);
 }
 
-void MipsMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind)
-{
+void MipsMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) {
 #if ANDROID_SMP != 0
   NewLIR1(kMipsSync, 0 /* Only stype currently supported */);
 #endif
@@ -454,8 +431,7 @@
  * high reg in next byte.
  */
 int MipsMir2Lir::AllocTypedTempPair(bool fp_hint,
-                  int reg_class)
-{
+                  int reg_class) {
   int high_reg;
   int low_reg;
   int res = 0;
@@ -473,17 +449,14 @@
   return res;
 }
 
-int MipsMir2Lir::AllocTypedTemp(bool fp_hint, int reg_class)
-{
-  if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg))
-{
+int MipsMir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) {
+  if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) {
     return AllocTempFloat();
 }
   return AllocTemp();
 }
 
-void MipsMir2Lir::CompilerInitializeRegAlloc()
-{
+void MipsMir2Lir::CompilerInitializeRegAlloc() {
   int num_regs = sizeof(core_regs)/sizeof(*core_regs);
   int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs);
   int num_temps = sizeof(core_temps)/sizeof(*core_temps);
@@ -518,8 +491,7 @@
   }
 }
 
-void MipsMir2Lir::FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free)
-{
+void MipsMir2Lir::FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) {
   if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) &&
     (rl_free.high_reg != rl_keep.low_reg) && (rl_free.high_reg != rl_keep.high_reg)) {
     // No overlap, free both
@@ -533,14 +505,12 @@
  * ensure that all branch instructions can be restarted if
  * there is a trap in the shadow.  Allocate a temp register.
  */
-int MipsMir2Lir::LoadHelper(int offset)
-{
+int MipsMir2Lir::LoadHelper(int offset) {
   LoadWordDisp(rMIPS_SELF, offset, r_T9);
   return r_T9;
 }
 
-void MipsMir2Lir::SpillCoreRegs()
-{
+void MipsMir2Lir::SpillCoreRegs() {
   if (num_core_spills_ == 0) {
     return;
   }
@@ -555,8 +525,7 @@
   }
 }
 
-void MipsMir2Lir::UnSpillCoreRegs()
-{
+void MipsMir2Lir::UnSpillCoreRegs() {
   if (num_core_spills_ == 0) {
     return;
   }
@@ -571,8 +540,7 @@
   OpRegImm(kOpAdd, rMIPS_SP, frame_size_);
 }
 
-bool MipsMir2Lir::IsUnconditionalBranch(LIR* lir)
-{
+bool MipsMir2Lir::IsUnconditionalBranch(LIR* lir) {
   return (lir->opcode == kMipsB);
 }
 
@@ -592,18 +560,15 @@
   return new MipsMir2Lir(cu, mir_graph, arena);
 }
 
-uint64_t MipsMir2Lir::GetTargetInstFlags(int opcode)
-{
+uint64_t MipsMir2Lir::GetTargetInstFlags(int opcode) {
   return MipsMir2Lir::EncodingMap[opcode].flags;
 }
 
-const char* MipsMir2Lir::GetTargetInstName(int opcode)
-{
+const char* MipsMir2Lir::GetTargetInstName(int opcode) {
   return MipsMir2Lir::EncodingMap[opcode].name;
 }
 
-const char* MipsMir2Lir::GetTargetInstFmt(int opcode)
-{
+const char* MipsMir2Lir::GetTargetInstFmt(int opcode) {
   return MipsMir2Lir::EncodingMap[opcode].fmt;
 }
 
diff --git a/compiler/dex/quick/mips/utility_mips.cc b/compiler/dex/quick/mips/utility_mips.cc
index 8daafc8..089764f 100644
--- a/compiler/dex/quick/mips/utility_mips.cc
+++ b/compiler/dex/quick/mips/utility_mips.cc
@@ -21,8 +21,7 @@
 namespace art {
 
 /* This file contains codegen for the MIPS32 ISA. */
-LIR* MipsMir2Lir::OpFpRegCopy(int r_dest, int r_src)
-{
+LIR* MipsMir2Lir::OpFpRegCopy(int r_dest, int r_src) {
   int opcode;
   /* must be both DOUBLE or both not DOUBLE */
   DCHECK_EQ(MIPS_DOUBLEREG(r_dest),MIPS_DOUBLEREG(r_src));
@@ -51,23 +50,19 @@
   return res;
 }
 
-bool MipsMir2Lir::InexpensiveConstantInt(int32_t value)
-{
+bool MipsMir2Lir::InexpensiveConstantInt(int32_t value) {
   return ((value == 0) || IsUint(16, value) || ((value < 0) && (value >= -32768)));
 }
 
-bool MipsMir2Lir::InexpensiveConstantFloat(int32_t value)
-{
+bool MipsMir2Lir::InexpensiveConstantFloat(int32_t value) {
   return false;  // TUNING
 }
 
-bool MipsMir2Lir::InexpensiveConstantLong(int64_t value)
-{
+bool MipsMir2Lir::InexpensiveConstantLong(int64_t value) {
   return false;  // TUNING
 }
 
-bool MipsMir2Lir::InexpensiveConstantDouble(int64_t value)
-{
+bool MipsMir2Lir::InexpensiveConstantDouble(int64_t value) {
   return false; // TUNING
 }
 
@@ -80,8 +75,7 @@
  * 1) r_dest is freshly returned from AllocTemp or
  * 2) The codegen is under fixed register usage
  */
-LIR* MipsMir2Lir::LoadConstantNoClobber(int r_dest, int value)
-{
+LIR* MipsMir2Lir::LoadConstantNoClobber(int r_dest, int value) {
   LIR *res;
 
   int r_dest_save = r_dest;
@@ -112,15 +106,13 @@
   return res;
 }
 
-LIR* MipsMir2Lir::OpUnconditionalBranch(LIR* target)
-{
+LIR* MipsMir2Lir::OpUnconditionalBranch(LIR* target) {
   LIR* res = NewLIR1(kMipsB, 0 /* offset to be patched during assembly*/ );
   res->target = target;
   return res;
 }
 
-LIR* MipsMir2Lir::OpReg(OpKind op, int r_dest_src)
-{
+LIR* MipsMir2Lir::OpReg(OpKind op, int r_dest_src) {
   MipsOpCode opcode = kMipsNop;
   switch (op) {
     case kOpBlx:
@@ -136,8 +128,7 @@
 }
 
 LIR* MipsMir2Lir::OpRegImm(OpKind op, int r_dest_src1,
-          int value)
-{
+          int value) {
   LIR *res;
   bool neg = (value < 0);
   int abs_value = (neg) ? -value : value;
@@ -167,8 +158,7 @@
   return res;
 }
 
-LIR* MipsMir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2)
-{
+LIR* MipsMir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2) {
   MipsOpCode opcode = kMipsNop;
   switch (op) {
     case kOpAdd:
@@ -209,8 +199,7 @@
   return NewLIR3(opcode, r_dest, r_src1, r_src2);
 }
 
-LIR* MipsMir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src1, int value)
-{
+LIR* MipsMir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src1, int value) {
   LIR *res;
   MipsOpCode opcode = kMipsNop;
   bool short_form = true;
@@ -298,8 +287,7 @@
   return res;
 }
 
-LIR* MipsMir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2)
-{
+LIR* MipsMir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2) {
   MipsOpCode opcode = kMipsNop;
   LIR *res;
   switch (op) {
@@ -342,8 +330,7 @@
   return NewLIR2(opcode, r_dest_src1, r_src2);
 }
 
-LIR* MipsMir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value)
-{
+LIR* MipsMir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) {
   LIR *res;
   res = LoadConstantNoClobber(r_dest_lo, Low32Bits(value));
   LoadConstantNoClobber(r_dest_hi, High32Bits(value));
@@ -352,8 +339,7 @@
 
 /* Load value from base + scaled index. */
 LIR* MipsMir2Lir::LoadBaseIndexed(int rBase, int r_index, int r_dest,
-                                  int scale, OpSize size)
-{
+                                  int scale, OpSize size) {
   LIR *first = NULL;
   LIR *res;
   MipsOpCode opcode = kMipsNop;
@@ -405,8 +391,7 @@
 
 /* store value base base + scaled index. */
 LIR* MipsMir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src,
-                                   int scale, OpSize size)
-{
+                                   int scale, OpSize size) {
   LIR *first = NULL;
   MipsOpCode opcode = kMipsNop;
   int r_new_index = r_index;
@@ -452,7 +437,7 @@
 }
 
 LIR* MipsMir2Lir::LoadBaseDispBody(int rBase, int displacement, int r_dest,
-                                   int r_dest_hi, OpSize size, int s_reg)
+                                   int r_dest_hi, OpSize size, int s_reg) {
 /*
  * Load value from base + displacement.  Optionally perform null check
  * on base (which must have an associated s_reg and MIR).  If not
@@ -461,7 +446,6 @@
  * and base and dest are the same, spill some other register to
  * rlp and then restore.
  */
-{
   LIR *res;
   LIR *load = NULL;
   LIR *load2 = NULL;
@@ -551,21 +535,18 @@
 }
 
 LIR* MipsMir2Lir::LoadBaseDisp(int rBase, int displacement, int r_dest,
-                               OpSize size, int s_reg)
-{
+                               OpSize size, int s_reg) {
   return LoadBaseDispBody(rBase, displacement, r_dest, -1,
                           size, s_reg);
 }
 
 LIR* MipsMir2Lir::LoadBaseDispWide(int rBase, int displacement,
-                                   int r_dest_lo, int r_dest_hi, int s_reg)
-{
+                                   int r_dest_lo, int r_dest_hi, int s_reg) {
   return LoadBaseDispBody(rBase, displacement, r_dest_lo, r_dest_hi, kLong, s_reg);
 }
 
 LIR* MipsMir2Lir::StoreBaseDispBody(int rBase, int displacement,
-                                    int r_src, int r_src_hi, OpSize size)
-{
+                                    int r_src, int r_src_hi, OpSize size) {
   LIR *res;
   LIR *store = NULL;
   LIR *store2 = NULL;
@@ -647,52 +628,44 @@
 }
 
 LIR* MipsMir2Lir::StoreBaseDisp(int rBase, int displacement, int r_src,
-                                OpSize size)
-{
+                                OpSize size) {
   return StoreBaseDispBody(rBase, displacement, r_src, -1, size);
 }
 
 LIR* MipsMir2Lir::StoreBaseDispWide(int rBase, int displacement,
-                                    int r_src_lo, int r_src_hi)
-{
+                                    int r_src_lo, int r_src_hi) {
   return StoreBaseDispBody(rBase, displacement, r_src_lo, r_src_hi, kLong);
 }
 
-LIR* MipsMir2Lir::OpThreadMem(OpKind op, int thread_offset)
-{
+LIR* MipsMir2Lir::OpThreadMem(OpKind op, int thread_offset) {
   LOG(FATAL) << "Unexpected use of OpThreadMem for MIPS";
   return NULL;
 }
 
-LIR* MipsMir2Lir::OpMem(OpKind op, int rBase, int disp)
-{
+LIR* MipsMir2Lir::OpMem(OpKind op, int rBase, int disp) {
   LOG(FATAL) << "Unexpected use of OpMem for MIPS";
   return NULL;
 }
 
 LIR* MipsMir2Lir::StoreBaseIndexedDisp( int rBase, int r_index, int scale, int displacement,
-                                        int r_src, int r_src_hi, OpSize size, int s_reg)
-{
+                                        int r_src, int r_src_hi, OpSize size, int s_reg) {
   LOG(FATAL) << "Unexpected use of StoreBaseIndexedDisp for MIPS";
   return NULL;
 }
 
 LIR* MipsMir2Lir::OpRegMem(OpKind op, int r_dest, int rBase,
-              int offset)
-{
+              int offset) {
   LOG(FATAL) << "Unexpected use of OpRegMem for MIPS";
   return NULL;
 }
 
 LIR* MipsMir2Lir::LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
-                                      int r_dest, int r_dest_hi, OpSize size, int s_reg)
-{
+                                      int r_dest, int r_dest_hi, OpSize size, int s_reg) {
   LOG(FATAL) << "Unexpected use of LoadBaseIndexedDisp for MIPS";
   return NULL;
 }
 
-LIR* MipsMir2Lir::OpCondBranch(ConditionCode cc, LIR* target)
-{
+LIR* MipsMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) {
   LOG(FATAL) << "Unexpected use of OpCondBranch for MIPS";
   return NULL;
 }
diff --git a/compiler/dex/quick/mir_to_lir.cc b/compiler/dex/quick/mir_to_lir.cc
index 4562482..b758fb5 100644
--- a/compiler/dex/quick/mir_to_lir.cc
+++ b/compiler/dex/quick/mir_to_lir.cc
@@ -26,8 +26,7 @@
  * load/store utilities here, or target-dependent genXX() handlers
  * when necessary.
  */
-void Mir2Lir::CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list)
-{
+void Mir2Lir::CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list) {
   RegLocation rl_src[3];
   RegLocation rl_dest = mir_graph_->GetBadLoc();
   RegLocation rl_result = mir_graph_->GetBadLoc();
@@ -659,8 +658,7 @@
 }
 
 // Process extended MIR instructions
-void Mir2Lir::HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir)
-{
+void Mir2Lir::HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir) {
   switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) {
     case kMirOpCopy: {
       RegLocation rl_src = mir_graph_->GetSrc(mir, 0);
@@ -692,8 +690,7 @@
 }
 
 // Handle the content in each basic block.
-bool Mir2Lir::MethodBlockCodeGen(BasicBlock* bb)
-{
+bool Mir2Lir::MethodBlockCodeGen(BasicBlock* bb) {
   if (bb->block_type == kDead) return false;
   current_dalvik_offset_ = bb->start_offset;
   MIR* mir;
@@ -787,8 +784,7 @@
   return false;
 }
 
-void Mir2Lir::SpecialMIR2LIR(SpecialCaseHandler special_case)
-{
+void Mir2Lir::SpecialMIR2LIR(SpecialCaseHandler special_case) {
   // Find the first DalvikByteCode block.
   int num_reachable_blocks = mir_graph_->GetNumReachableBlocks();
   BasicBlock*bb = NULL;
@@ -817,8 +813,7 @@
   GenSpecialCase(bb, mir, special_case);
 }
 
-void Mir2Lir::MethodMIR2LIR()
-{
+void Mir2Lir::MethodMIR2LIR() {
   // Hold the labels of each block.
   block_label_list_ =
       static_cast<LIR*>(arena_->NewMem(sizeof(LIR) * mir_graph_->GetNumBlocks(), true,
diff --git a/compiler/dex/quick/mir_to_lir.h b/compiler/dex/quick/mir_to_lir.h
index bec86c1..abb687c 100644
--- a/compiler/dex/quick/mir_to_lir.h
+++ b/compiler/dex/quick/mir_to_lir.h
@@ -226,7 +226,7 @@
       bool first_in_pair;
     };
 
-    virtual ~Mir2Lir(){};
+    virtual ~Mir2Lir() {};
 
     int32_t s4FromSwitchData(const void* switch_data) {
       return *reinterpret_cast<const int32_t*>(switch_data);
diff --git a/compiler/dex/quick/ralloc_util.cc b/compiler/dex/quick/ralloc_util.cc
index 8f43542..4c91223 100644
--- a/compiler/dex/quick/ralloc_util.cc
+++ b/compiler/dex/quick/ralloc_util.cc
@@ -27,8 +27,7 @@
  * not affect the "liveness" of a temp register, which will stay
  * live until it is either explicitly killed or reallocated.
  */
-void Mir2Lir::ResetRegPool()
-{
+void Mir2Lir::ResetRegPool() {
   int i;
   for (i=0; i < reg_pool_->num_core_regs; i++) {
     if (reg_pool_->core_regs[i].is_temp)
@@ -48,8 +47,7 @@
   * Set up temp & preserved register pools specialized by target.
   * Note: num_regs may be zero.
   */
-void Mir2Lir::CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num)
-{
+void Mir2Lir::CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num) {
   int i;
   for (i=0; i < num; i++) {
     regs[i].reg = reg_nums[i];
@@ -62,8 +60,7 @@
   }
 }
 
-void Mir2Lir::DumpRegPool(RegisterInfo* p, int num_regs)
-{
+void Mir2Lir::DumpRegPool(RegisterInfo* p, int num_regs) {
   LOG(INFO) << "================================================";
   for (int i = 0; i < num_regs; i++) {
     LOG(INFO) << StringPrintf(
@@ -75,18 +72,15 @@
   LOG(INFO) << "================================================";
 }
 
-void Mir2Lir::DumpCoreRegPool()
-{
+void Mir2Lir::DumpCoreRegPool() {
   DumpRegPool(reg_pool_->core_regs, reg_pool_->num_core_regs);
 }
 
-void Mir2Lir::DumpFpRegPool()
-{
+void Mir2Lir::DumpFpRegPool() {
   DumpRegPool(reg_pool_->FPRegs, reg_pool_->num_fp_regs);
 }
 
-void Mir2Lir::ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg)
-{
+void Mir2Lir::ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg) {
   int i;
   for (i=0; i< num_regs; i++) {
     if (p[i].s_reg == s_reg) {
@@ -110,8 +104,7 @@
  * changes (for example: INT_TO_FLOAT v1, v1).  Revisit when improved register allocation is
  * addressed.
  */
-void Mir2Lir::ClobberSReg(int s_reg)
-{
+void Mir2Lir::ClobberSReg(int s_reg) {
   /* Reset live temp tracking sanity checker */
   if (kIsDebugBuild) {
     if (s_reg == live_sreg_) {
@@ -131,8 +124,7 @@
  * ssa name (above the last original Dalvik register).  This function
  * maps SSA names to positions in the promotion_map array.
  */
-int Mir2Lir::SRegToPMap(int s_reg)
-{
+int Mir2Lir::SRegToPMap(int s_reg) {
   DCHECK_LT(s_reg, mir_graph_->GetNumSSARegs());
   DCHECK_GE(s_reg, 0);
   int v_reg = mir_graph_->SRegToVReg(s_reg);
@@ -146,8 +138,7 @@
   }
 }
 
-void Mir2Lir::RecordCorePromotion(int reg, int s_reg)
-{
+void Mir2Lir::RecordCorePromotion(int reg, int s_reg) {
   int p_map_idx = SRegToPMap(s_reg);
   int v_reg = mir_graph_->SRegToVReg(s_reg);
   GetRegInfo(reg)->in_use = true;
@@ -160,8 +151,7 @@
 }
 
 /* Reserve a callee-save register.  Return -1 if none available */
-int Mir2Lir::AllocPreservedCoreReg(int s_reg)
-{
+int Mir2Lir::AllocPreservedCoreReg(int s_reg) {
   int res = -1;
   RegisterInfo* core_regs = reg_pool_->core_regs;
   for (int i = 0; i < reg_pool_->num_core_regs; i++) {
@@ -174,8 +164,7 @@
   return res;
 }
 
-void Mir2Lir::RecordFpPromotion(int reg, int s_reg)
-{
+void Mir2Lir::RecordFpPromotion(int reg, int s_reg) {
   int p_map_idx = SRegToPMap(s_reg);
   int v_reg = mir_graph_->SRegToVReg(s_reg);
   GetRegInfo(reg)->in_use = true;
@@ -189,8 +178,7 @@
  * even/odd  allocation, but go ahead and allocate anything if not
  * available.  If nothing's available, return -1.
  */
-int Mir2Lir::AllocPreservedSingle(int s_reg, bool even)
-{
+int Mir2Lir::AllocPreservedSingle(int s_reg, bool even) {
   int res = -1;
   RegisterInfo* FPRegs = reg_pool_->FPRegs;
   for (int i = 0; i < reg_pool_->num_fp_regs; i++) {
@@ -212,8 +200,7 @@
  * allocate if we can't meet the requirements for the pair of
  * s_reg<=sX[even] & (s_reg+1)<= sX+1.
  */
-int Mir2Lir::AllocPreservedDouble(int s_reg)
-{
+int Mir2Lir::AllocPreservedDouble(int s_reg) {
   int res = -1; // Assume failure
   int v_reg = mir_graph_->SRegToVReg(s_reg);
   int p_map_idx = SRegToPMap(s_reg);
@@ -269,8 +256,7 @@
  * single regs (but if can't still attempt to allocate a single, preferring
  * first to allocate an odd register.
  */
-int Mir2Lir::AllocPreservedFPReg(int s_reg, bool double_start)
-{
+int Mir2Lir::AllocPreservedFPReg(int s_reg, bool double_start) {
   int res = -1;
   if (double_start) {
     res = AllocPreservedDouble(s_reg);
@@ -284,8 +270,7 @@
 }
 
 int Mir2Lir::AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp,
-                           bool required)
-{
+                           bool required) {
   int i;
   int next = *next_temp;
   for (i=0; i< num_regs; i++) {
@@ -323,8 +308,7 @@
 }
 
 //REDO: too many assumptions.
-int Mir2Lir::AllocTempDouble()
-{
+int Mir2Lir::AllocTempDouble() {
   RegisterInfo* p = reg_pool_->FPRegs;
   int num_regs = reg_pool_->num_fp_regs;
   /* Start looking at an even reg */
@@ -377,29 +361,25 @@
 }
 
 /* Return a temp if one is available, -1 otherwise */
-int Mir2Lir::AllocFreeTemp()
-{
+int Mir2Lir::AllocFreeTemp() {
   return AllocTempBody(reg_pool_->core_regs,
              reg_pool_->num_core_regs,
              &reg_pool_->next_core_reg, true);
 }
 
-int Mir2Lir::AllocTemp()
-{
+int Mir2Lir::AllocTemp() {
   return AllocTempBody(reg_pool_->core_regs,
              reg_pool_->num_core_regs,
              &reg_pool_->next_core_reg, true);
 }
 
-int Mir2Lir::AllocTempFloat()
-{
+int Mir2Lir::AllocTempFloat() {
   return AllocTempBody(reg_pool_->FPRegs,
              reg_pool_->num_fp_regs,
              &reg_pool_->next_fp_reg, true);
 }
 
-Mir2Lir::RegisterInfo* Mir2Lir::AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg)
-{
+Mir2Lir::RegisterInfo* Mir2Lir::AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg) {
   int i;
   if (s_reg == -1)
     return NULL;
@@ -413,8 +393,7 @@
   return NULL;
 }
 
-Mir2Lir::RegisterInfo* Mir2Lir::AllocLive(int s_reg, int reg_class)
-{
+Mir2Lir::RegisterInfo* Mir2Lir::AllocLive(int s_reg, int reg_class) {
   RegisterInfo* res = NULL;
   switch (reg_class) {
     case kAnyReg:
@@ -437,8 +416,7 @@
   return res;
 }
 
-void Mir2Lir::FreeTemp(int reg)
-{
+void Mir2Lir::FreeTemp(int reg) {
   RegisterInfo* p = reg_pool_->core_regs;
   int num_regs = reg_pool_->num_core_regs;
   int i;
@@ -465,8 +443,7 @@
   LOG(FATAL) << "Tried to free a non-existant temp: r" << reg;
 }
 
-Mir2Lir::RegisterInfo* Mir2Lir::IsLive(int reg)
-{
+Mir2Lir::RegisterInfo* Mir2Lir::IsLive(int reg) {
   RegisterInfo* p = reg_pool_->core_regs;
   int num_regs = reg_pool_->num_core_regs;
   int i;
@@ -485,20 +462,17 @@
   return NULL;
 }
 
-Mir2Lir::RegisterInfo* Mir2Lir::IsTemp(int reg)
-{
+Mir2Lir::RegisterInfo* Mir2Lir::IsTemp(int reg) {
   RegisterInfo* p = GetRegInfo(reg);
   return (p->is_temp) ? p : NULL;
 }
 
-Mir2Lir::RegisterInfo* Mir2Lir::IsPromoted(int reg)
-{
+Mir2Lir::RegisterInfo* Mir2Lir::IsPromoted(int reg) {
   RegisterInfo* p = GetRegInfo(reg);
   return (p->is_temp) ? NULL : p;
 }
 
-bool Mir2Lir::IsDirty(int reg)
-{
+bool Mir2Lir::IsDirty(int reg) {
   RegisterInfo* p = GetRegInfo(reg);
   return p->dirty;
 }
@@ -508,8 +482,7 @@
  * register.  No check is made to see if the register was previously
  * allocated.  Use with caution.
  */
-void Mir2Lir::LockTemp(int reg)
-{
+void Mir2Lir::LockTemp(int reg) {
   RegisterInfo* p = reg_pool_->core_regs;
   int num_regs = reg_pool_->num_core_regs;
   int i;
@@ -534,13 +507,11 @@
   LOG(FATAL) << "Tried to lock a non-existant temp: r" << reg;
 }
 
-void Mir2Lir::ResetDef(int reg)
-{
+void Mir2Lir::ResetDef(int reg) {
   ResetDefBody(GetRegInfo(reg));
 }
 
-void Mir2Lir::NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2)
-{
+void Mir2Lir::NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2) {
   if (start && finish) {
     LIR *p;
     DCHECK_EQ(s_reg1, s_reg2);
@@ -557,8 +528,7 @@
  * on entry start points to the LIR prior to the beginning of the
  * sequence.
  */
-void Mir2Lir::MarkDef(RegLocation rl, LIR *start, LIR *finish)
-{
+void Mir2Lir::MarkDef(RegLocation rl, LIR *start, LIR *finish) {
   DCHECK(!rl.wide);
   DCHECK(start && start->next);
   DCHECK(finish);
@@ -572,8 +542,7 @@
  * on entry start points to the LIR prior to the beginning of the
  * sequence.
  */
-void Mir2Lir::MarkDefWide(RegLocation rl, LIR *start, LIR *finish)
-{
+void Mir2Lir::MarkDefWide(RegLocation rl, LIR *start, LIR *finish) {
   DCHECK(rl.wide);
   DCHECK(start && start->next);
   DCHECK(finish);
@@ -583,8 +552,7 @@
   p->def_end = finish;
 }
 
-RegLocation Mir2Lir::WideToNarrow(RegLocation rl)
-{
+RegLocation Mir2Lir::WideToNarrow(RegLocation rl) {
   DCHECK(rl.wide);
   if (rl.location == kLocPhysReg) {
     RegisterInfo* info_lo = GetRegInfo(rl.low_reg);
@@ -604,8 +572,7 @@
   return rl;
 }
 
-void Mir2Lir::ResetDefLoc(RegLocation rl)
-{
+void Mir2Lir::ResetDefLoc(RegLocation rl) {
   DCHECK(!rl.wide);
   RegisterInfo* p = IsTemp(rl.low_reg);
   if (p && !(cu_->disable_opt & (1 << kSuppressLoads))) {
@@ -615,8 +582,7 @@
   ResetDef(rl.low_reg);
 }
 
-void Mir2Lir::ResetDefLocWide(RegLocation rl)
-{
+void Mir2Lir::ResetDefLocWide(RegLocation rl) {
   DCHECK(rl.wide);
   RegisterInfo* p_low = IsTemp(rl.low_reg);
   RegisterInfo* p_high = IsTemp(rl.high_reg);
@@ -631,8 +597,7 @@
   ResetDef(rl.high_reg);
 }
 
-void Mir2Lir::ResetDefTracking()
-{
+void Mir2Lir::ResetDefTracking() {
   int i;
   for (i=0; i< reg_pool_->num_core_regs; i++) {
     ResetDefBody(&reg_pool_->core_regs[i]);
@@ -642,8 +607,7 @@
   }
 }
 
-void Mir2Lir::ClobberAllRegs()
-{
+void Mir2Lir::ClobberAllRegs() {
   int i;
   for (i=0; i< reg_pool_->num_core_regs; i++) {
     ClobberBody(&reg_pool_->core_regs[i]);
@@ -654,8 +618,7 @@
 }
 
 // Make sure nothing is live and dirty
-void Mir2Lir::FlushAllRegsBody(RegisterInfo* info, int num_regs)
-{
+void Mir2Lir::FlushAllRegsBody(RegisterInfo* info, int num_regs) {
   int i;
   for (i=0; i < num_regs; i++) {
     if (info[i].live && info[i].dirty) {
@@ -668,8 +631,7 @@
   }
 }
 
-void Mir2Lir::FlushAllRegs()
-{
+void Mir2Lir::FlushAllRegs() {
   FlushAllRegsBody(reg_pool_->core_regs,
            reg_pool_->num_core_regs);
   FlushAllRegsBody(reg_pool_->FPRegs,
@@ -679,8 +641,7 @@
 
 
 //TUNING: rewrite all of this reg stuff.  Probably use an attribute table
-bool Mir2Lir::RegClassMatches(int reg_class, int reg)
-{
+bool Mir2Lir::RegClassMatches(int reg_class, int reg) {
   if (reg_class == kAnyReg) {
     return true;
   } else if (reg_class == kCoreReg) {
@@ -690,8 +651,7 @@
   }
 }
 
-void Mir2Lir::MarkLive(int reg, int s_reg)
-{
+void Mir2Lir::MarkLive(int reg, int s_reg) {
   RegisterInfo* info = GetRegInfo(reg);
   if ((info->reg == reg) && (info->s_reg == s_reg) && info->live) {
     return;  /* already live */
@@ -708,20 +668,17 @@
   info->s_reg = s_reg;
 }
 
-void Mir2Lir::MarkTemp(int reg)
-{
+void Mir2Lir::MarkTemp(int reg) {
   RegisterInfo* info = GetRegInfo(reg);
   info->is_temp = true;
 }
 
-void Mir2Lir::UnmarkTemp(int reg)
-{
+void Mir2Lir::UnmarkTemp(int reg) {
   RegisterInfo* info = GetRegInfo(reg);
   info->is_temp = false;
 }
 
-void Mir2Lir::MarkPair(int low_reg, int high_reg)
-{
+void Mir2Lir::MarkPair(int low_reg, int high_reg) {
   RegisterInfo* info_lo = GetRegInfo(low_reg);
   RegisterInfo* info_hi = GetRegInfo(high_reg);
   info_lo->pair = info_hi->pair = true;
@@ -729,8 +686,7 @@
   info_hi->partner = low_reg;
 }
 
-void Mir2Lir::MarkClean(RegLocation loc)
-{
+void Mir2Lir::MarkClean(RegLocation loc) {
   RegisterInfo* info = GetRegInfo(loc.low_reg);
   info->dirty = false;
   if (loc.wide) {
@@ -739,8 +695,7 @@
   }
 }
 
-void Mir2Lir::MarkDirty(RegLocation loc)
-{
+void Mir2Lir::MarkDirty(RegLocation loc) {
   if (loc.home) {
     // If already home, can't be dirty
     return;
@@ -753,14 +708,12 @@
   }
 }
 
-void Mir2Lir::MarkInUse(int reg)
-{
+void Mir2Lir::MarkInUse(int reg) {
     RegisterInfo* info = GetRegInfo(reg);
     info->in_use = true;
 }
 
-void Mir2Lir::CopyRegInfo(int new_reg, int old_reg)
-{
+void Mir2Lir::CopyRegInfo(int new_reg, int old_reg) {
   RegisterInfo* new_info = GetRegInfo(new_reg);
   RegisterInfo* old_info = GetRegInfo(old_reg);
   // Target temp status must not change
@@ -771,8 +724,7 @@
   new_info->reg = new_reg;
 }
 
-bool Mir2Lir::CheckCorePoolSanity()
-{
+bool Mir2Lir::CheckCorePoolSanity() {
    for (static int i = 0; i < reg_pool_->num_core_regs; i++) {
      if (reg_pool_->core_regs[i].pair) {
        static int my_reg = reg_pool_->core_regs[i].reg;
@@ -808,8 +760,7 @@
  * if it's worthwhile trying to be more clever here.
  */
 
-RegLocation Mir2Lir::UpdateLoc(RegLocation loc)
-{
+RegLocation Mir2Lir::UpdateLoc(RegLocation loc) {
   DCHECK(!loc.wide);
   DCHECK(CheckCorePoolSanity());
   if (loc.location != kLocPhysReg) {
@@ -832,8 +783,7 @@
 }
 
 /* see comments for update_loc */
-RegLocation Mir2Lir::UpdateLocWide(RegLocation loc)
-{
+RegLocation Mir2Lir::UpdateLocWide(RegLocation loc) {
   DCHECK(loc.wide);
   DCHECK(CheckCorePoolSanity());
   if (loc.location != kLocPhysReg) {
@@ -886,16 +836,14 @@
 
 
 /* For use in cases we don't know (or care) width */
-RegLocation Mir2Lir::UpdateRawLoc(RegLocation loc)
-{
+RegLocation Mir2Lir::UpdateRawLoc(RegLocation loc) {
   if (loc.wide)
     return UpdateLocWide(loc);
   else
     return UpdateLoc(loc);
 }
 
-RegLocation Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update)
-{
+RegLocation Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) {
   DCHECK(loc.wide);
   int new_regs;
   int low_reg;
@@ -942,8 +890,7 @@
   return loc;
 }
 
-RegLocation Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update)
-{
+RegLocation Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) {
   int new_reg;
 
   if (loc.wide)
@@ -992,15 +939,13 @@
 }
 
 /* qsort callback function, sort descending */
-static int SortCounts(const void *val1, const void *val2)
-{
+static int SortCounts(const void *val1, const void *val2) {
   const Mir2Lir::RefCounts* op1 = reinterpret_cast<const Mir2Lir::RefCounts*>(val1);
   const Mir2Lir::RefCounts* op2 = reinterpret_cast<const Mir2Lir::RefCounts*>(val2);
   return (op1->count == op2->count) ? 0 : (op1->count < op2->count ? 1 : -1);
 }
 
-void Mir2Lir::DumpCounts(const RefCounts* arr, int size, const char* msg)
-{
+void Mir2Lir::DumpCounts(const RefCounts* arr, int size, const char* msg) {
   LOG(INFO) << msg;
   for (int i = 0; i < size; i++) {
     LOG(INFO) << "s_reg[" << arr[i].s_reg << "]: " << arr[i].count;
@@ -1011,8 +956,7 @@
  * Note: some portions of this code required even if the kPromoteRegs
  * optimization is disabled.
  */
-void Mir2Lir::DoPromotion()
-{
+void Mir2Lir::DoPromotion() {
   int reg_bias = cu_->num_compiler_temps + 1;
   int dalvik_regs = cu_->num_dalvik_registers;
   int num_regs = dalvik_regs + reg_bias;
@@ -1158,21 +1102,18 @@
 }
 
 /* Returns sp-relative offset in bytes for a VReg */
-int Mir2Lir::VRegOffset(int v_reg)
-{
+int Mir2Lir::VRegOffset(int v_reg) {
   return StackVisitor::GetVRegOffset(cu_->code_item, core_spill_mask_,
                                      fp_spill_mask_, frame_size_, v_reg);
 }
 
 /* Returns sp-relative offset in bytes for a SReg */
-int Mir2Lir::SRegOffset(int s_reg)
-{
+int Mir2Lir::SRegOffset(int s_reg) {
   return VRegOffset(mir_graph_->SRegToVReg(s_reg));
 }
 
 /* Mark register usage state and return long retloc */
-RegLocation Mir2Lir::GetReturnWide(bool is_double)
-{
+RegLocation Mir2Lir::GetReturnWide(bool is_double) {
   RegLocation gpr_res = LocCReturnWide();
   RegLocation fpr_res = LocCReturnDouble();
   RegLocation res = is_double ? fpr_res : gpr_res;
@@ -1184,8 +1125,7 @@
   return res;
 }
 
-RegLocation Mir2Lir::GetReturn(bool is_float)
-{
+RegLocation Mir2Lir::GetReturn(bool is_float) {
   RegLocation gpr_res = LocCReturn();
   RegLocation fpr_res = LocCReturnFloat();
   RegLocation res = is_float ? fpr_res : gpr_res;
@@ -1198,8 +1138,7 @@
   return res;
 }
 
-void Mir2Lir::SimpleRegAlloc()
-{
+void Mir2Lir::SimpleRegAlloc() {
   DoPromotion();
 
   if (cu_->verbose && !(cu_->disable_opt & (1 << kPromoteRegs))) {
diff --git a/compiler/dex/quick/x86/call_x86.cc b/compiler/dex/quick/x86/call_x86.cc
index d60be72..1aeb39a 100644
--- a/compiler/dex/quick/x86/call_x86.cc
+++ b/compiler/dex/quick/x86/call_x86.cc
@@ -23,8 +23,7 @@
 namespace art {
 
 void X86Mir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir,
-                                SpecialCaseHandler special_case)
-{
+                                SpecialCaseHandler special_case) {
   // TODO
 }
 
@@ -33,8 +32,7 @@
  * pairs.
  */
 void X86Mir2Lir::GenSparseSwitch(MIR* mir, uint32_t table_offset,
-                                 RegLocation rl_src)
-{
+                                 RegLocation rl_src) {
   const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
   if (cu_->verbose) {
     DumpSparseSwitchTable(table);
@@ -69,8 +67,7 @@
  * done:
  */
 void X86Mir2Lir::GenPackedSwitch(MIR* mir, uint32_t table_offset,
-                                 RegLocation rl_src)
-{
+                                 RegLocation rl_src) {
   const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
   if (cu_->verbose) {
     DumpPackedSwitchTable(table);
@@ -130,8 +127,7 @@
  *
  * Total size is 4+(width * size + 1)/2 16-bit code units.
  */
-void X86Mir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src)
-{
+void X86Mir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src) {
   const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
   // Add the table to the list - we'll process it later
   FillArrayData *tab_rec =
@@ -156,8 +152,7 @@
                           rX86_ARG1, true);
 }
 
-void X86Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src)
-{
+void X86Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) {
   FlushAllRegs();
   LoadValueDirectFixed(rl_src, rCX);  // Get obj
   LockCallTemps();  // Prepare for explicit register usage
@@ -174,8 +169,7 @@
   branch->target = NewLIR0(kPseudoTargetLabel);
 }
 
-void X86Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src)
-{
+void X86Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) {
   FlushAllRegs();
   LoadValueDirectFixed(rl_src, rAX);  // Get obj
   LockCallTemps();  // Prepare for explicit register usage
@@ -195,8 +189,7 @@
   branch2->target = NewLIR0(kPseudoTargetLabel);
 }
 
-void X86Mir2Lir::GenMoveException(RegLocation rl_dest)
-{
+void X86Mir2Lir::GenMoveException(RegLocation rl_dest) {
   int ex_offset = Thread::ExceptionOffset().Int32Value();
   RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
   NewLIR2(kX86Mov32RT, rl_result.low_reg, ex_offset);
@@ -207,8 +200,7 @@
 /*
  * Mark garbage collection card. Skip if the value we're storing is null.
  */
-void X86Mir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg)
-{
+void X86Mir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg) {
   int reg_card_base = AllocTemp();
   int reg_card_no = AllocTemp();
   LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL);
@@ -222,8 +214,7 @@
   FreeTemp(reg_card_no);
 }
 
-void X86Mir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method)
-{
+void X86Mir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) {
   /*
    * On entry, rX86_ARG0, rX86_ARG1, rX86_ARG2 are live.  Let the register
    * allocation mechanism know so it doesn't try to use any of them when
diff --git a/compiler/dex/quick/x86/fp_x86.cc b/compiler/dex/quick/x86/fp_x86.cc
index 906b4cc..f2ecf6c 100644
--- a/compiler/dex/quick/x86/fp_x86.cc
+++ b/compiler/dex/quick/x86/fp_x86.cc
@@ -349,8 +349,7 @@
   OpCondBranch(ccode, taken);
 }
 
-void X86Mir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src)
-{
+void X86Mir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src) {
   RegLocation rl_result;
   rl_src = LoadValue(rl_src, kCoreReg);
   rl_result = EvalLoc(rl_dest, kCoreReg, true);
@@ -358,8 +357,7 @@
   StoreValue(rl_dest, rl_result);
 }
 
-void X86Mir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src)
-{
+void X86Mir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src) {
   RegLocation rl_result;
   rl_src = LoadValueWide(rl_src, kCoreReg);
   rl_result = EvalLoc(rl_dest, kCoreReg, true);
diff --git a/compiler/dex/quick/x86/int_x86.cc b/compiler/dex/quick/x86/int_x86.cc
index 97d9d2d..3be24df 100644
--- a/compiler/dex/quick/x86/int_x86.cc
+++ b/compiler/dex/quick/x86/int_x86.cc
@@ -27,8 +27,7 @@
  * Perform register memory operation.
  */
 LIR* X86Mir2Lir::GenRegMemCheck(ConditionCode c_code,
-                                int reg1, int base, int offset, ThrowKind kind)
-{
+                                int reg1, int base, int offset, ThrowKind kind) {
   LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind,
                     current_dalvik_offset_, reg1, base, offset);
   OpRegMem(kOpCmp, reg1, base, offset);
@@ -45,8 +44,7 @@
  *    x > y     return  1
  */
 void X86Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1,
-                            RegLocation rl_src2)
-{
+                            RegLocation rl_src2) {
   FlushAllRegs();
   LockCallTemps();  // Prepare for explicit register usage
   LoadValueDirectWideFixed(rl_src1, r0, r1);
@@ -88,8 +86,7 @@
 }
 
 LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, int src1, int src2,
-                             LIR* target)
-{
+                             LIR* target) {
   NewLIR2(kX86Cmp32RR, src1, src2);
   X86ConditionCode cc = X86ConditionEncoding(cond);
   LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ ,
@@ -99,8 +96,7 @@
 }
 
 LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, int reg,
-                                int check_value, LIR* target)
-{
+                                int check_value, LIR* target) {
   if ((check_value == 0) && (cond == kCondEq || cond == kCondNe)) {
     // TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode
     NewLIR2(kX86Test32RR, reg, reg);
@@ -113,8 +109,7 @@
   return branch;
 }
 
-LIR* X86Mir2Lir::OpRegCopyNoInsert(int r_dest, int r_src)
-{
+LIR* X86Mir2Lir::OpRegCopyNoInsert(int r_dest, int r_src) {
   if (X86_FPREG(r_dest) || X86_FPREG(r_src))
     return OpFpRegCopy(r_dest, r_src);
   LIR* res = RawLIR(current_dalvik_offset_, kX86Mov32RR,
@@ -125,16 +120,14 @@
   return res;
 }
 
-LIR* X86Mir2Lir::OpRegCopy(int r_dest, int r_src)
-{
+LIR* X86Mir2Lir::OpRegCopy(int r_dest, int r_src) {
   LIR *res = OpRegCopyNoInsert(r_dest, r_src);
   AppendLIR(res);
   return res;
 }
 
 void X86Mir2Lir::OpRegCopyWide(int dest_lo, int dest_hi,
-                               int src_lo, int src_hi)
-{
+                               int src_lo, int src_hi) {
   bool dest_fp = X86_FPREG(dest_lo) && X86_FPREG(dest_hi);
   bool src_fp = X86_FPREG(src_lo) && X86_FPREG(src_hi);
   assert(X86_FPREG(src_lo) == X86_FPREG(src_hi));
@@ -168,8 +161,7 @@
   }
 }
 
-void X86Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir)
-{
+void X86Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) {
   UNIMPLEMENTED(FATAL) << "Need codegen for GenSelect";
 }
 
@@ -213,21 +205,18 @@
 }
 
 RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, int reg_lo,
-                                     int lit, bool is_div)
-{
+                                     int lit, bool is_div) {
   LOG(FATAL) << "Unexpected use of GenDivRemLit for x86";
   return rl_dest;
 }
 
 RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, int reg_lo,
-                                  int reg_hi, bool is_div)
-{
+                                  int reg_hi, bool is_div) {
   LOG(FATAL) << "Unexpected use of GenDivRem for x86";
   return rl_dest;
 }
 
-bool X86Mir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min)
-{
+bool X86Mir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min) {
   DCHECK_EQ(cu_->instruction_set, kX86);
   RegLocation rl_src1 = info->args[0];
   RegLocation rl_src2 = info->args[1];
@@ -247,13 +236,11 @@
   return true;
 }
 
-void X86Mir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset)
-{
+void X86Mir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) {
   NewLIR5(kX86Lea32RA, rBase, reg1, reg2, scale, offset);
 }
 
-void X86Mir2Lir::OpTlsCmp(int offset, int val)
-{
+void X86Mir2Lir::OpTlsCmp(int offset, int val) {
   NewLIR2(kX86Cmp16TI8, offset, val);
 }
 
@@ -267,22 +254,19 @@
   return NULL;
 }
 
-LIR* X86Mir2Lir::OpVldm(int rBase, int count)
-{
+LIR* X86Mir2Lir::OpVldm(int rBase, int count) {
   LOG(FATAL) << "Unexpected use of OpVldm for x86";
   return NULL;
 }
 
-LIR* X86Mir2Lir::OpVstm(int rBase, int count)
-{
+LIR* X86Mir2Lir::OpVstm(int rBase, int count) {
   LOG(FATAL) << "Unexpected use of OpVstm for x86";
   return NULL;
 }
 
 void X86Mir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src,
                                                RegLocation rl_result, int lit,
-                                               int first_bit, int second_bit)
-{
+                                               int first_bit, int second_bit) {
   int t_reg = AllocTemp();
   OpRegRegImm(kOpLsl, t_reg, rl_src.low_reg, second_bit - first_bit);
   OpRegRegReg(kOpAdd, rl_result.low_reg, rl_src.low_reg, t_reg);
@@ -292,8 +276,7 @@
   }
 }
 
-void X86Mir2Lir::GenDivZeroCheck(int reg_lo, int reg_hi)
-{
+void X86Mir2Lir::GenDivZeroCheck(int reg_lo, int reg_hi) {
   int t_reg = AllocTemp();
   OpRegRegReg(kOpOr, t_reg, reg_lo, reg_hi);
   GenImmedCheck(kCondEq, t_reg, 0, kThrowDivZero);
@@ -301,40 +284,34 @@
 }
 
 // Test suspend flag, return target of taken suspend branch
-LIR* X86Mir2Lir::OpTestSuspend(LIR* target)
-{
+LIR* X86Mir2Lir::OpTestSuspend(LIR* target) {
   OpTlsCmp(Thread::ThreadFlagsOffset().Int32Value(), 0);
   return OpCondBranch((target == NULL) ? kCondNe : kCondEq, target);
 }
 
 // Decrement register and branch on condition
-LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target)
-{
+LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) {
   OpRegImm(kOpSub, reg, 1);
   return OpCmpImmBranch(c_code, reg, 0, target);
 }
 
 bool X86Mir2Lir::SmallLiteralDivide(Instruction::Code dalvik_opcode,
-                                    RegLocation rl_src, RegLocation rl_dest, int lit)
-{
+                                    RegLocation rl_src, RegLocation rl_dest, int lit) {
   LOG(FATAL) << "Unexpected use of smallLiteralDive in x86";
   return false;
 }
 
-LIR* X86Mir2Lir::OpIT(ConditionCode cond, const char* guide)
-{
+LIR* X86Mir2Lir::OpIT(ConditionCode cond, const char* guide) {
   LOG(FATAL) << "Unexpected use of OpIT in x86";
   return NULL;
 }
 
 void X86Mir2Lir::GenMulLong(RegLocation rl_dest, RegLocation rl_src1,
-                            RegLocation rl_src2)
-{
+                            RegLocation rl_src2) {
   LOG(FATAL) << "Unexpected use of GenX86Long for x86";
 }
 void X86Mir2Lir::GenAddLong(RegLocation rl_dest, RegLocation rl_src1,
-                         RegLocation rl_src2)
-{
+                         RegLocation rl_src2) {
   // TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart
   // enough.
   FlushAllRegs();
@@ -350,8 +327,7 @@
 }
 
 void X86Mir2Lir::GenSubLong(RegLocation rl_dest, RegLocation rl_src1,
-                            RegLocation rl_src2)
-{
+                            RegLocation rl_src2) {
   // TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart
   // enough.
   FlushAllRegs();
@@ -367,8 +343,7 @@
 }
 
 void X86Mir2Lir::GenAndLong(RegLocation rl_dest, RegLocation rl_src1,
-                            RegLocation rl_src2)
-{
+                            RegLocation rl_src2) {
   // TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart
   // enough.
   FlushAllRegs();
@@ -384,8 +359,7 @@
 }
 
 void X86Mir2Lir::GenOrLong(RegLocation rl_dest,
-                           RegLocation rl_src1, RegLocation rl_src2)
-{
+                           RegLocation rl_src1, RegLocation rl_src2) {
   // TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart
   // enough.
   FlushAllRegs();
@@ -401,8 +375,7 @@
 }
 
 void X86Mir2Lir::GenXorLong(RegLocation rl_dest,
-                            RegLocation rl_src1, RegLocation rl_src2)
-{
+                            RegLocation rl_src1, RegLocation rl_src2) {
   // TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart
   // enough.
   FlushAllRegs();
@@ -417,8 +390,7 @@
   StoreValueWide(rl_dest, rl_result);
 }
 
-void X86Mir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src)
-{
+void X86Mir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) {
   FlushAllRegs();
   LockCallTemps();  // Prepare for explicit register usage
   LoadValueDirectWideFixed(rl_src, r0, r1);
@@ -447,8 +419,7 @@
  * Generate array load
  */
 void X86Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
-                          RegLocation rl_index, RegLocation rl_dest, int scale)
-{
+                          RegLocation rl_index, RegLocation rl_dest, int scale) {
   RegisterClass reg_class = oat_reg_class_by_size(size);
   int len_offset = mirror::Array::LengthOffset().Int32Value();
   int data_offset;
@@ -495,8 +466,7 @@
  *
  */
 void X86Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
-                          RegLocation rl_index, RegLocation rl_src, int scale)
-{
+                             RegLocation rl_index, RegLocation rl_src, int scale) {
   RegisterClass reg_class = oat_reg_class_by_size(size);
   int len_offset = mirror::Array::LengthOffset().Int32Value();
   int data_offset;
@@ -539,8 +509,7 @@
  *
  */
 void X86Mir2Lir::GenArrayObjPut(int opt_flags, RegLocation rl_array,
-                             RegLocation rl_index, RegLocation rl_src, int scale)
-{
+                             RegLocation rl_index, RegLocation rl_src, int scale) {
   int len_offset = mirror::Array::LengthOffset().Int32Value();
   int data_offset = mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value();
 
@@ -590,15 +559,13 @@
 }
 
 void X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
-                                   RegLocation rl_src1, RegLocation rl_shift)
-{
+                                   RegLocation rl_src1, RegLocation rl_shift) {
   // Default implementation is just to ignore the constant case.
   GenShiftOpLong(opcode, rl_dest, rl_src1, rl_shift);
 }
 
 void X86Mir2Lir::GenArithImmOpLong(Instruction::Code opcode,
-                                   RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
-{
+                                   RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
   // Default - bail to non-const handler.
   GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2);
 }
diff --git a/compiler/dex/quick/x86/target_x86.cc b/compiler/dex/quick/x86/target_x86.cc
index c421ef3..5b64a6b 100644
--- a/compiler/dex/quick/x86/target_x86.cc
+++ b/compiler/dex/quick/x86/target_x86.cc
@@ -45,26 +45,22 @@
 #endif
 };
 
-RegLocation X86Mir2Lir::LocCReturn()
-{
+RegLocation X86Mir2Lir::LocCReturn() {
   RegLocation res = X86_LOC_C_RETURN;
   return res;
 }
 
-RegLocation X86Mir2Lir::LocCReturnWide()
-{
+RegLocation X86Mir2Lir::LocCReturnWide() {
   RegLocation res = X86_LOC_C_RETURN_WIDE;
   return res;
 }
 
-RegLocation X86Mir2Lir::LocCReturnFloat()
-{
+RegLocation X86Mir2Lir::LocCReturnFloat() {
   RegLocation res = X86_LOC_C_RETURN_FLOAT;
   return res;
 }
 
-RegLocation X86Mir2Lir::LocCReturnDouble()
-{
+RegLocation X86Mir2Lir::LocCReturnDouble() {
   RegLocation res = X86_LOC_C_RETURN_DOUBLE;
   return res;
 }
@@ -95,28 +91,24 @@
 }
 
 // Create a double from a pair of singles.
-int X86Mir2Lir::S2d(int low_reg, int high_reg)
-{
+int X86Mir2Lir::S2d(int low_reg, int high_reg) {
   return X86_S2D(low_reg, high_reg);
 }
 
 // Return mask to strip off fp reg flags and bias.
-uint32_t X86Mir2Lir::FpRegMask()
-{
+uint32_t X86Mir2Lir::FpRegMask() {
   return X86_FP_REG_MASK;
 }
 
 // True if both regs single, both core or both double.
-bool X86Mir2Lir::SameRegType(int reg1, int reg2)
-{
+bool X86Mir2Lir::SameRegType(int reg1, int reg2) {
   return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2));
 }
 
 /*
  * Decode the register id.
  */
-uint64_t X86Mir2Lir::GetRegMaskCommon(int reg)
-{
+uint64_t X86Mir2Lir::GetRegMaskCommon(int reg) {
   uint64_t seed;
   int shift;
   int reg_id;
@@ -131,8 +123,7 @@
   return (seed << shift);
 }
 
-uint64_t X86Mir2Lir::GetPCUseDefEncoding()
-{
+uint64_t X86Mir2Lir::GetPCUseDefEncoding() {
   /*
    * FIXME: might make sense to use a virtual resource encoding bit for pc.  Might be
    * able to clean up some of the x86/Arm_Mips differences
@@ -141,8 +132,7 @@
   return 0ULL;
 }
 
-void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir)
-{
+void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir) {
   DCHECK_EQ(cu_->instruction_set, kX86);
 
   // X86-specific resource map setup here.
@@ -263,8 +253,7 @@
   return buf;
 }
 
-void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix)
-{
+void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix) {
   char buf[256];
   buf[0] = 0;
 
@@ -317,16 +306,14 @@
  * include any holes in the mask.  Associate holes with
  * Dalvik register INVALID_VREG (0xFFFFU).
  */
-void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg)
-{
+void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg) {
   UNIMPLEMENTED(WARNING) << "MarkPreservedSingle";
 #if 0
   LOG(FATAL) << "No support yet for promoted FP regs";
 #endif
 }
 
-void X86Mir2Lir::FlushRegWide(int reg1, int reg2)
-{
+void X86Mir2Lir::FlushRegWide(int reg1, int reg2) {
   RegisterInfo* info1 = GetRegInfo(reg1);
   RegisterInfo* info2 = GetRegInfo(reg2);
   DCHECK(info1 && info2 && info1->pair && info2->pair &&
@@ -347,8 +334,7 @@
   }
 }
 
-void X86Mir2Lir::FlushReg(int reg)
-{
+void X86Mir2Lir::FlushReg(int reg) {
   RegisterInfo* info = GetRegInfo(reg);
   if (info->live && info->dirty) {
     info->dirty = false;
@@ -363,8 +349,7 @@
 }
 
 /* Clobber all regs that might be used by an external C call */
-void X86Mir2Lir::ClobberCalleeSave()
-{
+void X86Mir2Lir::ClobberCalleeSave() {
   Clobber(rAX);
   Clobber(rCX);
   Clobber(rDX);
@@ -382,8 +367,7 @@
   return res;
 }
 
-RegLocation X86Mir2Lir::GetReturnAlt()
-{
+RegLocation X86Mir2Lir::GetReturnAlt() {
   RegLocation res = LocCReturn();
   res.low_reg = rDX;
   Clobber(rDX);
@@ -391,15 +375,13 @@
   return res;
 }
 
-X86Mir2Lir::RegisterInfo* X86Mir2Lir::GetRegInfo(int reg)
-{
+X86Mir2Lir::RegisterInfo* X86Mir2Lir::GetRegInfo(int reg) {
   return X86_FPREG(reg) ? &reg_pool_->FPRegs[reg & X86_FP_REG_MASK]
                     : &reg_pool_->core_regs[reg];
 }
 
 /* To be used when explicitly managing register use */
-void X86Mir2Lir::LockCallTemps()
-{
+void X86Mir2Lir::LockCallTemps() {
   LockTemp(rX86_ARG0);
   LockTemp(rX86_ARG1);
   LockTemp(rX86_ARG2);
@@ -407,16 +389,14 @@
 }
 
 /* To be used when explicitly managing register use */
-void X86Mir2Lir::FreeCallTemps()
-{
+void X86Mir2Lir::FreeCallTemps() {
   FreeTemp(rX86_ARG0);
   FreeTemp(rX86_ARG1);
   FreeTemp(rX86_ARG2);
   FreeTemp(rX86_ARG3);
 }
 
-void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind)
-{
+void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) {
 #if ANDROID_SMP != 0
   // TODO: optimize fences
   NewLIR0(kX86Mfence);
@@ -427,8 +407,7 @@
  * high reg in next byte.
  */
 int X86Mir2Lir::AllocTypedTempPair(bool fp_hint,
-                          int reg_class)
-{
+                          int reg_class) {
   int high_reg;
   int low_reg;
   int res = 0;
@@ -485,8 +464,7 @@
 }
 
 void X86Mir2Lir::FreeRegLocTemps(RegLocation rl_keep,
-                     RegLocation rl_free)
-{
+                     RegLocation rl_free) {
   if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) &&
       (rl_free.high_reg != rl_keep.low_reg) && (rl_free.high_reg != rl_keep.high_reg)) {
     // No overlap, free both
@@ -525,8 +503,7 @@
   }
 }
 
-bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir)
-{
+bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) {
   return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32);
 }
 
@@ -547,24 +524,20 @@
 }
 
 // Not used in x86
-int X86Mir2Lir::LoadHelper(int offset)
-{
+int X86Mir2Lir::LoadHelper(int offset) {
   LOG(FATAL) << "Unexpected use of LoadHelper in x86";
   return INVALID_REG;
 }
 
-uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode)
-{
+uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) {
   return X86Mir2Lir::EncodingMap[opcode].flags;
 }
 
-const char* X86Mir2Lir::GetTargetInstName(int opcode)
-{
+const char* X86Mir2Lir::GetTargetInstName(int opcode) {
   return X86Mir2Lir::EncodingMap[opcode].name;
 }
 
-const char* X86Mir2Lir::GetTargetInstFmt(int opcode)
-{
+const char* X86Mir2Lir::GetTargetInstFmt(int opcode) {
   return X86Mir2Lir::EncodingMap[opcode].fmt;
 }
 
diff --git a/compiler/dex/quick/x86/utility_x86.cc b/compiler/dex/quick/x86/utility_x86.cc
index fb07ff1..6376e3b 100644
--- a/compiler/dex/quick/x86/utility_x86.cc
+++ b/compiler/dex/quick/x86/utility_x86.cc
@@ -22,8 +22,7 @@
 
 /* This file contains codegen for the X86 ISA */
 
-LIR* X86Mir2Lir::OpFpRegCopy(int r_dest, int r_src)
-{
+LIR* X86Mir2Lir::OpFpRegCopy(int r_dest, int r_src) {
   int opcode;
   /* must be both DOUBLE or both not DOUBLE */
   DCHECK_EQ(X86_DOUBLEREG(r_dest), X86_DOUBLEREG(r_src));
@@ -49,23 +48,19 @@
   return res;
 }
 
-bool X86Mir2Lir::InexpensiveConstantInt(int32_t value)
-{
+bool X86Mir2Lir::InexpensiveConstantInt(int32_t value) {
   return true;
 }
 
-bool X86Mir2Lir::InexpensiveConstantFloat(int32_t value)
-{
+bool X86Mir2Lir::InexpensiveConstantFloat(int32_t value) {
   return false;
 }
 
-bool X86Mir2Lir::InexpensiveConstantLong(int64_t value)
-{
+bool X86Mir2Lir::InexpensiveConstantLong(int64_t value) {
   return true;
 }
 
-bool X86Mir2Lir::InexpensiveConstantDouble(int64_t value)
-{
+bool X86Mir2Lir::InexpensiveConstantDouble(int64_t value) {
   return false; // TUNING
 }
 
@@ -78,8 +73,7 @@
  * 1) r_dest is freshly returned from AllocTemp or
  * 2) The codegen is under fixed register usage
  */
-LIR* X86Mir2Lir::LoadConstantNoClobber(int r_dest, int value)
-{
+LIR* X86Mir2Lir::LoadConstantNoClobber(int r_dest, int value) {
   int r_dest_save = r_dest;
   if (X86_FPREG(r_dest)) {
     if (value == 0) {
@@ -105,23 +99,20 @@
   return res;
 }
 
-LIR* X86Mir2Lir::OpUnconditionalBranch(LIR* target)
-{
+LIR* X86Mir2Lir::OpUnconditionalBranch(LIR* target) {
   LIR* res = NewLIR1(kX86Jmp8, 0 /* offset to be patched during assembly*/ );
   res->target = target;
   return res;
 }
 
-LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target)
-{
+LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) {
   LIR* branch = NewLIR2(kX86Jcc8, 0 /* offset to be patched */,
                         X86ConditionEncoding(cc));
   branch->target = target;
   return branch;
 }
 
-LIR* X86Mir2Lir::OpReg(OpKind op, int r_dest_src)
-{
+LIR* X86Mir2Lir::OpReg(OpKind op, int r_dest_src) {
   X86OpCode opcode = kX86Bkpt;
   switch (op) {
     case kOpNeg: opcode = kX86Neg32R; break;
@@ -133,8 +124,7 @@
   return NewLIR1(opcode, r_dest_src);
 }
 
-LIR* X86Mir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value)
-{
+LIR* X86Mir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value) {
   X86OpCode opcode = kX86Bkpt;
   bool byte_imm = IS_SIMM8(value);
   DCHECK(!X86_FPREG(r_dest_src1));
@@ -160,8 +150,7 @@
   return NewLIR2(opcode, r_dest_src1, value);
 }
 
-LIR* X86Mir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2)
-{
+LIR* X86Mir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2) {
     X86OpCode opcode = kX86Nop;
     bool src2_must_be_cx = false;
     switch (op) {
@@ -207,8 +196,7 @@
 }
 
 LIR* X86Mir2Lir::OpRegMem(OpKind op, int r_dest, int rBase,
-              int offset)
-{
+              int offset) {
   X86OpCode opcode = kX86Nop;
   switch (op) {
       // X86 binary opcodes
@@ -231,8 +219,7 @@
 }
 
 LIR* X86Mir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1,
-                 int r_src2)
-{
+                 int r_src2) {
   if (r_dest != r_src1 && r_dest != r_src2) {
     if (op == kOpAdd) { // lea special case, except can't encode rbp as base
       if (r_src1 == r_src2) {
@@ -280,8 +267,7 @@
 }
 
 LIR* X86Mir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src,
-                 int value)
-{
+                 int value) {
   if (op == kOpMul) {
     X86OpCode opcode = IS_SIMM8(value) ? kX86Imul32RRI8 : kX86Imul32RRI;
     return NewLIR3(opcode, r_dest, r_src, value);
@@ -306,8 +292,7 @@
   return OpRegImm(op, r_dest, value);
 }
 
-LIR* X86Mir2Lir::OpThreadMem(OpKind op, int thread_offset)
-{
+LIR* X86Mir2Lir::OpThreadMem(OpKind op, int thread_offset) {
   X86OpCode opcode = kX86Bkpt;
   switch (op) {
     case kOpBlx: opcode = kX86CallT;  break;
@@ -318,8 +303,7 @@
   return NewLIR1(opcode, thread_offset);
 }
 
-LIR* X86Mir2Lir::OpMem(OpKind op, int rBase, int disp)
-{
+LIR* X86Mir2Lir::OpMem(OpKind op, int rBase, int disp) {
   X86OpCode opcode = kX86Bkpt;
   switch (op) {
     case kOpBlx: opcode = kX86CallM;  break;
@@ -330,8 +314,7 @@
   return NewLIR2(opcode, rBase, disp);
 }
 
-LIR* X86Mir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value)
-{
+LIR* X86Mir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) {
     int32_t val_lo = Low32Bits(value);
     int32_t val_hi = High32Bits(value);
     LIR *res;
@@ -558,23 +541,20 @@
 
 /* store value base base + scaled index. */
 LIR* X86Mir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src,
-                      int scale, OpSize size)
-{
+                      int scale, OpSize size) {
   return StoreBaseIndexedDisp(rBase, r_index, scale, 0,
                               r_src, INVALID_REG, size, INVALID_SREG);
 }
 
 LIR* X86Mir2Lir::StoreBaseDisp(int rBase, int displacement,
-                               int r_src, OpSize size)
-{
+                               int r_src, OpSize size) {
     return StoreBaseIndexedDisp(rBase, INVALID_REG, 0,
                                 displacement, r_src, INVALID_REG, size,
                                 INVALID_SREG);
 }
 
 LIR* X86Mir2Lir::StoreBaseDispWide(int rBase, int displacement,
-                                   int r_src_lo, int r_src_hi)
-{
+                                   int r_src_lo, int r_src_hi) {
   return StoreBaseIndexedDisp(rBase, INVALID_REG, 0, displacement,
                               r_src_lo, r_src_hi, kLong, INVALID_SREG);
 }
diff --git a/compiler/dex/ssa_transformation.cc b/compiler/dex/ssa_transformation.cc
index 4182072..ccd2454 100644
--- a/compiler/dex/ssa_transformation.cc
+++ b/compiler/dex/ssa_transformation.cc
@@ -37,8 +37,7 @@
   return bb;
 }
 
-BasicBlock* MIRGraph::NextUnvisitedSuccessor(BasicBlock* bb)
-{
+BasicBlock* MIRGraph::NextUnvisitedSuccessor(BasicBlock* bb) {
   BasicBlock* res = NeedsVisit(bb->fall_through);
   if (res == NULL) {
     res = NeedsVisit(bb->taken);
@@ -57,15 +56,13 @@
   return res;
 }
 
-void MIRGraph::MarkPreOrder(BasicBlock* block)
-{
+void MIRGraph::MarkPreOrder(BasicBlock* block) {
   block->visited = true;
   /* Enqueue the pre_order block id */
   dfs_order_->Insert(block->id);
 }
 
-void MIRGraph::RecordDFSOrders(BasicBlock* block)
-{
+void MIRGraph::RecordDFSOrders(BasicBlock* block) {
   std::vector<BasicBlock*> succ;
   MarkPreOrder(block);
   succ.push_back(block);
@@ -84,8 +81,7 @@
 }
 
 /* Sort the blocks by the Depth-First-Search */
-void MIRGraph::ComputeDFSOrders()
-{
+void MIRGraph::ComputeDFSOrders() {
   /* Initialize or reset the DFS pre_order list */
   if (dfs_order_ == NULL) {
     dfs_order_ = new (arena_) GrowableArray<int>(arena_, GetNumBlocks(), kGrowableArrayDfsOrder);
@@ -115,8 +111,7 @@
  * Mark block bit on the per-Dalvik register vector to denote that Dalvik
  * register idx is defined in BasicBlock bb.
  */
-bool MIRGraph::FillDefBlockMatrix(BasicBlock* bb)
-{
+bool MIRGraph::FillDefBlockMatrix(BasicBlock* bb) {
   if (bb->data_flow_info == NULL) return false;
 
   ArenaBitVector::Iterator iterator(bb->data_flow_info->def_v);
@@ -129,8 +124,7 @@
   return true;
 }
 
-void MIRGraph::ComputeDefBlockMatrix()
-{
+void MIRGraph::ComputeDefBlockMatrix() {
   int num_registers = cu_->num_dalvik_registers;
   /* Allocate num_dalvik_registers bit vector pointers */
   def_block_matrix_ = static_cast<ArenaBitVector**>
@@ -203,8 +197,7 @@
 }
 
 void MIRGraph::CheckForDominanceFrontier(BasicBlock* dom_bb,
-                                         const BasicBlock* succ_bb)
-{
+                                         const BasicBlock* succ_bb) {
   /*
    * TODO - evaluate whether phi will ever need to be inserted into exit
    * blocks.
@@ -217,8 +210,7 @@
 }
 
 /* Worker function to compute the dominance frontier */
-bool MIRGraph::ComputeDominanceFrontier(BasicBlock* bb)
-{
+bool MIRGraph::ComputeDominanceFrontier(BasicBlock* bb) {
   /* Calculate DF_local */
   if (bb->taken) {
     CheckForDominanceFrontier(bb, bb->taken);
@@ -257,8 +249,7 @@
 }
 
 /* Worker function for initializing domination-related data structures */
-void MIRGraph::InitializeDominationInfo(BasicBlock* bb)
-{
+void MIRGraph::InitializeDominationInfo(BasicBlock* bb) {
   int num_total_blocks = GetBasicBlockListCount();
 
   if (bb->dominators == NULL ) {
@@ -284,8 +275,7 @@
  * Given the ordering of i_dom_list, this common parent represents the
  * last element of the intersection of block1 and block2 dominators.
   */
-int MIRGraph::FindCommonParent(int block1, int block2)
-{
+int MIRGraph::FindCommonParent(int block1, int block2) {
   while (block1 != block2) {
     while (block1 < block2) {
       block1 = i_dom_list_[block1];
@@ -300,8 +290,7 @@
 }
 
 /* Worker function to compute each block's immediate dominator */
-bool MIRGraph::ComputeblockIDom(BasicBlock* bb)
-{
+bool MIRGraph::ComputeblockIDom(BasicBlock* bb) {
   /* Special-case entry block */
   if (bb == GetEntryBlock()) {
     return false;
@@ -343,8 +332,7 @@
 }
 
 /* Worker function to compute each block's domintors */
-bool MIRGraph::ComputeBlockDominators(BasicBlock* bb)
-{
+bool MIRGraph::ComputeBlockDominators(BasicBlock* bb) {
   if (bb == GetEntryBlock()) {
     bb->dominators->ClearAllBits();
   } else {
@@ -354,8 +342,7 @@
   return false;
 }
 
-bool MIRGraph::SetDominators(BasicBlock* bb)
-{
+bool MIRGraph::SetDominators(BasicBlock* bb) {
   if (bb != GetEntryBlock()) {
     int idom_dfs_idx = i_dom_list_[bb->dfs_id];
     DCHECK_NE(idom_dfs_idx, NOTVISITED);
@@ -369,8 +356,7 @@
 }
 
 /* Compute dominators, immediate dominator, and dominance fronter */
-void MIRGraph::ComputeDominators()
-{
+void MIRGraph::ComputeDominators() {
   int num_reachable_blocks = num_reachable_blocks_;
   int num_total_blocks = GetBasicBlockListCount();
 
@@ -435,8 +421,7 @@
  * This is probably not general enough to be placed in BitVector.[ch].
  */
 void MIRGraph::ComputeSuccLineIn(ArenaBitVector* dest, const ArenaBitVector* src1,
-                                 const ArenaBitVector* src2)
-{
+                                 const ArenaBitVector* src2) {
   if (dest->GetStorageSize() != src1->GetStorageSize() ||
       dest->GetStorageSize() != src2->GetStorageSize() ||
       dest->IsExpandable() != src1->IsExpandable() ||
@@ -455,8 +440,7 @@
  * The calculated result is used for phi-node pruning - where we only need to
  * insert a phi node if the variable is live-in to the block.
  */
-bool MIRGraph::ComputeBlockLiveIns(BasicBlock* bb)
-{
+bool MIRGraph::ComputeBlockLiveIns(BasicBlock* bb) {
   ArenaBitVector* temp_dalvik_register_v = temp_dalvik_register_v_;
 
   if (bb->data_flow_info == NULL) return false;
@@ -487,8 +471,7 @@
 }
 
 /* Insert phi nodes to for each variable to the dominance frontiers */
-void MIRGraph::InsertPhiNodes()
-{
+void MIRGraph::InsertPhiNodes() {
   int dalvik_reg;
   ArenaBitVector* phi_blocks =
       new (arena_) ArenaBitVector(arena_, GetNumBlocks(), false, kBitMapPhi);
@@ -569,8 +552,7 @@
  * Worker function to insert phi-operands with latest SSA names from
  * predecessor blocks
  */
-bool MIRGraph::InsertPhiNodeOperands(BasicBlock* bb)
-{
+bool MIRGraph::InsertPhiNodeOperands(BasicBlock* bb) {
   MIR *mir;
   std::vector<int> uses;
   std::vector<int> incoming_arc;
@@ -622,8 +604,7 @@
   return true;
 }
 
-void MIRGraph::DoDFSPreOrderSSARename(BasicBlock* block)
-{
+void MIRGraph::DoDFSPreOrderSSARename(BasicBlock* block) {
 
   if (block->visited || block->hidden) return;
   block->visited = true;
@@ -663,8 +644,7 @@
 }
 
 /* Perform SSA transformation for the whole method */
-void MIRGraph::SSATransformation()
-{
+void MIRGraph::SSATransformation() {
   /* Compute the DFS order */
   ComputeDFSOrders();
 
diff --git a/compiler/dex/vreg_analysis.cc b/compiler/dex/vreg_analysis.cc
index adbda5c..8df6dd9 100644
--- a/compiler/dex/vreg_analysis.cc
+++ b/compiler/dex/vreg_analysis.cc
@@ -72,8 +72,7 @@
  * as it doesn't propagate.  We're guaranteed at least one pass through
  * the cfg.
  */
-bool MIRGraph::InferTypeAndSize(BasicBlock* bb)
-{
+bool MIRGraph::InferTypeAndSize(BasicBlock* bb) {
   MIR *mir;
   bool changed = false;   // Did anything change?
 
@@ -333,8 +332,7 @@
 
 static const char* storage_name[] = {" Frame ", "PhysReg", " Spill "};
 
-void MIRGraph::DumpRegLocTable(RegLocation* table, int count)
-{
+void MIRGraph::DumpRegLocTable(RegLocation* table, int count) {
   //FIXME: Quick-specific.  Move to Quick (and make a generic version for MIRGraph?
   Mir2Lir* cg = static_cast<Mir2Lir*>(cu_->cg.get());
   if (cg != NULL) {
@@ -374,8 +372,7 @@
  * allocation is done on the fly.  We also do some initialization and
  * type inference here.
  */
-void MIRGraph::BuildRegLocations()
-{
+void MIRGraph::BuildRegLocations() {
   int i;
   RegLocation* loc;
 
diff --git a/compiler/driver/compiler_driver.cc b/compiler/driver/compiler_driver.cc
index 9e71dff..d1d21b1 100644
--- a/compiler/driver/compiler_driver.cc
+++ b/compiler/driver/compiler_driver.cc
@@ -356,14 +356,14 @@
       jni_compiler_(NULL),
       compiler_enable_auto_elf_loading_(NULL),
       compiler_get_method_code_addr_(NULL),
-      support_boot_image_fixup_(true)
-{
+      support_boot_image_fixup_(true) {
+
   CHECK_PTHREAD_CALL(pthread_key_create, (&tls_key_, NULL), "compiler tls key");
 
   // TODO: more work needed to combine initializations and allow per-method backend selection
   typedef void (*InitCompilerContextFn)(CompilerDriver&);
   InitCompilerContextFn init_compiler_context;
-  if (compiler_backend_ == kPortable){
+  if (compiler_backend_ == kPortable) {
     // Initialize compiler_context_
     init_compiler_context = reinterpret_cast<void (*)(CompilerDriver&)>(ArtInitCompilerContext);
     compiler_ = reinterpret_cast<CompilerFn>(ArtCompileMethod);
@@ -1411,10 +1411,7 @@
           begin_(begin),
           end_(end),
           callback_(callback),
-          stripe_(stripe)
-    {
-
-    }
+          stripe_(stripe) {}
 
     virtual void Run(Thread* self) {
       for (size_t i = begin_; i < end_; i += stripe_) {
@@ -2095,7 +2092,7 @@
           }
           if (!is_black_listed) {
             LOG(INFO) << "Initializing: " << descriptor;
-            if (StringPiece(descriptor) == "Ljava/lang/Void;"){
+            if (StringPiece(descriptor) == "Ljava/lang/Void;") {
               // Hand initialize j.l.Void to avoid Dex file operations in un-started runtime.
               mirror::ObjectArray<mirror::Field>* fields = klass->GetSFields();
               CHECK_EQ(fields->GetLength(), 1);
diff --git a/compiler/image_writer.cc b/compiler/image_writer.cc
index 8d32a91..7fd1a7c 100644
--- a/compiler/image_writer.cc
+++ b/compiler/image_writer.cc
@@ -108,7 +108,7 @@
     return false;
   }
 #ifndef NDEBUG
-  {
+  { // NOLINT(whitespace/braces)
     ScopedObjectAccess soa(Thread::Current());
     CheckNonImageClassesRemoved();
   }
diff --git a/compiler/jni/jni_compiler_test.cc b/compiler/jni/jni_compiler_test.cc
index 560a146..4b6967f 100644
--- a/compiler/jni/jni_compiler_test.cc
+++ b/compiler/jni/jni_compiler_test.cc
@@ -68,7 +68,7 @@
   void SetUpForTest(bool direct, const char* method_name, const char* method_sig,
                     void* native_fnptr) {
     // Initialize class loader and compile method when runtime not started.
-    if (!runtime_->IsStarted()){
+    if (!runtime_->IsStarted()) {
       {
         ScopedObjectAccess soa(Thread::Current());
         class_loader_ = LoadDex("MyClassNatives");
diff --git a/compiler/llvm/runtime_support_builder.cc b/compiler/llvm/runtime_support_builder.cc
index 28405f6..976aa8f 100644
--- a/compiler/llvm/runtime_support_builder.cc
+++ b/compiler/llvm/runtime_support_builder.cc
@@ -38,8 +38,7 @@
 RuntimeSupportBuilder::RuntimeSupportBuilder(::llvm::LLVMContext& context,
                                              ::llvm::Module& module,
                                              IRBuilder& irb)
-    : context_(context), module_(module), irb_(irb)
-{
+    : context_(context), module_(module), irb_(irb) {
   memset(target_runtime_support_func_, 0, sizeof(target_runtime_support_func_));
 #define GET_RUNTIME_SUPPORT_FUNC_DECL(ID, NAME) \
   do { \
diff --git a/jdwpspy/Common.h b/jdwpspy/Common.h
index 33f1a67..30a49fb 100644
--- a/jdwpspy/Common.h
+++ b/jdwpspy/Common.h
@@ -26,16 +26,14 @@
 /*
  * Get 1 byte.  (Included to make the code more legible.)
  */
-INLINE u1 get1(unsigned const char* pSrc)
-{
+INLINE u1 get1(unsigned const char* pSrc) {
     return *pSrc;
 }
 
 /*
  * Get 2 big-endian bytes.
  */
-INLINE u2 get2BE(unsigned char const* pSrc)
-{
+INLINE u2 get2BE(unsigned char const* pSrc) {
     u2 result;
 
     result = *pSrc++ << 8;
@@ -47,8 +45,7 @@
 /*
  * Get 4 big-endian bytes.
  */
-INLINE u4 get4BE(unsigned char const* pSrc)
-{
+INLINE u4 get4BE(unsigned char const* pSrc) {
     u4 result;
 
     result = *pSrc++ << 24;
@@ -62,8 +59,7 @@
 /*
  * Get 8 big-endian bytes.
  */
-INLINE u8 get8BE(unsigned char const* pSrc)
-{
+INLINE u8 get8BE(unsigned char const* pSrc) {
     u8 result;
 
     result = (u8) *pSrc++ << 56;
diff --git a/runtime/base/mutex.cc b/runtime/base/mutex.cc
index fbec826..bb4b5c5 100644
--- a/runtime/base/mutex.cc
+++ b/runtime/base/mutex.cc
@@ -465,7 +465,7 @@
 #if ART_USE_FUTEXES
     , state_(0), exclusive_owner_(0), num_pending_readers_(0), num_pending_writers_(0)
 #endif
-{
+{ // NOLINT(whitespace/braces)
 #if !ART_USE_FUTEXES
   CHECK_MUTEX_CALL(pthread_rwlock_init, (&rwlock_, NULL));
 #endif
diff --git a/runtime/common_throws.cc b/runtime/common_throws.cc
index 0497901..2a55e31 100644
--- a/runtime/common_throws.cc
+++ b/runtime/common_throws.cc
@@ -169,7 +169,7 @@
                  msg.str().c_str());
 }
 
-void ThrowIllegalAccessError(mirror::Class* referrer, const char* fmt, ...){
+void ThrowIllegalAccessError(mirror::Class* referrer, const char* fmt, ...) {
   va_list args;
   va_start(args, fmt);
   ThrowException(NULL, "Ljava/lang/IllegalAccessError;", referrer, fmt, &args);
@@ -222,7 +222,7 @@
                  msg.str().c_str());
 }
 
-void ThrowIncompatibleClassChangeError(const mirror::Class* referrer, const char* fmt, ...){
+void ThrowIncompatibleClassChangeError(const mirror::Class* referrer, const char* fmt, ...) {
   va_list args;
   va_start(args, fmt);
   ThrowException(NULL, "Ljava/lang/IncompatibleClassChangeError;", referrer, fmt, &args);
diff --git a/runtime/compiled_method.cc b/runtime/compiled_method.cc
index 757a324..49706ae 100644
--- a/runtime/compiled_method.cc
+++ b/runtime/compiled_method.cc
@@ -19,8 +19,7 @@
 namespace art {
 
 CompiledCode::CompiledCode(InstructionSet instruction_set, const std::vector<uint8_t>& code)
-    : instruction_set_(instruction_set), code_(code)
-{
+    : instruction_set_(instruction_set), code_(code) {
   CHECK_NE(code.size(), 0U);
 }
 
@@ -118,8 +117,7 @@
                                const std::vector<uint8_t>& native_gc_map)
     : CompiledCode(instruction_set, code), frame_size_in_bytes_(frame_size_in_bytes),
       core_spill_mask_(core_spill_mask), fp_spill_mask_(fp_spill_mask),
-      gc_map_(native_gc_map)
-{
+      gc_map_(native_gc_map) {
   DCHECK_EQ(vmap_table.size(),
             static_cast<uint32_t>(__builtin_popcount(core_spill_mask)
                                   + __builtin_popcount(fp_spill_mask)));
diff --git a/runtime/dex_file.cc b/runtime/dex_file.cc
index 1e37dcd..cd34c3c 100644
--- a/runtime/dex_file.cc
+++ b/runtime/dex_file.cc
@@ -252,7 +252,7 @@
 
 class ScopedJniMonitorLock {
  public:
-  ScopedJniMonitorLock(JNIEnv* env, jobject locked) : env_(env), locked_(locked){
+  ScopedJniMonitorLock(JNIEnv* env, jobject locked) : env_(env), locked_(locked) {
     env->MonitorEnter(locked_);
   }
   ~ScopedJniMonitorLock() {
diff --git a/runtime/dex_instruction.h b/runtime/dex_instruction.h
index d2ad989..c3424dc 100644
--- a/runtime/dex_instruction.h
+++ b/runtime/dex_instruction.h
@@ -82,7 +82,7 @@
   // TODO: the code layout below is deliberate to avoid this enum being picked up by
   //       generate-operator-out.py.
   enum Code
-  {
+  { // NOLINT(whitespace/braces)
 #define INSTRUCTION_ENUM(opcode, cname, p, f, r, i, a, v) cname = opcode,
 #include "dex_instruction_list.h"
     DEX_INSTRUCTION_LIST(INSTRUCTION_ENUM)
diff --git a/runtime/gc/space/large_object_space.cc b/runtime/gc/space/large_object_space.cc
index 3cee1b7..f7d776f 100644
--- a/runtime/gc/space/large_object_space.cc
+++ b/runtime/gc/space/large_object_space.cc
@@ -49,8 +49,7 @@
 
 LargeObjectMapSpace::LargeObjectMapSpace(const std::string& name)
     : LargeObjectSpace(name),
-      lock_("large object map space lock", kAllocSpaceLock)
-{
+      lock_("large object map space lock", kAllocSpaceLock) {
 
 }
 
@@ -274,7 +273,7 @@
   return reinterpret_cast<mirror::Object*>(addr);
 }
 
-void FreeListSpace::Dump(std::ostream& os) const{
+void FreeListSpace::Dump(std::ostream& os) const {
   os << GetName() << " -"
      << " begin: " << reinterpret_cast<void*>(Begin())
      << " end: " << reinterpret_cast<void*>(End());
diff --git a/runtime/interpreter/interpreter.cc b/runtime/interpreter/interpreter.cc
index 16e04a5..2fb272c 100644
--- a/runtime/interpreter/interpreter.cc
+++ b/runtime/interpreter/interpreter.cc
@@ -2574,7 +2574,7 @@
         POSSIBLY_HANDLE_PENDING_EXCEPTION(Next_1xx);
         break;
       }
-      case Instruction::SHL_INT_2ADDR:{
+      case Instruction::SHL_INT_2ADDR: {
         PREAMBLE();
         uint32_t vregA = inst->VRegA_12x();
         shadow_frame.SetVReg(vregA,
diff --git a/runtime/mirror/abstract_method.cc b/runtime/mirror/abstract_method.cc
index 88a9dc1..58ef5f7 100644
--- a/runtime/mirror/abstract_method.cc
+++ b/runtime/mirror/abstract_method.cc
@@ -262,7 +262,7 @@
 
   Runtime* runtime = Runtime::Current();
   // Call the invoke stub, passing everything as arguments.
-  if (UNLIKELY(!runtime->IsStarted())){
+  if (UNLIKELY(!runtime->IsStarted())) {
     LOG(INFO) << "Not invoking " << PrettyMethod(this) << " for a runtime that isn't started";
     if (result != NULL) {
       result->SetJ(0);
diff --git a/runtime/mirror/class-inl.h b/runtime/mirror/class-inl.h
index d323c33..52906a2 100644
--- a/runtime/mirror/class-inl.h
+++ b/runtime/mirror/class-inl.h
@@ -75,7 +75,7 @@
 }
 
 inline void Class::SetDirectMethod(uint32_t i, AbstractMethod* f)  // TODO: uint16_t
-    SHARED_LOCKS_REQUIRED(Locks::mutator_lock_){
+    SHARED_LOCKS_REQUIRED(Locks::mutator_lock_) {
   ObjectArray<AbstractMethod>* direct_methods =
       GetFieldObject<ObjectArray<AbstractMethod>*>(
           OFFSET_OF_OBJECT_MEMBER(Class, direct_methods_), false);
@@ -308,13 +308,13 @@
 }
 
 inline Field* Class::GetInstanceField(uint32_t i) const  // TODO: uint16_t
-    SHARED_LOCKS_REQUIRED(Locks::mutator_lock_){
+    SHARED_LOCKS_REQUIRED(Locks::mutator_lock_) {
   DCHECK_NE(NumInstanceFields(), 0U);
   return GetIFields()->Get(i);
 }
 
 inline void Class::SetInstanceField(uint32_t i, Field* f)  // TODO: uint16_t
-    SHARED_LOCKS_REQUIRED(Locks::mutator_lock_){
+    SHARED_LOCKS_REQUIRED(Locks::mutator_lock_) {
   ObjectArray<Field>* ifields= GetFieldObject<ObjectArray<Field>*>(
       OFFSET_OF_OBJECT_MEMBER(Class, ifields_), false);
   ifields->Set(i, f);
diff --git a/runtime/native/dalvik_system_Zygote.cc b/runtime/native/dalvik_system_Zygote.cc
index 9b995f4..e6b4513 100644
--- a/runtime/native/dalvik_system_Zygote.cc
+++ b/runtime/native/dalvik_system_Zygote.cc
@@ -492,7 +492,7 @@
     SetSchedulerPolicy();
 
 #if defined(HAVE_ANDROID_OS)
-    {
+    { // NOLINT(whitespace/braces)
       const char* se_info_c_str = NULL;
       UniquePtr<ScopedUtfChars> se_info;
       if (java_se_info != NULL) {
diff --git a/runtime/oat/runtime/support_jni.cc b/runtime/oat/runtime/support_jni.cc
index 8f0f7ca..25f6930 100644
--- a/runtime/oat/runtime/support_jni.cc
+++ b/runtime/oat/runtime/support_jni.cc
@@ -104,7 +104,7 @@
 }
 
 extern "C" const void* artWorkAroundAppJniBugs(Thread* self, intptr_t* sp)
-    SHARED_LOCKS_REQUIRED(Locks::mutator_lock_){
+    SHARED_LOCKS_REQUIRED(Locks::mutator_lock_) {
   DCHECK(Thread::Current() == self);
   // TODO: this code is specific to ARM
   // On entry the stack pointed by sp is:
diff --git a/runtime/oat/runtime/x86/context_x86.cc b/runtime/oat/runtime/x86/context_x86.cc
index ceb10bd..c728ae9 100644
--- a/runtime/oat/runtime/x86/context_x86.cc
+++ b/runtime/oat/runtime/x86/context_x86.cc
@@ -61,7 +61,7 @@
   gprs_[EBX] = NULL;
 }
 
-void X86Context::SetGPR(uint32_t reg, uintptr_t value){
+void X86Context::SetGPR(uint32_t reg, uintptr_t value) {
   CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
   CHECK_NE(gprs_[reg], &gZero);
   CHECK(gprs_[reg] != NULL);
diff --git a/runtime/oat_file.cc b/runtime/oat_file.cc
index 0f29915..bb8341e 100644
--- a/runtime/oat_file.cc
+++ b/runtime/oat_file.cc
@@ -358,8 +358,7 @@
     fp_spill_mask_(fp_spill_mask),
     mapping_table_offset_(mapping_table_offset),
     vmap_table_offset_(vmap_table_offset),
-    native_gc_map_offset_(gc_map_offset)
-{
+    native_gc_map_offset_(gc_map_offset) {
 #ifndef NDEBUG
   if (mapping_table_offset_ != 0) {  // implies non-native, non-stub code
     if (vmap_table_offset_ == 0) {
diff --git a/runtime/runtime.cc b/runtime/runtime.cc
index e5fb46f..14d4c8a 100644
--- a/runtime/runtime.cc
+++ b/runtime/runtime.cc
@@ -566,7 +566,7 @@
       Trace::SetDefaultClockSource(kProfilerClockSourceDual);
     } else if (option == "-small") {
       parsed->small_mode_ = true;
-    }else if (option == "-sea_ir") {
+    } else if (option == "-sea_ir") {
       parsed->sea_ir_mode_ = true;
     } else if (StartsWith(option, "-small-mode-methods-max:")) {
       parsed->small_mode_method_threshold_ = ParseIntegerOrDie(option);
diff --git a/runtime/thread_pool.cc b/runtime/thread_pool.cc
index f0f6f18..784a7ca 100644
--- a/runtime/thread_pool.cc
+++ b/runtime/thread_pool.cc
@@ -60,7 +60,7 @@
   return NULL;
 }
 
-void ThreadPool::AddTask(Thread* self, Task* task){
+void ThreadPool::AddTask(Thread* self, Task* task) {
   MutexLock mu(self, task_queue_lock_);
   tasks_.push_back(task);
   // If we have any waiters, signal one.
@@ -173,7 +173,7 @@
   }
 }
 
-size_t ThreadPool::GetTaskCount(Thread* self){
+size_t ThreadPool::GetTaskCount(Thread* self) {
   MutexLock mu(self, task_queue_lock_);
   return tasks_.size();
 }