Support for cross compilation.

Refactor architecture specific files into arm and x86 name spaces. Make
assemblers and calling conventions use the factory pattern and an
instruction set specifier.

Change-Id: I20cd7aecacc1ae3d418221d98bbe1d69be9162a7
diff --git a/build/Android.common.mk b/build/Android.common.mk
index d7346db..ec10d65 100644
--- a/build/Android.common.mk
+++ b/build/Android.common.mk
@@ -43,7 +43,11 @@
 
 LIBART_COMMON_SRC_FILES := \
 	src/assembler.cc \
+	src/assembler_arm.cc \
+	src/assembler_x86.cc \
 	src/calling_convention.cc \
+	src/calling_convention_arm.cc \
+	src/calling_convention_x86.cc \
 	src/check_jni.cc \
 	src/class_linker.cc \
 	src/class_loader.cc \
@@ -79,9 +83,13 @@
 	src/java_util_concurrent_atomic_AtomicLong.cc \
 	src/jni_compiler.cc \
 	src/jni_internal.cc \
+	src/jni_internal_arm.cc \
+	src/jni_internal_x86.cc \
 	src/logging.cc \
 	src/mark_stack.cc \
 	src/mark_sweep.cc \
+	src/managed_register_arm.cc \
+	src/managed_register_x86.cc \
 	src/memory_region.cc \
 	src/mspace.c \
 	src/object.cc \
@@ -102,21 +110,13 @@
 
 LIBART_TARGET_SRC_FILES := \
 	$(LIBART_COMMON_SRC_FILES) \
-	src/assembler_arm.cc \
-	src/calling_convention_arm.cc \
-	src/jni_internal_arm.cc \
 	src/logging_android.cc \
-	src/managed_register_arm.cc \
 	src/runtime_android.cc \
 	src/thread_arm.cc
 
 LIBART_HOST_SRC_FILES := \
 	$(LIBART_COMMON_SRC_FILES) \
-	src/assembler_x86.cc \
-	src/calling_convention_x86.cc \
-	src/jni_internal_x86.cc \
 	src/logging_linux.cc \
-	src/managed_register_x86.cc \
 	src/runtime_linux.cc \
 	src/thread_x86.cc
 
@@ -137,6 +137,8 @@
 	src/intern_table_test.cc \
 	src/jni_internal_test.cc \
 	src/jni_compiler_test.cc \
+	src/managed_register_arm_test.cc \
+	src/managed_register_x86_test.cc \
 	src/object_test.cc \
 	src/reference_table_test.cc \
 	src/runtime_test.cc \
@@ -146,13 +148,11 @@
 	src/compiler_test.cc
 
 TEST_TARGET_SRC_FILES := \
-	$(TEST_COMMON_SRC_FILES) \
-	src/managed_register_arm_test.cc
+	$(TEST_COMMON_SRC_FILES)
 
 TEST_HOST_SRC_FILES := \
 	$(TEST_COMMON_SRC_FILES) \
-	src/assembler_x86_test.cc \
-	src/managed_register_x86_test.cc
+	src/assembler_x86_test.cc
 
 # subdirectories of test/
 TEST_DEX_DIRECTORIES := \
diff --git a/src/assembler.cc b/src/assembler.cc
index 9e67f12..4ab882e 100644
--- a/src/assembler.cc
+++ b/src/assembler.cc
@@ -1,8 +1,12 @@
 // Copyright 2011 Google Inc. All Rights Reserved.
 
+#include "assembler.h"
+
 #include <algorithm>
 #include <vector>
-#include "assembler.h"
+
+#include "assembler_arm.h"
+#include "assembler_x86.h"
 #include "globals.h"
 #include "memory_region.h"
 
@@ -118,4 +122,14 @@
   CHECK_EQ(Size(), old_size);
 }
 
+
+Assembler* Assembler::Create(InstructionSet instruction_set) {
+  if (instruction_set == kX86) {
+    return new x86::X86Assembler();
+  } else {
+    CHECK(instruction_set == kArm || instruction_set == kThumb2);
+    return new arm::ArmAssembler();
+  }
+}
+
 }  // namespace art
diff --git a/src/assembler.h b/src/assembler.h
index 96d5ff0..7b5e77a 100644
--- a/src/assembler.h
+++ b/src/assembler.h
@@ -3,6 +3,9 @@
 #ifndef ART_SRC_ASSEMBLER_H_
 #define ART_SRC_ASSEMBLER_H_
 
+#include <vector>
+
+#include "constants.h"
 #include "logging.h"
 #include "macros.h"
 #include "managed_register.h"
@@ -15,6 +18,13 @@
 class AssemblerBuffer;
 class AssemblerFixup;
 
+namespace arm {
+  class ArmAssembler;
+}
+namespace x86 {
+  class X86Assembler;
+}
+
 class Label {
  public:
   Label() : position_(0) {}
@@ -59,7 +69,9 @@
     CHECK(IsLinked());
   }
 
-  friend class Assembler;
+  friend class arm::ArmAssembler;
+  friend class x86::X86Assembler;
+
   DISALLOW_COPY_AND_ASSIGN(Label);
 };
 
@@ -108,30 +120,6 @@
   DISALLOW_COPY_AND_ASSIGN(SlowPath);
 };
 
-// Slowpath entered when Thread::Current()->_exception is non-null
-class ExceptionSlowPath : public SlowPath {
- public:
-  ExceptionSlowPath() {}
-  virtual void Emit(Assembler *sp_asm);
-};
-
-// Slowpath entered when Thread::Current()->_suspend_count is non-zero
-class SuspendCountSlowPath : public SlowPath {
- public:
-  SuspendCountSlowPath(ManagedRegister return_reg,
-                       FrameOffset return_save_location,
-                       size_t return_size) :
-     return_register_(return_reg), return_save_location_(return_save_location),
-     return_size_(return_size) {}
-  virtual void Emit(Assembler *sp_asm);
-
- private:
-  // Remember how to save the return value
-  const ManagedRegister return_register_;
-  const FrameOffset return_save_location_;
-  const size_t return_size_;
-};
-
 class AssemblerBuffer {
  public:
   AssemblerBuffer();
@@ -297,12 +285,140 @@
   friend class AssemblerFixup;
 };
 
+class Assembler {
+ public:
+  static Assembler* Create(InstructionSet instruction_set);
+
+  // Emit slow paths queued during assembly
+  void EmitSlowPaths() { buffer_.EmitSlowPaths(this); }
+
+  // Size of generated code
+  size_t CodeSize() const { return buffer_.Size(); }
+
+  // Copy instructions out of assembly buffer into the given region of memory
+  void FinalizeInstructions(const MemoryRegion& region) {
+    buffer_.FinalizeInstructions(region);
+  }
+
+  // Emit code that will create an activation on the stack
+  virtual void BuildFrame(size_t frame_size, ManagedRegister method_reg,
+                          const std::vector<ManagedRegister>& spill_regs) = 0;
+
+  // Emit code that will remove an activation from the stack
+  virtual void RemoveFrame(size_t frame_size,
+                           const std::vector<ManagedRegister>& spill_regs) = 0;
+
+  // Fill list of registers from spill area
+  virtual void FillFromSpillArea(const std::vector<ManagedRegister>& spill_regs,
+                                 size_t displacement) = 0;
+
+  virtual void IncreaseFrameSize(size_t adjust) = 0;
+  virtual void DecreaseFrameSize(size_t adjust) = 0;
+
+  // Store routines
+  virtual void Store(FrameOffset offs, ManagedRegister src, size_t size) = 0;
+  virtual void StoreRef(FrameOffset dest, ManagedRegister src) = 0;
+  virtual void StoreRawPtr(FrameOffset dest, ManagedRegister src) = 0;
+
+  virtual void StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
+                                     ManagedRegister scratch) = 0;
+
+  virtual void StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
+                                      ManagedRegister scratch) = 0;
+
+  virtual void StoreStackOffsetToThread(ThreadOffset thr_offs,
+                                        FrameOffset fr_offs,
+                                        ManagedRegister scratch) = 0;
+
+  virtual void StoreStackPointerToThread(ThreadOffset thr_offs) = 0;
+
+  virtual void StoreSpanning(FrameOffset dest, ManagedRegister src,
+                             FrameOffset in_off, ManagedRegister scratch) = 0;
+
+  // Load routines
+  virtual void Load(ManagedRegister dest, FrameOffset src, size_t size) = 0;
+
+  virtual void LoadRef(ManagedRegister dest, FrameOffset  src) = 0;
+
+  virtual void LoadRef(ManagedRegister dest, ManagedRegister base,
+                       MemberOffset offs) = 0;
+
+  virtual void LoadRawPtr(ManagedRegister dest, ManagedRegister base,
+                          Offset offs) = 0;
+
+  virtual void LoadRawPtrFromThread(ManagedRegister dest,
+                                    ThreadOffset offs) = 0;
+
+  // Copying routines
+  virtual void Move(ManagedRegister dest, ManagedRegister src) = 0;
+
+  virtual void CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs,
+                                    ManagedRegister scratch) = 0;
+
+  virtual void CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
+                                  ManagedRegister scratch) = 0;
+
+  virtual void CopyRef(FrameOffset dest, FrameOffset src,
+                       ManagedRegister scratch) = 0;
+
+  virtual void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch,
+                    unsigned int size) = 0;
+
+  // Exploit fast access in managed code to Thread::Current()
+  virtual void GetCurrentThread(ManagedRegister tr) = 0;
+  virtual void GetCurrentThread(FrameOffset dest_offset,
+                                ManagedRegister scratch) = 0;
+
+  // Set up out_reg to hold a Object** into the SIRT, or to be NULL if the
+  // value is null and null_allowed. in_reg holds a possibly stale reference
+  // that can be used to avoid loading the SIRT entry to see if the value is
+  // NULL.
+  virtual void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset,
+                               ManagedRegister in_reg, bool null_allowed) = 0;
+
+  // Set up out_off to hold a Object** into the SIRT, or to be NULL if the
+  // value is null and null_allowed.
+  virtual void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset,
+                               ManagedRegister scratch, bool null_allowed) = 0;
+
+  // src holds a SIRT entry (Object**) load this into dst
+  virtual void LoadReferenceFromSirt(ManagedRegister dst,
+                                     ManagedRegister src) = 0;
+
+  // Heap::VerifyObject on src. In some cases (such as a reference to this) we
+  // know that src may not be null.
+  virtual void VerifyObject(ManagedRegister src, bool could_be_null) = 0;
+  virtual void VerifyObject(FrameOffset src, bool could_be_null) = 0;
+
+  // Call to address held at [base+offset]
+  virtual void Call(ManagedRegister base, Offset offset,
+                    ManagedRegister scratch) = 0;
+  virtual void Call(FrameOffset base, Offset offset,
+                    ManagedRegister scratch) = 0;
+  virtual void Call(uintptr_t addr, ManagedRegister scratch) = 0;
+
+  // Generate code to check if Thread::Current()->suspend_count_ is non-zero
+  // and branch to a SuspendSlowPath if it is. The SuspendSlowPath will continue
+  // at the next instruction.
+  virtual void SuspendPoll(ManagedRegister scratch, ManagedRegister return_reg,
+                           FrameOffset return_save_location,
+                           size_t return_size) = 0;
+
+  // Generate code to check if Thread::Current()->exception_ is non-null
+  // and branch to a ExceptionSlowPath if it is.
+  virtual void ExceptionPoll(ManagedRegister scratch) = 0;
+
+  virtual ~Assembler() {}
+
+ protected:
+  Assembler() : buffer_() {}
+
+  AssemblerBuffer buffer_;
+};
+
 }  // namespace art
 
-#if defined(__i386__)
 #include "assembler_x86.h"
-#elif defined(__arm__)
 #include "assembler_arm.h"
-#endif
 
 #endif  // ART_SRC_ASSEMBLER_H_
diff --git a/src/assembler_arm.cc b/src/assembler_arm.cc
index 9f4e03f..591012f 100644
--- a/src/assembler_arm.cc
+++ b/src/assembler_arm.cc
@@ -1,12 +1,14 @@
 // Copyright 2011 Google Inc. All Rights Reserved.
 
-#include "assembler.h"
+#include "assembler_arm.h"
+
 #include "logging.h"
 #include "offsets.h"
 #include "thread.h"
 #include "utils.h"
 
 namespace art {
+namespace arm {
 
 // Instruction encoding bits.
 enum {
@@ -111,20 +113,19 @@
   return os;
 }
 
-
-void Assembler::Emit(int32_t value) {
+void ArmAssembler::Emit(int32_t value) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   buffer_.Emit<int32_t>(value);
 }
 
 
-void Assembler::EmitType01(Condition cond,
-                           int type,
-                           Opcode opcode,
-                           int set_cc,
-                           Register rn,
-                           Register rd,
-                           ShifterOperand so) {
+void ArmAssembler::EmitType01(Condition cond,
+                              int type,
+                              Opcode opcode,
+                              int set_cc,
+                              Register rn,
+                              Register rd,
+                              ShifterOperand so) {
   CHECK_NE(rd, kNoRegister);
   CHECK_NE(cond, kNoCondition);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
@@ -138,20 +139,20 @@
 }
 
 
-void Assembler::EmitType5(Condition cond, int offset, bool link) {
+void ArmAssembler::EmitType5(Condition cond, int offset, bool link) {
   CHECK_NE(cond, kNoCondition);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      5 << kTypeShift |
                      (link ? 1 : 0) << kLinkShift;
-  Emit(Assembler::EncodeBranchOffset(offset, encoding));
+  Emit(ArmAssembler::EncodeBranchOffset(offset, encoding));
 }
 
 
-void Assembler::EmitMemOp(Condition cond,
-                          bool load,
-                          bool byte,
-                          Register rd,
-                          Address ad) {
+void ArmAssembler::EmitMemOp(Condition cond,
+                             bool load,
+                             bool byte,
+                             Register rd,
+                             Address ad) {
   CHECK_NE(rd, kNoRegister);
   CHECK_NE(cond, kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
@@ -164,10 +165,10 @@
 }
 
 
-void Assembler::EmitMemOpAddressMode3(Condition cond,
-                                      int32_t mode,
-                                      Register rd,
-                                      Address ad) {
+void ArmAssembler::EmitMemOpAddressMode3(Condition cond,
+                                         int32_t mode,
+                                         Register rd,
+                                         Address ad) {
   CHECK_NE(rd, kNoRegister);
   CHECK_NE(cond, kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
@@ -179,11 +180,11 @@
 }
 
 
-void Assembler::EmitMultiMemOp(Condition cond,
-                               BlockAddressMode am,
-                               bool load,
-                               Register base,
-                               RegList regs) {
+void ArmAssembler::EmitMultiMemOp(Condition cond,
+                                  BlockAddressMode am,
+                                  bool load,
+                                  Register base,
+                                  RegList regs) {
   CHECK_NE(base, kNoRegister);
   CHECK_NE(cond, kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
@@ -196,11 +197,11 @@
 }
 
 
-void Assembler::EmitShiftImmediate(Condition cond,
-                                   Shift opcode,
-                                   Register rd,
-                                   Register rm,
-                                   ShifterOperand so) {
+void ArmAssembler::EmitShiftImmediate(Condition cond,
+                                      Shift opcode,
+                                      Register rd,
+                                      Register rm,
+                                      ShifterOperand so) {
   CHECK_NE(cond, kNoCondition);
   CHECK_EQ(so.type(), 1U);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
@@ -213,11 +214,11 @@
 }
 
 
-void Assembler::EmitShiftRegister(Condition cond,
-                                  Shift opcode,
-                                  Register rd,
-                                  Register rm,
-                                  ShifterOperand so) {
+void ArmAssembler::EmitShiftRegister(Condition cond,
+                                     Shift opcode,
+                                     Register rd,
+                                     Register rm,
+                                     ShifterOperand so) {
   CHECK_NE(cond, kNoCondition);
   CHECK_EQ(so.type(), 0U);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
@@ -231,7 +232,7 @@
 }
 
 
-void Assembler::EmitBranch(Condition cond, Label* label, bool link) {
+void ArmAssembler::EmitBranch(Condition cond, Label* label, bool link) {
   if (label->IsBound()) {
     EmitType5(cond, label->Position() - buffer_.Size(), link);
   } else {
@@ -242,131 +243,131 @@
   }
 }
 
-void Assembler::and_(Register rd, Register rn, ShifterOperand so,
-                     Condition cond) {
+void ArmAssembler::and_(Register rd, Register rn, ShifterOperand so,
+                        Condition cond) {
   EmitType01(cond, so.type(), AND, 0, rn, rd, so);
 }
 
 
-void Assembler::eor(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
+void ArmAssembler::eor(Register rd, Register rn, ShifterOperand so,
+                       Condition cond) {
   EmitType01(cond, so.type(), EOR, 0, rn, rd, so);
 }
 
 
-void Assembler::sub(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
+void ArmAssembler::sub(Register rd, Register rn, ShifterOperand so,
+                       Condition cond) {
   EmitType01(cond, so.type(), SUB, 0, rn, rd, so);
 }
 
-void Assembler::rsb(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
+void ArmAssembler::rsb(Register rd, Register rn, ShifterOperand so,
+                       Condition cond) {
   EmitType01(cond, so.type(), RSB, 0, rn, rd, so);
 }
 
-void Assembler::rsbs(Register rd, Register rn, ShifterOperand so,
-                     Condition cond) {
+void ArmAssembler::rsbs(Register rd, Register rn, ShifterOperand so,
+                        Condition cond) {
   EmitType01(cond, so.type(), RSB, 1, rn, rd, so);
 }
 
 
-void Assembler::add(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
+void ArmAssembler::add(Register rd, Register rn, ShifterOperand so,
+                       Condition cond) {
   EmitType01(cond, so.type(), ADD, 0, rn, rd, so);
 }
 
 
-void Assembler::adds(Register rd, Register rn, ShifterOperand so,
-                     Condition cond) {
+void ArmAssembler::adds(Register rd, Register rn, ShifterOperand so,
+                        Condition cond) {
   EmitType01(cond, so.type(), ADD, 1, rn, rd, so);
 }
 
 
-void Assembler::subs(Register rd, Register rn, ShifterOperand so,
-                     Condition cond) {
+void ArmAssembler::subs(Register rd, Register rn, ShifterOperand so,
+                        Condition cond) {
   EmitType01(cond, so.type(), SUB, 1, rn, rd, so);
 }
 
 
-void Assembler::adc(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
+void ArmAssembler::adc(Register rd, Register rn, ShifterOperand so,
+                       Condition cond) {
   EmitType01(cond, so.type(), ADC, 0, rn, rd, so);
 }
 
 
-void Assembler::sbc(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
+void ArmAssembler::sbc(Register rd, Register rn, ShifterOperand so,
+                       Condition cond) {
   EmitType01(cond, so.type(), SBC, 0, rn, rd, so);
 }
 
 
-void Assembler::rsc(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
+void ArmAssembler::rsc(Register rd, Register rn, ShifterOperand so,
+                       Condition cond) {
   EmitType01(cond, so.type(), RSC, 0, rn, rd, so);
 }
 
 
-void Assembler::tst(Register rn, ShifterOperand so, Condition cond) {
+void ArmAssembler::tst(Register rn, ShifterOperand so, Condition cond) {
   CHECK_NE(rn, PC);  // Reserve tst pc instruction for exception handler marker.
   EmitType01(cond, so.type(), TST, 1, rn, R0, so);
 }
 
 
-void Assembler::teq(Register rn, ShifterOperand so, Condition cond) {
+void ArmAssembler::teq(Register rn, ShifterOperand so, Condition cond) {
   CHECK_NE(rn, PC);  // Reserve teq pc instruction for exception handler marker.
   EmitType01(cond, so.type(), TEQ, 1, rn, R0, so);
 }
 
 
-void Assembler::cmp(Register rn, ShifterOperand so, Condition cond) {
+void ArmAssembler::cmp(Register rn, ShifterOperand so, Condition cond) {
   EmitType01(cond, so.type(), CMP, 1, rn, R0, so);
 }
 
 
-void Assembler::cmn(Register rn, ShifterOperand so, Condition cond) {
+void ArmAssembler::cmn(Register rn, ShifterOperand so, Condition cond) {
   EmitType01(cond, so.type(), CMN, 1, rn, R0, so);
 }
 
 
-void Assembler::orr(Register rd, Register rn,
+void ArmAssembler::orr(Register rd, Register rn,
                     ShifterOperand so, Condition cond) {
   EmitType01(cond, so.type(), ORR, 0, rn, rd, so);
 }
 
 
-void Assembler::orrs(Register rd, Register rn,
-                     ShifterOperand so, Condition cond) {
+void ArmAssembler::orrs(Register rd, Register rn,
+                        ShifterOperand so, Condition cond) {
   EmitType01(cond, so.type(), ORR, 1, rn, rd, so);
 }
 
 
-void Assembler::mov(Register rd, ShifterOperand so, Condition cond) {
+void ArmAssembler::mov(Register rd, ShifterOperand so, Condition cond) {
   EmitType01(cond, so.type(), MOV, 0, R0, rd, so);
 }
 
 
-void Assembler::movs(Register rd, ShifterOperand so, Condition cond) {
+void ArmAssembler::movs(Register rd, ShifterOperand so, Condition cond) {
   EmitType01(cond, so.type(), MOV, 1, R0, rd, so);
 }
 
 
-void Assembler::bic(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
+void ArmAssembler::bic(Register rd, Register rn, ShifterOperand so,
+                       Condition cond) {
   EmitType01(cond, so.type(), BIC, 0, rn, rd, so);
 }
 
 
-void Assembler::mvn(Register rd, ShifterOperand so, Condition cond) {
+void ArmAssembler::mvn(Register rd, ShifterOperand so, Condition cond) {
   EmitType01(cond, so.type(), MVN, 0, R0, rd, so);
 }
 
 
-void Assembler::mvns(Register rd, ShifterOperand so, Condition cond) {
+void ArmAssembler::mvns(Register rd, ShifterOperand so, Condition cond) {
   EmitType01(cond, so.type(), MVN, 1, R0, rd, so);
 }
 
 
-void Assembler::clz(Register rd, Register rm, Condition cond) {
+void ArmAssembler::clz(Register rd, Register rm, Condition cond) {
   CHECK_NE(rd, kNoRegister);
   CHECK_NE(rm, kNoRegister);
   CHECK_NE(cond, kNoCondition);
@@ -380,7 +381,7 @@
 }
 
 
-void Assembler::movw(Register rd, uint16_t imm16, Condition cond) {
+void ArmAssembler::movw(Register rd, uint16_t imm16, Condition cond) {
   CHECK_NE(cond, kNoCondition);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      B25 | B24 | ((imm16 >> 12) << 16) |
@@ -389,7 +390,7 @@
 }
 
 
-void Assembler::movt(Register rd, uint16_t imm16, Condition cond) {
+void ArmAssembler::movt(Register rd, uint16_t imm16, Condition cond) {
   CHECK_NE(cond, kNoCondition);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      B25 | B24 | B22 | ((imm16 >> 12) << 16) |
@@ -398,9 +399,9 @@
 }
 
 
-void Assembler::EmitMulOp(Condition cond, int32_t opcode,
-                          Register rd, Register rn,
-                          Register rm, Register rs) {
+void ArmAssembler::EmitMulOp(Condition cond, int32_t opcode,
+                             Register rd, Register rn,
+                             Register rm, Register rs) {
   CHECK_NE(rd, kNoRegister);
   CHECK_NE(rn, kNoRegister);
   CHECK_NE(rm, kNoRegister);
@@ -417,103 +418,102 @@
 }
 
 
-void Assembler::mul(Register rd, Register rn,
-                    Register rm, Condition cond) {
+void ArmAssembler::mul(Register rd, Register rn, Register rm, Condition cond) {
   // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
   EmitMulOp(cond, 0, R0, rd, rn, rm);
 }
 
 
-void Assembler::mla(Register rd, Register rn,
-                    Register rm, Register ra, Condition cond) {
+void ArmAssembler::mla(Register rd, Register rn, Register rm, Register ra,
+                       Condition cond) {
   // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
   EmitMulOp(cond, B21, ra, rd, rn, rm);
 }
 
 
-void Assembler::mls(Register rd, Register rn,
-                    Register rm, Register ra, Condition cond) {
+void ArmAssembler::mls(Register rd, Register rn, Register rm, Register ra,
+                       Condition cond) {
   // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
   EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
 }
 
 
-void Assembler::umull(Register rd_lo, Register rd_hi,
-                      Register rn, Register rm, Condition cond) {
+void ArmAssembler::umull(Register rd_lo, Register rd_hi, Register rn,
+                         Register rm, Condition cond) {
   // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
   EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm);
 }
 
 
-void Assembler::ldr(Register rd, Address ad, Condition cond) {
+void ArmAssembler::ldr(Register rd, Address ad, Condition cond) {
   EmitMemOp(cond, true, false, rd, ad);
 }
 
 
-void Assembler::str(Register rd, Address ad, Condition cond) {
+void ArmAssembler::str(Register rd, Address ad, Condition cond) {
   EmitMemOp(cond, false, false, rd, ad);
 }
 
 
-void Assembler::ldrb(Register rd, Address ad, Condition cond) {
+void ArmAssembler::ldrb(Register rd, Address ad, Condition cond) {
   EmitMemOp(cond, true, true, rd, ad);
 }
 
 
-void Assembler::strb(Register rd, Address ad, Condition cond) {
+void ArmAssembler::strb(Register rd, Address ad, Condition cond) {
   EmitMemOp(cond, false, true, rd, ad);
 }
 
 
-void Assembler::ldrh(Register rd, Address ad, Condition cond) {
+void ArmAssembler::ldrh(Register rd, Address ad, Condition cond) {
   EmitMemOpAddressMode3(cond, L | B7 | H | B4, rd, ad);
 }
 
 
-void Assembler::strh(Register rd, Address ad, Condition cond) {
+void ArmAssembler::strh(Register rd, Address ad, Condition cond) {
   EmitMemOpAddressMode3(cond, B7 | H | B4, rd, ad);
 }
 
 
-void Assembler::ldrsb(Register rd, Address ad, Condition cond) {
+void ArmAssembler::ldrsb(Register rd, Address ad, Condition cond) {
   EmitMemOpAddressMode3(cond, L | B7 | B6 | B4, rd, ad);
 }
 
 
-void Assembler::ldrsh(Register rd, Address ad, Condition cond) {
+void ArmAssembler::ldrsh(Register rd, Address ad, Condition cond) {
   EmitMemOpAddressMode3(cond, L | B7 | B6 | H | B4, rd, ad);
 }
 
 
-void Assembler::ldrd(Register rd, Address ad, Condition cond) {
+void ArmAssembler::ldrd(Register rd, Address ad, Condition cond) {
   CHECK_EQ(rd % 2, 0);
   EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, ad);
 }
 
 
-void Assembler::strd(Register rd, Address ad, Condition cond) {
+void ArmAssembler::strd(Register rd, Address ad, Condition cond) {
   CHECK_EQ(rd % 2, 0);
   EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, ad);
 }
 
 
-void Assembler::ldm(BlockAddressMode am,
-                    Register base,
-                    RegList regs,
-                    Condition cond) {
+void ArmAssembler::ldm(BlockAddressMode am,
+                       Register base,
+                       RegList regs,
+                       Condition cond) {
   EmitMultiMemOp(cond, am, true, base, regs);
 }
 
 
-void Assembler::stm(BlockAddressMode am,
-                    Register base,
-                    RegList regs,
-                    Condition cond) {
+void ArmAssembler::stm(BlockAddressMode am,
+                       Register base,
+                       RegList regs,
+                       Condition cond) {
   EmitMultiMemOp(cond, am, false, base, regs);
 }
 
 
-void Assembler::ldrex(Register rt, Register rn, Condition cond) {
+void ArmAssembler::ldrex(Register rt, Register rn, Condition cond) {
   CHECK_NE(rn, kNoRegister);
   CHECK_NE(rt, kNoRegister);
   CHECK_NE(cond, kNoCondition);
@@ -528,10 +528,10 @@
 }
 
 
-void Assembler::strex(Register rd,
-                      Register rt,
-                      Register rn,
-                      Condition cond) {
+void ArmAssembler::strex(Register rd,
+                         Register rt,
+                         Register rn,
+                         Condition cond) {
   CHECK_NE(rn, kNoRegister);
   CHECK_NE(rd, kNoRegister);
   CHECK_NE(rt, kNoRegister);
@@ -547,14 +547,14 @@
 }
 
 
-void Assembler::clrex() {
+void ArmAssembler::clrex() {
   int32_t encoding = (kSpecialCondition << kConditionShift) |
                      B26 | B24 | B22 | B21 | B20 | (0xff << 12) | B4 | 0xf;
   Emit(encoding);
 }
 
 
-void Assembler::nop(Condition cond) {
+void ArmAssembler::nop(Condition cond) {
   CHECK_NE(cond, kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
                      B25 | B24 | B21 | (0xf << 12);
@@ -562,7 +562,7 @@
 }
 
 
-void Assembler::vmovsr(SRegister sn, Register rt, Condition cond) {
+void ArmAssembler::vmovsr(SRegister sn, Register rt, Condition cond) {
   CHECK_NE(sn, kNoSRegister);
   CHECK_NE(rt, kNoRegister);
   CHECK_NE(rt, SP);
@@ -577,7 +577,7 @@
 }
 
 
-void Assembler::vmovrs(Register rt, SRegister sn, Condition cond) {
+void ArmAssembler::vmovrs(Register rt, SRegister sn, Condition cond) {
   CHECK_NE(sn, kNoSRegister);
   CHECK_NE(rt, kNoRegister);
   CHECK_NE(rt, SP);
@@ -592,8 +592,8 @@
 }
 
 
-void Assembler::vmovsrr(SRegister sm, Register rt, Register rt2,
-                        Condition cond) {
+void ArmAssembler::vmovsrr(SRegister sm, Register rt, Register rt2,
+                           Condition cond) {
   CHECK_NE(sm, kNoSRegister);
   CHECK_NE(sm, S31);
   CHECK_NE(rt, kNoRegister);
@@ -613,8 +613,8 @@
 }
 
 
-void Assembler::vmovrrs(Register rt, Register rt2, SRegister sm,
-                        Condition cond) {
+void ArmAssembler::vmovrrs(Register rt, Register rt2, SRegister sm,
+                           Condition cond) {
   CHECK_NE(sm, kNoSRegister);
   CHECK_NE(sm, S31);
   CHECK_NE(rt, kNoRegister);
@@ -635,8 +635,8 @@
 }
 
 
-void Assembler::vmovdrr(DRegister dm, Register rt, Register rt2,
-                        Condition cond) {
+void ArmAssembler::vmovdrr(DRegister dm, Register rt, Register rt2,
+                           Condition cond) {
   CHECK_NE(dm, kNoDRegister);
   CHECK_NE(rt, kNoRegister);
   CHECK_NE(rt, SP);
@@ -655,8 +655,8 @@
 }
 
 
-void Assembler::vmovrrd(Register rt, Register rt2, DRegister dm,
-                              Condition cond) {
+void ArmAssembler::vmovrrd(Register rt, Register rt2, DRegister dm,
+                           Condition cond) {
   CHECK_NE(dm, kNoDRegister);
   CHECK_NE(rt, kNoRegister);
   CHECK_NE(rt, SP);
@@ -676,7 +676,7 @@
 }
 
 
-void Assembler::vldrs(SRegister sd, Address ad, Condition cond) {
+void ArmAssembler::vldrs(SRegister sd, Address ad, Condition cond) {
   CHECK_NE(sd, kNoSRegister);
   CHECK_NE(cond, kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
@@ -688,7 +688,7 @@
 }
 
 
-void Assembler::vstrs(SRegister sd, Address ad, Condition cond) {
+void ArmAssembler::vstrs(SRegister sd, Address ad, Condition cond) {
   CHECK_NE(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)), PC);
   CHECK_NE(sd, kNoSRegister);
   CHECK_NE(cond, kNoCondition);
@@ -701,7 +701,7 @@
 }
 
 
-void Assembler::vldrd(DRegister dd, Address ad, Condition cond) {
+void ArmAssembler::vldrd(DRegister dd, Address ad, Condition cond) {
   CHECK_NE(dd, kNoDRegister);
   CHECK_NE(cond, kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
@@ -713,7 +713,7 @@
 }
 
 
-void Assembler::vstrd(DRegister dd, Address ad, Condition cond) {
+void ArmAssembler::vstrd(DRegister dd, Address ad, Condition cond) {
   CHECK_NE(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)), PC);
   CHECK_NE(dd, kNoDRegister);
   CHECK_NE(cond, kNoCondition);
@@ -726,8 +726,8 @@
 }
 
 
-void Assembler::EmitVFPsss(Condition cond, int32_t opcode,
-                           SRegister sd, SRegister sn, SRegister sm) {
+void ArmAssembler::EmitVFPsss(Condition cond, int32_t opcode,
+                              SRegister sd, SRegister sn, SRegister sm) {
   CHECK_NE(sd, kNoSRegister);
   CHECK_NE(sn, kNoSRegister);
   CHECK_NE(sm, kNoSRegister);
@@ -744,8 +744,8 @@
 }
 
 
-void Assembler::EmitVFPddd(Condition cond, int32_t opcode,
-                           DRegister dd, DRegister dn, DRegister dm) {
+void ArmAssembler::EmitVFPddd(Condition cond, int32_t opcode,
+                              DRegister dd, DRegister dn, DRegister dm) {
   CHECK_NE(dd, kNoDRegister);
   CHECK_NE(dn, kNoDRegister);
   CHECK_NE(dm, kNoDRegister);
@@ -762,17 +762,17 @@
 }
 
 
-void Assembler::vmovs(SRegister sd, SRegister sm, Condition cond) {
+void ArmAssembler::vmovs(SRegister sd, SRegister sm, Condition cond) {
   EmitVFPsss(cond, B23 | B21 | B20 | B6, sd, S0, sm);
 }
 
 
-void Assembler::vmovd(DRegister dd, DRegister dm, Condition cond) {
+void ArmAssembler::vmovd(DRegister dd, DRegister dm, Condition cond) {
   EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm);
 }
 
 
-bool Assembler::vmovs(SRegister sd, float s_imm, Condition cond) {
+bool ArmAssembler::vmovs(SRegister sd, float s_imm, Condition cond) {
   uint32_t imm32 = bit_cast<uint32_t, float>(s_imm);
   if (((imm32 & ((1 << 19) - 1)) == 0) &&
       ((((imm32 >> 25) & ((1 << 6) - 1)) == (1 << 5)) ||
@@ -787,7 +787,7 @@
 }
 
 
-bool Assembler::vmovd(DRegister dd, double d_imm, Condition cond) {
+bool ArmAssembler::vmovd(DRegister dd, double d_imm, Condition cond) {
   uint64_t imm64 = bit_cast<uint64_t, double>(d_imm);
   if (((imm64 & ((1LL << 48) - 1)) == 0) &&
       ((((imm64 >> 54) & ((1 << 9) - 1)) == (1 << 8)) ||
@@ -802,109 +802,109 @@
 }
 
 
-void Assembler::vadds(SRegister sd, SRegister sn, SRegister sm,
-                      Condition cond) {
+void ArmAssembler::vadds(SRegister sd, SRegister sn, SRegister sm,
+                         Condition cond) {
   EmitVFPsss(cond, B21 | B20, sd, sn, sm);
 }
 
 
-void Assembler::vaddd(DRegister dd, DRegister dn, DRegister dm,
-                      Condition cond) {
+void ArmAssembler::vaddd(DRegister dd, DRegister dn, DRegister dm,
+                         Condition cond) {
   EmitVFPddd(cond, B21 | B20, dd, dn, dm);
 }
 
 
-void Assembler::vsubs(SRegister sd, SRegister sn, SRegister sm,
-                      Condition cond) {
+void ArmAssembler::vsubs(SRegister sd, SRegister sn, SRegister sm,
+                         Condition cond) {
   EmitVFPsss(cond, B21 | B20 | B6, sd, sn, sm);
 }
 
 
-void Assembler::vsubd(DRegister dd, DRegister dn, DRegister dm,
-                      Condition cond) {
+void ArmAssembler::vsubd(DRegister dd, DRegister dn, DRegister dm,
+                         Condition cond) {
   EmitVFPddd(cond, B21 | B20 | B6, dd, dn, dm);
 }
 
 
-void Assembler::vmuls(SRegister sd, SRegister sn, SRegister sm,
-                      Condition cond) {
+void ArmAssembler::vmuls(SRegister sd, SRegister sn, SRegister sm,
+                         Condition cond) {
   EmitVFPsss(cond, B21, sd, sn, sm);
 }
 
 
-void Assembler::vmuld(DRegister dd, DRegister dn, DRegister dm,
-                      Condition cond) {
+void ArmAssembler::vmuld(DRegister dd, DRegister dn, DRegister dm,
+                         Condition cond) {
   EmitVFPddd(cond, B21, dd, dn, dm);
 }
 
 
-void Assembler::vmlas(SRegister sd, SRegister sn, SRegister sm,
-                      Condition cond) {
+void ArmAssembler::vmlas(SRegister sd, SRegister sn, SRegister sm,
+                         Condition cond) {
   EmitVFPsss(cond, 0, sd, sn, sm);
 }
 
 
-void Assembler::vmlad(DRegister dd, DRegister dn, DRegister dm,
-                      Condition cond) {
+void ArmAssembler::vmlad(DRegister dd, DRegister dn, DRegister dm,
+                         Condition cond) {
   EmitVFPddd(cond, 0, dd, dn, dm);
 }
 
 
-void Assembler::vmlss(SRegister sd, SRegister sn, SRegister sm,
-                      Condition cond) {
+void ArmAssembler::vmlss(SRegister sd, SRegister sn, SRegister sm,
+                         Condition cond) {
   EmitVFPsss(cond, B6, sd, sn, sm);
 }
 
 
-void Assembler::vmlsd(DRegister dd, DRegister dn, DRegister dm,
-                      Condition cond) {
+void ArmAssembler::vmlsd(DRegister dd, DRegister dn, DRegister dm,
+                         Condition cond) {
   EmitVFPddd(cond, B6, dd, dn, dm);
 }
 
 
-void Assembler::vdivs(SRegister sd, SRegister sn, SRegister sm,
-                      Condition cond) {
+void ArmAssembler::vdivs(SRegister sd, SRegister sn, SRegister sm,
+                         Condition cond) {
   EmitVFPsss(cond, B23, sd, sn, sm);
 }
 
 
-void Assembler::vdivd(DRegister dd, DRegister dn, DRegister dm,
-                      Condition cond) {
+void ArmAssembler::vdivd(DRegister dd, DRegister dn, DRegister dm,
+                         Condition cond) {
   EmitVFPddd(cond, B23, dd, dn, dm);
 }
 
 
-void Assembler::vabss(SRegister sd, SRegister sm, Condition cond) {
+void ArmAssembler::vabss(SRegister sd, SRegister sm, Condition cond) {
   EmitVFPsss(cond, B23 | B21 | B20 | B7 | B6, sd, S0, sm);
 }
 
 
-void Assembler::vabsd(DRegister dd, DRegister dm, Condition cond) {
+void ArmAssembler::vabsd(DRegister dd, DRegister dm, Condition cond) {
   EmitVFPddd(cond, B23 | B21 | B20 | B7 | B6, dd, D0, dm);
 }
 
 
-void Assembler::vnegs(SRegister sd, SRegister sm, Condition cond) {
+void ArmAssembler::vnegs(SRegister sd, SRegister sm, Condition cond) {
   EmitVFPsss(cond, B23 | B21 | B20 | B16 | B6, sd, S0, sm);
 }
 
 
-void Assembler::vnegd(DRegister dd, DRegister dm, Condition cond) {
+void ArmAssembler::vnegd(DRegister dd, DRegister dm, Condition cond) {
   EmitVFPddd(cond, B23 | B21 | B20 | B16 | B6, dd, D0, dm);
 }
 
 
-void Assembler::vsqrts(SRegister sd, SRegister sm, Condition cond) {
+void ArmAssembler::vsqrts(SRegister sd, SRegister sm, Condition cond) {
   EmitVFPsss(cond, B23 | B21 | B20 | B16 | B7 | B6, sd, S0, sm);
 }
 
-void Assembler::vsqrtd(DRegister dd, DRegister dm, Condition cond) {
+void ArmAssembler::vsqrtd(DRegister dd, DRegister dm, Condition cond) {
   EmitVFPddd(cond, B23 | B21 | B20 | B16 | B7 | B6, dd, D0, dm);
 }
 
 
-void Assembler::EmitVFPsd(Condition cond, int32_t opcode,
-                          SRegister sd, DRegister dm) {
+void ArmAssembler::EmitVFPsd(Condition cond, int32_t opcode,
+                             SRegister sd, DRegister dm) {
   CHECK_NE(sd, kNoSRegister);
   CHECK_NE(dm, kNoDRegister);
   CHECK_NE(cond, kNoCondition);
@@ -918,8 +918,8 @@
 }
 
 
-void Assembler::EmitVFPds(Condition cond, int32_t opcode,
-                          DRegister dd, SRegister sm) {
+void ArmAssembler::EmitVFPds(Condition cond, int32_t opcode,
+                             DRegister dd, SRegister sm) {
   CHECK_NE(dd, kNoDRegister);
   CHECK_NE(sm, kNoSRegister);
   CHECK_NE(cond, kNoCondition);
@@ -933,77 +933,77 @@
 }
 
 
-void Assembler::vcvtsd(SRegister sd, DRegister dm, Condition cond) {
+void ArmAssembler::vcvtsd(SRegister sd, DRegister dm, Condition cond) {
   EmitVFPsd(cond, B23 | B21 | B20 | B18 | B17 | B16 | B8 | B7 | B6, sd, dm);
 }
 
 
-void Assembler::vcvtds(DRegister dd, SRegister sm, Condition cond) {
+void ArmAssembler::vcvtds(DRegister dd, SRegister sm, Condition cond) {
   EmitVFPds(cond, B23 | B21 | B20 | B18 | B17 | B16 | B7 | B6, dd, sm);
 }
 
 
-void Assembler::vcvtis(SRegister sd, SRegister sm, Condition cond) {
+void ArmAssembler::vcvtis(SRegister sd, SRegister sm, Condition cond) {
   EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm);
 }
 
 
-void Assembler::vcvtid(SRegister sd, DRegister dm, Condition cond) {
+void ArmAssembler::vcvtid(SRegister sd, DRegister dm, Condition cond) {
   EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B16 | B8 | B7 | B6, sd, dm);
 }
 
 
-void Assembler::vcvtsi(SRegister sd, SRegister sm, Condition cond) {
+void ArmAssembler::vcvtsi(SRegister sd, SRegister sm, Condition cond) {
   EmitVFPsss(cond, B23 | B21 | B20 | B19 | B7 | B6, sd, S0, sm);
 }
 
 
-void Assembler::vcvtdi(DRegister dd, SRegister sm, Condition cond) {
+void ArmAssembler::vcvtdi(DRegister dd, SRegister sm, Condition cond) {
   EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B7 | B6, dd, sm);
 }
 
 
-void Assembler::vcvtus(SRegister sd, SRegister sm, Condition cond) {
+void ArmAssembler::vcvtus(SRegister sd, SRegister sm, Condition cond) {
   EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B7 | B6, sd, S0, sm);
 }
 
 
-void Assembler::vcvtud(SRegister sd, DRegister dm, Condition cond) {
+void ArmAssembler::vcvtud(SRegister sd, DRegister dm, Condition cond) {
   EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B8 | B7 | B6, sd, dm);
 }
 
 
-void Assembler::vcvtsu(SRegister sd, SRegister sm, Condition cond) {
+void ArmAssembler::vcvtsu(SRegister sd, SRegister sm, Condition cond) {
   EmitVFPsss(cond, B23 | B21 | B20 | B19 | B6, sd, S0, sm);
 }
 
 
-void Assembler::vcvtdu(DRegister dd, SRegister sm, Condition cond) {
+void ArmAssembler::vcvtdu(DRegister dd, SRegister sm, Condition cond) {
   EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B6, dd, sm);
 }
 
 
-void Assembler::vcmps(SRegister sd, SRegister sm, Condition cond) {
+void ArmAssembler::vcmps(SRegister sd, SRegister sm, Condition cond) {
   EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm);
 }
 
 
-void Assembler::vcmpd(DRegister dd, DRegister dm, Condition cond) {
+void ArmAssembler::vcmpd(DRegister dd, DRegister dm, Condition cond) {
   EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm);
 }
 
 
-void Assembler::vcmpsz(SRegister sd, Condition cond) {
+void ArmAssembler::vcmpsz(SRegister sd, Condition cond) {
   EmitVFPsss(cond, B23 | B21 | B20 | B18 | B16 | B6, sd, S0, S0);
 }
 
 
-void Assembler::vcmpdz(DRegister dd, Condition cond) {
+void ArmAssembler::vcmpdz(DRegister dd, Condition cond) {
   EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0);
 }
 
 
-void Assembler::vmstat(Condition cond) {  // VMRS APSR_nzcv, FPSCR
+void ArmAssembler::vmstat(Condition cond) {  // VMRS APSR_nzcv, FPSCR
   CHECK_NE(cond, kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
                      B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 |
@@ -1013,31 +1013,31 @@
 }
 
 
-void Assembler::svc(uint32_t imm24) {
+void ArmAssembler::svc(uint32_t imm24) {
   CHECK(IsUint(24, imm24));
   int32_t encoding = (AL << kConditionShift) | B27 | B26 | B25 | B24 | imm24;
   Emit(encoding);
 }
 
 
-void Assembler::bkpt(uint16_t imm16) {
+void ArmAssembler::bkpt(uint16_t imm16) {
   int32_t encoding = (AL << kConditionShift) | B24 | B21 |
                      ((imm16 >> 4) << 8) | B6 | B5 | B4 | (imm16 & 0xf);
   Emit(encoding);
 }
 
 
-void Assembler::b(Label* label, Condition cond) {
+void ArmAssembler::b(Label* label, Condition cond) {
   EmitBranch(cond, label, false);
 }
 
 
-void Assembler::bl(Label* label, Condition cond) {
+void ArmAssembler::bl(Label* label, Condition cond) {
   EmitBranch(cond, label, true);
 }
 
 
-void Assembler::blx(Register rm, Condition cond) {
+void ArmAssembler::blx(Register rm, Condition cond) {
   CHECK_NE(rm, kNoRegister);
   CHECK_NE(cond, kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
@@ -1047,7 +1047,7 @@
 }
 
 
-void Assembler::MarkExceptionHandler(Label* label) {
+void ArmAssembler::MarkExceptionHandler(Label* label) {
   EmitType01(AL, 1, TST, 1, PC, R0, ShifterOperand(0));
   Label l;
   b(&l);
@@ -1056,21 +1056,21 @@
 }
 
 
-void Assembler::Bind(Label* label) {
+void ArmAssembler::Bind(Label* label) {
   CHECK(!label->IsBound());
   int bound_pc = buffer_.Size();
   while (label->IsLinked()) {
     int32_t position = label->Position();
     int32_t next = buffer_.Load<int32_t>(position);
-    int32_t encoded = Assembler::EncodeBranchOffset(bound_pc - position, next);
+    int32_t encoded = ArmAssembler::EncodeBranchOffset(bound_pc - position, next);
     buffer_.Store<int32_t>(position, encoded);
-    label->position_ = Assembler::DecodeBranchOffset(next);
+    label->position_ = ArmAssembler::DecodeBranchOffset(next);
   }
   label->BindTo(bound_pc);
 }
 
 
-void Assembler::EncodeUint32InTstInstructions(uint32_t data) {
+void ArmAssembler::EncodeUint32InTstInstructions(uint32_t data) {
   // TODO: Consider using movw ip, <16 bits>.
   while (!IsUint(8, data)) {
     tst(R0, ShifterOperand(data & 0xFF), VS);
@@ -1080,7 +1080,7 @@
 }
 
 
-int32_t Assembler::EncodeBranchOffset(int offset, int32_t inst) {
+int32_t ArmAssembler::EncodeBranchOffset(int offset, int32_t inst) {
   // The offset is off by 8 due to the way the ARM CPUs read PC.
   offset -= 8;
   CHECK(IsAligned(offset, 4));
@@ -1093,18 +1093,18 @@
 }
 
 
-int Assembler::DecodeBranchOffset(int32_t inst) {
+int ArmAssembler::DecodeBranchOffset(int32_t inst) {
   // Sign-extend, left-shift by 2, then add 8.
   return ((((inst & kBranchOffsetMask) << 8) >> 6) + 8);
 }
 
-void Assembler::AddConstant(Register rd, int32_t value, Condition cond) {
+void ArmAssembler::AddConstant(Register rd, int32_t value, Condition cond) {
   AddConstant(rd, rd, value, cond);
 }
 
 
-void Assembler::AddConstant(Register rd, Register rn, int32_t value,
-                            Condition cond) {
+void ArmAssembler::AddConstant(Register rd, Register rn, int32_t value,
+                               Condition cond) {
   if (value == 0) {
     if (rd != rn) {
       mov(rd, ShifterOperand(rn), cond);
@@ -1139,8 +1139,8 @@
 }
 
 
-void Assembler::AddConstantSetFlags(Register rd, Register rn, int32_t value,
-                                    Condition cond) {
+void ArmAssembler::AddConstantSetFlags(Register rd, Register rn, int32_t value,
+                                       Condition cond) {
   ShifterOperand shifter_op;
   if (ShifterOperand::CanHold(value, &shifter_op)) {
     adds(rd, rn, shifter_op, cond);
@@ -1166,7 +1166,7 @@
 }
 
 
-void Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) {
+void ArmAssembler::LoadImmediate(Register rd, int32_t value, Condition cond) {
   ShifterOperand shifter_op;
   if (ShifterOperand::CanHold(value, &shifter_op)) {
     mov(rd, shifter_op, cond);
@@ -1222,7 +1222,7 @@
 
 // Implementation note: this method must emit at most one instruction when
 // Address::CanHoldLoadOffset.
-void Assembler::LoadFromOffset(LoadOperandType type,
+void ArmAssembler::LoadFromOffset(LoadOperandType type,
                                Register reg,
                                Register base,
                                int32_t offset,
@@ -1261,10 +1261,10 @@
 
 // Implementation note: this method must emit at most one instruction when
 // Address::CanHoldLoadOffset, as expected by JIT::GuardedLoadFromOffset.
-void Assembler::LoadSFromOffset(SRegister reg,
-                                Register base,
-                                int32_t offset,
-                                Condition cond) {
+void ArmAssembler::LoadSFromOffset(SRegister reg,
+                                   Register base,
+                                   int32_t offset,
+                                   Condition cond) {
   if (!Address::CanHoldLoadOffset(kLoadSWord, offset)) {
     CHECK_NE(base, IP);
     LoadImmediate(IP, offset, cond);
@@ -1278,10 +1278,10 @@
 
 // Implementation note: this method must emit at most one instruction when
 // Address::CanHoldLoadOffset, as expected by JIT::GuardedLoadFromOffset.
-void Assembler::LoadDFromOffset(DRegister reg,
-                                Register base,
-                                int32_t offset,
-                                Condition cond) {
+void ArmAssembler::LoadDFromOffset(DRegister reg,
+                                   Register base,
+                                   int32_t offset,
+                                   Condition cond) {
   if (!Address::CanHoldLoadOffset(kLoadDWord, offset)) {
     CHECK_NE(base, IP);
     LoadImmediate(IP, offset, cond);
@@ -1295,11 +1295,11 @@
 
 // Implementation note: this method must emit at most one instruction when
 // Address::CanHoldStoreOffset.
-void Assembler::StoreToOffset(StoreOperandType type,
-                              Register reg,
-                              Register base,
-                              int32_t offset,
-                              Condition cond) {
+void ArmAssembler::StoreToOffset(StoreOperandType type,
+                                 Register reg,
+                                 Register base,
+                                 int32_t offset,
+                                 Condition cond) {
   if (!Address::CanHoldStoreOffset(type, offset)) {
     CHECK(reg != IP);
     CHECK(base != IP);
@@ -1329,10 +1329,10 @@
 
 // Implementation note: this method must emit at most one instruction when
 // Address::CanHoldStoreOffset, as expected by JIT::GuardedStoreToOffset.
-void Assembler::StoreSToOffset(SRegister reg,
-                               Register base,
-                               int32_t offset,
-                               Condition cond) {
+void ArmAssembler::StoreSToOffset(SRegister reg,
+                                  Register base,
+                                  int32_t offset,
+                                  Condition cond) {
   if (!Address::CanHoldStoreOffset(kStoreSWord, offset)) {
     CHECK_NE(base, IP);
     LoadImmediate(IP, offset, cond);
@@ -1346,10 +1346,10 @@
 
 // Implementation note: this method must emit at most one instruction when
 // Address::CanHoldStoreOffset, as expected by JIT::GuardedStoreSToOffset.
-void Assembler::StoreDToOffset(DRegister reg,
-                               Register base,
-                               int32_t offset,
-                               Condition cond) {
+void ArmAssembler::StoreDToOffset(DRegister reg,
+                                  Register base,
+                                  int32_t offset,
+                                  Condition cond) {
   if (!Address::CanHoldStoreOffset(kStoreDWord, offset)) {
     CHECK_NE(base, IP);
     LoadImmediate(IP, offset, cond);
@@ -1361,66 +1361,66 @@
   vstrd(reg, Address(base, offset), cond);
 }
 
-void Assembler::Push(Register rd, Condition cond) {
+void ArmAssembler::Push(Register rd, Condition cond) {
   str(rd, Address(SP, -kRegisterSize, Address::PreIndex), cond);
 }
 
-void Assembler::Pop(Register rd, Condition cond) {
+void ArmAssembler::Pop(Register rd, Condition cond) {
   ldr(rd, Address(SP, kRegisterSize, Address::PostIndex), cond);
 }
 
-void Assembler::PushList(RegList regs, Condition cond) {
+void ArmAssembler::PushList(RegList regs, Condition cond) {
   stm(DB_W, SP, regs, cond);
 }
 
-void Assembler::PopList(RegList regs, Condition cond) {
+void ArmAssembler::PopList(RegList regs, Condition cond) {
   ldm(IA_W, SP, regs, cond);
 }
 
-void Assembler::Mov(Register rd, Register rm, Condition cond) {
+void ArmAssembler::Mov(Register rd, Register rm, Condition cond) {
   if (rd != rm) {
     mov(rd, ShifterOperand(rm), cond);
   }
 }
 
-void Assembler::Lsl(Register rd, Register rm, uint32_t shift_imm,
-                    Condition cond) {
+void ArmAssembler::Lsl(Register rd, Register rm, uint32_t shift_imm,
+                       Condition cond) {
   CHECK_NE(shift_imm, 0u);  // Do not use Lsl if no shift is wanted.
   mov(rd, ShifterOperand(rm, LSL, shift_imm), cond);
 }
 
-void Assembler::Lsr(Register rd, Register rm, uint32_t shift_imm,
-                    Condition cond) {
+void ArmAssembler::Lsr(Register rd, Register rm, uint32_t shift_imm,
+                       Condition cond) {
   CHECK_NE(shift_imm, 0u);  // Do not use Lsr if no shift is wanted.
   if (shift_imm == 32) shift_imm = 0;  // Comply to UAL syntax.
   mov(rd, ShifterOperand(rm, LSR, shift_imm), cond);
 }
 
-void Assembler::Asr(Register rd, Register rm, uint32_t shift_imm,
-                    Condition cond) {
+void ArmAssembler::Asr(Register rd, Register rm, uint32_t shift_imm,
+                       Condition cond) {
   CHECK_NE(shift_imm, 0u);  // Do not use Asr if no shift is wanted.
   if (shift_imm == 32) shift_imm = 0;  // Comply to UAL syntax.
   mov(rd, ShifterOperand(rm, ASR, shift_imm), cond);
 }
 
-void Assembler::Ror(Register rd, Register rm, uint32_t shift_imm,
-                    Condition cond) {
+void ArmAssembler::Ror(Register rd, Register rm, uint32_t shift_imm,
+                       Condition cond) {
   CHECK_NE(shift_imm, 0u);  // Use Rrx instruction.
   mov(rd, ShifterOperand(rm, ROR, shift_imm), cond);
 }
 
-void Assembler::Rrx(Register rd, Register rm, Condition cond) {
+void ArmAssembler::Rrx(Register rd, Register rm, Condition cond) {
   mov(rd, ShifterOperand(rm, ROR, 0), cond);
 }
 
-void Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg,
-                           const std::vector<ManagedRegister>& spill_regs) {
+void ArmAssembler::BuildFrame(size_t frame_size, ManagedRegister method_reg,
+                              const std::vector<ManagedRegister>& spill_regs) {
   CHECK(IsAligned(frame_size, kStackAlignment));
-  CHECK_EQ(R0, method_reg.AsCoreRegister());
+  CHECK_EQ(R0, method_reg.AsArm().AsCoreRegister());
   AddConstant(SP, -frame_size);
   RegList spill_list = 1 << R0 | 1 << LR;
   for (size_t i = 0; i < spill_regs.size(); i++) {
-    Register reg = spill_regs.at(i).AsCoreRegister();
+    Register reg = spill_regs.at(i).AsArm().AsCoreRegister();
     // check assumption LR is the last register that gets spilled
     CHECK_LT(reg, LR);
     spill_list |= 1 << reg;
@@ -1430,8 +1430,8 @@
   stm(IA, SP, spill_list, AL);
 }
 
-void Assembler::RemoveFrame(size_t frame_size,
-                            const std::vector<ManagedRegister>& spill_regs) {
+void ArmAssembler::RemoveFrame(size_t frame_size,
+                              const std::vector<ManagedRegister>& spill_regs) {
   CHECK(IsAligned(frame_size, kStackAlignment));
   // Reload LR. TODO: reload any saved callee saves from spill_regs
   LoadFromOffset(kLoadWord, LR, SP, (spill_regs.size() + 1) * kPointerSize);
@@ -1439,25 +1439,26 @@
   mov(PC, ShifterOperand(LR));
 }
 
-void Assembler::FillFromSpillArea(const std::vector<ManagedRegister>& spill_regs,
-                                  size_t displacement) {
+void ArmAssembler::FillFromSpillArea(const std::vector<ManagedRegister>& spill_regs,
+                                     size_t displacement) {
   for(size_t i = 0; i < spill_regs.size(); i++) {
-    Register reg = spill_regs.at(i).AsCoreRegister();
+    Register reg = spill_regs.at(i).AsArm().AsCoreRegister();
     LoadFromOffset(kLoadWord, reg, SP, displacement + ((i + 1) * kPointerSize));
   }
 }
 
-void Assembler::IncreaseFrameSize(size_t adjust) {
+void ArmAssembler::IncreaseFrameSize(size_t adjust) {
   CHECK(IsAligned(adjust, kStackAlignment));
   AddConstant(SP, -adjust);
 }
 
-void Assembler::DecreaseFrameSize(size_t adjust) {
+void ArmAssembler::DecreaseFrameSize(size_t adjust) {
   CHECK(IsAligned(adjust, kStackAlignment));
   AddConstant(SP, adjust);
 }
 
-void Assembler::Store(FrameOffset dest, ManagedRegister src, size_t size) {
+void ArmAssembler::Store(FrameOffset dest, ManagedRegister msrc, size_t size) {
+  ArmManagedRegister src = msrc.AsArm();
   if (src.IsNoRegister()) {
     CHECK_EQ(0u, size);
   } else if (src.IsCoreRegister()) {
@@ -1476,58 +1477,75 @@
   }
 }
 
-void Assembler::StoreRef(FrameOffset dest, ManagedRegister src) {
+void ArmAssembler::StoreRef(FrameOffset dest, ManagedRegister msrc) {
+  ArmManagedRegister src = msrc.AsArm();
   CHECK(src.IsCoreRegister());
   StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
 }
 
-void Assembler::StoreRawPtr(FrameOffset dest, ManagedRegister src) {
+void ArmAssembler::StoreRawPtr(FrameOffset dest, ManagedRegister msrc) {
+  ArmManagedRegister src = msrc.AsArm();
   CHECK(src.IsCoreRegister());
   StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
 }
 
-void Assembler::StoreSpanning(FrameOffset dest, ManagedRegister src,
-                              FrameOffset in_off, ManagedRegister scratch) {
+void ArmAssembler::StoreSpanning(FrameOffset dest, ManagedRegister msrc,
+                              FrameOffset in_off, ManagedRegister mscratch) {
+  ArmManagedRegister src = msrc.AsArm();
+  ArmManagedRegister scratch = mscratch.AsArm();
   StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
   LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, in_off.Int32Value());
   StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value() + 4);
 }
 
-void Assembler::CopyRef(FrameOffset dest, FrameOffset src,
-                        ManagedRegister scratch) {
+void ArmAssembler::CopyRef(FrameOffset dest, FrameOffset src,
+                        ManagedRegister mscratch) {
+  ArmManagedRegister scratch = mscratch.AsArm();
   LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, src.Int32Value());
   StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value());
 }
 
-void Assembler::LoadRef(ManagedRegister dest, ManagedRegister base,
-                        MemberOffset offs) {
+void ArmAssembler::LoadRef(ManagedRegister mdest, ManagedRegister base,
+                           MemberOffset offs) {
+  ArmManagedRegister dest = mdest.AsArm();
   CHECK(dest.IsCoreRegister() && dest.IsCoreRegister());
   LoadFromOffset(kLoadWord, dest.AsCoreRegister(),
-                 base.AsCoreRegister(), offs.Int32Value());
+                 base.AsArm().AsCoreRegister(), offs.Int32Value());
 }
 
-void Assembler::LoadRawPtr(ManagedRegister dest, ManagedRegister base,
+void ArmAssembler::LoadRef(ManagedRegister mdest, FrameOffset  src) {
+  ArmManagedRegister dest = mdest.AsArm();
+   CHECK(dest.IsCoreRegister());
+   LoadFromOffset(kLoadWord, dest.AsCoreRegister(),
+                  SP, src.Int32Value());
+ }
+
+void ArmAssembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base,
                            Offset offs) {
+  ArmManagedRegister dest = mdest.AsArm();
   CHECK(dest.IsCoreRegister() && dest.IsCoreRegister());
   LoadFromOffset(kLoadWord, dest.AsCoreRegister(),
-                 base.AsCoreRegister(), offs.Int32Value());
+                 base.AsArm().AsCoreRegister(), offs.Int32Value());
 }
 
-void Assembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
-                                      ManagedRegister scratch) {
+void ArmAssembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
+                                      ManagedRegister mscratch) {
+  ArmManagedRegister scratch = mscratch.AsArm();
   CHECK(scratch.IsCoreRegister());
   LoadImmediate(scratch.AsCoreRegister(), imm);
   StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value());
 }
 
-void Assembler::StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
-                                       ManagedRegister scratch) {
+void ArmAssembler::StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
+                                       ManagedRegister mscratch) {
+  ArmManagedRegister scratch = mscratch.AsArm();
   CHECK(scratch.IsCoreRegister());
   LoadImmediate(scratch.AsCoreRegister(), imm);
   StoreToOffset(kStoreWord, scratch.AsCoreRegister(), TR, dest.Int32Value());
 }
 
-void Assembler::Load(ManagedRegister dest, FrameOffset src, size_t size) {
+void ArmAssembler::Load(ManagedRegister mdest, FrameOffset src, size_t size) {
+  ArmManagedRegister dest = mdest.AsArm();
   if (dest.IsNoRegister()) {
     CHECK_EQ(0u, size);
   } else if (dest.IsCoreRegister()) {
@@ -1546,14 +1564,18 @@
   }
 }
 
-void Assembler::LoadRawPtrFromThread(ManagedRegister dest, ThreadOffset offs) {
+void ArmAssembler::LoadRawPtrFromThread(ManagedRegister mdest,
+                                        ThreadOffset offs) {
+  ArmManagedRegister dest = mdest.AsArm();
   CHECK(dest.IsCoreRegister());
   LoadFromOffset(kLoadWord, dest.AsCoreRegister(),
                  TR, offs.Int32Value());
 }
 
-void Assembler::CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs,
-                                     ManagedRegister scratch) {
+void ArmAssembler::CopyRawPtrFromThread(FrameOffset fr_offs,
+                                        ThreadOffset thr_offs,
+                                        ManagedRegister mscratch) {
+  ArmManagedRegister scratch = mscratch.AsArm();
   CHECK(scratch.IsCoreRegister());
   LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
                  TR, thr_offs.Int32Value());
@@ -1561,8 +1583,10 @@
                 SP, fr_offs.Int32Value());
 }
 
-void Assembler::CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
-                                   ManagedRegister scratch) {
+void ArmAssembler::CopyRawPtrToThread(ThreadOffset thr_offs,
+                                      FrameOffset fr_offs,
+                                      ManagedRegister mscratch) {
+  ArmManagedRegister scratch = mscratch.AsArm();
   CHECK(scratch.IsCoreRegister());
   LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
                  SP, fr_offs.Int32Value());
@@ -1570,20 +1594,23 @@
                 TR, thr_offs.Int32Value());
 }
 
-void Assembler::StoreStackOffsetToThread(ThreadOffset thr_offs,
-                                         FrameOffset fr_offs,
-                                         ManagedRegister scratch) {
+void ArmAssembler::StoreStackOffsetToThread(ThreadOffset thr_offs,
+                                            FrameOffset fr_offs,
+                                            ManagedRegister mscratch) {
+  ArmManagedRegister scratch = mscratch.AsArm();
   CHECK(scratch.IsCoreRegister());
   AddConstant(scratch.AsCoreRegister(), SP, fr_offs.Int32Value(), AL);
   StoreToOffset(kStoreWord, scratch.AsCoreRegister(),
                 TR, thr_offs.Int32Value());
 }
 
-void Assembler::StoreStackPointerToThread(ThreadOffset thr_offs) {
+void ArmAssembler::StoreStackPointerToThread(ThreadOffset thr_offs) {
   StoreToOffset(kStoreWord, SP, TR, thr_offs.Int32Value());
 }
 
-void Assembler::Move(ManagedRegister dest, ManagedRegister src) {
+void ArmAssembler::Move(ManagedRegister mdest, ManagedRegister msrc) {
+  ArmManagedRegister dest = mdest.AsArm();
+  ArmManagedRegister src = msrc.AsArm();
   if (!dest.Equals(src)) {
     if (dest.IsCoreRegister()) {
       CHECK(src.IsCoreRegister());
@@ -1609,8 +1636,9 @@
   }
 }
 
-void Assembler::Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch,
-                     size_t size) {
+void ArmAssembler::Copy(FrameOffset dest, FrameOffset src,
+                        ManagedRegister mscratch, size_t size) {
+  ArmManagedRegister scratch = mscratch.AsArm();
   CHECK(scratch.IsCoreRegister());
   CHECK(size == 4 || size == 8);
   if (size == 4) {
@@ -1630,9 +1658,11 @@
   }
 }
 
-void Assembler::CreateSirtEntry(ManagedRegister out_reg,
-                                FrameOffset sirt_offset,
-                                ManagedRegister in_reg, bool null_allowed) {
+void ArmAssembler::CreateSirtEntry(ManagedRegister mout_reg,
+                                   FrameOffset sirt_offset,
+                                   ManagedRegister min_reg, bool null_allowed) {
+  ArmManagedRegister out_reg = mout_reg.AsArm();
+  ArmManagedRegister in_reg = min_reg.AsArm();
   CHECK(in_reg.IsNoRegister() || in_reg.IsCoreRegister());
   CHECK(out_reg.IsCoreRegister());
   if (null_allowed) {
@@ -1654,9 +1684,11 @@
   }
 }
 
-void Assembler::CreateSirtEntry(FrameOffset out_off,
-                                FrameOffset sirt_offset,
-                                ManagedRegister scratch, bool null_allowed) {
+void ArmAssembler::CreateSirtEntry(FrameOffset out_off,
+                                   FrameOffset sirt_offset,
+                                   ManagedRegister mscratch,
+                                   bool null_allowed) {
+  ArmManagedRegister scratch = mscratch.AsArm();
   CHECK(scratch.IsCoreRegister());
   if (null_allowed) {
     LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP,
@@ -1672,8 +1704,10 @@
   StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, out_off.Int32Value());
 }
 
-void Assembler::LoadReferenceFromSirt(ManagedRegister out_reg,
-                                      ManagedRegister in_reg) {
+void ArmAssembler::LoadReferenceFromSirt(ManagedRegister mout_reg,
+                                         ManagedRegister min_reg) {
+  ArmManagedRegister out_reg = mout_reg.AsArm();
+  ArmManagedRegister in_reg = min_reg.AsArm();
   CHECK(out_reg.IsCoreRegister());
   CHECK(in_reg.IsCoreRegister());
   Label null_arg;
@@ -1685,16 +1719,18 @@
                  in_reg.AsCoreRegister(), 0, NE);
 }
 
-void Assembler::VerifyObject(ManagedRegister src, bool could_be_null) {
+void ArmAssembler::VerifyObject(ManagedRegister src, bool could_be_null) {
   // TODO: not validating references
 }
 
-void Assembler::VerifyObject(FrameOffset src, bool could_be_null) {
+void ArmAssembler::VerifyObject(FrameOffset src, bool could_be_null) {
   // TODO: not validating references
 }
 
-void Assembler::Call(ManagedRegister base, Offset offset,
-                     ManagedRegister scratch) {
+void ArmAssembler::Call(ManagedRegister mbase, Offset offset,
+                        ManagedRegister mscratch) {
+  ArmManagedRegister base = mbase.AsArm();
+  ArmManagedRegister scratch = mscratch.AsArm();
   CHECK(base.IsCoreRegister());
   CHECK(scratch.IsCoreRegister());
   LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
@@ -1703,8 +1739,9 @@
   // TODO: place reference map on call
 }
 
-void Assembler::Call(FrameOffset base, Offset offset,
-                     ManagedRegister scratch) {
+void ArmAssembler::Call(FrameOffset base, Offset offset,
+                        ManagedRegister mscratch) {
+  ArmManagedRegister scratch = mscratch.AsArm();
   CHECK(scratch.IsCoreRegister());
   // Call *(*(SP + base) + offset)
   LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
@@ -1715,8 +1752,8 @@
   // TODO: place reference map on call
 }
 
-void Assembler::Call(uintptr_t addr,
-                     ManagedRegister scratch) {
+void ArmAssembler::Call(uintptr_t addr, ManagedRegister mscratch) {
+  ArmManagedRegister scratch = mscratch.AsArm();
   CHECK(scratch.IsCoreRegister());
   CHECK(sizeof(uintptr_t) == sizeof(int32_t));
   LoadImmediate(scratch.AsCoreRegister(), static_cast<int32_t>(addr));
@@ -1724,20 +1761,23 @@
   // TODO: place reference map on call
 }
 
-void Assembler::GetCurrentThread(ManagedRegister tr) {
-  mov(tr.AsCoreRegister(), ShifterOperand(TR));
+void ArmAssembler::GetCurrentThread(ManagedRegister tr) {
+  mov(tr.AsArm().AsCoreRegister(), ShifterOperand(TR));
 }
 
-void Assembler::GetCurrentThread(FrameOffset offset, ManagedRegister scratch) {
+void ArmAssembler::GetCurrentThread(FrameOffset offset,
+                                    ManagedRegister scratch) {
   StoreToOffset(kStoreWord, TR, SP, offset.Int32Value(), AL);
 }
 
-void Assembler::SuspendPoll(ManagedRegister scratch, ManagedRegister return_reg,
-                            FrameOffset return_save_location,
-                            size_t return_size) {
-  SuspendCountSlowPath* slow = new SuspendCountSlowPath(return_reg,
-                                                        return_save_location,
-                                                        return_size);
+void ArmAssembler::SuspendPoll(ManagedRegister mscratch,
+                               ManagedRegister return_reg,
+                               FrameOffset return_save_location,
+                               size_t return_size) {
+  ArmManagedRegister scratch = mscratch.AsArm();
+  ArmSuspendCountSlowPath* slow =
+      new ArmSuspendCountSlowPath(return_reg.AsArm(), return_save_location,
+                                  return_size);
   buffer_.EnqueueSlowPath(slow);
   LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
                  TR, Thread::SuspendCountOffset().Int32Value());
@@ -1746,23 +1786,27 @@
   Bind(slow->Continuation());
 }
 
-void SuspendCountSlowPath::Emit(Assembler* sp_asm) {
-  sp_asm->Bind(&entry_);
+void ArmSuspendCountSlowPath::Emit(Assembler* sasm) {
+  ArmAssembler* sp_asm = down_cast<ArmAssembler*>(sasm);
+#define __ sp_asm->
+  __ Bind(&entry_);
   // Save return value
-  sp_asm->Store(return_save_location_, return_register_, return_size_);
+  __ Store(return_save_location_, return_register_, return_size_);
   // Pass top of stack as argument
-  sp_asm->mov(R0, ShifterOperand(SP));
-  sp_asm->LoadFromOffset(kLoadWord, R12, TR,
+  __ mov(R0, ShifterOperand(SP));
+  __ LoadFromOffset(kLoadWord, R12, TR,
                          Thread::SuspendCountEntryPointOffset().Int32Value());
   // Note: assume that link register will be spilled/filled on method entry/exit
-  sp_asm->blx(R12);
+  __ blx(R12);
   // Reload return value
-  sp_asm->Load(return_register_, return_save_location_, return_size_);
-  sp_asm->b(&continuation_);
+  __ Load(return_register_, return_save_location_, return_size_);
+  __ b(&continuation_);
+#undef __
 }
 
-void Assembler::ExceptionPoll(ManagedRegister scratch) {
-  ExceptionSlowPath* slow = new ExceptionSlowPath();
+void ArmAssembler::ExceptionPoll(ManagedRegister mscratch) {
+  ArmManagedRegister scratch = mscratch.AsArm();
+  ArmExceptionSlowPath* slow = new ArmExceptionSlowPath();
   buffer_.EnqueueSlowPath(slow);
   LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
                  TR, Thread::ExceptionOffset().Int32Value());
@@ -1771,17 +1815,21 @@
   Bind(slow->Continuation());
 }
 
-void ExceptionSlowPath::Emit(Assembler* sp_asm) {
-  sp_asm->Bind(&entry_);
+void ArmExceptionSlowPath::Emit(Assembler* sasm) {
+  ArmAssembler* sp_asm = down_cast<ArmAssembler*>(sasm);
+#define __ sp_asm->
+  __ Bind(&entry_);
   // Pass top of stack as argument
-  sp_asm->mov(R0, ShifterOperand(SP));
-  sp_asm->LoadFromOffset(kLoadWord, R12, TR,
+  __ mov(R0, ShifterOperand(SP));
+  __ LoadFromOffset(kLoadWord, R12, TR,
                          Thread::ExceptionEntryPointOffset().Int32Value());
   // Note: assume that link register will be spilled/filled on method entry/exit
-  sp_asm->blx(R12);
+  __ blx(R12);
   // TODO: this call should never return as it should make a long jump to
   // the appropriate catch block
-  sp_asm->b(&continuation_);
+  __ b(&continuation_);
+#undef __
 }
 
+}  // namespace arm
 }  // namespace art
diff --git a/src/assembler_arm.h b/src/assembler_arm.h
index 0eafb5f..d4bf93d 100644
--- a/src/assembler_arm.h
+++ b/src/assembler_arm.h
@@ -3,14 +3,16 @@
 #ifndef ART_SRC_ASSEMBLER_ARM_H_
 #define ART_SRC_ASSEMBLER_ARM_H_
 
+#include "assembler.h"
 #include "constants.h"
-#include "managed_register.h"
+#include "managed_register_arm.h"
 #include "logging.h"
 #include "offsets.h"
 #include "utils.h"
 #include <vector>
 
 namespace art {
+namespace arm {
 
 // Encodes Addressing Mode 1 - Data-processing operands defined in Section 5.1.
 class ShifterOperand {
@@ -92,7 +94,7 @@
   uint32_t type_;  // Encodes the type field (bits 27-25) in the instruction.
   uint32_t encoding_;
 
-  friend class Assembler;
+  friend class ArmAssembler;
 #ifdef SOURCE_ASSEMBLER_SUPPORT
   friend class BinaryAssembler;
 #endif
@@ -189,17 +191,14 @@
 
   uint32_t encoding_;
 
-  friend class Assembler;
+  friend class ArmAssembler;
 };
 
 
-class Assembler {
+class ArmAssembler : public Assembler {
  public:
-  Assembler() : buffer_() {}
-
-  InstructionSet GetInstructionSet() const {
-    return kArm;
-  }
+  ArmAssembler() {}
+  virtual ~ArmAssembler() {}
 
   // Data-processing instructions.
   void and_(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
@@ -413,98 +412,124 @@
   static uint32_t DecodeUint32FromTstInstructions(uword pc);
   static bool IsInstructionForExceptionHandling(uword pc);
 
-  // Emit code that will create an activation on the stack
-  void BuildFrame(size_t frame_size, ManagedRegister method_reg,
-                  const std::vector<ManagedRegister>& spill_regs);
-
-  // Emit code that will remove an activation from the stack
-  void RemoveFrame(size_t frame_size,
-                   const std::vector<ManagedRegister>& spill_regs);
-
-  // Fill registers from spill area, excluding R0 (Method*) and LR
-  void FillFromSpillArea(const std::vector<ManagedRegister>& spill_regs,
-                         size_t displacement);
-
-  void IncreaseFrameSize(size_t adjust);
-  void DecreaseFrameSize(size_t adjust);
-
-  // Store bytes from the given register onto the stack
-  void Store(FrameOffset dest, ManagedRegister src, size_t size);
-  void StoreRef(FrameOffset dest, ManagedRegister src);
-  void StoreRawPtr(FrameOffset dest, ManagedRegister src);
-  void StoreSpanning(FrameOffset dest, ManagedRegister src, FrameOffset in_off,
-                     ManagedRegister scratch);
-
-  void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister scratch);
-  void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs);
-  void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs);
-
-  void StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
-                             ManagedRegister scratch);
-  void StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
-                              ManagedRegister scratch);
-
-  void Load(ManagedRegister dest, FrameOffset src, size_t size);
-
-  void LoadRawPtrFromThread(ManagedRegister dest, ThreadOffset offs);
-  void CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs,
-                            ManagedRegister scratch);
-  void CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
-                          ManagedRegister scratch);
-
-  void StoreStackOffsetToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
-                                ManagedRegister scratch);
-  void StoreStackPointerToThread(ThreadOffset thr_offs);
-
-  void Move(ManagedRegister dest, ManagedRegister src);
-  void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch,
-            size_t size);
-  void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset,
-                       ManagedRegister in_reg, bool null_allowed);
-
-  void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset,
-                       ManagedRegister scratch, bool null_allowed);
-
-  void LoadReferenceFromSirt(ManagedRegister dst, ManagedRegister src);
-
-  void VerifyObject(ManagedRegister src, bool could_be_null);
-
-  void VerifyObject(FrameOffset src, bool could_be_null);
-
-  void Call(ManagedRegister base, Offset offset, ManagedRegister scratch);
-  void Call(FrameOffset base, Offset offset, ManagedRegister scratch);
-  void Call(uintptr_t addr, ManagedRegister scratch);
-
-  void GetCurrentThread(ManagedRegister tr);
-  void GetCurrentThread(FrameOffset offset, ManagedRegister scratch);
-
-  // Generate code to check if Thread::Current()->suspend_count_ is non-zero
-  // and branch to a SuspendSlowPath if it is. The SuspendSlowPath will continue
-  // at the next instruction.
-  void SuspendPoll(ManagedRegister scratch, ManagedRegister return_reg,
-                   FrameOffset return_save_location, size_t return_size);
-
-  // Generate code to check if Thread::Current()->exception_ is non-null
-  // and branch to a ExceptionSlowPath if it is.
-  void ExceptionPoll(ManagedRegister scratch);
-
   // Emit data (e.g. encoded instruction or immediate) to the
   // instruction stream.
   void Emit(int32_t value);
 
   void Bind(Label* label);
 
-  void EmitSlowPaths() { buffer_.EmitSlowPaths(this); }
+  //
+  // Overridden common assembler high-level functionality
+  //
 
-  size_t CodeSize() const { return buffer_.Size(); }
+  // Emit code that will create an activation on the stack
+  virtual void BuildFrame(size_t frame_size, ManagedRegister method_reg,
+                          const std::vector<ManagedRegister>& spill_regs);
 
-  void FinalizeInstructions(const MemoryRegion& region) {
-    buffer_.FinalizeInstructions(region);
-  }
+  // Emit code that will remove an activation from the stack
+  virtual void RemoveFrame(size_t frame_size,
+                           const std::vector<ManagedRegister>& spill_regs);
+
+  // Fill list of registers from spill area
+  virtual void FillFromSpillArea(const std::vector<ManagedRegister>& spill_regs,
+                                 size_t displacement);
+
+  virtual void IncreaseFrameSize(size_t adjust);
+  virtual void DecreaseFrameSize(size_t adjust);
+
+  // Store routines
+  virtual void Store(FrameOffset offs, ManagedRegister src, size_t size);
+  virtual void StoreRef(FrameOffset dest, ManagedRegister src);
+  virtual void StoreRawPtr(FrameOffset dest, ManagedRegister src);
+  virtual void StoreSpanning(FrameOffset dest, ManagedRegister src,
+                             FrameOffset in_off, ManagedRegister scratch);
+
+  virtual void StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
+                                     ManagedRegister scratch);
+
+  virtual void StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
+                                      ManagedRegister scratch);
+
+  virtual void StoreStackOffsetToThread(ThreadOffset thr_offs,
+                                        FrameOffset fr_offs,
+                                        ManagedRegister scratch);
+
+  virtual void StoreStackPointerToThread(ThreadOffset thr_offs);
+
+  // Load routines
+  virtual void Load(ManagedRegister dest, FrameOffset src, size_t size);
+
+  virtual void LoadRef(ManagedRegister dest, FrameOffset  src);
+
+  virtual void LoadRef(ManagedRegister dest, ManagedRegister base,
+                       MemberOffset offs);
+
+  virtual void LoadRawPtr(ManagedRegister dest, ManagedRegister base,
+                          Offset offs);
+
+  virtual void LoadRawPtrFromThread(ManagedRegister dest,
+                                    ThreadOffset offs);
+
+  // Copying routines
+  virtual void Move(ManagedRegister dest, ManagedRegister src);
+
+  virtual void CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs,
+                                    ManagedRegister scratch);
+
+  virtual void CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
+                                  ManagedRegister scratch);
+
+  virtual void CopyRef(FrameOffset dest, FrameOffset src,
+                       ManagedRegister scratch);
+
+  virtual void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch,
+                    unsigned int size);
+
+  // Exploit fast access in managed code to Thread::Current()
+  virtual void GetCurrentThread(ManagedRegister tr);
+  virtual void GetCurrentThread(FrameOffset dest_offset,
+                                ManagedRegister scratch);
+
+  // Set up out_reg to hold a Object** into the SIRT, or to be NULL if the
+  // value is null and null_allowed. in_reg holds a possibly stale reference
+  // that can be used to avoid loading the SIRT entry to see if the value is
+  // NULL.
+  virtual void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset,
+                               ManagedRegister in_reg, bool null_allowed);
+
+  // Set up out_off to hold a Object** into the SIRT, or to be NULL if the
+  // value is null and null_allowed.
+  virtual void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset,
+                               ManagedRegister scratch, bool null_allowed);
+
+  // src holds a SIRT entry (Object**) load this into dst
+  virtual void LoadReferenceFromSirt(ManagedRegister dst,
+                                     ManagedRegister src);
+
+  // Heap::VerifyObject on src. In some cases (such as a reference to this) we
+  // know that src may not be null.
+  virtual void VerifyObject(ManagedRegister src, bool could_be_null);
+  virtual void VerifyObject(FrameOffset src, bool could_be_null);
+
+  // Call to address held at [base+offset]
+  virtual void Call(ManagedRegister base, Offset offset,
+                    ManagedRegister scratch);
+  virtual void Call(FrameOffset base, Offset offset,
+                    ManagedRegister scratch);
+  virtual void Call(uintptr_t addr, ManagedRegister scratch);
+
+  // Generate code to check if Thread::Current()->suspend_count_ is non-zero
+  // and branch to a SuspendSlowPath if it is. The SuspendSlowPath will continue
+  // at the next instruction.
+  virtual void SuspendPoll(ManagedRegister scratch, ManagedRegister return_reg,
+                           FrameOffset return_save_location,
+                           size_t return_size);
+
+  // Generate code to check if Thread::Current()->exception_ is non-null
+  // and branch to a ExceptionSlowPath if it is.
+  virtual void ExceptionPoll(ManagedRegister scratch);
 
  private:
-  AssemblerBuffer buffer_;
-
   void EmitType01(Condition cond,
                   int type,
                   Opcode opcode,
@@ -585,6 +610,31 @@
   }
 };
 
+// Slowpath entered when Thread::Current()->_exception is non-null
+class ArmExceptionSlowPath : public SlowPath {
+ public:
+  ArmExceptionSlowPath() {}
+  virtual void Emit(Assembler *sp_asm);
+};
+
+// Slowpath entered when Thread::Current()->_suspend_count is non-zero
+class ArmSuspendCountSlowPath : public SlowPath {
+ public:
+  ArmSuspendCountSlowPath(ArmManagedRegister return_reg,
+                          FrameOffset return_save_location,
+                          size_t return_size) :
+     return_register_(return_reg), return_save_location_(return_save_location),
+     return_size_(return_size) {}
+  virtual void Emit(Assembler *sp_asm);
+
+ private:
+  // Remember how to save the return value
+  const ArmManagedRegister return_register_;
+  const FrameOffset return_save_location_;
+  const size_t return_size_;
+};
+
+}  // namespace arm
 }  // namespace art
 
 #endif  // ART_SRC_ASSEMBLER_ARM_H_
diff --git a/src/assembler_x86.cc b/src/assembler_x86.cc
index 6334bd9..c303fb1 100644
--- a/src/assembler_x86.cc
+++ b/src/assembler_x86.cc
@@ -1,13 +1,13 @@
 // Copyright 2011 Google Inc. All Rights Reserved.
 
-#include "assembler.h"
+#include "assembler_x86.h"
+
 #include "casts.h"
-#include "globals.h"
 #include "memory_region.h"
-#include "offsets.h"
 #include "thread.h"
 
 namespace art {
+namespace x86 {
 
 class DirectCallRelocation : public AssemblerFixup {
  public:
@@ -40,25 +40,25 @@
   return os << "ST" << static_cast<int>(reg);
 }
 
-void Assembler::InitializeMemoryWithBreakpoints(byte* data, size_t length) {
+void X86Assembler::InitializeMemoryWithBreakpoints(byte* data, size_t length) {
   memset(reinterpret_cast<void*>(data), Instr::kBreakPointInstruction, length);
 }
 
-void Assembler::call(Register reg) {
+void X86Assembler::call(Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xFF);
   EmitRegisterOperand(2, reg);
 }
 
 
-void Assembler::call(const Address& address) {
+void X86Assembler::call(const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xFF);
   EmitOperand(2, address);
 }
 
 
-void Assembler::call(Label* label) {
+void X86Assembler::call(Label* label) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xE8);
   static const int kSize = 5;
@@ -66,68 +66,68 @@
 }
 
 
-void Assembler::pushl(Register reg) {
+void X86Assembler::pushl(Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x50 + reg);
 }
 
 
-void Assembler::pushl(const Address& address) {
+void X86Assembler::pushl(const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xFF);
   EmitOperand(6, address);
 }
 
 
-void Assembler::pushl(const Immediate& imm) {
+void X86Assembler::pushl(const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x68);
   EmitImmediate(imm);
 }
 
 
-void Assembler::popl(Register reg) {
+void X86Assembler::popl(Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x58 + reg);
 }
 
 
-void Assembler::popl(const Address& address) {
+void X86Assembler::popl(const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x8F);
   EmitOperand(0, address);
 }
 
 
-void Assembler::movl(Register dst, const Immediate& imm) {
+void X86Assembler::movl(Register dst, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xB8 + dst);
   EmitImmediate(imm);
 }
 
 
-void Assembler::movl(Register dst, Register src) {
+void X86Assembler::movl(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x89);
   EmitRegisterOperand(src, dst);
 }
 
 
-void Assembler::movl(Register dst, const Address& src) {
+void X86Assembler::movl(Register dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x8B);
   EmitOperand(dst, src);
 }
 
 
-void Assembler::movl(const Address& dst, Register src) {
+void X86Assembler::movl(const Address& dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x89);
   EmitOperand(src, dst);
 }
 
 
-void Assembler::movl(const Address& dst, const Immediate& imm) {
+void X86Assembler::movl(const Address& dst, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xC7);
   EmitOperand(0, dst);
@@ -135,7 +135,7 @@
 }
 
 
-void Assembler::movzxb(Register dst, ByteRegister src) {
+void X86Assembler::movzxb(Register dst, ByteRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0xB6);
@@ -143,7 +143,7 @@
 }
 
 
-void Assembler::movzxb(Register dst, const Address& src) {
+void X86Assembler::movzxb(Register dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0xB6);
@@ -151,7 +151,7 @@
 }
 
 
-void Assembler::movsxb(Register dst, ByteRegister src) {
+void X86Assembler::movsxb(Register dst, ByteRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0xBE);
@@ -159,7 +159,7 @@
 }
 
 
-void Assembler::movsxb(Register dst, const Address& src) {
+void X86Assembler::movsxb(Register dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0xBE);
@@ -167,19 +167,19 @@
 }
 
 
-void Assembler::movb(Register dst, const Address& src) {
+void X86Assembler::movb(Register dst, const Address& src) {
   LOG(FATAL) << "Use movzxb or movsxb instead.";
 }
 
 
-void Assembler::movb(const Address& dst, ByteRegister src) {
+void X86Assembler::movb(const Address& dst, ByteRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x88);
   EmitOperand(src, dst);
 }
 
 
-void Assembler::movb(const Address& dst, const Immediate& imm) {
+void X86Assembler::movb(const Address& dst, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xC6);
   EmitOperand(EAX, dst);
@@ -188,7 +188,7 @@
 }
 
 
-void Assembler::movzxw(Register dst, Register src) {
+void X86Assembler::movzxw(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0xB7);
@@ -196,7 +196,7 @@
 }
 
 
-void Assembler::movzxw(Register dst, const Address& src) {
+void X86Assembler::movzxw(Register dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0xB7);
@@ -204,7 +204,7 @@
 }
 
 
-void Assembler::movsxw(Register dst, Register src) {
+void X86Assembler::movsxw(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0xBF);
@@ -212,7 +212,7 @@
 }
 
 
-void Assembler::movsxw(Register dst, const Address& src) {
+void X86Assembler::movsxw(Register dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0xBF);
@@ -220,12 +220,12 @@
 }
 
 
-void Assembler::movw(Register dst, const Address& src) {
+void X86Assembler::movw(Register dst, const Address& src) {
   LOG(FATAL) << "Use movzxw or movsxw instead.";
 }
 
 
-void Assembler::movw(const Address& dst, Register src) {
+void X86Assembler::movw(const Address& dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitOperandSizeOverride();
   EmitUint8(0x89);
@@ -233,14 +233,14 @@
 }
 
 
-void Assembler::leal(Register dst, const Address& src) {
+void X86Assembler::leal(Register dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x8D);
   EmitOperand(dst, src);
 }
 
 
-void Assembler::cmovl(Condition condition, Register dst, Register src) {
+void X86Assembler::cmovl(Condition condition, Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0x40 + condition);
@@ -248,7 +248,7 @@
 }
 
 
-void Assembler::setb(Condition condition, Register dst) {
+void X86Assembler::setb(Condition condition, Register dst) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0x90 + condition);
@@ -256,7 +256,7 @@
 }
 
 
-void Assembler::movss(XmmRegister dst, const Address& src) {
+void X86Assembler::movss(XmmRegister dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
@@ -265,7 +265,7 @@
 }
 
 
-void Assembler::movss(const Address& dst, XmmRegister src) {
+void X86Assembler::movss(const Address& dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
@@ -274,7 +274,7 @@
 }
 
 
-void Assembler::movss(XmmRegister dst, XmmRegister src) {
+void X86Assembler::movss(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
@@ -283,7 +283,7 @@
 }
 
 
-void Assembler::movd(XmmRegister dst, Register src) {
+void X86Assembler::movd(XmmRegister dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x66);
   EmitUint8(0x0F);
@@ -292,7 +292,7 @@
 }
 
 
-void Assembler::movd(Register dst, XmmRegister src) {
+void X86Assembler::movd(Register dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x66);
   EmitUint8(0x0F);
@@ -301,7 +301,7 @@
 }
 
 
-void Assembler::addss(XmmRegister dst, XmmRegister src) {
+void X86Assembler::addss(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
@@ -310,7 +310,7 @@
 }
 
 
-void Assembler::addss(XmmRegister dst, const Address& src) {
+void X86Assembler::addss(XmmRegister dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
@@ -319,7 +319,7 @@
 }
 
 
-void Assembler::subss(XmmRegister dst, XmmRegister src) {
+void X86Assembler::subss(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
@@ -328,7 +328,7 @@
 }
 
 
-void Assembler::subss(XmmRegister dst, const Address& src) {
+void X86Assembler::subss(XmmRegister dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
@@ -337,7 +337,7 @@
 }
 
 
-void Assembler::mulss(XmmRegister dst, XmmRegister src) {
+void X86Assembler::mulss(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
@@ -346,7 +346,7 @@
 }
 
 
-void Assembler::mulss(XmmRegister dst, const Address& src) {
+void X86Assembler::mulss(XmmRegister dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
@@ -355,7 +355,7 @@
 }
 
 
-void Assembler::divss(XmmRegister dst, XmmRegister src) {
+void X86Assembler::divss(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
@@ -364,7 +364,7 @@
 }
 
 
-void Assembler::divss(XmmRegister dst, const Address& src) {
+void X86Assembler::divss(XmmRegister dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
@@ -373,21 +373,21 @@
 }
 
 
-void Assembler::flds(const Address& src) {
+void X86Assembler::flds(const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xD9);
   EmitOperand(0, src);
 }
 
 
-void Assembler::fstps(const Address& dst) {
+void X86Assembler::fstps(const Address& dst) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xD9);
   EmitOperand(3, dst);
 }
 
 
-void Assembler::movsd(XmmRegister dst, const Address& src) {
+void X86Assembler::movsd(XmmRegister dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF2);
   EmitUint8(0x0F);
@@ -396,7 +396,7 @@
 }
 
 
-void Assembler::movsd(const Address& dst, XmmRegister src) {
+void X86Assembler::movsd(const Address& dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF2);
   EmitUint8(0x0F);
@@ -405,7 +405,7 @@
 }
 
 
-void Assembler::movsd(XmmRegister dst, XmmRegister src) {
+void X86Assembler::movsd(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF2);
   EmitUint8(0x0F);
@@ -414,7 +414,7 @@
 }
 
 
-void Assembler::addsd(XmmRegister dst, XmmRegister src) {
+void X86Assembler::addsd(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF2);
   EmitUint8(0x0F);
@@ -423,7 +423,7 @@
 }
 
 
-void Assembler::addsd(XmmRegister dst, const Address& src) {
+void X86Assembler::addsd(XmmRegister dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF2);
   EmitUint8(0x0F);
@@ -432,7 +432,7 @@
 }
 
 
-void Assembler::subsd(XmmRegister dst, XmmRegister src) {
+void X86Assembler::subsd(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF2);
   EmitUint8(0x0F);
@@ -441,7 +441,7 @@
 }
 
 
-void Assembler::subsd(XmmRegister dst, const Address& src) {
+void X86Assembler::subsd(XmmRegister dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF2);
   EmitUint8(0x0F);
@@ -450,7 +450,7 @@
 }
 
 
-void Assembler::mulsd(XmmRegister dst, XmmRegister src) {
+void X86Assembler::mulsd(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF2);
   EmitUint8(0x0F);
@@ -459,7 +459,7 @@
 }
 
 
-void Assembler::mulsd(XmmRegister dst, const Address& src) {
+void X86Assembler::mulsd(XmmRegister dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF2);
   EmitUint8(0x0F);
@@ -468,7 +468,7 @@
 }
 
 
-void Assembler::divsd(XmmRegister dst, XmmRegister src) {
+void X86Assembler::divsd(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF2);
   EmitUint8(0x0F);
@@ -477,7 +477,7 @@
 }
 
 
-void Assembler::divsd(XmmRegister dst, const Address& src) {
+void X86Assembler::divsd(XmmRegister dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF2);
   EmitUint8(0x0F);
@@ -486,7 +486,7 @@
 }
 
 
-void Assembler::cvtsi2ss(XmmRegister dst, Register src) {
+void X86Assembler::cvtsi2ss(XmmRegister dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
@@ -495,7 +495,7 @@
 }
 
 
-void Assembler::cvtsi2sd(XmmRegister dst, Register src) {
+void X86Assembler::cvtsi2sd(XmmRegister dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF2);
   EmitUint8(0x0F);
@@ -504,7 +504,7 @@
 }
 
 
-void Assembler::cvtss2si(Register dst, XmmRegister src) {
+void X86Assembler::cvtss2si(Register dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
@@ -513,7 +513,7 @@
 }
 
 
-void Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
+void X86Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
@@ -522,7 +522,7 @@
 }
 
 
-void Assembler::cvtsd2si(Register dst, XmmRegister src) {
+void X86Assembler::cvtsd2si(Register dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF2);
   EmitUint8(0x0F);
@@ -531,7 +531,7 @@
 }
 
 
-void Assembler::cvttss2si(Register dst, XmmRegister src) {
+void X86Assembler::cvttss2si(Register dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
@@ -540,7 +540,7 @@
 }
 
 
-void Assembler::cvttsd2si(Register dst, XmmRegister src) {
+void X86Assembler::cvttsd2si(Register dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF2);
   EmitUint8(0x0F);
@@ -549,7 +549,7 @@
 }
 
 
-void Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
+void X86Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF2);
   EmitUint8(0x0F);
@@ -558,7 +558,7 @@
 }
 
 
-void Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
+void X86Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
@@ -567,7 +567,7 @@
 }
 
 
-void Assembler::comiss(XmmRegister a, XmmRegister b) {
+void X86Assembler::comiss(XmmRegister a, XmmRegister b) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0x2F);
@@ -575,7 +575,7 @@
 }
 
 
-void Assembler::comisd(XmmRegister a, XmmRegister b) {
+void X86Assembler::comisd(XmmRegister a, XmmRegister b) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x66);
   EmitUint8(0x0F);
@@ -584,7 +584,7 @@
 }
 
 
-void Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
+void X86Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF2);
   EmitUint8(0x0F);
@@ -593,7 +593,7 @@
 }
 
 
-void Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
+void X86Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF3);
   EmitUint8(0x0F);
@@ -602,7 +602,7 @@
 }
 
 
-void Assembler::xorpd(XmmRegister dst, const Address& src) {
+void X86Assembler::xorpd(XmmRegister dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x66);
   EmitUint8(0x0F);
@@ -611,7 +611,7 @@
 }
 
 
-void Assembler::xorpd(XmmRegister dst, XmmRegister src) {
+void X86Assembler::xorpd(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x66);
   EmitUint8(0x0F);
@@ -620,7 +620,7 @@
 }
 
 
-void Assembler::xorps(XmmRegister dst, const Address& src) {
+void X86Assembler::xorps(XmmRegister dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0x57);
@@ -628,7 +628,7 @@
 }
 
 
-void Assembler::xorps(XmmRegister dst, XmmRegister src) {
+void X86Assembler::xorps(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0x57);
@@ -636,7 +636,7 @@
 }
 
 
-void Assembler::andpd(XmmRegister dst, const Address& src) {
+void X86Assembler::andpd(XmmRegister dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x66);
   EmitUint8(0x0F);
@@ -645,63 +645,63 @@
 }
 
 
-void Assembler::fldl(const Address& src) {
+void X86Assembler::fldl(const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xDD);
   EmitOperand(0, src);
 }
 
 
-void Assembler::fstpl(const Address& dst) {
+void X86Assembler::fstpl(const Address& dst) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xDD);
   EmitOperand(3, dst);
 }
 
 
-void Assembler::fnstcw(const Address& dst) {
+void X86Assembler::fnstcw(const Address& dst) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xD9);
   EmitOperand(7, dst);
 }
 
 
-void Assembler::fldcw(const Address& src) {
+void X86Assembler::fldcw(const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xD9);
   EmitOperand(5, src);
 }
 
 
-void Assembler::fistpl(const Address& dst) {
+void X86Assembler::fistpl(const Address& dst) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xDF);
   EmitOperand(7, dst);
 }
 
 
-void Assembler::fistps(const Address& dst) {
+void X86Assembler::fistps(const Address& dst) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xDB);
   EmitOperand(3, dst);
 }
 
 
-void Assembler::fildl(const Address& src) {
+void X86Assembler::fildl(const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xDF);
   EmitOperand(5, src);
 }
 
 
-void Assembler::fincstp() {
+void X86Assembler::fincstp() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xD9);
   EmitUint8(0xF7);
 }
 
 
-void Assembler::ffree(const Immediate& index) {
+void X86Assembler::ffree(const Immediate& index) {
   CHECK_LT(index.value(), 7);
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xDD);
@@ -709,89 +709,89 @@
 }
 
 
-void Assembler::fsin() {
+void X86Assembler::fsin() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xD9);
   EmitUint8(0xFE);
 }
 
 
-void Assembler::fcos() {
+void X86Assembler::fcos() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xD9);
   EmitUint8(0xFF);
 }
 
 
-void Assembler::fptan() {
+void X86Assembler::fptan() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xD9);
   EmitUint8(0xF2);
 }
 
 
-void Assembler::xchgl(Register dst, Register src) {
+void X86Assembler::xchgl(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x87);
   EmitRegisterOperand(dst, src);
 }
 
 
-void Assembler::cmpl(Register reg, const Immediate& imm) {
+void X86Assembler::cmpl(Register reg, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitComplex(7, Operand(reg), imm);
 }
 
 
-void Assembler::cmpl(Register reg0, Register reg1) {
+void X86Assembler::cmpl(Register reg0, Register reg1) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x3B);
   EmitOperand(reg0, Operand(reg1));
 }
 
 
-void Assembler::cmpl(Register reg, const Address& address) {
+void X86Assembler::cmpl(Register reg, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x3B);
   EmitOperand(reg, address);
 }
 
 
-void Assembler::addl(Register dst, Register src) {
+void X86Assembler::addl(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x03);
   EmitRegisterOperand(dst, src);
 }
 
 
-void Assembler::addl(Register reg, const Address& address) {
+void X86Assembler::addl(Register reg, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x03);
   EmitOperand(reg, address);
 }
 
 
-void Assembler::cmpl(const Address& address, Register reg) {
+void X86Assembler::cmpl(const Address& address, Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x39);
   EmitOperand(reg, address);
 }
 
 
-void Assembler::cmpl(const Address& address, const Immediate& imm) {
+void X86Assembler::cmpl(const Address& address, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitComplex(7, address, imm);
 }
 
 
-void Assembler::testl(Register reg1, Register reg2) {
+void X86Assembler::testl(Register reg1, Register reg2) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x85);
   EmitRegisterOperand(reg1, reg2);
 }
 
 
-void Assembler::testl(Register reg, const Immediate& immediate) {
+void X86Assembler::testl(Register reg, const Immediate& immediate) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   // For registers that have a byte variant (EAX, EBX, ECX, and EDX)
   // we only test the byte register to keep the encoding short.
@@ -816,112 +816,112 @@
 }
 
 
-void Assembler::andl(Register dst, Register src) {
+void X86Assembler::andl(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x23);
   EmitOperand(dst, Operand(src));
 }
 
 
-void Assembler::andl(Register dst, const Immediate& imm) {
+void X86Assembler::andl(Register dst, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitComplex(4, Operand(dst), imm);
 }
 
 
-void Assembler::orl(Register dst, Register src) {
+void X86Assembler::orl(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0B);
   EmitOperand(dst, Operand(src));
 }
 
 
-void Assembler::orl(Register dst, const Immediate& imm) {
+void X86Assembler::orl(Register dst, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitComplex(1, Operand(dst), imm);
 }
 
 
-void Assembler::xorl(Register dst, Register src) {
+void X86Assembler::xorl(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x33);
   EmitOperand(dst, Operand(src));
 }
 
 
-void Assembler::addl(Register reg, const Immediate& imm) {
+void X86Assembler::addl(Register reg, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitComplex(0, Operand(reg), imm);
 }
 
 
-void Assembler::addl(const Address& address, Register reg) {
+void X86Assembler::addl(const Address& address, Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x01);
   EmitOperand(reg, address);
 }
 
 
-void Assembler::addl(const Address& address, const Immediate& imm) {
+void X86Assembler::addl(const Address& address, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitComplex(0, address, imm);
 }
 
 
-void Assembler::adcl(Register reg, const Immediate& imm) {
+void X86Assembler::adcl(Register reg, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitComplex(2, Operand(reg), imm);
 }
 
 
-void Assembler::adcl(Register dst, Register src) {
+void X86Assembler::adcl(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x13);
   EmitOperand(dst, Operand(src));
 }
 
 
-void Assembler::adcl(Register dst, const Address& address) {
+void X86Assembler::adcl(Register dst, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x13);
   EmitOperand(dst, address);
 }
 
 
-void Assembler::subl(Register dst, Register src) {
+void X86Assembler::subl(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x2B);
   EmitOperand(dst, Operand(src));
 }
 
 
-void Assembler::subl(Register reg, const Immediate& imm) {
+void X86Assembler::subl(Register reg, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitComplex(5, Operand(reg), imm);
 }
 
 
-void Assembler::subl(Register reg, const Address& address) {
+void X86Assembler::subl(Register reg, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x2B);
   EmitOperand(reg, address);
 }
 
 
-void Assembler::cdq() {
+void X86Assembler::cdq() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x99);
 }
 
 
-void Assembler::idivl(Register reg) {
+void X86Assembler::idivl(Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF7);
   EmitUint8(0xF8 | reg);
 }
 
 
-void Assembler::imull(Register dst, Register src) {
+void X86Assembler::imull(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0xAF);
@@ -929,7 +929,7 @@
 }
 
 
-void Assembler::imull(Register reg, const Immediate& imm) {
+void X86Assembler::imull(Register reg, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x69);
   EmitOperand(reg, Operand(reg));
@@ -937,7 +937,7 @@
 }
 
 
-void Assembler::imull(Register reg, const Address& address) {
+void X86Assembler::imull(Register reg, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0xAF);
@@ -945,111 +945,111 @@
 }
 
 
-void Assembler::imull(Register reg) {
+void X86Assembler::imull(Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF7);
   EmitOperand(5, Operand(reg));
 }
 
 
-void Assembler::imull(const Address& address) {
+void X86Assembler::imull(const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF7);
   EmitOperand(5, address);
 }
 
 
-void Assembler::mull(Register reg) {
+void X86Assembler::mull(Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF7);
   EmitOperand(4, Operand(reg));
 }
 
 
-void Assembler::mull(const Address& address) {
+void X86Assembler::mull(const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF7);
   EmitOperand(4, address);
 }
 
 
-void Assembler::sbbl(Register dst, Register src) {
+void X86Assembler::sbbl(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x1B);
   EmitOperand(dst, Operand(src));
 }
 
 
-void Assembler::sbbl(Register reg, const Immediate& imm) {
+void X86Assembler::sbbl(Register reg, const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitComplex(3, Operand(reg), imm);
 }
 
 
-void Assembler::sbbl(Register dst, const Address& address) {
+void X86Assembler::sbbl(Register dst, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x1B);
   EmitOperand(dst, address);
 }
 
 
-void Assembler::incl(Register reg) {
+void X86Assembler::incl(Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x40 + reg);
 }
 
 
-void Assembler::incl(const Address& address) {
+void X86Assembler::incl(const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xFF);
   EmitOperand(0, address);
 }
 
 
-void Assembler::decl(Register reg) {
+void X86Assembler::decl(Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x48 + reg);
 }
 
 
-void Assembler::decl(const Address& address) {
+void X86Assembler::decl(const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xFF);
   EmitOperand(1, address);
 }
 
 
-void Assembler::shll(Register reg, const Immediate& imm) {
+void X86Assembler::shll(Register reg, const Immediate& imm) {
   EmitGenericShift(4, reg, imm);
 }
 
 
-void Assembler::shll(Register operand, Register shifter) {
+void X86Assembler::shll(Register operand, Register shifter) {
   EmitGenericShift(4, operand, shifter);
 }
 
 
-void Assembler::shrl(Register reg, const Immediate& imm) {
+void X86Assembler::shrl(Register reg, const Immediate& imm) {
   EmitGenericShift(5, reg, imm);
 }
 
 
-void Assembler::shrl(Register operand, Register shifter) {
+void X86Assembler::shrl(Register operand, Register shifter) {
   EmitGenericShift(5, operand, shifter);
 }
 
 
-void Assembler::sarl(Register reg, const Immediate& imm) {
+void X86Assembler::sarl(Register reg, const Immediate& imm) {
   EmitGenericShift(7, reg, imm);
 }
 
 
-void Assembler::sarl(Register operand, Register shifter) {
+void X86Assembler::sarl(Register operand, Register shifter) {
   EmitGenericShift(7, operand, shifter);
 }
 
 
-void Assembler::shld(Register dst, Register src) {
+void X86Assembler::shld(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0xA5);
@@ -1057,21 +1057,21 @@
 }
 
 
-void Assembler::negl(Register reg) {
+void X86Assembler::negl(Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF7);
   EmitOperand(3, Operand(reg));
 }
 
 
-void Assembler::notl(Register reg) {
+void X86Assembler::notl(Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF7);
   EmitUint8(0xD0 | reg);
 }
 
 
-void Assembler::enter(const Immediate& imm) {
+void X86Assembler::enter(const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xC8);
   CHECK(imm.is_uint16());
@@ -1081,19 +1081,19 @@
 }
 
 
-void Assembler::leave() {
+void X86Assembler::leave() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xC9);
 }
 
 
-void Assembler::ret() {
+void X86Assembler::ret() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xC3);
 }
 
 
-void Assembler::ret(const Immediate& imm) {
+void X86Assembler::ret(const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xC2);
   CHECK(imm.is_uint16());
@@ -1103,25 +1103,25 @@
 
 
 
-void Assembler::nop() {
+void X86Assembler::nop() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x90);
 }
 
 
-void Assembler::int3() {
+void X86Assembler::int3() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xCC);
 }
 
 
-void Assembler::hlt() {
+void X86Assembler::hlt() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF4);
 }
 
 
-void Assembler::j(Condition condition, Label* label) {
+void X86Assembler::j(Condition condition, Label* label) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (label->IsBound()) {
     static const int kShortSize = 2;
@@ -1144,14 +1144,14 @@
 }
 
 
-void Assembler::jmp(Register reg) {
+void X86Assembler::jmp(Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xFF);
   EmitRegisterOperand(4, reg);
 }
 
 
-void Assembler::jmp(Label* label) {
+void X86Assembler::jmp(Label* label) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   if (label->IsBound()) {
     static const int kShortSize = 2;
@@ -1172,28 +1172,28 @@
 }
 
 
-Assembler* Assembler::lock() {
+X86Assembler* X86Assembler::lock() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF0);
   return this;
 }
 
 
-void Assembler::cmpxchgl(const Address& address, Register reg) {
+void X86Assembler::cmpxchgl(const Address& address, Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
   EmitUint8(0xB1);
   EmitOperand(reg, address);
 }
 
-Assembler* Assembler::fs() {
+X86Assembler* X86Assembler::fs() {
   // TODO: fs is a prefix and not an instruction
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x64);
   return this;
 }
 
-void Assembler::AddImmediate(Register reg, const Immediate& imm) {
+void X86Assembler::AddImmediate(Register reg, const Immediate& imm) {
   int value = imm.value();
   if (value > 0) {
     if (value == 1) {
@@ -1212,7 +1212,7 @@
 }
 
 
-void Assembler::LoadDoubleConstant(XmmRegister dst, double value) {
+void X86Assembler::LoadDoubleConstant(XmmRegister dst, double value) {
   // TODO: Need to have a code constants table.
   int64_t constant = bit_cast<int64_t, double>(value);
   pushl(Immediate(High32Bits(constant)));
@@ -1222,7 +1222,7 @@
 }
 
 
-void Assembler::FloatNegate(XmmRegister f) {
+void X86Assembler::FloatNegate(XmmRegister f) {
   static const struct {
     uint32_t a;
     uint32_t b;
@@ -1234,7 +1234,7 @@
 }
 
 
-void Assembler::DoubleNegate(XmmRegister d) {
+void X86Assembler::DoubleNegate(XmmRegister d) {
   static const struct {
     uint64_t a;
     uint64_t b;
@@ -1244,7 +1244,7 @@
 }
 
 
-void Assembler::DoubleAbs(XmmRegister reg) {
+void X86Assembler::DoubleAbs(XmmRegister reg) {
   static const struct {
     uint64_t a;
     uint64_t b;
@@ -1254,7 +1254,7 @@
 }
 
 
-void Assembler::Align(int alignment, int offset) {
+void X86Assembler::Align(int alignment, int offset) {
   CHECK(IsPowerOfTwo(alignment));
   // Emit nop instruction until the real position is aligned.
   while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) {
@@ -1263,7 +1263,7 @@
 }
 
 
-void Assembler::Bind(Label* label) {
+void X86Assembler::Bind(Label* label) {
   int bound = buffer_.Size();
   CHECK(!label->IsBound());  // Labels can only be bound once.
   while (label->IsLinked()) {
@@ -1276,7 +1276,7 @@
 }
 
 
-void Assembler::Stop(const char* message) {
+void X86Assembler::Stop(const char* message) {
   // Emit the message address as immediate operand in the test rax instruction,
   // followed by the int3 instruction.
   // Execution can be resumed with the 'cont' command in gdb.
@@ -1285,7 +1285,7 @@
 }
 
 
-void Assembler::EmitOperand(int rm, const Operand& operand) {
+void X86Assembler::EmitOperand(int rm, const Operand& operand) {
   CHECK_GE(rm, 0);
   CHECK_LT(rm, 8);
   const int length = operand.length_;
@@ -1300,14 +1300,14 @@
 }
 
 
-void Assembler::EmitImmediate(const Immediate& imm) {
+void X86Assembler::EmitImmediate(const Immediate& imm) {
   EmitInt32(imm.value());
 }
 
 
-void Assembler::EmitComplex(int rm,
-                            const Operand& operand,
-                            const Immediate& immediate) {
+void X86Assembler::EmitComplex(int rm,
+                               const Operand& operand,
+                               const Immediate& immediate) {
   CHECK_GE(rm, 0);
   CHECK_LT(rm, 8);
   if (immediate.is_int8()) {
@@ -1327,7 +1327,7 @@
 }
 
 
-void Assembler::EmitLabel(Label* label, int instruction_size) {
+void X86Assembler::EmitLabel(Label* label, int instruction_size) {
   if (label->IsBound()) {
     int offset = label->Position() - buffer_.Size();
     CHECK_LE(offset, 0);
@@ -1338,7 +1338,7 @@
 }
 
 
-void Assembler::EmitLabelLink(Label* label) {
+void X86Assembler::EmitLabelLink(Label* label) {
   CHECK(!label->IsBound());
   int position = buffer_.Size();
   EmitInt32(label->position_);
@@ -1346,9 +1346,9 @@
 }
 
 
-void Assembler::EmitGenericShift(int rm,
-                                 Register reg,
-                                 const Immediate& imm) {
+void X86Assembler::EmitGenericShift(int rm,
+                                    Register reg,
+                                    const Immediate& imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   CHECK(imm.is_int8());
   if (imm.value() == 1) {
@@ -1362,26 +1362,26 @@
 }
 
 
-void Assembler::EmitGenericShift(int rm,
-                                 Register operand,
-                                 Register shifter) {
+void X86Assembler::EmitGenericShift(int rm,
+                                    Register operand,
+                                    Register shifter) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   CHECK_EQ(shifter, ECX);
   EmitUint8(0xD3);
   EmitOperand(rm, Operand(operand));
 }
 
-void Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg,
-                           const std::vector<ManagedRegister>& spill_regs) {
+void X86Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg,
+                              const std::vector<ManagedRegister>& spill_regs) {
   CHECK(IsAligned(frame_size, kStackAlignment));
   CHECK_EQ(0u, spill_regs.size());  // no spilled regs on x86
   // return address then method on stack
   addl(ESP, Immediate(-frame_size + kPointerSize /*method*/ +
                       kPointerSize /*return address*/));
-  pushl(method_reg.AsCpuRegister());
+  pushl(method_reg.AsX86().AsCpuRegister());
 }
 
-void Assembler::RemoveFrame(size_t frame_size,
+void X86Assembler::RemoveFrame(size_t frame_size,
                             const std::vector<ManagedRegister>& spill_regs) {
   CHECK(IsAligned(frame_size, kStackAlignment));
   CHECK_EQ(0u, spill_regs.size());  // no spilled regs on x86
@@ -1389,22 +1389,23 @@
   ret();
 }
 
-void Assembler::FillFromSpillArea(const std::vector<ManagedRegister>& spill_regs,
-                                  size_t displacement) {
+void X86Assembler::FillFromSpillArea(
+    const std::vector<ManagedRegister>& spill_regs, size_t displacement) {
   CHECK_EQ(0u, spill_regs.size());  // no spilled regs on x86
 }
 
-void Assembler::IncreaseFrameSize(size_t adjust) {
+void X86Assembler::IncreaseFrameSize(size_t adjust) {
   CHECK(IsAligned(adjust, kStackAlignment));
   addl(ESP, Immediate(-adjust));
 }
 
-void Assembler::DecreaseFrameSize(size_t adjust) {
+void X86Assembler::DecreaseFrameSize(size_t adjust) {
   CHECK(IsAligned(adjust, kStackAlignment));
   addl(ESP, Immediate(adjust));
 }
 
-void Assembler::Store(FrameOffset offs, ManagedRegister src, size_t size) {
+void X86Assembler::Store(FrameOffset offs, ManagedRegister msrc, size_t size) {
+  X86ManagedRegister src = msrc.AsX86();
   if (src.IsNoRegister()) {
     CHECK_EQ(0u, size);
   } else if (src.IsCpuRegister()) {
@@ -1431,34 +1432,48 @@
   }
 }
 
-void Assembler::StoreRef(FrameOffset dest, ManagedRegister src) {
+void X86Assembler::StoreRef(FrameOffset dest, ManagedRegister msrc) {
+  X86ManagedRegister src = msrc.AsX86();
   CHECK(src.IsCpuRegister());
   movl(Address(ESP, dest), src.AsCpuRegister());
 }
 
-void Assembler::StoreRawPtr(FrameOffset dest, ManagedRegister src) {
+void X86Assembler::StoreRawPtr(FrameOffset dest, ManagedRegister msrc) {
+  X86ManagedRegister src = msrc.AsX86();
   CHECK(src.IsCpuRegister());
   movl(Address(ESP, dest), src.AsCpuRegister());
 }
 
-void Assembler::CopyRef(FrameOffset dest, FrameOffset src,
-                        ManagedRegister scratch) {
-  CHECK(scratch.IsCpuRegister());
-  movl(scratch.AsCpuRegister(), Address(ESP, src));
-  movl(Address(ESP, dest), scratch.AsCpuRegister());
-}
-
-void Assembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
-                                      ManagedRegister) {
+void X86Assembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
+                                         ManagedRegister) {
   movl(Address(ESP, dest), Immediate(imm));
 }
 
-void Assembler::StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
-                                       ManagedRegister) {
+void X86Assembler::StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
+                                          ManagedRegister) {
   fs()->movl(Address::Absolute(dest), Immediate(imm));
 }
 
-void Assembler::Load(ManagedRegister dest, FrameOffset src, size_t size) {
+void X86Assembler::StoreStackOffsetToThread(ThreadOffset thr_offs,
+                                            FrameOffset fr_offs,
+                                            ManagedRegister mscratch) {
+  X86ManagedRegister scratch = mscratch.AsX86();
+  CHECK(scratch.IsCpuRegister());
+  leal(scratch.AsCpuRegister(), Address(ESP, fr_offs));
+  fs()->movl(Address::Absolute(thr_offs), scratch.AsCpuRegister());
+}
+
+void X86Assembler::StoreStackPointerToThread(ThreadOffset thr_offs) {
+  fs()->movl(Address::Absolute(thr_offs), ESP);
+}
+
+void X86Assembler::StoreSpanning(FrameOffset dest, ManagedRegister src,
+                                 FrameOffset in_off, ManagedRegister scratch) {
+  UNIMPLEMENTED(FATAL);  // this case only currently exists for ARM
+}
+
+void X86Assembler::Load(ManagedRegister mdest, FrameOffset src, size_t size) {
+  X86ManagedRegister dest = mdest.AsX86();
   if (dest.IsNoRegister()) {
     CHECK_EQ(0u, size);
   } else if (dest.IsCpuRegister()) {
@@ -1484,67 +1499,76 @@
   }
 }
 
-void Assembler::LoadRef(ManagedRegister dest, FrameOffset  src) {
+void X86Assembler::LoadRef(ManagedRegister mdest, FrameOffset  src) {
+  X86ManagedRegister dest = mdest.AsX86();
   CHECK(dest.IsCpuRegister());
   movl(dest.AsCpuRegister(), Address(ESP, src));
 }
 
-void Assembler::LoadRef(ManagedRegister dest, ManagedRegister base,
-                        MemberOffset offs) {
+void X86Assembler::LoadRef(ManagedRegister mdest, ManagedRegister base,
+                           MemberOffset offs) {
+  X86ManagedRegister dest = mdest.AsX86();
   CHECK(dest.IsCpuRegister() && dest.IsCpuRegister());
-  movl(dest.AsCpuRegister(), Address(base.AsCpuRegister(), offs));
+  movl(dest.AsCpuRegister(), Address(base.AsX86().AsCpuRegister(), offs));
 }
 
-void Assembler::LoadRawPtr(ManagedRegister dest, ManagedRegister base,
-                           Offset offs) {
+void X86Assembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base,
+                              Offset offs) {
+  X86ManagedRegister dest = mdest.AsX86();
   CHECK(dest.IsCpuRegister() && dest.IsCpuRegister());
-  movl(dest.AsCpuRegister(), Address(base.AsCpuRegister(), offs));
+  movl(dest.AsCpuRegister(), Address(base.AsX86().AsCpuRegister(), offs));
 }
 
-void Assembler::LoadRawPtrFromThread(ManagedRegister dest, ThreadOffset offs) {
+void X86Assembler::LoadRawPtrFromThread(ManagedRegister mdest,
+                                        ThreadOffset offs) {
+  X86ManagedRegister dest = mdest.AsX86();
   CHECK(dest.IsCpuRegister());
   fs()->movl(dest.AsCpuRegister(), Address::Absolute(offs));
 }
 
-void Assembler::CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs,
-                          ManagedRegister scratch) {
-  CHECK(scratch.IsCpuRegister());
-  fs()->movl(scratch.AsCpuRegister(), Address::Absolute(thr_offs));
-  Store(fr_offs, scratch, 4);
-}
-
-void Assembler::CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
-                                   ManagedRegister scratch) {
-  CHECK(scratch.IsCpuRegister());
-  Load(scratch, fr_offs, 4);
-  fs()->movl(Address::Absolute(thr_offs), scratch.AsCpuRegister());
-}
-
-void Assembler::StoreStackOffsetToThread(ThreadOffset thr_offs,
-                                         FrameOffset fr_offs,
-                                         ManagedRegister scratch) {
-  CHECK(scratch.IsCpuRegister());
-  leal(scratch.AsCpuRegister(), Address(ESP, fr_offs));
-  fs()->movl(Address::Absolute(thr_offs), scratch.AsCpuRegister());
-}
-
-void Assembler::StoreStackPointerToThread(ThreadOffset thr_offs) {
-  fs()->movl(Address::Absolute(thr_offs), ESP);
-}
-
-void Assembler::Move(ManagedRegister dest, ManagedRegister src) {
+void X86Assembler::Move(ManagedRegister mdest, ManagedRegister msrc) {
+  X86ManagedRegister dest = mdest.AsX86();
+  X86ManagedRegister src = msrc.AsX86();
   if (!dest.Equals(src)) {
     if (dest.IsCpuRegister() && src.IsCpuRegister()) {
       movl(dest.AsCpuRegister(), src.AsCpuRegister());
     } else {
       // TODO: x87, SSE
-      UNIMPLEMENTED(FATAL) << ": x87, SSE";
+      UNIMPLEMENTED(FATAL) << ": Move " << dest << ", " << src;
     }
   }
 }
 
-void Assembler::Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch,
-                     size_t size) {
+void X86Assembler::CopyRef(FrameOffset dest, FrameOffset src,
+                           ManagedRegister mscratch) {
+  X86ManagedRegister scratch = mscratch.AsX86();
+  CHECK(scratch.IsCpuRegister());
+  movl(scratch.AsCpuRegister(), Address(ESP, src));
+  movl(Address(ESP, dest), scratch.AsCpuRegister());
+}
+
+void X86Assembler::CopyRawPtrFromThread(FrameOffset fr_offs,
+                                        ThreadOffset thr_offs,
+                                        ManagedRegister mscratch) {
+  X86ManagedRegister scratch = mscratch.AsX86();
+  CHECK(scratch.IsCpuRegister());
+  fs()->movl(scratch.AsCpuRegister(), Address::Absolute(thr_offs));
+  Store(fr_offs, scratch, 4);
+}
+
+void X86Assembler::CopyRawPtrToThread(ThreadOffset thr_offs,
+                                      FrameOffset fr_offs,
+                                      ManagedRegister mscratch) {
+  X86ManagedRegister scratch = mscratch.AsX86();
+  CHECK(scratch.IsCpuRegister());
+  Load(scratch, fr_offs, 4);
+  fs()->movl(Address::Absolute(thr_offs), scratch.AsCpuRegister());
+}
+
+void X86Assembler::Copy(FrameOffset dest, FrameOffset src,
+                        ManagedRegister mscratch,
+                        size_t size) {
+  X86ManagedRegister scratch = mscratch.AsX86();
   if (scratch.IsCpuRegister() && size == 8) {
     Load(scratch, src, 4);
     Store(dest, scratch, 4);
@@ -1556,9 +1580,11 @@
   }
 }
 
-void Assembler::CreateSirtEntry(ManagedRegister out_reg,
-                                FrameOffset sirt_offset,
-                                ManagedRegister in_reg, bool null_allowed) {
+void X86Assembler::CreateSirtEntry(ManagedRegister mout_reg,
+                                   FrameOffset sirt_offset,
+                                   ManagedRegister min_reg, bool null_allowed) {
+  X86ManagedRegister out_reg = mout_reg.AsX86();
+  X86ManagedRegister in_reg = min_reg.AsX86();
   CHECK(in_reg.IsCpuRegister());
   CHECK(out_reg.IsCpuRegister());
   VerifyObject(in_reg, null_allowed);
@@ -1576,9 +1602,11 @@
   }
 }
 
-void Assembler::CreateSirtEntry(FrameOffset out_off,
-                                FrameOffset sirt_offset,
-                                ManagedRegister scratch, bool null_allowed) {
+void X86Assembler::CreateSirtEntry(FrameOffset out_off,
+                                   FrameOffset sirt_offset,
+                                   ManagedRegister mscratch,
+                                   bool null_allowed) {
+  X86ManagedRegister scratch = mscratch.AsX86();
   CHECK(scratch.IsCpuRegister());
   if (null_allowed) {
     Label null_arg;
@@ -1594,8 +1622,10 @@
 }
 
 // Given a SIRT entry, load the associated reference.
-void Assembler::LoadReferenceFromSirt(ManagedRegister out_reg,
-                                      ManagedRegister in_reg) {
+void X86Assembler::LoadReferenceFromSirt(ManagedRegister mout_reg,
+                                         ManagedRegister min_reg) {
+  X86ManagedRegister out_reg = mout_reg.AsX86();
+  X86ManagedRegister in_reg = min_reg.AsX86();
   CHECK(out_reg.IsCpuRegister());
   CHECK(in_reg.IsCpuRegister());
   Label null_arg;
@@ -1608,53 +1638,58 @@
   Bind(&null_arg);
 }
 
-void Assembler::VerifyObject(ManagedRegister src, bool could_be_null) {
+void X86Assembler::VerifyObject(ManagedRegister src, bool could_be_null) {
   // TODO: not validating references
 }
 
-void Assembler::VerifyObject(FrameOffset src, bool could_be_null) {
+void X86Assembler::VerifyObject(FrameOffset src, bool could_be_null) {
   // TODO: not validating references
 }
 
-void Assembler::Call(ManagedRegister base, Offset offset,
-                     ManagedRegister) {
+void X86Assembler::Call(ManagedRegister mbase, Offset offset, ManagedRegister) {
+  X86ManagedRegister base = mbase.AsX86();
   CHECK(base.IsCpuRegister());
   call(Address(base.AsCpuRegister(), offset.Int32Value()));
   // TODO: place reference map on call
 }
 
-void Assembler::Call(FrameOffset base, Offset offset,
-                     ManagedRegister) {
+void X86Assembler::Call(FrameOffset base, Offset offset, ManagedRegister) {
   UNIMPLEMENTED(FATAL);
 }
 
-void Assembler::Call(uintptr_t addr,
-                     ManagedRegister scratch) {
-  leal(scratch.AsCpuRegister(), Address::Absolute(addr));
-  call(scratch.AsCpuRegister());
+void X86Assembler::Call(uintptr_t addr, ManagedRegister mscratch) {
+  Register scratch = mscratch.AsX86().AsCpuRegister();
+  movl(scratch, Immediate(addr));
+  call(scratch);
 }
 
-void Assembler::GetCurrentThread(ManagedRegister tr) {
-  fs()->movl(tr.AsCpuRegister(), Address::Absolute(Thread::SelfOffset()));
+void X86Assembler::GetCurrentThread(ManagedRegister tr) {
+  fs()->movl(tr.AsX86().AsCpuRegister(),
+             Address::Absolute(Thread::SelfOffset()));
 }
 
-void Assembler::GetCurrentThread(FrameOffset offset, ManagedRegister scratch) {
+void X86Assembler::GetCurrentThread(FrameOffset offset,
+                                    ManagedRegister mscratch) {
+  X86ManagedRegister scratch = mscratch.AsX86();
   fs()->movl(scratch.AsCpuRegister(), Address::Absolute(Thread::SelfOffset()));
   movl(Address(ESP, offset), scratch.AsCpuRegister());
 }
 
-void Assembler::SuspendPoll(ManagedRegister scratch, ManagedRegister return_reg,
-                            FrameOffset return_save_location,
-                            size_t return_size) {
-  SuspendCountSlowPath* slow =
-      new SuspendCountSlowPath(return_reg, return_save_location, return_size);
+void X86Assembler::SuspendPoll(ManagedRegister scratch,
+                               ManagedRegister return_reg,
+                               FrameOffset return_save_location,
+                               size_t return_size) {
+  X86SuspendCountSlowPath* slow =
+      new X86SuspendCountSlowPath(return_reg.AsX86(), return_save_location,
+                                  return_size);
   buffer_.EnqueueSlowPath(slow);
   fs()->cmpl(Address::Absolute(Thread::SuspendCountOffset()), Immediate(0));
   j(kNotEqual, slow->Entry());
   Bind(slow->Continuation());
 }
 
-void SuspendCountSlowPath::Emit(Assembler *sp_asm) {
+void X86SuspendCountSlowPath::Emit(Assembler *sasm) {
+  X86Assembler* sp_asm = down_cast<X86Assembler*>(sasm);
 #define __ sp_asm->
   __ Bind(&entry_);
   // Save return value
@@ -1670,15 +1705,16 @@
 #undef __
 }
 
-void Assembler::ExceptionPoll(ManagedRegister scratch) {
-  ExceptionSlowPath* slow = new ExceptionSlowPath();
+void X86Assembler::ExceptionPoll(ManagedRegister scratch) {
+  X86ExceptionSlowPath* slow = new X86ExceptionSlowPath();
   buffer_.EnqueueSlowPath(slow);
   fs()->cmpl(Address::Absolute(Thread::ExceptionOffset()), Immediate(0));
   j(kNotEqual, slow->Entry());
   Bind(slow->Continuation());
 }
 
-void ExceptionSlowPath::Emit(Assembler *sp_asm) {
+void X86ExceptionSlowPath::Emit(Assembler *sasm) {
+  X86Assembler* sp_asm = down_cast<X86Assembler*>(sasm);
 #define __ sp_asm->
   __ Bind(&entry_);
   // NB the return value is dead
@@ -1693,4 +1729,5 @@
 #undef __
 }
 
+}  // namespace x86
 }  // namespace art
diff --git a/src/assembler_x86.h b/src/assembler_x86.h
index 372c61b..c893633 100644
--- a/src/assembler_x86.h
+++ b/src/assembler_x86.h
@@ -7,12 +7,13 @@
 #include "assembler.h"
 #include "constants.h"
 #include "globals.h"
-#include "managed_register.h"
+#include "managed_register_x86.h"
 #include "macros.h"
 #include "offsets.h"
 #include "utils.h"
 
 namespace art {
+namespace x86 {
 
 class Immediate {
  public:
@@ -113,7 +114,7 @@
     return encoding_[index];
   }
 
-  friend class Assembler;
+  friend class X86Assembler;
 
   DISALLOW_COPY_AND_ASSIGN(Operand);
 };
@@ -195,14 +196,10 @@
 };
 
 
-class Assembler {
+class X86Assembler : public Assembler {
  public:
-  Assembler() : buffer_() {}
-  ~Assembler() {}
-
-  InstructionSet GetInstructionSet() const {
-    return kX86;
-  }
+  X86Assembler() {}
+  virtual ~X86Assembler() {}
 
   /*
    * Emit Machine Instructions.
@@ -407,100 +404,15 @@
   void jmp(Register reg);
   void jmp(Label* label);
 
-  Assembler* lock();
+  X86Assembler* lock();
   void cmpxchgl(const Address& address, Register reg);
 
-  Assembler* fs();
+  X86Assembler* fs();
 
   //
   // Macros for High-level operations.
   //
 
-  // Emit code that will create an activation on the stack
-  void BuildFrame(size_t frame_size, ManagedRegister method_reg,
-                  const std::vector<ManagedRegister>& spill_regs);
-
-  // Emit code that will remove an activation from the stack
-  void RemoveFrame(size_t frame_size,
-                   const std::vector<ManagedRegister>& spill_regs);
-
-  // Fill registers from spill area - no-op on x86
-  void FillFromSpillArea(const std::vector<ManagedRegister>& spill_regs,
-                         size_t displacement);
-
-  void IncreaseFrameSize(size_t adjust);
-  void DecreaseFrameSize(size_t adjust);
-
-  // Store bytes from the given register onto the stack
-  void Store(FrameOffset offs, ManagedRegister src, size_t size);
-  void StoreRef(FrameOffset dest, ManagedRegister src);
-  void StoreRawPtr(FrameOffset dest, ManagedRegister src);
-  void StoreSpanning(FrameOffset dest, ManagedRegister src, FrameOffset in_off,
-                     ManagedRegister scratch) {
-    UNIMPLEMENTED(FATAL);  // this case only currently exists for ARM
-  }
-
-  void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister scratch);
-
-  void StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
-                             ManagedRegister scratch);
-
-  void StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
-                              ManagedRegister scratch);
-
-  void Load(ManagedRegister dest, FrameOffset src, size_t size);
-
-  void LoadRef(ManagedRegister dest, FrameOffset  src);
-
-  void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs);
-
-  void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs);
-
-  void LoadRawPtrFromThread(ManagedRegister dest, ThreadOffset offs);
-
-  void CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs,
-                            ManagedRegister scratch);
-
-  void CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
-                          ManagedRegister scratch);
-
-  void StoreStackOffsetToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
-                                ManagedRegister scratch);
-  void StoreStackPointerToThread(ThreadOffset thr_offs);
-
-  void Move(ManagedRegister dest, ManagedRegister src);
-
-  void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch,
-            unsigned int size);
-
-  void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset,
-                       ManagedRegister in_reg, bool null_allowed);
-
-  void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset,
-                       ManagedRegister scratch, bool null_allowed);
-
-  void LoadReferenceFromSirt(ManagedRegister dst, ManagedRegister src);
-
-  void VerifyObject(ManagedRegister src, bool could_be_null);
-  void VerifyObject(FrameOffset src, bool could_be_null);
-
-  void Call(ManagedRegister base, Offset offset, ManagedRegister scratch);
-  void Call(FrameOffset base, Offset offset, ManagedRegister scratch);
-  void Call(uintptr_t addr, ManagedRegister scratch);
-
-  void GetCurrentThread(ManagedRegister tr);
-  void GetCurrentThread(FrameOffset offset, ManagedRegister scratch);
-
-  // Generate code to check if Thread::Current()->suspend_count_ is non-zero
-  // and branch to a SuspendSlowPath if it is. The SuspendSlowPath will continue
-  // at the next instruction.
-  void SuspendPoll(ManagedRegister scratch, ManagedRegister return_reg,
-                   FrameOffset return_save_location, size_t return_size);
-
-  // Generate code to check if Thread::Current()->exception_ is non-null
-  // and branch to a ExceptionSlowPath if it is.
-  void ExceptionPoll(ManagedRegister scratch);
-
   void AddImmediate(Register reg, const Immediate& imm);
 
   void LoadDoubleConstant(XmmRegister dst, double value);
@@ -521,22 +433,124 @@
   void Align(int alignment, int offset);
   void Bind(Label* label);
 
-  void EmitSlowPaths() { buffer_.EmitSlowPaths(this); }
-
-  size_t CodeSize() const { return buffer_.Size(); }
-
-  void FinalizeInstructions(const MemoryRegion& region) {
-    buffer_.FinalizeInstructions(region);
-  }
-
   // Debugging and bringup support.
   void Stop(const char* message);
 
   static void InitializeMemoryWithBreakpoints(byte* data, size_t length);
 
- private:
-  AssemblerBuffer buffer_;
+  //
+  // Overridden common assembler high-level functionality
+  //
 
+  // Emit code that will create an activation on the stack
+  virtual void BuildFrame(size_t frame_size, ManagedRegister method_reg,
+                          const std::vector<ManagedRegister>& spill_regs);
+
+  // Emit code that will remove an activation from the stack
+  virtual void RemoveFrame(size_t frame_size,
+                           const std::vector<ManagedRegister>& spill_regs);
+
+  // Fill list of registers from spill area
+  virtual void FillFromSpillArea(const std::vector<ManagedRegister>& spill_regs,
+                                 size_t displacement);
+
+  virtual void IncreaseFrameSize(size_t adjust);
+  virtual void DecreaseFrameSize(size_t adjust);
+
+  // Store routines
+  virtual void Store(FrameOffset offs, ManagedRegister src, size_t size);
+  virtual void StoreRef(FrameOffset dest, ManagedRegister src);
+  virtual void StoreRawPtr(FrameOffset dest, ManagedRegister src);
+
+  virtual void StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
+                                     ManagedRegister scratch);
+
+  virtual void StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
+                                      ManagedRegister scratch);
+
+  virtual void StoreStackOffsetToThread(ThreadOffset thr_offs,
+                                        FrameOffset fr_offs,
+                                        ManagedRegister scratch);
+
+  virtual void StoreStackPointerToThread(ThreadOffset thr_offs);
+
+  virtual void StoreSpanning(FrameOffset dest, ManagedRegister src,
+                             FrameOffset in_off, ManagedRegister scratch);
+
+  // Load routines
+  virtual void Load(ManagedRegister dest, FrameOffset src, size_t size);
+
+  virtual void LoadRef(ManagedRegister dest, FrameOffset  src);
+
+  virtual void LoadRef(ManagedRegister dest, ManagedRegister base,
+                       MemberOffset offs);
+
+  virtual void LoadRawPtr(ManagedRegister dest, ManagedRegister base,
+                          Offset offs);
+
+  virtual void LoadRawPtrFromThread(ManagedRegister dest,
+                                    ThreadOffset offs);
+
+  // Copying routines
+  virtual void Move(ManagedRegister dest, ManagedRegister src);
+
+  virtual void CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs,
+                                    ManagedRegister scratch);
+
+  virtual void CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
+                                  ManagedRegister scratch);
+
+  virtual void CopyRef(FrameOffset dest, FrameOffset src,
+                       ManagedRegister scratch);
+
+  virtual void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch,
+                    size_t size);
+
+  // Exploit fast access in managed code to Thread::Current()
+  virtual void GetCurrentThread(ManagedRegister tr);
+  virtual void GetCurrentThread(FrameOffset dest_offset,
+                                ManagedRegister scratch);
+
+  // Set up out_reg to hold a Object** into the SIRT, or to be NULL if the
+  // value is null and null_allowed. in_reg holds a possibly stale reference
+  // that can be used to avoid loading the SIRT entry to see if the value is
+  // NULL.
+  virtual void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset,
+                               ManagedRegister in_reg, bool null_allowed);
+
+  // Set up out_off to hold a Object** into the SIRT, or to be NULL if the
+  // value is null and null_allowed.
+  virtual void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset,
+                               ManagedRegister scratch, bool null_allowed);
+
+  // src holds a SIRT entry (Object**) load this into dst
+  virtual void LoadReferenceFromSirt(ManagedRegister dst,
+                                     ManagedRegister src);
+
+  // Heap::VerifyObject on src. In some cases (such as a reference to this) we
+  // know that src may not be null.
+  virtual void VerifyObject(ManagedRegister src, bool could_be_null);
+  virtual void VerifyObject(FrameOffset src, bool could_be_null);
+
+  // Call to address held at [base+offset]
+  virtual void Call(ManagedRegister base, Offset offset,
+                    ManagedRegister scratch);
+  virtual void Call(FrameOffset base, Offset offset,
+                    ManagedRegister scratch);
+  virtual void Call(uintptr_t addr, ManagedRegister scratch);
+
+  // Generate code to check if Thread::Current()->suspend_count_ is non-zero
+  // and branch to a SuspendSlowPath if it is. The SuspendSlowPath will continue
+  // at the next instruction.
+  virtual void SuspendPoll(ManagedRegister scratch, ManagedRegister return_reg,
+                           FrameOffset return_save_location,
+                           size_t return_size);
+
+  // Generate code to check if Thread::Current()->exception_ is non-null
+  // and branch to a ExceptionSlowPath if it is.
+  virtual void ExceptionPoll(ManagedRegister scratch);
+
+ private:
   inline void EmitUint8(uint8_t value);
   inline void EmitInt32(int32_t value);
   inline void EmitRegisterOperand(int rm, int reg);
@@ -554,41 +568,60 @@
   void EmitGenericShift(int rm, Register reg, const Immediate& imm);
   void EmitGenericShift(int rm, Register operand, Register shifter);
 
-  DISALLOW_COPY_AND_ASSIGN(Assembler);
+  DISALLOW_COPY_AND_ASSIGN(X86Assembler);
 };
 
-
-inline void Assembler::EmitUint8(uint8_t value) {
+inline void X86Assembler::EmitUint8(uint8_t value) {
   buffer_.Emit<uint8_t>(value);
 }
 
-
-inline void Assembler::EmitInt32(int32_t value) {
+inline void X86Assembler::EmitInt32(int32_t value) {
   buffer_.Emit<int32_t>(value);
 }
 
-
-inline void Assembler::EmitRegisterOperand(int rm, int reg) {
+inline void X86Assembler::EmitRegisterOperand(int rm, int reg) {
   CHECK_GE(rm, 0);
   CHECK_LT(rm, 8);
   buffer_.Emit<uint8_t>(0xC0 + (rm << 3) + reg);
 }
 
-
-inline void Assembler::EmitXmmRegisterOperand(int rm, XmmRegister reg) {
+inline void X86Assembler::EmitXmmRegisterOperand(int rm, XmmRegister reg) {
   EmitRegisterOperand(rm, static_cast<Register>(reg));
 }
 
-
-inline void Assembler::EmitFixup(AssemblerFixup* fixup) {
+inline void X86Assembler::EmitFixup(AssemblerFixup* fixup) {
   buffer_.EmitFixup(fixup);
 }
 
-
-inline void Assembler::EmitOperandSizeOverride() {
+inline void X86Assembler::EmitOperandSizeOverride() {
   EmitUint8(0x66);
 }
 
+// Slowpath entered when Thread::Current()->_exception is non-null
+class X86ExceptionSlowPath : public SlowPath {
+ public:
+  X86ExceptionSlowPath() {}
+  virtual void Emit(Assembler *sp_asm);
+};
+
+// Slowpath entered when Thread::Current()->_suspend_count is non-zero
+class X86SuspendCountSlowPath : public SlowPath {
+ public:
+  X86SuspendCountSlowPath(X86ManagedRegister return_reg,
+                          FrameOffset return_save_location,
+                          size_t return_size) :
+     return_register_(return_reg), return_save_location_(return_save_location),
+     return_size_(return_size) {}
+  virtual void Emit(Assembler *sp_asm);
+
+ private:
+  // Remember how to save the return value
+  const X86ManagedRegister return_register_;
+  const FrameOffset return_save_location_;
+  const size_t return_size_;
+};
+
+}  // namespace x86
 }  // namespace art
 
 #endif  // ART_SRC_ASSEMBLER_X86_H_
diff --git a/src/calling_convention.cc b/src/calling_convention.cc
index 0cd653b..49b4348 100644
--- a/src/calling_convention.cc
+++ b/src/calling_convention.cc
@@ -1,6 +1,9 @@
 // Copyright 2011 Google Inc. All Rights Reserved.
 
 #include "calling_convention.h"
+
+#include "calling_convention_arm.h"
+#include "calling_convention_x86.h"
 #include "logging.h"
 #include "utils.h"
 
@@ -13,9 +16,18 @@
 
 // Managed runtime calling convention
 
+ManagedRuntimeCallingConvention* ManagedRuntimeCallingConvention::Create(
+    Method* native_method, InstructionSet instruction_set) {
+  if (instruction_set == kX86) {
+    return new x86::X86ManagedRuntimeCallingConvention(native_method);
+  } else {
+    CHECK(instruction_set == kArm || instruction_set == kThumb2);
+    return new arm::ArmManagedRuntimeCallingConvention(native_method);
+  }
+}
+
 size_t ManagedRuntimeCallingConvention::FrameSize() {
-  UNIMPLEMENTED(FATAL);
-  return 0;
+  return GetMethod()->GetFrameSizeInBytes();
 }
 
 bool ManagedRuntimeCallingConvention::HasNext() {
@@ -55,6 +67,16 @@
 
 // JNI calling convention
 
+JniCallingConvention* JniCallingConvention::Create(Method* native_method,
+                                               InstructionSet instruction_set) {
+  if (instruction_set == kX86) {
+    return new x86::X86JniCallingConvention(native_method);
+  } else {
+    CHECK(instruction_set == kArm || instruction_set == kThumb2);
+    return new arm::ArmJniCallingConvention(native_method);
+  }
+}
+
 size_t JniCallingConvention::ReferenceCount() {
   const Method* method = GetMethod();
   return method->NumReferenceArgs() + (method->IsStatic() ? 1 : 0);
@@ -125,11 +147,10 @@
   }
 }
 
-size_t JniCallingConvention::NumberOfExtraArgumentsForJni(
-    const Method* method) {
+size_t JniCallingConvention::NumberOfExtraArgumentsForJni(Method* method) {
   // The first argument is the JNIEnv*.
   // Static methods have an extra argument which is the jclass.
-  return (method->IsStatic() ? 2 : 1);
+  return method->IsStatic() ? 2 : 1;
 }
 
 }  // namespace art
diff --git a/src/calling_convention.h b/src/calling_convention.h
index 3b773d6..dcca3bc 100644
--- a/src/calling_convention.h
+++ b/src/calling_convention.h
@@ -13,20 +13,14 @@
 // Top-level abstraction for different calling conventions
 class CallingConvention {
  public:
-  CallingConvention* GetCallingConvention(Method* method);
-
   bool IsReturnAReference() const { return method_->IsReturnAReference(); }
 
   size_t SizeOfReturnValue() const { return method_->ReturnSize(); }
 
-  // Register that holds the incoming method argument
-  ManagedRegister MethodRegister();
   // Register that holds result of this method
-  ManagedRegister ReturnRegister();
+  virtual ManagedRegister ReturnRegister() = 0;
   // Register reserved for scratch usage during procedure calls
-  ManagedRegister InterproceduralScratchRegister();
-
-  ManagedRegister ThreadRegister();
+  virtual ManagedRegister InterproceduralScratchRegister() = 0;
 
   // Offset of Method within the frame
   FrameOffset MethodStackOffset();
@@ -44,10 +38,13 @@
     itr_longs_and_doubles_ = 0;
   }
 
+  virtual ~CallingConvention() {}
+
  protected:
   explicit CallingConvention(Method* method) : displacement_(0),
                                                method_(method) {}
-  const Method* GetMethod() const { return method_; }
+
+  Method* GetMethod() const { return method_; }
 
   // The slot number for current calling_convention argument.
   // Note that each slot is 32-bit. When the current argument is bigger
@@ -63,30 +60,37 @@
   FrameOffset displacement_;
 
  private:
-  const Method* method_;
+  Method* method_;
 };
 
 // Abstraction for managed code's calling conventions
 class ManagedRuntimeCallingConvention : public CallingConvention {
  public:
-  explicit ManagedRuntimeCallingConvention(Method* method) :
-                                          CallingConvention(method) {}
+  static ManagedRuntimeCallingConvention* Create(Method* native_method,
+                                                InstructionSet instruction_set);
 
   size_t FrameSize();
 
+  // Register that holds the incoming method argument
+  virtual ManagedRegister MethodRegister() = 0;
+
   // Iterator interface
   bool HasNext();
   void Next();
   bool IsCurrentParamAReference();
-  bool IsCurrentParamInRegister();
-  bool IsCurrentParamOnStack();
   bool IsCurrentArgExplicit();  // ie a non-implict argument such as this
   bool IsCurrentArgPossiblyNull();
   size_t CurrentParamSize();
-  ManagedRegister CurrentParamRegister();
-  FrameOffset CurrentParamStackOffset();
+  virtual bool IsCurrentParamInRegister() = 0;
+  virtual bool IsCurrentParamOnStack() = 0;
+  virtual ManagedRegister CurrentParamRegister() = 0;
+  virtual FrameOffset CurrentParamStackOffset() = 0;
 
-  DISALLOW_COPY_AND_ASSIGN(ManagedRuntimeCallingConvention);
+  virtual ~ManagedRuntimeCallingConvention() {}
+
+ protected:
+  explicit ManagedRuntimeCallingConvention(Method* method) :
+                                          CallingConvention(method) {}
 };
 
 // Abstraction for JNI calling conventions
@@ -103,23 +107,21 @@
 // | Native frame           |
 class JniCallingConvention : public CallingConvention {
  public:
-  explicit JniCallingConvention(Method* native_method)
-      : CallingConvention(native_method) {
-    ComputeRegsToSpillPreCall(spill_regs_);
-  }
+  static JniCallingConvention* Create(Method* native_method,
+                                      InstructionSet instruction_set);
 
   // Size of frame excluding space for outgoing args (its assumed Method* is
   // always at the bottom of a frame, but this doesn't work for outgoing
   // native args). Includes alignment.
-  size_t FrameSize();
+  virtual size_t FrameSize() = 0;
   // Offset within the frame of the return pc
-  size_t ReturnPcOffset();
+  virtual size_t ReturnPcOffset() = 0;
   // Size of outgoing arguments, including alignment
-  size_t OutArgSize();
+  virtual size_t OutArgSize() = 0;
+  // Size of area used to hold spilled registers
+  virtual size_t SpillAreaSize() = 0;
   // Number of references in stack indirect reference table
   size_t ReferenceCount();
-  // Size of area used to hold spilled registers
-  size_t SpillAreaSize();
   // Location where the return value of a call can be squirreled if another
   // call is made following the native call
   FrameOffset ReturnValueSaveLocation();
@@ -132,17 +134,17 @@
 
   // Returns true if the register will be clobbered by an outgoing
   // argument value.
-  bool IsOutArgRegister(ManagedRegister reg);
+  virtual bool IsOutArgRegister(ManagedRegister reg) = 0;
 
   // Iterator interface
   bool HasNext();
   void Next();
   bool IsCurrentParamAReference();
-  bool IsCurrentParamInRegister();
-  bool IsCurrentParamOnStack();
   size_t CurrentParamSize();
-  ManagedRegister CurrentParamRegister();
-  FrameOffset CurrentParamStackOffset();
+  virtual bool IsCurrentParamInRegister() = 0;
+  virtual bool IsCurrentParamOnStack() = 0;
+  virtual ManagedRegister CurrentParamRegister() = 0;
+  virtual FrameOffset CurrentParamStackOffset() = 0;
 
   // Iterator interface extension for JNI
   FrameOffset CurrentParamSirtEntryOffset();
@@ -162,25 +164,27 @@
                        StackIndirectReferenceTable::LinkOffset());
   }
 
- private:
+  virtual ~JniCallingConvention() {}
+
+ protected:
   // Named iterator positions
   enum IteratorPos {
     kJniEnv = 0,
     kObjectOrClass = 1
   };
 
+  explicit JniCallingConvention(Method* native_method) :
+      CallingConvention(native_method) {}
+
   // Number of stack slots for outgoing arguments, above which the SIRT is
   // located
-  size_t NumberOfOutgoingStackArgs();
+  virtual size_t NumberOfOutgoingStackArgs() = 0;
 
-  // Compute registers for RegsToSpillPreCall
-  void ComputeRegsToSpillPreCall(std::vector<ManagedRegister>& regs);
+ protected:
+  static size_t NumberOfExtraArgumentsForJni(Method* method);
 
   // Extra registers to spill before the call into native
   std::vector<ManagedRegister> spill_regs_;
-
-  static size_t NumberOfExtraArgumentsForJni(const Method* method);
-  DISALLOW_COPY_AND_ASSIGN(JniCallingConvention);
 };
 
 }  // namespace art
diff --git a/src/calling_convention_arm.cc b/src/calling_convention_arm.cc
index 527ce5f..4b4a146 100644
--- a/src/calling_convention_arm.cc
+++ b/src/calling_convention_arm.cc
@@ -1,44 +1,55 @@
 // Copyright 2011 Google Inc. All Rights Reserved.
 
-#include "calling_convention.h"
+#include "calling_convention_arm.h"
 #include "logging.h"
+#include "managed_register_arm.h"
 
 namespace art {
+namespace arm {
 
-ManagedRegister CallingConvention::MethodRegister() {
-  return ManagedRegister::FromCoreRegister(R0);
+// Calling convention
+
+ManagedRegister ArmManagedRuntimeCallingConvention::InterproceduralScratchRegister() {
+  return ArmManagedRegister::FromCoreRegister(IP);  // R12
 }
 
-ManagedRegister CallingConvention::ThreadRegister() {
-  return ManagedRegister::FromCoreRegister(TR);
+ManagedRegister ArmJniCallingConvention::InterproceduralScratchRegister() {
+  return ArmManagedRegister::FromCoreRegister(IP);  // R12
 }
 
-ManagedRegister CallingConvention::InterproceduralScratchRegister() {
-  return ManagedRegister::FromCoreRegister(R12);
-}
-
-ManagedRegister CallingConvention::ReturnRegister() {
-  const Method *method = GetMethod();
-  if (GetMethod()->IsReturnAFloat()) {
-    return ManagedRegister::FromCoreRegister(R0);
-  } else if (GetMethod()->IsReturnADouble()) {
-    return ManagedRegister::FromRegisterPair(R0_R1);
+static ManagedRegister ReturnRegisterForMethod(Method* method) {
+  if (method->IsReturnAFloat()) {
+    return ArmManagedRegister::FromCoreRegister(R0);
+  } else if (method->IsReturnADouble()) {
+    return ArmManagedRegister::FromRegisterPair(R0_R1);
   } else if (method->IsReturnALong()) {
-    return ManagedRegister::FromRegisterPair(R0_R1);
+    return ArmManagedRegister::FromRegisterPair(R0_R1);
   } else if (method->IsReturnVoid()) {
-    return ManagedRegister::NoRegister();
+    return ArmManagedRegister::NoRegister();
   } else {
-    return ManagedRegister::FromCoreRegister(R0);
+    return ArmManagedRegister::FromCoreRegister(R0);
   }
 }
 
+ManagedRegister ArmManagedRuntimeCallingConvention::ReturnRegister() {
+  return ReturnRegisterForMethod(GetMethod());
+}
+
+ManagedRegister ArmJniCallingConvention::ReturnRegister() {
+  return ReturnRegisterForMethod(GetMethod());
+}
+
 // Managed runtime calling convention
 
-bool ManagedRuntimeCallingConvention::IsCurrentParamInRegister() {
+ManagedRegister ArmManagedRuntimeCallingConvention::MethodRegister() {
+  return ArmManagedRegister::FromCoreRegister(R0);
+}
+
+bool ArmManagedRuntimeCallingConvention::IsCurrentParamInRegister() {
   return itr_slots_ < 3;
 }
 
-bool ManagedRuntimeCallingConvention::IsCurrentParamOnStack() {
+bool ArmManagedRuntimeCallingConvention::IsCurrentParamOnStack() {
   if (itr_slots_ < 2) {
     return false;
   } else if (itr_slots_ > 2) {
@@ -52,26 +63,26 @@
 static const Register kManagedArgumentRegisters[] = {
   R1, R2, R3
 };
-ManagedRegister ManagedRuntimeCallingConvention::CurrentParamRegister() {
+ManagedRegister ArmManagedRuntimeCallingConvention::CurrentParamRegister() {
   CHECK(IsCurrentParamInRegister());
   const Method* method = GetMethod();
   if (method->IsParamALongOrDouble(itr_args_)) {
     if (itr_slots_ == 0) {
-      return ManagedRegister::FromRegisterPair(R1_R2);
+      return ArmManagedRegister::FromRegisterPair(R1_R2);
     } else if (itr_slots_ == 1) {
-      return ManagedRegister::FromRegisterPair(R2_R3);
+      return ArmManagedRegister::FromRegisterPair(R2_R3);
     } else {
       // This is a long/double split between registers and the stack
-      return ManagedRegister::FromCoreRegister(
+      return ArmManagedRegister::FromCoreRegister(
         kManagedArgumentRegisters[itr_slots_]);
     }
   } else {
     return
-      ManagedRegister::FromCoreRegister(kManagedArgumentRegisters[itr_slots_]);
+      ArmManagedRegister::FromCoreRegister(kManagedArgumentRegisters[itr_slots_]);
   }
 }
 
-FrameOffset ManagedRuntimeCallingConvention::CurrentParamStackOffset() {
+FrameOffset ArmManagedRuntimeCallingConvention::CurrentParamStackOffset() {
   CHECK(IsCurrentParamOnStack());
   FrameOffset result =
       FrameOffset(displacement_.Int32Value() +   // displacement
@@ -88,7 +99,18 @@
 
 // JNI calling convention
 
-size_t JniCallingConvention::FrameSize() {
+ArmJniCallingConvention::ArmJniCallingConvention(Method* method) :
+    JniCallingConvention(method) {
+  // A synchronized method will call monitor enter clobbering R1, R2 and R3
+  // unless they are spilled.
+  if (method->IsSynchronized()) {
+    spill_regs_.push_back(ArmManagedRegister::FromCoreRegister(R1));
+    spill_regs_.push_back(ArmManagedRegister::FromCoreRegister(R2));
+    spill_regs_.push_back(ArmManagedRegister::FromCoreRegister(R3));
+  }
+}
+
+size_t ArmJniCallingConvention::FrameSize() {
   // Method* and spill area size
   size_t frame_data_size = kPointerSize + SpillAreaSize();
   // References plus 2 words for SIRT header
@@ -98,7 +120,7 @@
                  kStackAlignment);
 }
 
-size_t JniCallingConvention::OutArgSize() {
+size_t ArmJniCallingConvention::OutArgSize() {
   const Method* method = GetMethod();
   size_t padding;  // padding to ensure longs and doubles are not split in AAPCS
   if (method->IsStatic()) {
@@ -112,32 +134,22 @@
                  kStackAlignment);
 }
 
-size_t JniCallingConvention::ReturnPcOffset() {
+size_t ArmJniCallingConvention::ReturnPcOffset() {
   // Link register is always the last value spilled, skip forward one word for
   // the Method* then skip back one word to get the link register (ie +0)
   return SpillAreaSize();
 }
 
-size_t JniCallingConvention::SpillAreaSize() {
+size_t ArmJniCallingConvention::SpillAreaSize() {
   // Space for link register. For synchronized methods we need enough space to
   // save R1, R2 and R3 (R0 is the method register and always preserved)
   return GetMethod()->IsSynchronized() ? (4 * kPointerSize) : kPointerSize;
 }
 
-void JniCallingConvention::ComputeRegsToSpillPreCall(std::vector<ManagedRegister>& regs) {
-  // A synchronized method will call monitor enter clobbering R1, R2 and R3
-  // unless they are spilled.
-  if (GetMethod()->IsSynchronized()) {
-    regs.push_back(ManagedRegister::FromCoreRegister(R1));
-    regs.push_back(ManagedRegister::FromCoreRegister(R2));
-    regs.push_back(ManagedRegister::FromCoreRegister(R3));
-  }
-}
-
 // Will reg be crushed by an outgoing argument?
-bool JniCallingConvention::IsOutArgRegister(ManagedRegister) {
-  // R0 holds the method register and will be crushed by the JNIEnv*
-  return true;
+bool ArmJniCallingConvention::IsOutArgRegister(ManagedRegister mreg) {
+  Register reg = mreg.AsArm().AsCoreRegister();
+  return reg >= R0 && reg <= R3;
 }
 
 // JniCallingConvention ABI follows AAPCS
@@ -146,9 +158,9 @@
 // or IsCurrentParamOnStack() will be called first.
 // Both functions will ensure that we conform to AAPCS.
 //
-bool JniCallingConvention::IsCurrentParamInRegister() {
+bool ArmJniCallingConvention::IsCurrentParamInRegister() {
   // AAPCS processing
-  const Method* method = GetMethod();
+  Method* method = GetMethod();
   int arg_pos = itr_args_ - NumberOfExtraArgumentsForJni(method);
   if ((itr_args_ >= 2) && method->IsParamALongOrDouble(arg_pos)) {
     // itr_slots_ needs to be an even number, according to AAPCS.
@@ -160,34 +172,34 @@
   return itr_slots_ < 4;
 }
 
-bool JniCallingConvention::IsCurrentParamOnStack() {
+bool ArmJniCallingConvention::IsCurrentParamOnStack() {
   return !IsCurrentParamInRegister();
 }
 
 static const Register kJniArgumentRegisters[] = {
   R0, R1, R2, R3
 };
-ManagedRegister JniCallingConvention::CurrentParamRegister() {
+ManagedRegister ArmJniCallingConvention::CurrentParamRegister() {
   CHECK_LT(itr_slots_, 4u);
-  const Method* method = GetMethod();
+  Method* method = GetMethod();
   int arg_pos = itr_args_ - NumberOfExtraArgumentsForJni(method);
   if ((itr_args_ >= 2) && method->IsParamALongOrDouble(arg_pos)) {
     CHECK_EQ(itr_slots_, 2u);
-    return ManagedRegister::FromRegisterPair(R2_R3);
+    return ArmManagedRegister::FromRegisterPair(R2_R3);
   } else {
     return
-      ManagedRegister::FromCoreRegister(kJniArgumentRegisters[itr_slots_]);
+      ArmManagedRegister::FromCoreRegister(kJniArgumentRegisters[itr_slots_]);
   }
 }
 
-FrameOffset JniCallingConvention::CurrentParamStackOffset() {
+FrameOffset ArmJniCallingConvention::CurrentParamStackOffset() {
   CHECK_GE(itr_slots_, 4u);
   return FrameOffset(displacement_.Int32Value() - OutArgSize()
                + ((itr_slots_ - 4) * kPointerSize));
 }
 
-size_t JniCallingConvention::NumberOfOutgoingStackArgs() {
-  const Method* method = GetMethod();
+size_t ArmJniCallingConvention::NumberOfOutgoingStackArgs() {
+  Method* method = GetMethod();
   size_t static_args = method->IsStatic() ? 1 : 0;  // count jclass
   // regular argument parameters and this
   size_t param_args = method->NumArgs() +
@@ -196,4 +208,5 @@
   return static_args + param_args + 1 - 4;
 }
 
+}  // namespace arm
 }  // namespace art
diff --git a/src/calling_convention_arm.h b/src/calling_convention_arm.h
new file mode 100644
index 0000000..e9c8ab0
--- /dev/null
+++ b/src/calling_convention_arm.h
@@ -0,0 +1,58 @@
+// Copyright 2011 Google Inc. All Rights Reserved.
+
+#ifndef ART_SRC_CALLING_CONVENTION_ARM_H_
+#define ART_SRC_CALLING_CONVENTION_ARM_H_
+
+#include "calling_convention.h"
+
+namespace art {
+namespace arm {
+
+class ArmManagedRuntimeCallingConvention : public ManagedRuntimeCallingConvention {
+ public:
+  explicit ArmManagedRuntimeCallingConvention(Method* method) :
+                                     ManagedRuntimeCallingConvention(method) {}
+  virtual ~ArmManagedRuntimeCallingConvention() {}
+  // Calling convention
+  virtual ManagedRegister ReturnRegister();
+  virtual ManagedRegister InterproceduralScratchRegister();
+  // Managed runtime calling convention
+  virtual ManagedRegister MethodRegister();
+  virtual bool IsCurrentParamInRegister();
+  virtual bool IsCurrentParamOnStack();
+  virtual ManagedRegister CurrentParamRegister();
+  virtual FrameOffset CurrentParamStackOffset();
+
+ private:
+  DISALLOW_COPY_AND_ASSIGN(ArmManagedRuntimeCallingConvention);
+};
+
+class ArmJniCallingConvention : public JniCallingConvention {
+ public:
+  explicit ArmJniCallingConvention(Method* method);
+  virtual ~ArmJniCallingConvention() {}
+  // Calling convention
+  virtual ManagedRegister ReturnRegister();
+  virtual ManagedRegister InterproceduralScratchRegister();
+  // JNI calling convention
+  virtual size_t FrameSize();
+  virtual size_t ReturnPcOffset();
+  virtual size_t OutArgSize();
+  virtual size_t SpillAreaSize();
+  virtual bool IsOutArgRegister(ManagedRegister reg);
+  virtual bool IsCurrentParamInRegister();
+  virtual bool IsCurrentParamOnStack();
+  virtual ManagedRegister CurrentParamRegister();
+  virtual FrameOffset CurrentParamStackOffset();
+
+ protected:
+  virtual size_t NumberOfOutgoingStackArgs();
+
+ private:
+  DISALLOW_COPY_AND_ASSIGN(ArmJniCallingConvention);
+};
+
+}  // namespace arm
+}  // namespace art
+
+#endif  // ART_SRC_CALLING_CONVENTION_ARM_H_
diff --git a/src/calling_convention_x86.cc b/src/calling_convention_x86.cc
index 92ca780..6cc556a 100644
--- a/src/calling_convention_x86.cc
+++ b/src/calling_convention_x86.cc
@@ -1,48 +1,63 @@
 // Copyright 2011 Google Inc. All Rights Reserved.
 
-#include "calling_convention.h"
+#include "calling_convention_x86.h"
 #include "logging.h"
+#include "managed_register_x86.h"
 #include "utils.h"
 
 namespace art {
+namespace x86 {
 
-ManagedRegister CallingConvention::MethodRegister() {
-  return ManagedRegister::FromCpuRegister(EDI);
+// Calling convention
+
+ManagedRegister X86ManagedRuntimeCallingConvention::InterproceduralScratchRegister() {
+  return X86ManagedRegister::FromCpuRegister(ECX);
 }
 
-ManagedRegister CallingConvention::InterproceduralScratchRegister() {
-  return ManagedRegister::FromCpuRegister(ECX);
+ManagedRegister X86JniCallingConvention::InterproceduralScratchRegister() {
+  return X86ManagedRegister::FromCpuRegister(ECX);
 }
 
-ManagedRegister CallingConvention::ReturnRegister() {
-  const Method *method = GetMethod();
+static ManagedRegister ReturnRegisterForMethod(Method* method) {
   if (method->IsReturnAFloatOrDouble()) {
-    return ManagedRegister::FromX87Register(ST0);
+    return X86ManagedRegister::FromX87Register(ST0);
   } else if (method->IsReturnALong()) {
-    return ManagedRegister::FromRegisterPair(EAX_EDX);
+    return X86ManagedRegister::FromRegisterPair(EAX_EDX);
   } else if (method->IsReturnVoid()) {
     return ManagedRegister::NoRegister();
   } else {
-    return ManagedRegister::FromCpuRegister(EAX);
+    return X86ManagedRegister::FromCpuRegister(EAX);
   }
 }
 
+ManagedRegister X86ManagedRuntimeCallingConvention::ReturnRegister() {
+  return ReturnRegisterForMethod(GetMethod());
+}
+
+ManagedRegister X86JniCallingConvention::ReturnRegister() {
+  return ReturnRegisterForMethod(GetMethod());
+}
+
 // Managed runtime calling convention
 
-bool ManagedRuntimeCallingConvention::IsCurrentParamInRegister() {
+ManagedRegister X86ManagedRuntimeCallingConvention::MethodRegister() {
+  return X86ManagedRegister::FromCpuRegister(EDI);
+}
+
+bool X86ManagedRuntimeCallingConvention::IsCurrentParamInRegister() {
   return false;  // Everything is passed by stack
 }
 
-bool ManagedRuntimeCallingConvention::IsCurrentParamOnStack() {
+bool X86ManagedRuntimeCallingConvention::IsCurrentParamOnStack() {
   return true;  // Everything is passed by stack
 }
 
-ManagedRegister ManagedRuntimeCallingConvention::CurrentParamRegister() {
+ManagedRegister X86ManagedRuntimeCallingConvention::CurrentParamRegister() {
   LOG(FATAL) << "Should not reach here";
   return ManagedRegister::NoRegister();
 }
 
-FrameOffset ManagedRuntimeCallingConvention::CurrentParamStackOffset() {
+FrameOffset X86ManagedRuntimeCallingConvention::CurrentParamStackOffset() {
   return FrameOffset(displacement_.Int32Value() +   // displacement
                      kPointerSize +                 // Method*
                      (itr_slots_ * kPointerSize));  // offset into in args
@@ -50,7 +65,7 @@
 
 // JNI calling convention
 
-size_t JniCallingConvention::FrameSize() {
+size_t X86JniCallingConvention::FrameSize() {
   // Return address and Method*
   size_t frame_data_size = 2 * kPointerSize;
   // References plus 2 words for SIRT header
@@ -60,49 +75,44 @@
                  kStackAlignment);
 }
 
-size_t JniCallingConvention::OutArgSize() {
+size_t X86JniCallingConvention::OutArgSize() {
   return RoundUp(NumberOfOutgoingStackArgs() * kPointerSize, kStackAlignment);
 }
 
-size_t JniCallingConvention::ReturnPcOffset() {
+size_t X86JniCallingConvention::ReturnPcOffset() {
   // Return PC is pushed at the top of the frame by the call into the method
   return FrameSize() - kPointerSize;
 }
 
 
-size_t JniCallingConvention::SpillAreaSize() {
+size_t X86JniCallingConvention::SpillAreaSize() {
   // No spills, return address was pushed at the top of the frame
   return 0;
 }
 
-void JniCallingConvention::ComputeRegsToSpillPreCall(std::vector<ManagedRegister>& regs) {
-  // No live values in registers (everything is on the stack) so never anything
-  // to preserve.
-}
-
-bool JniCallingConvention::IsOutArgRegister(ManagedRegister) {
+bool X86JniCallingConvention::IsOutArgRegister(ManagedRegister) {
   return false;  // Everything is passed by stack
 }
 
-bool JniCallingConvention::IsCurrentParamInRegister() {
+bool X86JniCallingConvention::IsCurrentParamInRegister() {
   return false;  // Everything is passed by stack
 }
 
-bool JniCallingConvention::IsCurrentParamOnStack() {
+bool X86JniCallingConvention::IsCurrentParamOnStack() {
   return true;  // Everything is passed by stack
 }
 
-ManagedRegister JniCallingConvention::CurrentParamRegister() {
+ManagedRegister X86JniCallingConvention::CurrentParamRegister() {
   LOG(FATAL) << "Should not reach here";
   return ManagedRegister::NoRegister();
 }
 
-FrameOffset JniCallingConvention::CurrentParamStackOffset() {
+FrameOffset X86JniCallingConvention::CurrentParamStackOffset() {
   return FrameOffset(displacement_.Int32Value() - OutArgSize() +
                      (itr_slots_ * kPointerSize));
 }
 
-size_t JniCallingConvention::NumberOfOutgoingStackArgs() {
+size_t X86JniCallingConvention::NumberOfOutgoingStackArgs() {
   size_t static_args = GetMethod()->IsStatic() ? 1 : 0;  // count jclass
   // regular argument parameters and this
   size_t param_args = GetMethod()->NumArgs() +
@@ -110,4 +120,5 @@
   return static_args + param_args + 1;  // count JNIEnv*
 }
 
+}  // namespace x86
 }  // namespace art
diff --git a/src/calling_convention_x86.h b/src/calling_convention_x86.h
new file mode 100644
index 0000000..d8dda57
--- /dev/null
+++ b/src/calling_convention_x86.h
@@ -0,0 +1,59 @@
+// Copyright 2011 Google Inc. All Rights Reserved.
+
+#ifndef ART_SRC_CALLING_CONVENTION_X86_H_
+#define ART_SRC_CALLING_CONVENTION_X86_H_
+
+#include "calling_convention.h"
+
+namespace art {
+namespace x86 {
+
+class X86ManagedRuntimeCallingConvention : public ManagedRuntimeCallingConvention {
+ public:
+  explicit X86ManagedRuntimeCallingConvention(Method* method) :
+                                     ManagedRuntimeCallingConvention(method) {}
+  virtual ~X86ManagedRuntimeCallingConvention() {}
+  // Calling convention
+  virtual ManagedRegister ReturnRegister();
+  virtual ManagedRegister InterproceduralScratchRegister();
+  // Managed runtime calling convention
+  virtual ManagedRegister MethodRegister();
+  virtual bool IsCurrentParamInRegister();
+  virtual bool IsCurrentParamOnStack();
+  virtual ManagedRegister CurrentParamRegister();
+  virtual FrameOffset CurrentParamStackOffset();
+
+ private:
+  DISALLOW_COPY_AND_ASSIGN(X86ManagedRuntimeCallingConvention);
+};
+
+class X86JniCallingConvention : public JniCallingConvention {
+ public:
+  explicit X86JniCallingConvention(Method* method) :
+                                   JniCallingConvention(method) {}
+  virtual ~X86JniCallingConvention() {}
+  // Calling convention
+  virtual ManagedRegister ReturnRegister();
+  virtual ManagedRegister InterproceduralScratchRegister();
+  // JNI calling convention
+  virtual size_t FrameSize();
+  virtual size_t ReturnPcOffset();
+  virtual size_t OutArgSize();
+  virtual size_t SpillAreaSize();
+  virtual bool IsOutArgRegister(ManagedRegister reg);
+  virtual bool IsCurrentParamInRegister();
+  virtual bool IsCurrentParamOnStack();
+  virtual ManagedRegister CurrentParamRegister();
+  virtual FrameOffset CurrentParamStackOffset();
+
+ protected:
+  virtual size_t NumberOfOutgoingStackArgs();
+
+ private:
+  DISALLOW_COPY_AND_ASSIGN(X86JniCallingConvention);
+};
+
+}  // namespace x86
+}  // namespace art
+
+#endif  // ART_SRC_CALLING_CONVENTION_X86_H_
diff --git a/src/common_test.h b/src/common_test.h
index 98d9127..1f3f063 100644
--- a/src/common_test.h
+++ b/src/common_test.h
@@ -10,6 +10,7 @@
 #include "class_linker.h"
 #include "class_loader.h"
 #include "compiler.h"
+#include "constants.h"
 #include "dex_file.h"
 #include "gtest/gtest.h"
 #include "heap.h"
@@ -108,6 +109,14 @@
     runtime_->Start();
     class_linker_ = runtime_->GetClassLinker();
 
+#if defined(__i386__)
+    compiler_ = new Compiler(kX86);
+#elif defined(__arm__)
+    compiler_ = new Compiler(kThumb2);
+#else
+    compiler_ = new Compiler(kNone);
+#endif
+
     Heap::VerifyHeap();  // Check for heap corruption before the test
   }
 
@@ -148,6 +157,8 @@
     IcuCleanupFn icu_cleanup_fn = reinterpret_cast<IcuCleanupFn>(sym);
     (*icu_cleanup_fn)();
 
+    delete compiler_;
+
     Heap::VerifyHeap();  // Check for heap corruption after the test
   }
 
@@ -237,8 +248,7 @@
 
   void CompileMethod(Method* method) {
     CHECK(method != NULL);
-    Compiler compiler;
-    compiler.CompileOne(method);
+    compiler_->CompileOne(method);
     MakeExecutable(method->GetCodeArray());
     MakeExecutable(method->GetInvokeStubArray());
   }
@@ -276,6 +286,7 @@
   std::vector<const DexFile*> boot_class_path_;
   UniquePtr<Runtime> runtime_;
   ClassLinker* class_linker_;
+  Compiler* compiler_;
 
  private:
   std::vector<const DexFile*> loaded_dex_files_;
diff --git a/src/compiler.cc b/src/compiler.cc
index 4e3c052..be12121 100644
--- a/src/compiler.cc
+++ b/src/compiler.cc
@@ -14,7 +14,6 @@
 
 namespace art {
 
-// TODO need to specify target
 void Compiler::CompileAll(const ClassLoader* class_loader) {
   Resolve(class_loader);
   // TODO add verification step
@@ -97,34 +96,16 @@
   }
 }
 
-// This is private API, but with two different implementations: ARM and x86.
-void CreateInvokeStub(Assembler* assembler, Method* method);
-
-namespace {
-
-void CompileInvokeStub(Method* method) {
-  if (method->GetInvokeStub() != NULL) {
-    return;
-  }
-  // TODO: use signature to find a matching stub
-  // TODO: failed, acquire a lock on the stub table
-  Assembler assembler;
-  art::CreateInvokeStub(&assembler, method);
-  // TODO: store native_entry in the stub table
-  ByteArray* code = ByteArray::Alloc(assembler.CodeSize());
-  MemoryRegion region(code->GetData(), code->GetLength());
-  assembler.FinalizeInstructions(region);
-  method->SetInvokeStub(code);
-  CHECK(method->GetInvokeStub() != NULL);
+namespace arm {
+  void ArmCreateInvokeStub(Method* method);
 }
-
-} // namespace
+namespace x86 {
+  void X86CreateInvokeStub(Method* method);
+}
 
 void Compiler::CompileMethod(Method* method) {
   if (method->IsNative()) {
-    Assembler jni_asm;
-    JniCompiler jni_compiler;
-    jni_compiler.Compile(&jni_asm, method);
+    jni_compiler_.Compile(method);
   } else if (method->IsAbstract()) {
     // TODO: This might be also noted in the ClassLinker.
     // Probably makes more sense to do here?
@@ -134,7 +115,13 @@
   }
   // CHECK(method->HasCode());  // TODO: enable this check ASAP
 
-  CompileInvokeStub(method);
+  if (instruction_set_ == kX86) {
+    art::x86::X86CreateInvokeStub(method);
+  } else {
+    CHECK(instruction_set_ == kArm || instruction_set_ == kThumb2);
+    // Generates invocation stub using ARM instruction set
+    art::arm::ArmCreateInvokeStub(method);
+  }
   CHECK(method->GetInvokeStub() != NULL);
 }
 
diff --git a/src/compiler.h b/src/compiler.h
index 1214d3c..e818a1c 100644
--- a/src/compiler.h
+++ b/src/compiler.h
@@ -3,13 +3,18 @@
 #ifndef ART_SRC_COMPILER_H_
 #define ART_SRC_COMPILER_H_
 
+#include "constants.h"
 #include "dex_file.h"
+#include "jni_compiler.h"
 #include "object.h"
 
 namespace art {
 
 class Compiler {
  public:
+  explicit Compiler(InstructionSet insns) : instruction_set_(insns),
+      jni_compiler_(insns) {}
+
   // Compile all Methods of all the Classes of all the DexFiles that are part of a ClassLoader.
   void CompileAll(const ClassLoader* class_loader);
 
@@ -32,6 +37,11 @@
   // method pointers of CodeAndDirectMethods entries in the DexCaches.
   void SetCodeAndDirectMethods(const ClassLoader* class_loader);
   void SetCodeAndDirectMethodsDexFile(const DexFile& dex_file);
+
+  InstructionSet instruction_set_;
+  JniCompiler jni_compiler_;
+
+  DISALLOW_COPY_AND_ASSIGN(Compiler);
 };
 
 }  // namespace art
diff --git a/src/compiler_test.cc b/src/compiler_test.cc
index 5766a4f..2620d14 100644
--- a/src/compiler_test.cc
+++ b/src/compiler_test.cc
@@ -58,8 +58,7 @@
 
 // Disabled due to 10 second runtime on host
 TEST_F(CompilerTest, DISABLED_CompileDexLibCore) {
-  Compiler compiler;
-  compiler.CompileAll(NULL);
+  compiler_->CompileAll(NULL);
 
   // All libcore references should resolve
   const DexFile* dex = java_lang_dex_file_.get();
diff --git a/src/constants.h b/src/constants.h
index f71857e..836c0c4 100644
--- a/src/constants.h
+++ b/src/constants.h
@@ -14,10 +14,7 @@
 
 }  // namespace art
 
-#if defined(__i386__)
 #include "constants_x86.h"
-#elif defined(__arm__)
 #include "constants_arm.h"
-#endif
 
 #endif  // ART_SRC_CONSTANTS_H_
diff --git a/src/constants_arm.h b/src/constants_arm.h
index 2d2acb7..097c6bc 100644
--- a/src/constants_arm.h
+++ b/src/constants_arm.h
@@ -10,6 +10,7 @@
 #include "logging.h"
 
 namespace art {
+namespace arm {
 
 // Defines constants and accessor classes to assemble, disassemble and
 // simulate ARM instructions.
@@ -548,6 +549,7 @@
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
+}  // namespace arm
 }  // namespace art
 
 #endif  // ART_SRC_CONSTANTS_ARM_H_
diff --git a/src/constants_x86.h b/src/constants_x86.h
index 36019ae..8712185 100644
--- a/src/constants_x86.h
+++ b/src/constants_x86.h
@@ -9,6 +9,7 @@
 #include "macros.h"
 
 namespace art {
+namespace x86 {
 
 enum Register {
   EAX = 0,
@@ -120,6 +121,7 @@
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
+}  // namespace x86
 }  // namespace art
 
 #endif  // ART_SRC_CONSTANTS_X86_H_
diff --git a/src/dex2oat.cc b/src/dex2oat.cc
index 4d071a7..64e0aaa 100644
--- a/src/dex2oat.cc
+++ b/src/dex2oat.cc
@@ -162,7 +162,7 @@
     class_loader = PathClassLoader::Alloc(dex_files);
   }
 
-  Compiler compiler;
+  Compiler compiler(kThumb2);
   if (method_names.empty()) {
     compiler.CompileAll(class_loader);
   } else {
diff --git a/src/jni_compiler.cc b/src/jni_compiler.cc
index fec11da..bb1e965 100644
--- a/src/jni_compiler.cc
+++ b/src/jni_compiler.cc
@@ -1,5 +1,4 @@
 // Copyright 2011 Google Inc. All Rights Reserved.
-// Author: irogers@google.com (Ian Rogers)
 
 #include "jni_compiler.h"
 
@@ -8,14 +7,28 @@
 
 #include "assembler.h"
 #include "calling_convention.h"
+#include "constants.h"
 #include "jni_internal.h"
 #include "macros.h"
 #include "managed_register.h"
 #include "logging.h"
 #include "thread.h"
+#include "UniquePtr.h"
 
 namespace art {
 
+JniCompiler::JniCompiler(InstructionSet insns) {
+  if (insns == kThumb2) {
+    // currently only ARM code generation is supported
+    instruction_set_ = kArm;
+  } else {
+    instruction_set_ = insns;
+  }
+}
+
+JniCompiler::~JniCompiler() {}
+
+// Return value helper for jobject return types
 static Object* DecodeJObjectInThread(Thread* thread, jobject obj) {
   return thread->DecodeJObject(obj);
 }
@@ -25,125 +38,140 @@
 //   registers, a reference to the method object is supplied as part of this
 //   convention.
 //
-void JniCompiler::Compile(Assembler* jni_asm, Method* native_method) {
+void JniCompiler::Compile(Method* native_method) {
   CHECK(native_method->IsNative());
-  JniCallingConvention jni_conv(native_method);
-  ManagedRuntimeCallingConvention mr_conv(native_method);
+
+  // Calling conventions used to iterate over parameters to method
+  UniquePtr<JniCallingConvention> jni_conv(
+      JniCallingConvention::Create(native_method, instruction_set_));
+  UniquePtr<ManagedRuntimeCallingConvention> mr_conv(
+      ManagedRuntimeCallingConvention::Create(native_method, instruction_set_));
+
+  // Assembler that holds generated instructions
+  UniquePtr<Assembler> jni_asm(Assembler::Create(instruction_set_));
+#define __ jni_asm->
+
+  // Offsets into data structures
+  // TODO: if cross compiling these offsets are for the host not the target
+  const Offset functions(OFFSETOF_MEMBER(JNIEnvExt, functions));
+  const Offset monitor_enter(OFFSETOF_MEMBER(JNINativeInterface, MonitorEnter));
+  const Offset monitor_exit(OFFSETOF_MEMBER(JNINativeInterface, MonitorExit));
+
+  // Cache of IsStatic as we call it often enough
   const bool is_static = native_method->IsStatic();
-  static Offset functions(OFFSETOF_MEMBER(JNIEnvExt, functions));
-  static Offset monitor_enter(OFFSETOF_MEMBER(JNINativeInterface, MonitorEnter));
-  static Offset monitor_exit(OFFSETOF_MEMBER(JNINativeInterface, MonitorExit));
+
 
   // 1. Build the frame
-  const size_t frame_size(jni_conv.FrameSize());
-  const std::vector<ManagedRegister>& spill_regs = jni_conv.RegsToSpillPreCall();
-  jni_asm->BuildFrame(frame_size, mr_conv.MethodRegister(), spill_regs);
+  const size_t frame_size(jni_conv->FrameSize());
+  const std::vector<ManagedRegister>& spill_regs = jni_conv->RegsToSpillPreCall();
+  __ BuildFrame(frame_size, mr_conv->MethodRegister(), spill_regs);
 
   // 2. Save callee save registers that aren't callee save in the native code
   // TODO: implement computing the difference of the callee saves
   // and saving
 
   // 3. Set up the StackIndirectReferenceTable
-  mr_conv.ResetIterator(FrameOffset(frame_size));
-  jni_conv.ResetIterator(FrameOffset(0));
-  jni_asm->StoreImmediateToFrame(jni_conv.SirtNumRefsOffset(),
-                                 jni_conv.ReferenceCount(),
-                                 mr_conv.InterproceduralScratchRegister());
-  jni_asm->CopyRawPtrFromThread(jni_conv.SirtLinkOffset(),
-                                Thread::TopSirtOffset(),
-                                mr_conv.InterproceduralScratchRegister());
-  jni_asm->StoreStackOffsetToThread(Thread::TopSirtOffset(),
-                                    jni_conv.SirtOffset(),
-                                    mr_conv.InterproceduralScratchRegister());
+  mr_conv->ResetIterator(FrameOffset(frame_size));
+  jni_conv->ResetIterator(FrameOffset(0));
+  __ StoreImmediateToFrame(jni_conv->SirtNumRefsOffset(),
+                           jni_conv->ReferenceCount(),
+                           mr_conv->InterproceduralScratchRegister());
+  __ CopyRawPtrFromThread(jni_conv->SirtLinkOffset(),
+                          Thread::TopSirtOffset(),
+                          mr_conv->InterproceduralScratchRegister());
+  __ StoreStackOffsetToThread(Thread::TopSirtOffset(),
+                              jni_conv->SirtOffset(),
+                              mr_conv->InterproceduralScratchRegister());
 
   // 4. Place incoming reference arguments into SIRT
-  jni_conv.Next();  // Skip JNIEnv*
+  jni_conv->Next();  // Skip JNIEnv*
   // 4.5. Create Class argument for static methods out of passed method
   if (is_static) {
-    FrameOffset sirt_offset = jni_conv.CurrentParamSirtEntryOffset();
+    FrameOffset sirt_offset = jni_conv->CurrentParamSirtEntryOffset();
     // Check sirt offset is within frame
     CHECK_LT(sirt_offset.Uint32Value(), frame_size);
-    jni_asm->LoadRef(jni_conv.InterproceduralScratchRegister(),
-                     mr_conv.MethodRegister(), Method::DeclaringClassOffset());
-    jni_asm->VerifyObject(jni_conv.InterproceduralScratchRegister(), false);
-    jni_asm->StoreRef(sirt_offset, jni_conv.InterproceduralScratchRegister());
-    jni_conv.Next();  // in SIRT so move to next argument
+    __ LoadRef(jni_conv->InterproceduralScratchRegister(),
+               mr_conv->MethodRegister(), Method::DeclaringClassOffset());
+    __ VerifyObject(jni_conv->InterproceduralScratchRegister(), false);
+    __ StoreRef(sirt_offset, jni_conv->InterproceduralScratchRegister());
+    jni_conv->Next();  // in SIRT so move to next argument
   }
-  while (mr_conv.HasNext()) {
-    CHECK(jni_conv.HasNext());
-    bool ref_param = jni_conv.IsCurrentParamAReference();
-    CHECK(!ref_param || mr_conv.IsCurrentParamAReference());
+  while (mr_conv->HasNext()) {
+    CHECK(jni_conv->HasNext());
+    bool ref_param = jni_conv->IsCurrentParamAReference();
+    CHECK(!ref_param || mr_conv->IsCurrentParamAReference());
     // References need placing in SIRT and the entry value passing
     if (ref_param) {
       // Compute SIRT entry, note null is placed in the SIRT but its boxed value
       // must be NULL
-      FrameOffset sirt_offset = jni_conv.CurrentParamSirtEntryOffset();
+      FrameOffset sirt_offset = jni_conv->CurrentParamSirtEntryOffset();
       // Check SIRT offset is within frame
       CHECK_LT(sirt_offset.Uint32Value(), frame_size);
-      bool input_in_reg = mr_conv.IsCurrentParamInRegister();
-      bool input_on_stack = mr_conv.IsCurrentParamOnStack();
+      bool input_in_reg = mr_conv->IsCurrentParamInRegister();
+      bool input_on_stack = mr_conv->IsCurrentParamOnStack();
       CHECK(input_in_reg || input_on_stack);
 
       if (input_in_reg) {
-        ManagedRegister in_reg  =  mr_conv.CurrentParamRegister();
-        jni_asm->VerifyObject(in_reg, mr_conv.IsCurrentArgPossiblyNull());
-        jni_asm->StoreRef(sirt_offset, in_reg);
+        ManagedRegister in_reg  =  mr_conv->CurrentParamRegister();
+        __ VerifyObject(in_reg, mr_conv->IsCurrentArgPossiblyNull());
+        __ StoreRef(sirt_offset, in_reg);
       } else if (input_on_stack) {
-        FrameOffset in_off  = mr_conv.CurrentParamStackOffset();
-        jni_asm->VerifyObject(in_off, mr_conv.IsCurrentArgPossiblyNull());
-        jni_asm->CopyRef(sirt_offset, in_off,
-                         mr_conv.InterproceduralScratchRegister());
+        FrameOffset in_off  = mr_conv->CurrentParamStackOffset();
+        __ VerifyObject(in_off, mr_conv->IsCurrentArgPossiblyNull());
+        __ CopyRef(sirt_offset, in_off,
+                   mr_conv->InterproceduralScratchRegister());
       }
     }
-    mr_conv.Next();
-    jni_conv.Next();
+    mr_conv->Next();
+    jni_conv->Next();
   }
 
   // 5. Transition from being in managed to native code
   // TODO: ensure the transition to native follow a store fence.
-  jni_asm->StoreStackPointerToThread(Thread::TopOfManagedStackOffset());
-  jni_asm->StoreImmediateToThread(Thread::StateOffset(), Thread::kNative,
-                                  mr_conv.InterproceduralScratchRegister());
+  __ StoreStackPointerToThread(Thread::TopOfManagedStackOffset());
+  __ StoreImmediateToThread(Thread::StateOffset(), Thread::kNative,
+                                  mr_conv->InterproceduralScratchRegister());
 
   // 6. Move frame down to allow space for out going args. Do for as short a
   //    time as possible to aid profiling..
-  const size_t out_arg_size = jni_conv.OutArgSize();
-  jni_asm->IncreaseFrameSize(out_arg_size);
+  const size_t out_arg_size = jni_conv->OutArgSize();
+  __ IncreaseFrameSize(out_arg_size);
 
   // 7. Acquire lock for synchronized methods.
   if (native_method->IsSynchronized()) {
     // TODO: preserve incoming arguments in registers
-    mr_conv.ResetIterator(FrameOffset(frame_size+out_arg_size));
-    jni_conv.ResetIterator(FrameOffset(out_arg_size));
-    jni_conv.Next();  // Skip JNIEnv*
+    mr_conv->ResetIterator(FrameOffset(frame_size+out_arg_size));
+    jni_conv->ResetIterator(FrameOffset(out_arg_size));
+    jni_conv->Next();  // Skip JNIEnv*
     // Get SIRT entry for 1st argument
     if (is_static) {
-      FrameOffset sirt_offset = jni_conv.CurrentParamSirtEntryOffset();
-      if (jni_conv.IsCurrentParamOnStack()) {
-        FrameOffset out_off = jni_conv.CurrentParamStackOffset();
-        jni_asm->CreateSirtEntry(out_off, sirt_offset,
-                                 mr_conv.InterproceduralScratchRegister(),
-                                 false);
+      FrameOffset sirt_offset = jni_conv->CurrentParamSirtEntryOffset();
+      if (jni_conv->IsCurrentParamOnStack()) {
+        FrameOffset out_off = jni_conv->CurrentParamStackOffset();
+        __ CreateSirtEntry(out_off, sirt_offset,
+                           mr_conv->InterproceduralScratchRegister(),
+                           false);
       } else {
-        ManagedRegister out_reg = jni_conv.CurrentParamRegister();
-        jni_asm->CreateSirtEntry(out_reg, sirt_offset,
-                                 ManagedRegister::NoRegister(), false);
+        ManagedRegister out_reg = jni_conv->CurrentParamRegister();
+        __ CreateSirtEntry(out_reg, sirt_offset,
+                           ManagedRegister::NoRegister(), false);
       }
     } else {
-      CopyParameter(jni_asm, &mr_conv, &jni_conv, frame_size, out_arg_size);
+      CopyParameter(jni_asm.get(), mr_conv.get(), jni_conv.get(), frame_size,
+                    out_arg_size);
     }
     // Generate JNIEnv* in place and leave a copy in jni_fns_register
-    jni_conv.ResetIterator(FrameOffset(out_arg_size));
+    jni_conv->ResetIterator(FrameOffset(out_arg_size));
     ManagedRegister jni_fns_register =
-        jni_conv.InterproceduralScratchRegister();
-    jni_asm->LoadRawPtrFromThread(jni_fns_register, Thread::JniEnvOffset());
-    SetNativeParameter(jni_asm, &jni_conv, jni_fns_register);
+        jni_conv->InterproceduralScratchRegister();
+    __ LoadRawPtrFromThread(jni_fns_register, Thread::JniEnvOffset());
+    SetNativeParameter(jni_asm.get(), jni_conv.get(), jni_fns_register);
     // Call JNIEnv->MonitorEnter(object)
-    jni_asm->LoadRawPtr(jni_fns_register, jni_fns_register, functions);
-    jni_asm->Call(jni_fns_register, monitor_enter,
-                  jni_conv.InterproceduralScratchRegister());
-    jni_asm->FillFromSpillArea(spill_regs, out_arg_size);
-    jni_asm->ExceptionPoll(jni_conv.InterproceduralScratchRegister());
+    __ LoadRawPtr(jni_fns_register, jni_fns_register, functions);
+    __ Call(jni_fns_register, monitor_enter,
+                  jni_conv->InterproceduralScratchRegister());
+    __ FillFromSpillArea(spill_regs, out_arg_size);
+    __ ExceptionPoll(jni_conv->InterproceduralScratchRegister());
   }
 
   // 8. Iterate over arguments placing values from managed calling convention in
@@ -152,192 +180,198 @@
   //    NULL (which must be encoded as NULL).
   //    NB. we do this prior to materializing the JNIEnv* and static's jclass to
   //    give as many free registers for the shuffle as possible
-  mr_conv.ResetIterator(FrameOffset(frame_size+out_arg_size));
+  mr_conv->ResetIterator(FrameOffset(frame_size+out_arg_size));
   uint32_t args_count = 0;
-  while (mr_conv.HasNext()) {
+  while (mr_conv->HasNext()) {
     args_count++;
-    mr_conv.Next();
+    mr_conv->Next();
   }
 
   // Do a backward pass over arguments, so that the generated code will be "mov
   // R2, R3; mov R1, R2" instead of "mov R1, R2; mov R2, R3."
   // TODO: A reverse iterator to improve readability.
   for (uint32_t i = 0; i < args_count; ++i) {
-    mr_conv.ResetIterator(FrameOffset(frame_size+out_arg_size));
-    jni_conv.ResetIterator(FrameOffset(out_arg_size));
-    jni_conv.Next();  // Skip JNIEnv*
+    mr_conv->ResetIterator(FrameOffset(frame_size + out_arg_size));
+    jni_conv->ResetIterator(FrameOffset(out_arg_size));
+    jni_conv->Next();  // Skip JNIEnv*
     if (is_static) {
-      jni_conv.Next();  // Skip Class for now
+      jni_conv->Next();  // Skip Class for now
     }
     for (uint32_t j = 0; j < args_count - i - 1; ++j) {
-      mr_conv.Next();
-      jni_conv.Next();
+      mr_conv->Next();
+      jni_conv->Next();
     }
-    CopyParameter(jni_asm, &mr_conv, &jni_conv, frame_size, out_arg_size);
+    CopyParameter(jni_asm.get(), mr_conv.get(), jni_conv.get(), frame_size,
+                  out_arg_size);
   }
 
   if (is_static) {
     // Create argument for Class
-    mr_conv.ResetIterator(FrameOffset(frame_size+out_arg_size));
-    jni_conv.ResetIterator(FrameOffset(out_arg_size));
-    jni_conv.Next();  // Skip JNIEnv*
-    FrameOffset sirt_offset = jni_conv.CurrentParamSirtEntryOffset();
-    if (jni_conv.IsCurrentParamOnStack()) {
-      FrameOffset out_off = jni_conv.CurrentParamStackOffset();
-      jni_asm->CreateSirtEntry(out_off, sirt_offset,
-                               mr_conv.InterproceduralScratchRegister(),
-                               false);
+    mr_conv->ResetIterator(FrameOffset(frame_size+out_arg_size));
+    jni_conv->ResetIterator(FrameOffset(out_arg_size));
+    jni_conv->Next();  // Skip JNIEnv*
+    FrameOffset sirt_offset = jni_conv->CurrentParamSirtEntryOffset();
+    if (jni_conv->IsCurrentParamOnStack()) {
+      FrameOffset out_off = jni_conv->CurrentParamStackOffset();
+      __ CreateSirtEntry(out_off, sirt_offset,
+                         mr_conv->InterproceduralScratchRegister(),
+                         false);
     } else {
-      ManagedRegister out_reg = jni_conv.CurrentParamRegister();
-      jni_asm->CreateSirtEntry(out_reg, sirt_offset,
-                               ManagedRegister::NoRegister(), false);
+      ManagedRegister out_reg = jni_conv->CurrentParamRegister();
+      __ CreateSirtEntry(out_reg, sirt_offset,
+                         ManagedRegister::NoRegister(), false);
     }
   }
   // 9. Create 1st argument, the JNI environment ptr
-  jni_conv.ResetIterator(FrameOffset(out_arg_size));
-  if (jni_conv.IsCurrentParamInRegister()) {
-    jni_asm->LoadRawPtrFromThread(jni_conv.CurrentParamRegister(),
-                                  Thread::JniEnvOffset());
+  jni_conv->ResetIterator(FrameOffset(out_arg_size));
+  if (jni_conv->IsCurrentParamInRegister()) {
+    __ LoadRawPtrFromThread(jni_conv->CurrentParamRegister(),
+                            Thread::JniEnvOffset());
   } else {
-    jni_asm->CopyRawPtrFromThread(jni_conv.CurrentParamStackOffset(),
-                                  Thread::JniEnvOffset(),
-                                  jni_conv.InterproceduralScratchRegister());
+    __ CopyRawPtrFromThread(jni_conv->CurrentParamStackOffset(),
+                            Thread::JniEnvOffset(),
+                            jni_conv->InterproceduralScratchRegister());
   }
 
   // 10. Plant call to native code associated with method
-  if (!jni_conv.IsOutArgRegister(mr_conv.MethodRegister())) {
+  if (!jni_conv->IsOutArgRegister(mr_conv->MethodRegister())) {
     // Method register shouldn't have been crushed by setting up outgoing
     // arguments
-    jni_asm->Call(mr_conv.MethodRegister(), Method::NativeMethodOffset(),
-                  mr_conv.InterproceduralScratchRegister());
+    __ Call(mr_conv->MethodRegister(), Method::NativeMethodOffset(),
+            mr_conv->InterproceduralScratchRegister());
   } else {
-    jni_asm->Call(jni_conv.MethodStackOffset(), Method::NativeMethodOffset(),
-                  mr_conv.InterproceduralScratchRegister());
+    __ Call(jni_conv->MethodStackOffset(), Method::NativeMethodOffset(),
+            mr_conv->InterproceduralScratchRegister());
   }
   // 11. Release lock for synchronized methods.
   if (native_method->IsSynchronized()) {
-    mr_conv.ResetIterator(FrameOffset(frame_size+out_arg_size));
-    jni_conv.ResetIterator(FrameOffset(out_arg_size));
-    jni_conv.Next();  // Skip JNIEnv*
+    mr_conv->ResetIterator(FrameOffset(frame_size+out_arg_size));
+    jni_conv->ResetIterator(FrameOffset(out_arg_size));
+    jni_conv->Next();  // Skip JNIEnv*
     // Save return value
-    FrameOffset return_save_location = jni_conv.ReturnValueSaveLocation();
-    if (jni_conv.SizeOfReturnValue() != 0) {
-      FrameOffset return_save_location = jni_conv.ReturnValueSaveLocation();
+    FrameOffset return_save_location = jni_conv->ReturnValueSaveLocation();
+    if (jni_conv->SizeOfReturnValue() != 0) {
+      FrameOffset return_save_location = jni_conv->ReturnValueSaveLocation();
       CHECK_LT(return_save_location.Uint32Value(), frame_size+out_arg_size);
-      jni_asm->Store(return_save_location, jni_conv.ReturnRegister(),
-                     jni_conv.SizeOfReturnValue());
+      __ Store(return_save_location, jni_conv->ReturnRegister(),
+               jni_conv->SizeOfReturnValue());
     }
     // Get SIRT entry for 1st argument
     if (is_static) {
-      FrameOffset sirt_offset = jni_conv.CurrentParamSirtEntryOffset();
-      if (jni_conv.IsCurrentParamOnStack()) {
-        FrameOffset out_off = jni_conv.CurrentParamStackOffset();
-        jni_asm->CreateSirtEntry(out_off, sirt_offset,
-                                 mr_conv.InterproceduralScratchRegister(),
-                                 false);
+      FrameOffset sirt_offset = jni_conv->CurrentParamSirtEntryOffset();
+      if (jni_conv->IsCurrentParamOnStack()) {
+        FrameOffset out_off = jni_conv->CurrentParamStackOffset();
+        __ CreateSirtEntry(out_off, sirt_offset,
+                           mr_conv->InterproceduralScratchRegister(),
+                           false);
       } else {
-        ManagedRegister out_reg = jni_conv.CurrentParamRegister();
-        jni_asm->CreateSirtEntry(out_reg, sirt_offset,
-                                 ManagedRegister::NoRegister(), false);
+        ManagedRegister out_reg = jni_conv->CurrentParamRegister();
+        __ CreateSirtEntry(out_reg, sirt_offset,
+                           ManagedRegister::NoRegister(), false);
       }
     } else {
-      CopyParameter(jni_asm, &mr_conv, &jni_conv, frame_size, out_arg_size);
+      CopyParameter(jni_asm.get(), mr_conv.get(), jni_conv.get(), frame_size,
+                    out_arg_size);
     }
     // Generate JNIEnv* in place and leave a copy in jni_env_register
-    jni_conv.ResetIterator(FrameOffset(out_arg_size));
+    jni_conv->ResetIterator(FrameOffset(out_arg_size));
     ManagedRegister jni_env_register =
-        jni_conv.InterproceduralScratchRegister();
-    jni_asm->LoadRawPtrFromThread(jni_env_register, Thread::JniEnvOffset());
-    SetNativeParameter(jni_asm, &jni_conv, jni_env_register);
+        jni_conv->InterproceduralScratchRegister();
+    __ LoadRawPtrFromThread(jni_env_register, Thread::JniEnvOffset());
+    SetNativeParameter(jni_asm.get(), jni_conv.get(), jni_env_register);
     // Call JNIEnv->MonitorExit(object)
-    jni_asm->LoadRawPtr(jni_env_register, jni_env_register, functions);
-    jni_asm->Call(jni_env_register, monitor_exit,
-                  jni_conv.InterproceduralScratchRegister());
+    __ LoadRawPtr(jni_env_register, jni_env_register, functions);
+    __ Call(jni_env_register, monitor_exit,
+            jni_conv->InterproceduralScratchRegister());
     // Reload return value
-    if (jni_conv.SizeOfReturnValue() != 0) {
-      jni_asm->Load(jni_conv.ReturnRegister(), return_save_location,
-                    jni_conv.SizeOfReturnValue());
+    if (jni_conv->SizeOfReturnValue() != 0) {
+      __ Load(jni_conv->ReturnRegister(), return_save_location,
+              jni_conv->SizeOfReturnValue());
     }
   }
 
   // 12. Release outgoing argument area
-  jni_asm->DecreaseFrameSize(out_arg_size);
-  mr_conv.ResetIterator(FrameOffset(frame_size));
-  jni_conv.ResetIterator(FrameOffset(0));
+  __ DecreaseFrameSize(out_arg_size);
+  mr_conv->ResetIterator(FrameOffset(frame_size));
+  jni_conv->ResetIterator(FrameOffset(0));
 
   // 13. Transition from being in native to managed code, possibly entering a
   //     safepoint
-  CHECK(!jni_conv.InterproceduralScratchRegister()
-                 .Equals(jni_conv.ReturnRegister()));  // don't clobber result
+  CHECK(!jni_conv->InterproceduralScratchRegister()
+        .Equals(jni_conv->ReturnRegister()));  // don't clobber result
   // Location to preserve result on slow path, ensuring its within the frame
-  FrameOffset return_save_location = jni_conv.ReturnValueSaveLocation();
+  FrameOffset return_save_location = jni_conv->ReturnValueSaveLocation();
   CHECK(return_save_location.Uint32Value() < frame_size ||
-        jni_conv.SizeOfReturnValue() == 0);
-  jni_asm->SuspendPoll(jni_conv.InterproceduralScratchRegister(),
-                       jni_conv.ReturnRegister(), return_save_location,
-                       jni_conv.SizeOfReturnValue());
-  jni_asm->ExceptionPoll(jni_conv.InterproceduralScratchRegister());
-  jni_asm->StoreImmediateToThread(Thread::StateOffset(), Thread::kRunnable,
-                                  jni_conv.InterproceduralScratchRegister());
+        jni_conv->SizeOfReturnValue() == 0);
+  __ SuspendPoll(jni_conv->InterproceduralScratchRegister(),
+                 jni_conv->ReturnRegister(), return_save_location,
+                 jni_conv->SizeOfReturnValue());
+  __ ExceptionPoll(jni_conv->InterproceduralScratchRegister());
+  __ StoreImmediateToThread(Thread::StateOffset(), Thread::kRunnable,
+                            jni_conv->InterproceduralScratchRegister());
 
 
   // 14. Place result in correct register possibly loading from indirect
   //     reference table
-  if (jni_conv.IsReturnAReference()) {
-    jni_asm->IncreaseFrameSize(out_arg_size);
-    jni_conv.ResetIterator(FrameOffset(out_arg_size));
+  if (jni_conv->IsReturnAReference()) {
+    __ IncreaseFrameSize(out_arg_size);
+    jni_conv->ResetIterator(FrameOffset(out_arg_size));
 
-    jni_conv.Next();  // Skip Thread* argument
+    jni_conv->Next();  // Skip Thread* argument
     // Pass result as arg2
-    SetNativeParameter(jni_asm, &jni_conv, jni_conv.ReturnRegister());
+    SetNativeParameter(jni_asm.get(), jni_conv.get(),
+                       jni_conv->ReturnRegister());
 
     // Pass Thread*
-    jni_conv.ResetIterator(FrameOffset(out_arg_size));
-    if (jni_conv.IsCurrentParamInRegister()) {
-      jni_asm->GetCurrentThread(jni_conv.CurrentParamRegister());
+    jni_conv->ResetIterator(FrameOffset(out_arg_size));
+    if (jni_conv->IsCurrentParamInRegister()) {
+      __ GetCurrentThread(jni_conv->CurrentParamRegister());
     } else {
-      jni_asm->GetCurrentThread(jni_conv.CurrentParamStackOffset(),
-                                jni_conv.InterproceduralScratchRegister());
+      __ GetCurrentThread(jni_conv->CurrentParamStackOffset(),
+                          jni_conv->InterproceduralScratchRegister());
     }
 
-    jni_asm->Call(reinterpret_cast<uintptr_t>(DecodeJObjectInThread),
-                  jni_conv.InterproceduralScratchRegister());
+    __ Call(reinterpret_cast<uintptr_t>(DecodeJObjectInThread),
+            jni_conv->InterproceduralScratchRegister());
 
-    jni_asm->DecreaseFrameSize(out_arg_size);
-    jni_conv.ResetIterator(FrameOffset(0));
+    __ DecreaseFrameSize(out_arg_size);
+    jni_conv->ResetIterator(FrameOffset(0));
   }
-  jni_asm->Move(mr_conv.ReturnRegister(), jni_conv.ReturnRegister());
+  __ Move(mr_conv->ReturnRegister(), jni_conv->ReturnRegister());
 
   // 15. Remove SIRT from thread
-  jni_asm->CopyRawPtrToThread(Thread::TopSirtOffset(), jni_conv.SirtLinkOffset(),
-                              jni_conv.InterproceduralScratchRegister());
+  __ CopyRawPtrToThread(Thread::TopSirtOffset(), jni_conv->SirtLinkOffset(),
+                        jni_conv->InterproceduralScratchRegister());
 
   // 16. Remove activation
-  jni_asm->RemoveFrame(frame_size, spill_regs);
+  __ RemoveFrame(frame_size, spill_regs);
 
   // 17. Finalize code generation
-  jni_asm->EmitSlowPaths();
-  size_t cs = jni_asm->CodeSize();
+  __ EmitSlowPaths();
+  size_t cs = __ CodeSize();
   ByteArray* managed_code = ByteArray::Alloc(cs);
   CHECK(managed_code != NULL);
   MemoryRegion code(managed_code->GetData(), managed_code->GetLength());
-  jni_asm->FinalizeInstructions(code);
-  native_method->SetCode(managed_code, jni_asm->GetInstructionSet());
+  __ FinalizeInstructions(code);
+  native_method->SetCode(managed_code, instruction_set_);
   native_method->SetFrameSizeInBytes(frame_size);
-  native_method->SetReturnPcOffsetInBytes(jni_conv.ReturnPcOffset());
+  native_method->SetReturnPcOffsetInBytes(jni_conv->ReturnPcOffset());
+#undef __
 }
 
-void JniCompiler::SetNativeParameter(Assembler *jni_asm,
-                                     JniCallingConvention *jni_conv,
+void JniCompiler::SetNativeParameter(Assembler* jni_asm,
+                                     JniCallingConvention* jni_conv,
                                      ManagedRegister in_reg) {
+#define __ jni_asm->
   if (jni_conv->IsCurrentParamOnStack()) {
     FrameOffset dest = jni_conv->CurrentParamStackOffset();
-    jni_asm->StoreRawPtr(dest, in_reg);
+    __ StoreRawPtr(dest, in_reg);
   } else {
     if (!jni_conv->CurrentParamRegister().Equals(in_reg)) {
-      jni_asm->Move(jni_conv->CurrentParamRegister(), in_reg);
+      __ Move(jni_conv->CurrentParamRegister(), in_reg);
     }
   }
+#undef __
 }
 
 // Copy a single parameter from the managed to the JNI calling convention
@@ -345,6 +379,7 @@
                                 ManagedRuntimeCallingConvention* mr_conv,
                                 JniCallingConvention* jni_conv,
                                 size_t frame_size, size_t out_arg_size) {
+
   bool input_in_reg = mr_conv->IsCurrentParamInRegister();
   bool output_in_reg = jni_conv->IsCurrentParamInRegister();
   FrameOffset sirt_offset(0);
@@ -368,15 +403,16 @@
     // Check SIRT offset is within frame.
     CHECK_LT(sirt_offset.Uint32Value(), (frame_size+out_arg_size));
   }
+#define __ jni_asm->
   if (input_in_reg && output_in_reg) {
     ManagedRegister in_reg = mr_conv->CurrentParamRegister();
     ManagedRegister out_reg = jni_conv->CurrentParamRegister();
     if (ref_param) {
-      jni_asm->CreateSirtEntry(out_reg, sirt_offset, in_reg, null_allowed);
+      __ CreateSirtEntry(out_reg, sirt_offset, in_reg, null_allowed);
     } else {
       if (!mr_conv->IsCurrentParamOnStack()) {
         // regular non-straddling move
-        jni_asm->Move(out_reg, in_reg);
+        __ Move(out_reg, in_reg);
       } else {
         UNIMPLEMENTED(FATAL);  // we currently don't expect to see this case
       }
@@ -384,15 +420,15 @@
   } else if (!input_in_reg && !output_in_reg) {
     FrameOffset out_off = jni_conv->CurrentParamStackOffset();
     if (ref_param) {
-      jni_asm->CreateSirtEntry(out_off, sirt_offset,
-                               mr_conv->InterproceduralScratchRegister(),
-                               null_allowed);
+      __ CreateSirtEntry(out_off, sirt_offset,
+                         mr_conv->InterproceduralScratchRegister(),
+                         null_allowed);
     } else {
       FrameOffset in_off = mr_conv->CurrentParamStackOffset();
       size_t param_size = mr_conv->CurrentParamSize();
       CHECK_EQ(param_size, jni_conv->CurrentParamSize());
-      jni_asm->Copy(out_off, in_off, mr_conv->InterproceduralScratchRegister(),
-                    param_size);
+      __ Copy(out_off, in_off, mr_conv->InterproceduralScratchRegister(),
+              param_size);
     }
   } else if (!input_in_reg && output_in_reg) {
     FrameOffset in_off = mr_conv->CurrentParamStackOffset();
@@ -400,12 +436,12 @@
     // Check that incoming stack arguments are above the current stack frame.
     CHECK_GT(in_off.Uint32Value(), frame_size);
     if (ref_param) {
-      jni_asm->CreateSirtEntry(out_reg, sirt_offset,
-                               ManagedRegister::NoRegister(), null_allowed);
+      __ CreateSirtEntry(out_reg, sirt_offset,
+                         ManagedRegister::NoRegister(), null_allowed);
     } else {
       unsigned int param_size = mr_conv->CurrentParamSize();
       CHECK_EQ(param_size, jni_conv->CurrentParamSize());
-      jni_asm->Load(out_reg, in_off, param_size);
+      __ Load(out_reg, in_off, param_size);
     }
   } else {
     CHECK(input_in_reg && !output_in_reg);
@@ -415,28 +451,25 @@
     CHECK_LT(out_off.Uint32Value(), frame_size);
     if (ref_param) {
       // TODO: recycle value in in_reg rather than reload from SIRT
-      jni_asm->CreateSirtEntry(out_off, sirt_offset,
-                               mr_conv->InterproceduralScratchRegister(),
-                               null_allowed);
+      __ CreateSirtEntry(out_off, sirt_offset,
+                         mr_conv->InterproceduralScratchRegister(),
+                         null_allowed);
     } else {
       size_t param_size = mr_conv->CurrentParamSize();
       CHECK_EQ(param_size, jni_conv->CurrentParamSize());
       if (!mr_conv->IsCurrentParamOnStack()) {
         // regular non-straddling store
-        jni_asm->Store(out_off, in_reg, param_size);
+        __ Store(out_off, in_reg, param_size);
       } else {
         // store where input straddles registers and stack
         CHECK_EQ(param_size, 8u);
         FrameOffset in_off = mr_conv->CurrentParamStackOffset();
-        jni_asm->StoreSpanning(out_off, in_reg, in_off,
-                               mr_conv->InterproceduralScratchRegister());
+        __ StoreSpanning(out_off, in_reg, in_off,
+                         mr_conv->InterproceduralScratchRegister());
       }
     }
   }
+#undef __
 }
 
-JniCompiler::JniCompiler() {}
-
-JniCompiler::~JniCompiler() {}
-
 }  // namespace art
diff --git a/src/jni_compiler.h b/src/jni_compiler.h
index ece0dea..ec2e23c 100644
--- a/src/jni_compiler.h
+++ b/src/jni_compiler.h
@@ -3,15 +3,15 @@
 #ifndef ART_SRC_JNI_COMPILER_H_
 #define ART_SRC_JNI_COMPILER_H_
 
-#include "UniquePtr.h"
-#include "calling_convention.h"
-#include "globals.h"
+#include "constants.h"
 #include "macros.h"
-#include "mem_map.h"
 
 namespace art {
 
 class Assembler;
+class JniCallingConvention;
+class ManagedRegister;
+class ManagedRuntimeCallingConvention;
 class Method;
 
 // A JNI compiler generates code that acts as the bridge between managed code
@@ -19,9 +19,10 @@
 // TODO: move the responsibility of managing memory to somewhere else
 class JniCompiler {
  public:
-  JniCompiler();
+  explicit JniCompiler(InstructionSet insns);
   ~JniCompiler();
-  void Compile(Assembler* jni_asm, Method* method);
+
+  void Compile(Method* method);
 
  private:
   // Copy a single parameter from the managed to the JNI calling convention
@@ -30,10 +31,12 @@
                      JniCallingConvention* jni_conv,
                      size_t frame_size, size_t out_arg_size);
 
-  void SetNativeParameter(Assembler *jni_asm,
-                          JniCallingConvention *jni_conv,
+  void SetNativeParameter(Assembler* jni_asm,
+                          JniCallingConvention* jni_conv,
                           ManagedRegister in_reg);
 
+  InstructionSet instruction_set_;
+
   DISALLOW_COPY_AND_ASSIGN(JniCompiler);
 };
 
diff --git a/src/jni_compiler_test.cc b/src/jni_compiler_test.cc
index 026c826..59a0423 100644
--- a/src/jni_compiler_test.cc
+++ b/src/jni_compiler_test.cc
@@ -65,8 +65,6 @@
   static jobject jobj_;
  protected:
   const ClassLoader* class_loader_;
-  Assembler jni_asm_;
-  JniCompiler jni_compiler_;
   JNIEnv* env_;
   jmethodID jmethod_;
 };
diff --git a/src/jni_internal_arm.cc b/src/jni_internal_arm.cc
index 99b4dc3..ed42c12 100644
--- a/src/jni_internal_arm.cc
+++ b/src/jni_internal_arm.cc
@@ -7,9 +7,8 @@
 #include "assembler.h"
 #include "object.h"
 
-#define __ assembler->
-
 namespace art {
+namespace arm {
 
 // Creates a function which invokes a managed method with an array of
 // arguments.
@@ -28,7 +27,10 @@
 // register and transfer arguments from the array into register and on
 // the stack, if needed.  On return, the thread register must be
 // shuffled and the return value must be store into the result JValue.
-void CreateInvokeStub(Assembler* assembler, Method* method) {
+void ArmCreateInvokeStub(Method* method) {
+  UniquePtr<ArmAssembler> assembler(
+      down_cast<ArmAssembler*>(Assembler::Create(kArm)));
+#define __ assembler->
   // Size of frame - spill of R9/LR + Method* + possible receiver + arg array
   size_t unpadded_frame_size = (3 * kPointerSize) +
                                (method->IsStatic() ? 0 : kPointerSize) +
@@ -115,6 +117,14 @@
 
   // Pop R9 and the LR into PC
   __ PopList(save | (1 << PC));
+  // TODO: store native_entry in the stub table
+  ByteArray* code = ByteArray::Alloc(assembler->CodeSize());
+  MemoryRegion region(code->GetData(), code->GetLength());
+  assembler->FinalizeInstructions(region);
+  method->SetInvokeStub(code);
+  CHECK(method->GetInvokeStub() != NULL);
+#undef __
 }
 
+}  // namespace arm
 }  // namespace art
diff --git a/src/jni_internal_x86.cc b/src/jni_internal_x86.cc
index 782ff66..a6917d4 100644
--- a/src/jni_internal_x86.cc
+++ b/src/jni_internal_x86.cc
@@ -6,9 +6,7 @@
 #include "object.h"
 
 namespace art {
-
-
-#define __ assembler->
+namespace x86 {
 
 // Creates a function which invokes a managed method with an array of
 // arguments.
@@ -26,7 +24,10 @@
 // "running" state the remaining responsibilities of this routine are
 // to save the native registers and set up the managed registers. On
 // return, the return value must be store into the result JValue.
-void CreateInvokeStub(Assembler* assembler, Method* method) {
+void X86CreateInvokeStub(Method* method) {
+  UniquePtr<X86Assembler> assembler(
+      down_cast<X86Assembler*>(Assembler::Create(kX86)));
+#define __ assembler->
   // Size of frame - spill of EDI + Method* + possible receiver + arg array
   size_t frame_size = (2 * kPointerSize) +
                       (method->IsStatic() ? 0 : kPointerSize) +
@@ -78,6 +79,14 @@
   }
   __ popl(EDI);  // restore EDI
   __ ret();
+  // TODO: store native_entry in the stub table
+  ByteArray* code = ByteArray::Alloc(assembler->CodeSize());
+  MemoryRegion region(code->GetData(), code->GetLength());
+  assembler->FinalizeInstructions(region);
+  method->SetInvokeStub(code);
+  CHECK(method->GetInvokeStub() != NULL);
+#undef __
 }
 
+}  // namespace x86
 }  // namespace art
diff --git a/src/managed_register.h b/src/managed_register.h
index 2540895..5aa96e4 100644
--- a/src/managed_register.h
+++ b/src/managed_register.h
@@ -3,12 +3,52 @@
 #ifndef ART_SRC_MANAGED_REGISTER_H_
 #define ART_SRC_MANAGED_REGISTER_H_
 
-#if defined(__i386__)
-#include "managed_register_x86.h"
-#elif defined(__arm__)
-#include "managed_register_arm.h"
-#else
-#error Unknown architecture.
-#endif
+namespace art {
+
+namespace x86 {
+class X86ManagedRegister;
+}
+namespace arm {
+class ArmManagedRegister;
+}
+
+class ManagedRegister {
+ public:
+  // ManagedRegister is a value class. There exists no method to change the
+  // internal state. We therefore allow a copy constructor and an
+  // assignment-operator.
+  ManagedRegister(const ManagedRegister& other) : id_(other.id_) { }
+
+  ManagedRegister& operator=(const ManagedRegister& other) {
+    id_ = other.id_;
+    return *this;
+  }
+
+  x86::X86ManagedRegister AsX86() const;
+  arm::ArmManagedRegister AsArm() const;
+
+  // It is valid to invoke Equals on and with a NoRegister.
+  bool Equals(const ManagedRegister& other) const {
+    return id_ == other.id_;
+  }
+
+  bool IsNoRegister() const {
+    return id_ == kNoRegister;
+  }
+
+  static ManagedRegister NoRegister() {
+    return ManagedRegister();
+  }
+
+ protected:
+  static const int kNoRegister = -1;
+
+  ManagedRegister() : id_(kNoRegister) { }
+  ManagedRegister(int reg_id) : id_(reg_id) { }
+
+  int id_;
+};
+
+}  // namespace art
 
 #endif  // ART_SRC_MANAGED_REGISTER_H_
diff --git a/src/managed_register_arm.cc b/src/managed_register_arm.cc
index 5973be1..984bb53 100644
--- a/src/managed_register_arm.cc
+++ b/src/managed_register_arm.cc
@@ -1,10 +1,12 @@
 // Copyright 2011 Google Inc. All Rights Reserved.
 
+#include "managed_register_arm.h"
+
 #include "globals.h"
 #include "calling_convention.h"
-#include "managed_register.h"
 
 namespace art {
+namespace arm {
 
 // We need all registers for caching of locals.
 // Register R9 .. R15 are reserved.
@@ -17,14 +19,14 @@
 
 
 // Returns true if this managed-register overlaps the other managed-register.
-bool ManagedRegister::Overlaps(const ManagedRegister& other) const {
+bool ArmManagedRegister::Overlaps(const ArmManagedRegister& other) const {
   if (IsNoRegister() || other.IsNoRegister()) return false;
   if (Equals(other)) return true;
   if (IsRegisterPair()) {
     Register low = AsRegisterPairLow();
     Register high = AsRegisterPairHigh();
-    return ManagedRegister::FromCoreRegister(low).Overlaps(other) ||
-        ManagedRegister::FromCoreRegister(high).Overlaps(other);
+    return ArmManagedRegister::FromCoreRegister(low).Overlaps(other) ||
+        ArmManagedRegister::FromCoreRegister(high).Overlaps(other);
   }
   if (IsOverlappingDRegister()) {
     if (other.IsDRegister()) return Equals(other);
@@ -43,7 +45,7 @@
 }
 
 
-int ManagedRegister::AllocIdLow() const {
+int ArmManagedRegister::AllocIdLow() const {
   CHECK(IsOverlappingDRegister() || IsRegisterPair());
   const int r = RegId() - (kNumberOfCoreRegIds + kNumberOfSRegIds);
   int low;
@@ -62,12 +64,12 @@
 }
 
 
-int ManagedRegister::AllocIdHigh() const {
+int ArmManagedRegister::AllocIdHigh() const {
   return AllocIdLow() + 1;
 }
 
 
-void ManagedRegister::Print(std::ostream& os) const {
+void ArmManagedRegister::Print(std::ostream& os) const {
   if (!IsValidManagedRegister()) {
     os << "No Register";
   } else if (IsCoreRegister()) {
@@ -84,14 +86,15 @@
   }
 }
 
-std::ostream& operator<<(std::ostream& os, const ManagedRegister& reg) {
+std::ostream& operator<<(std::ostream& os, const ArmManagedRegister& reg) {
   reg.Print(os);
   return os;
 }
 
 std::ostream& operator<<(std::ostream& os, const RegisterPair& r) {
-  os << ManagedRegister::FromRegisterPair(r);
+  os << ArmManagedRegister::FromRegisterPair(r);
   return os;
 }
 
+}  // namespace arm
 }  // namespace art
diff --git a/src/managed_register_arm.h b/src/managed_register_arm.h
index 93cbc1b..f25b2f4 100644
--- a/src/managed_register_arm.h
+++ b/src/managed_register_arm.h
@@ -5,8 +5,10 @@
 
 #include "constants.h"
 #include "logging.h"
+#include "managed_register.h"
 
 namespace art {
+namespace arm {
 
 // Values for register pairs.
 enum RegisterPair {
@@ -66,18 +68,8 @@
 // (enum SRegister), or a VFP double precision register (enum DRegister).
 // 'ManagedRegister::NoRegister()' returns an invalid ManagedRegister.
 // There is a one-to-one mapping between ManagedRegister and register id.
-class ManagedRegister {
+class ArmManagedRegister : public ManagedRegister {
  public:
-  // ManagedRegister is a value class. There exists no method to change the
-  // internal state. We therefore allow a copy constructor and an
-  // assignment-operator.
-  ManagedRegister(const ManagedRegister& other) : id_(other.id_) { }
-
-  ManagedRegister& operator=(const ManagedRegister& other) {
-    id_ = other.id_;
-    return *this;
-  }
-
   Register AsCoreRegister() const {
     CHECK(IsCoreRegister());
     return static_cast<Register>(id_);
@@ -158,7 +150,7 @@
     return (0 <= test) && (test < kNumberOfPairRegIds);
   }
 
-  bool IsSameType(ManagedRegister test) const {
+  bool IsSameType(ArmManagedRegister test) const {
     CHECK(IsValidManagedRegister() && test.IsValidManagedRegister());
     return
       (IsCoreRegister() && test.IsCoreRegister()) ||
@@ -167,49 +159,37 @@
       (IsRegisterPair() && test.IsRegisterPair());
   }
 
-  bool IsNoRegister() const {
-    return id_ == kNoRegister;
-  }
-
-  // It is valid to invoke Equals on and with a NoRegister.
-  bool Equals(const ManagedRegister& other) const {
-    return id_ == other.id_;
-  }
 
   // Returns true if the two managed-registers ('this' and 'other') overlap.
   // Either managed-register may be the NoRegister. If both are the NoRegister
   // then false is returned.
-  bool Overlaps(const ManagedRegister& other) const;
+  bool Overlaps(const ArmManagedRegister& other) const;
 
   void Print(std::ostream& os) const;
 
-  static ManagedRegister NoRegister() {
-    return ManagedRegister();
-  }
-
-  static ManagedRegister FromCoreRegister(Register r) {
+  static ArmManagedRegister FromCoreRegister(Register r) {
     CHECK_NE(r, kNoRegister);
     return FromRegId(r);
   }
 
-  static ManagedRegister FromSRegister(SRegister r) {
+  static ArmManagedRegister FromSRegister(SRegister r) {
     CHECK_NE(r, kNoSRegister);
     return FromRegId(r + kNumberOfCoreRegIds);
   }
 
-  static ManagedRegister FromDRegister(DRegister r) {
+  static ArmManagedRegister FromDRegister(DRegister r) {
     CHECK_NE(r, kNoDRegister);
     return FromRegId(r + (kNumberOfCoreRegIds + kNumberOfSRegIds));
   }
 
-  static ManagedRegister FromRegisterPair(RegisterPair r) {
+  static ArmManagedRegister FromRegisterPair(RegisterPair r) {
     CHECK_NE(r, kNoRegisterPair);
     return FromRegId(r + (kNumberOfCoreRegIds +
                           kNumberOfSRegIds + kNumberOfDRegIds));
   }
 
   // Return a RegisterPair consisting of Register r_low and r_low + 1.
-  static ManagedRegister FromCoreRegisterPair(Register r_low) {
+  static ArmManagedRegister FromCoreRegisterPair(Register r_low) {
     if (r_low != R1) {  // not the dalvik special case
       CHECK_NE(r_low, kNoRegister);
       CHECK_EQ(0, (r_low % 2));
@@ -222,7 +202,7 @@
   }
 
   // Return a DRegister overlapping SRegister r_low and r_low + 1.
-  static ManagedRegister FromSRegisterPair(SRegister r_low) {
+  static ArmManagedRegister FromSRegisterPair(SRegister r_low) {
     CHECK_NE(r_low, kNoSRegister);
     CHECK_EQ(0, (r_low % 2));
     const int r = r_low / 2;
@@ -231,10 +211,6 @@
   }
 
  private:
-  static const int kNoRegister = -1;
-
-  ManagedRegister() : id_(kNoRegister) { }
-
   bool IsValidManagedRegister() const {
     return (0 <= id_) && (id_ < kNumberOfRegIds);
   }
@@ -258,17 +234,26 @@
   int AllocIdLow() const;
   int AllocIdHigh() const;
 
-  static ManagedRegister FromRegId(int reg_id) {
-    ManagedRegister reg;
-    reg.id_ = reg_id;
+  friend class ManagedRegister;
+
+  ArmManagedRegister(int reg_id) : ManagedRegister(reg_id) {}
+
+  static ArmManagedRegister FromRegId(int reg_id) {
+    ArmManagedRegister reg(reg_id);
     CHECK(reg.IsValidManagedRegister());
     return reg;
   }
-
-  int id_;
 };
 
-std::ostream& operator<<(std::ostream& os, const ManagedRegister& reg);
+std::ostream& operator<<(std::ostream& os, const ArmManagedRegister& reg);
+
+}  // namespace arm
+
+inline arm::ArmManagedRegister ManagedRegister::AsArm() const {
+  arm::ArmManagedRegister reg(id_);
+  CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister());
+  return reg;
+}
 
 }  // namespace art
 
diff --git a/src/managed_register_arm_test.cc b/src/managed_register_arm_test.cc
index 66c7811..6a8d043 100644
--- a/src/managed_register_arm_test.cc
+++ b/src/managed_register_arm_test.cc
@@ -5,15 +5,16 @@
 #include "gtest/gtest.h"
 
 namespace art {
+namespace arm {
 
-TEST(ManagedRegister, NoRegister) {
-  ManagedRegister reg = ManagedRegister::NoRegister();
+TEST(ArmManagedRegister, NoRegister) {
+  ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm();
   EXPECT_TRUE(reg.IsNoRegister());
   EXPECT_TRUE(!reg.Overlaps(reg));
 }
 
-TEST(ManagedRegister, CoreRegister) {
-  ManagedRegister reg = ManagedRegister::FromCoreRegister(R0);
+TEST(ArmManagedRegister, CoreRegister) {
+  ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -21,7 +22,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(R0, reg.AsCoreRegister());
 
-  reg = ManagedRegister::FromCoreRegister(R1);
+  reg = ArmManagedRegister::FromCoreRegister(R1);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -30,7 +31,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(R1, reg.AsCoreRegister());
 
-  reg = ManagedRegister::FromCoreRegister(R8);
+  reg = ArmManagedRegister::FromCoreRegister(R8);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -39,7 +40,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(R8, reg.AsCoreRegister());
 
-  reg = ManagedRegister::FromCoreRegister(R15);
+  reg = ArmManagedRegister::FromCoreRegister(R15);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -50,8 +51,8 @@
 }
 
 
-TEST(ManagedRegister, SRegister) {
-  ManagedRegister reg = ManagedRegister::FromSRegister(S0);
+TEST(ArmManagedRegister, SRegister) {
+  ArmManagedRegister reg = ArmManagedRegister::FromSRegister(S0);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(reg.IsSRegister());
@@ -60,7 +61,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(S0, reg.AsSRegister());
 
-  reg = ManagedRegister::FromSRegister(S1);
+  reg = ArmManagedRegister::FromSRegister(S1);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(reg.IsSRegister());
@@ -69,7 +70,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(S1, reg.AsSRegister());
 
-  reg = ManagedRegister::FromSRegister(S3);
+  reg = ArmManagedRegister::FromSRegister(S3);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(reg.IsSRegister());
@@ -78,7 +79,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(S3, reg.AsSRegister());
 
-  reg = ManagedRegister::FromSRegister(S15);
+  reg = ArmManagedRegister::FromSRegister(S15);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(reg.IsSRegister());
@@ -87,7 +88,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(S15, reg.AsSRegister());
 
-  reg = ManagedRegister::FromSRegister(S30);
+  reg = ArmManagedRegister::FromSRegister(S30);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(reg.IsSRegister());
@@ -96,7 +97,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(S30, reg.AsSRegister());
 
-  reg = ManagedRegister::FromSRegister(S31);
+  reg = ArmManagedRegister::FromSRegister(S31);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(reg.IsSRegister());
@@ -107,8 +108,8 @@
 }
 
 
-TEST(ManagedRegister, DRegister) {
-  ManagedRegister reg = ManagedRegister::FromDRegister(D0);
+TEST(ArmManagedRegister, DRegister) {
+  ArmManagedRegister reg = ArmManagedRegister::FromDRegister(D0);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -118,9 +119,9 @@
   EXPECT_EQ(D0, reg.AsDRegister());
   EXPECT_EQ(S0, reg.AsOverlappingDRegisterLow());
   EXPECT_EQ(S1, reg.AsOverlappingDRegisterHigh());
-  EXPECT_TRUE(reg.Equals(ManagedRegister::FromSRegisterPair(S0)));
+  EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromSRegisterPair(S0)));
 
-  reg = ManagedRegister::FromDRegister(D1);
+  reg = ArmManagedRegister::FromDRegister(D1);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -130,9 +131,9 @@
   EXPECT_EQ(D1, reg.AsDRegister());
   EXPECT_EQ(S2, reg.AsOverlappingDRegisterLow());
   EXPECT_EQ(S3, reg.AsOverlappingDRegisterHigh());
-  EXPECT_TRUE(reg.Equals(ManagedRegister::FromSRegisterPair(S2)));
+  EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromSRegisterPair(S2)));
 
-  reg = ManagedRegister::FromDRegister(D6);
+  reg = ArmManagedRegister::FromDRegister(D6);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -142,9 +143,9 @@
   EXPECT_EQ(D6, reg.AsDRegister());
   EXPECT_EQ(S12, reg.AsOverlappingDRegisterLow());
   EXPECT_EQ(S13, reg.AsOverlappingDRegisterHigh());
-  EXPECT_TRUE(reg.Equals(ManagedRegister::FromSRegisterPair(S12)));
+  EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromSRegisterPair(S12)));
 
-  reg = ManagedRegister::FromDRegister(D14);
+  reg = ArmManagedRegister::FromDRegister(D14);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -154,9 +155,9 @@
   EXPECT_EQ(D14, reg.AsDRegister());
   EXPECT_EQ(S28, reg.AsOverlappingDRegisterLow());
   EXPECT_EQ(S29, reg.AsOverlappingDRegisterHigh());
-  EXPECT_TRUE(reg.Equals(ManagedRegister::FromSRegisterPair(S28)));
+  EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromSRegisterPair(S28)));
 
-  reg = ManagedRegister::FromDRegister(D15);
+  reg = ArmManagedRegister::FromDRegister(D15);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -166,10 +167,10 @@
   EXPECT_EQ(D15, reg.AsDRegister());
   EXPECT_EQ(S30, reg.AsOverlappingDRegisterLow());
   EXPECT_EQ(S31, reg.AsOverlappingDRegisterHigh());
-  EXPECT_TRUE(reg.Equals(ManagedRegister::FromSRegisterPair(S30)));
+  EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromSRegisterPair(S30)));
 
 #ifdef VFPv3_D32
-  reg = ManagedRegister::FromDRegister(D16);
+  reg = ArmManagedRegister::FromDRegister(D16);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -178,7 +179,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(D16, reg.AsDRegister());
 
-  reg = ManagedRegister::FromDRegister(D18);
+  reg = ArmManagedRegister::FromDRegister(D18);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -187,7 +188,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(D18, reg.AsDRegister());
 
-  reg = ManagedRegister::FromDRegister(D30);
+  reg = ArmManagedRegister::FromDRegister(D30);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -196,7 +197,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(D30, reg.AsDRegister());
 
-  reg = ManagedRegister::FromDRegister(D31);
+  reg = ArmManagedRegister::FromDRegister(D31);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -208,8 +209,8 @@
 }
 
 
-TEST(ManagedRegister, Pair) {
-  ManagedRegister reg = ManagedRegister::FromRegisterPair(R0_R1);
+TEST(ArmManagedRegister, Pair) {
+  ArmManagedRegister reg = ArmManagedRegister::FromRegisterPair(R0_R1);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -219,9 +220,9 @@
   EXPECT_EQ(R0_R1, reg.AsRegisterPair());
   EXPECT_EQ(R0, reg.AsRegisterPairLow());
   EXPECT_EQ(R1, reg.AsRegisterPairHigh());
-  EXPECT_TRUE(reg.Equals(ManagedRegister::FromCoreRegisterPair(R0)));
+  EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromCoreRegisterPair(R0)));
 
-  reg = ManagedRegister::FromRegisterPair(R1_R2);
+  reg = ArmManagedRegister::FromRegisterPair(R1_R2);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -231,9 +232,9 @@
   EXPECT_EQ(R1_R2, reg.AsRegisterPair());
   EXPECT_EQ(R1, reg.AsRegisterPairLow());
   EXPECT_EQ(R2, reg.AsRegisterPairHigh());
-  EXPECT_TRUE(reg.Equals(ManagedRegister::FromCoreRegisterPair(R1)));
+  EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromCoreRegisterPair(R1)));
 
-  reg = ManagedRegister::FromRegisterPair(R2_R3);
+  reg = ArmManagedRegister::FromRegisterPair(R2_R3);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -243,9 +244,9 @@
   EXPECT_EQ(R2_R3, reg.AsRegisterPair());
   EXPECT_EQ(R2, reg.AsRegisterPairLow());
   EXPECT_EQ(R3, reg.AsRegisterPairHigh());
-  EXPECT_TRUE(reg.Equals(ManagedRegister::FromCoreRegisterPair(R2)));
+  EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromCoreRegisterPair(R2)));
 
-  reg = ManagedRegister::FromRegisterPair(R4_R5);
+  reg = ArmManagedRegister::FromRegisterPair(R4_R5);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -255,9 +256,9 @@
   EXPECT_EQ(R4_R5, reg.AsRegisterPair());
   EXPECT_EQ(R4, reg.AsRegisterPairLow());
   EXPECT_EQ(R5, reg.AsRegisterPairHigh());
-  EXPECT_TRUE(reg.Equals(ManagedRegister::FromCoreRegisterPair(R4)));
+  EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromCoreRegisterPair(R4)));
 
-  reg = ManagedRegister::FromRegisterPair(R6_R7);
+  reg = ArmManagedRegister::FromRegisterPair(R6_R7);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCoreRegister());
   EXPECT_TRUE(!reg.IsSRegister());
@@ -267,485 +268,486 @@
   EXPECT_EQ(R6_R7, reg.AsRegisterPair());
   EXPECT_EQ(R6, reg.AsRegisterPairLow());
   EXPECT_EQ(R7, reg.AsRegisterPairHigh());
-  EXPECT_TRUE(reg.Equals(ManagedRegister::FromCoreRegisterPair(R6)));
+  EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromCoreRegisterPair(R6)));
 }
 
 
-TEST(ManagedRegister, Equals) {
+TEST(ArmManagedRegister, Equals) {
   ManagedRegister no_reg = ManagedRegister::NoRegister();
-  EXPECT_TRUE(no_reg.Equals(ManagedRegister::NoRegister()));
-  EXPECT_TRUE(!no_reg.Equals(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!no_reg.Equals(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!no_reg.Equals(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!no_reg.Equals(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!no_reg.Equals(ManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(no_reg.Equals(ArmManagedRegister::NoRegister()));
+  EXPECT_TRUE(!no_reg.Equals(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!no_reg.Equals(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!no_reg.Equals(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!no_reg.Equals(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!no_reg.Equals(ArmManagedRegister::FromRegisterPair(R0_R1)));
 
-  ManagedRegister reg_R0 = ManagedRegister::FromCoreRegister(R0);
-  EXPECT_TRUE(!reg_R0.Equals(ManagedRegister::NoRegister()));
-  EXPECT_TRUE(reg_R0.Equals(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg_R0.Equals(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg_R0.Equals(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg_R0.Equals(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg_R0.Equals(ManagedRegister::FromRegisterPair(R0_R1)));
+  ArmManagedRegister reg_R0 = ArmManagedRegister::FromCoreRegister(R0);
+  EXPECT_TRUE(!reg_R0.Equals(ArmManagedRegister::NoRegister()));
+  EXPECT_TRUE(reg_R0.Equals(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg_R0.Equals(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg_R0.Equals(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg_R0.Equals(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg_R0.Equals(ArmManagedRegister::FromRegisterPair(R0_R1)));
 
-  ManagedRegister reg_R1 = ManagedRegister::FromCoreRegister(R1);
-  EXPECT_TRUE(!reg_R1.Equals(ManagedRegister::NoRegister()));
-  EXPECT_TRUE(!reg_R1.Equals(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(reg_R1.Equals(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg_R1.Equals(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg_R1.Equals(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg_R1.Equals(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg_R1.Equals(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg_R1.Equals(ManagedRegister::FromRegisterPair(R0_R1)));
+  ArmManagedRegister reg_R1 = ArmManagedRegister::FromCoreRegister(R1);
+  EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::NoRegister()));
+  EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(reg_R1.Equals(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromRegisterPair(R0_R1)));
 
-  ManagedRegister reg_R8 = ManagedRegister::FromCoreRegister(R8);
-  EXPECT_TRUE(!reg_R8.Equals(ManagedRegister::NoRegister()));
-  EXPECT_TRUE(!reg_R8.Equals(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(reg_R8.Equals(ManagedRegister::FromCoreRegister(R8)));
-  EXPECT_TRUE(!reg_R8.Equals(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg_R8.Equals(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg_R8.Equals(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg_R8.Equals(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg_R8.Equals(ManagedRegister::FromRegisterPair(R0_R1)));
+  ArmManagedRegister reg_R8 = ArmManagedRegister::FromCoreRegister(R8);
+  EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::NoRegister()));
+  EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(reg_R8.Equals(ArmManagedRegister::FromCoreRegister(R8)));
+  EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromRegisterPair(R0_R1)));
 
-  ManagedRegister reg_S0 = ManagedRegister::FromSRegister(S0);
-  EXPECT_TRUE(!reg_S0.Equals(ManagedRegister::NoRegister()));
-  EXPECT_TRUE(!reg_S0.Equals(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg_S0.Equals(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(reg_S0.Equals(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg_S0.Equals(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg_S0.Equals(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg_S0.Equals(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg_S0.Equals(ManagedRegister::FromRegisterPair(R0_R1)));
+  ArmManagedRegister reg_S0 = ArmManagedRegister::FromSRegister(S0);
+  EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::NoRegister()));
+  EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(reg_S0.Equals(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromRegisterPair(R0_R1)));
 
-  ManagedRegister reg_S1 = ManagedRegister::FromSRegister(S1);
-  EXPECT_TRUE(!reg_S1.Equals(ManagedRegister::NoRegister()));
-  EXPECT_TRUE(!reg_S1.Equals(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg_S1.Equals(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg_S1.Equals(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(reg_S1.Equals(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg_S1.Equals(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg_S1.Equals(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg_S1.Equals(ManagedRegister::FromRegisterPair(R0_R1)));
+  ArmManagedRegister reg_S1 = ArmManagedRegister::FromSRegister(S1);
+  EXPECT_TRUE(!reg_S1.Equals(ArmManagedRegister::NoRegister()));
+  EXPECT_TRUE(!reg_S1.Equals(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg_S1.Equals(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg_S1.Equals(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(reg_S1.Equals(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg_S1.Equals(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg_S1.Equals(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg_S1.Equals(ArmManagedRegister::FromRegisterPair(R0_R1)));
 
-  ManagedRegister reg_S31 = ManagedRegister::FromSRegister(S31);
-  EXPECT_TRUE(!reg_S31.Equals(ManagedRegister::NoRegister()));
-  EXPECT_TRUE(!reg_S31.Equals(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg_S31.Equals(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg_S31.Equals(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(reg_S31.Equals(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg_S31.Equals(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg_S31.Equals(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg_S31.Equals(ManagedRegister::FromRegisterPair(R0_R1)));
+  ArmManagedRegister reg_S31 = ArmManagedRegister::FromSRegister(S31);
+  EXPECT_TRUE(!reg_S31.Equals(ArmManagedRegister::NoRegister()));
+  EXPECT_TRUE(!reg_S31.Equals(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg_S31.Equals(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg_S31.Equals(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(reg_S31.Equals(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg_S31.Equals(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg_S31.Equals(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg_S31.Equals(ArmManagedRegister::FromRegisterPair(R0_R1)));
 
-  ManagedRegister reg_D0 = ManagedRegister::FromDRegister(D0);
-  EXPECT_TRUE(!reg_D0.Equals(ManagedRegister::NoRegister()));
-  EXPECT_TRUE(!reg_D0.Equals(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg_D0.Equals(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg_D0.Equals(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg_D0.Equals(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(reg_D0.Equals(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg_D0.Equals(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg_D0.Equals(ManagedRegister::FromRegisterPair(R0_R1)));
+  ArmManagedRegister reg_D0 = ArmManagedRegister::FromDRegister(D0);
+  EXPECT_TRUE(!reg_D0.Equals(ArmManagedRegister::NoRegister()));
+  EXPECT_TRUE(!reg_D0.Equals(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg_D0.Equals(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg_D0.Equals(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg_D0.Equals(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(reg_D0.Equals(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg_D0.Equals(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg_D0.Equals(ArmManagedRegister::FromRegisterPair(R0_R1)));
 
-  ManagedRegister reg_D15 = ManagedRegister::FromDRegister(D15);
-  EXPECT_TRUE(!reg_D15.Equals(ManagedRegister::NoRegister()));
-  EXPECT_TRUE(!reg_D15.Equals(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg_D15.Equals(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg_D15.Equals(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg_D15.Equals(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg_D15.Equals(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg_D15.Equals(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(reg_D15.Equals(ManagedRegister::FromDRegister(D15)));
-  EXPECT_TRUE(!reg_D15.Equals(ManagedRegister::FromRegisterPair(R0_R1)));
+  ArmManagedRegister reg_D15 = ArmManagedRegister::FromDRegister(D15);
+  EXPECT_TRUE(!reg_D15.Equals(ArmManagedRegister::NoRegister()));
+  EXPECT_TRUE(!reg_D15.Equals(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg_D15.Equals(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg_D15.Equals(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg_D15.Equals(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg_D15.Equals(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg_D15.Equals(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(reg_D15.Equals(ArmManagedRegister::FromDRegister(D15)));
+  EXPECT_TRUE(!reg_D15.Equals(ArmManagedRegister::FromRegisterPair(R0_R1)));
 
 #ifdef VFPv3_D32
-  ManagedRegister reg_D16 = ManagedRegister::FromDRegister(D16);
-  EXPECT_TRUE(!reg_D16.Equals(ManagedRegister::NoRegister()));
-  EXPECT_TRUE(!reg_D16.Equals(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg_D16.Equals(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg_D16.Equals(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg_D16.Equals(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg_D16.Equals(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg_D16.Equals(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg_D16.Equals(ManagedRegister::FromDRegister(D15)));
-  EXPECT_TRUE(reg_D16.Equals(ManagedRegister::FromDRegister(D16)));
-  EXPECT_TRUE(!reg_D16.Equals(ManagedRegister::FromRegisterPair(R0_R1)));
+  ArmManagedRegister reg_D16 = ArmManagedRegister::FromDRegister(D16);
+  EXPECT_TRUE(!reg_D16.Equals(ArmManagedRegister::NoRegister()));
+  EXPECT_TRUE(!reg_D16.Equals(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg_D16.Equals(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg_D16.Equals(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg_D16.Equals(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg_D16.Equals(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg_D16.Equals(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg_D16.Equals(ArmManagedRegister::FromDRegister(D15)));
+  EXPECT_TRUE(reg_D16.Equals(ArmManagedRegister::FromDRegister(D16)));
+  EXPECT_TRUE(!reg_D16.Equals(ArmManagedRegister::FromRegisterPair(R0_R1)));
 
-  ManagedRegister reg_D30 = ManagedRegister::FromDRegister(D30);
-  EXPECT_TRUE(!reg_D30.Equals(ManagedRegister::NoRegister()));
-  EXPECT_TRUE(!reg_D30.Equals(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg_D30.Equals(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg_D30.Equals(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg_D30.Equals(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg_D30.Equals(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg_D30.Equals(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg_D30.Equals(ManagedRegister::FromDRegister(D15)));
-  EXPECT_TRUE(!reg_D30.Equals(ManagedRegister::FromDRegister(D16)));
-  EXPECT_TRUE(reg_D30.Equals(ManagedRegister::FromDRegister(D30)));
-  EXPECT_TRUE(!reg_D30.Equals(ManagedRegister::FromRegisterPair(R0_R1)));
+  ArmManagedRegister reg_D30 = ArmManagedRegister::FromDRegister(D30);
+  EXPECT_TRUE(!reg_D30.Equals(ArmManagedRegister::NoRegister()));
+  EXPECT_TRUE(!reg_D30.Equals(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg_D30.Equals(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg_D30.Equals(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg_D30.Equals(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg_D30.Equals(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg_D30.Equals(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg_D30.Equals(ArmManagedRegister::FromDRegister(D15)));
+  EXPECT_TRUE(!reg_D30.Equals(ArmManagedRegister::FromDRegister(D16)));
+  EXPECT_TRUE(reg_D30.Equals(ArmManagedRegister::FromDRegister(D30)));
+  EXPECT_TRUE(!reg_D30.Equals(ArmManagedRegister::FromRegisterPair(R0_R1)));
 
-  ManagedRegister reg_D31 = ManagedRegister::FromDRegister(D30);
-  EXPECT_TRUE(!reg_D31.Equals(ManagedRegister::NoRegister()));
-  EXPECT_TRUE(!reg_D31.Equals(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg_D31.Equals(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg_D31.Equals(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg_D31.Equals(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg_D31.Equals(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg_D31.Equals(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg_D31.Equals(ManagedRegister::FromDRegister(D15)));
-  EXPECT_TRUE(!reg_D31.Equals(ManagedRegister::FromDRegister(D16)));
-  EXPECT_TRUE(!reg_D31.Equals(ManagedRegister::FromDRegister(D30)));
-  EXPECT_TRUE(reg_D31.Equals(ManagedRegister::FromDRegister(D31)));
-  EXPECT_TRUE(!reg_D31.Equals(ManagedRegister::FromRegisterPair(R0_R1)));
+  ArmManagedRegister reg_D31 = ArmManagedRegister::FromDRegister(D30);
+  EXPECT_TRUE(!reg_D31.Equals(ArmManagedRegister::NoRegister()));
+  EXPECT_TRUE(!reg_D31.Equals(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg_D31.Equals(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg_D31.Equals(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg_D31.Equals(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg_D31.Equals(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg_D31.Equals(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg_D31.Equals(ArmManagedRegister::FromDRegister(D15)));
+  EXPECT_TRUE(!reg_D31.Equals(ArmManagedRegister::FromDRegister(D16)));
+  EXPECT_TRUE(!reg_D31.Equals(ArmManagedRegister::FromDRegister(D30)));
+  EXPECT_TRUE(reg_D31.Equals(ArmManagedRegister::FromDRegister(D31)));
+  EXPECT_TRUE(!reg_D31.Equals(ArmManagedRegister::FromRegisterPair(R0_R1)));
 #endif  // VFPv3_D32
 
-  ManagedRegister reg_R0R1 = ManagedRegister::FromRegisterPair(R0_R1);
-  EXPECT_TRUE(!reg_R0R1.Equals(ManagedRegister::NoRegister()));
-  EXPECT_TRUE(!reg_R0R1.Equals(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg_R0R1.Equals(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg_R0R1.Equals(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg_R0R1.Equals(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg_R0R1.Equals(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg_R0R1.Equals(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg_R0R1.Equals(ManagedRegister::FromDRegister(D15)));
-  EXPECT_TRUE(reg_R0R1.Equals(ManagedRegister::FromRegisterPair(R0_R1)));
-  EXPECT_TRUE(!reg_R0R1.Equals(ManagedRegister::FromRegisterPair(R2_R3)));
+  ArmManagedRegister reg_R0R1 = ArmManagedRegister::FromRegisterPair(R0_R1);
+  EXPECT_TRUE(!reg_R0R1.Equals(ArmManagedRegister::NoRegister()));
+  EXPECT_TRUE(!reg_R0R1.Equals(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg_R0R1.Equals(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg_R0R1.Equals(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg_R0R1.Equals(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg_R0R1.Equals(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg_R0R1.Equals(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg_R0R1.Equals(ArmManagedRegister::FromDRegister(D15)));
+  EXPECT_TRUE(reg_R0R1.Equals(ArmManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(!reg_R0R1.Equals(ArmManagedRegister::FromRegisterPair(R2_R3)));
 
-  ManagedRegister reg_R4R5 = ManagedRegister::FromRegisterPair(R4_R5);
-  EXPECT_TRUE(!reg_R4R5.Equals(ManagedRegister::NoRegister()));
-  EXPECT_TRUE(!reg_R4R5.Equals(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg_R4R5.Equals(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg_R4R5.Equals(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg_R4R5.Equals(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg_R4R5.Equals(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg_R4R5.Equals(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg_R4R5.Equals(ManagedRegister::FromDRegister(D15)));
-  EXPECT_TRUE(!reg_R4R5.Equals(ManagedRegister::FromRegisterPair(R0_R1)));
-  EXPECT_TRUE(reg_R4R5.Equals(ManagedRegister::FromRegisterPair(R4_R5)));
-  EXPECT_TRUE(!reg_R4R5.Equals(ManagedRegister::FromRegisterPair(R6_R7)));
+  ArmManagedRegister reg_R4R5 = ArmManagedRegister::FromRegisterPair(R4_R5);
+  EXPECT_TRUE(!reg_R4R5.Equals(ArmManagedRegister::NoRegister()));
+  EXPECT_TRUE(!reg_R4R5.Equals(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg_R4R5.Equals(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg_R4R5.Equals(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg_R4R5.Equals(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg_R4R5.Equals(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg_R4R5.Equals(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg_R4R5.Equals(ArmManagedRegister::FromDRegister(D15)));
+  EXPECT_TRUE(!reg_R4R5.Equals(ArmManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(reg_R4R5.Equals(ArmManagedRegister::FromRegisterPair(R4_R5)));
+  EXPECT_TRUE(!reg_R4R5.Equals(ArmManagedRegister::FromRegisterPair(R6_R7)));
 
-  ManagedRegister reg_R6R7 = ManagedRegister::FromRegisterPair(R6_R7);
-  EXPECT_TRUE(!reg_R6R7.Equals(ManagedRegister::NoRegister()));
-  EXPECT_TRUE(!reg_R6R7.Equals(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg_R6R7.Equals(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg_R6R7.Equals(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg_R6R7.Equals(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg_R6R7.Equals(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg_R6R7.Equals(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg_R6R7.Equals(ManagedRegister::FromDRegister(D15)));
-  EXPECT_TRUE(!reg_R6R7.Equals(ManagedRegister::FromRegisterPair(R0_R1)));
-  EXPECT_TRUE(!reg_R6R7.Equals(ManagedRegister::FromRegisterPair(R4_R5)));
-  EXPECT_TRUE(reg_R6R7.Equals(ManagedRegister::FromRegisterPair(R6_R7)));
+  ArmManagedRegister reg_R6R7 = ArmManagedRegister::FromRegisterPair(R6_R7);
+  EXPECT_TRUE(!reg_R6R7.Equals(ArmManagedRegister::NoRegister()));
+  EXPECT_TRUE(!reg_R6R7.Equals(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg_R6R7.Equals(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg_R6R7.Equals(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg_R6R7.Equals(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg_R6R7.Equals(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg_R6R7.Equals(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg_R6R7.Equals(ArmManagedRegister::FromDRegister(D15)));
+  EXPECT_TRUE(!reg_R6R7.Equals(ArmManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(!reg_R6R7.Equals(ArmManagedRegister::FromRegisterPair(R4_R5)));
+  EXPECT_TRUE(reg_R6R7.Equals(ArmManagedRegister::FromRegisterPair(R6_R7)));
 }
 
 
-TEST(ManagedRegister, Overlaps) {
-  ManagedRegister reg = ManagedRegister::FromCoreRegister(R0);
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R8)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S2)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S15)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S30)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D15)));
+TEST(ArmManagedRegister, Overlaps) {
+  ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0);
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R8)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S15)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S30)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D15)));
 #ifdef VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D16)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D31)));
 #endif  // VFPv3_D32
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromRegisterPair(R0_R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R4_R5)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R4_R5)));
 
-  reg = ManagedRegister::FromCoreRegister(R1);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R8)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S2)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S15)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S30)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D15)));
+  reg = ArmManagedRegister::FromCoreRegister(R1);
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R8)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S15)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S30)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D15)));
 #ifdef VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D16)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D31)));
 #endif  // VFPv3_D32
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromRegisterPair(R0_R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R4_R5)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R4_R5)));
 
-  reg = ManagedRegister::FromCoreRegister(R7);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromCoreRegister(R7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R8)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S2)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S15)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S30)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D15)));
+  reg = ArmManagedRegister::FromCoreRegister(R7);
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R8)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S15)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S30)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D15)));
 #ifdef VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D16)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D31)));
 #endif  // VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R0_R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R4_R5)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R4_R5)));
 
-  reg = ManagedRegister::FromSRegister(S0);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R8)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S2)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S15)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S30)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D15)));
+  reg = ArmManagedRegister::FromSRegister(S0);
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R8)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S15)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S30)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D15)));
 #ifdef VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D16)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D31)));
 #endif  // VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R0_R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R4_R5)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R4_R5)));
 
-  reg = ManagedRegister::FromSRegister(S1);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R8)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S2)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S15)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S30)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D15)));
+  reg = ArmManagedRegister::FromSRegister(S1);
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R8)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S15)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S30)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D15)));
 #ifdef VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D16)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D31)));
 #endif  // VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R0_R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R4_R5)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R4_R5)));
 
-  reg = ManagedRegister::FromSRegister(S15);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R8)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S2)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromSRegister(S15)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S30)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromDRegister(D7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D15)));
+  reg = ArmManagedRegister::FromSRegister(S15);
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R8)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromSRegister(S15)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S30)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromDRegister(D7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D15)));
 #ifdef VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D16)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D31)));
 #endif  // VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R0_R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R4_R5)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R4_R5)));
 
-  reg = ManagedRegister::FromSRegister(S31);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R8)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S2)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S15)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S30)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D7)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromDRegister(D15)));
+  reg = ArmManagedRegister::FromSRegister(S31);
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R8)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S15)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S30)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D7)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromDRegister(D15)));
 #ifdef VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D16)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D31)));
 #endif  // VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R0_R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R4_R5)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R4_R5)));
 
-  reg = ManagedRegister::FromDRegister(D0);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R8)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S2)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S15)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S30)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D15)));
+  reg = ArmManagedRegister::FromDRegister(D0);
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R8)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S15)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S30)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D15)));
 #ifdef VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D16)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D31)));
 #endif  // VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R0_R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R4_R5)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R4_R5)));
 
-  reg = ManagedRegister::FromDRegister(D7);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R8)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S2)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromSRegister(S15)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S30)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromDRegister(D7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D15)));
+  reg = ArmManagedRegister::FromDRegister(D7);
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R8)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromSRegister(S15)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S30)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromDRegister(D7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D15)));
 #ifdef VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D16)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D31)));
 #endif  // VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R0_R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R4_R5)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R4_R5)));
 
-  reg = ManagedRegister::FromDRegister(D15);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R8)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S2)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S15)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromSRegister(S30)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D7)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromDRegister(D15)));
+  reg = ArmManagedRegister::FromDRegister(D15);
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R8)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S15)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromSRegister(S30)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D7)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromDRegister(D15)));
 #ifdef VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D16)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D31)));
 #endif  // VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R0_R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R4_R5)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R4_R5)));
 
 #ifdef VFPv3_D32
-  reg = ManagedRegister::FromDRegister(D16);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R8)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S2)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S15)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S30)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D15)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromDRegister(D16)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D31)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R0_R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R4_R5)));
+  reg = ArmManagedRegister::FromDRegister(D16);
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R8)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S15)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S30)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D15)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R4_R5)));
 
-  reg = ManagedRegister::FromDRegister(D31);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R8)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S2)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S15)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S30)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D15)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D16)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromDRegister(D31)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R0_R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R4_R5)));
+  reg = ArmManagedRegister::FromDRegister(D31);
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R8)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S15)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S30)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D15)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromDRegister(D31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R4_R5)));
 #endif  // VFPv3_D32
 
-  reg = ManagedRegister::FromRegisterPair(R0_R1);
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R8)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S2)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S15)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S30)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D15)));
+  reg = ArmManagedRegister::FromRegisterPair(R0_R1);
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R8)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S15)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S30)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D15)));
 #ifdef VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D16)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D31)));
 #endif  // VFPv3_D32
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromRegisterPair(R0_R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R4_R5)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R4_R5)));
 
-  reg = ManagedRegister::FromRegisterPair(R4_R5);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCoreRegister(R8)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S2)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S15)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S30)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromSRegister(S31)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D1)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D15)));
+  reg = ArmManagedRegister::FromRegisterPair(R4_R5);
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R8)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S15)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S30)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D0)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D1)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D7)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D15)));
 #ifdef VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D16)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromDRegister(D31)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D16)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromDRegister(D31)));
 #endif  // VFPv3_D32
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(R0_R1)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromRegisterPair(R4_R5)));
+  EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromRegisterPair(R0_R1)));
+  EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromRegisterPair(R4_R5)));
 }
 
+}  // namespace arm
 }  // namespace art
diff --git a/src/managed_register_x86.cc b/src/managed_register_x86.cc
index d2271fb..45f73d6 100644
--- a/src/managed_register_x86.cc
+++ b/src/managed_register_x86.cc
@@ -1,10 +1,12 @@
 // Copyright 2011 Google Inc. All Rights Reserved.
 
+#include "managed_register_x86.h"
+
 #include "globals.h"
 #include "calling_convention.h"
-#include "managed_register.h"
 
 namespace art {
+namespace x86 {
 
 // These cpu registers are never available for allocation.
 static const Register kReservedCpuRegistersArray[] = { EBP, ESP };
@@ -48,11 +50,11 @@
 };
 
 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) {
-  os << ManagedRegister::FromRegisterPair(reg);
+  os << X86ManagedRegister::FromRegisterPair(reg);
   return os;
 }
 
-bool ManagedRegister::Overlaps(const ManagedRegister& other) const {
+bool X86ManagedRegister::Overlaps(const X86ManagedRegister& other) const {
   if (IsNoRegister() || other.IsNoRegister()) return false;
   CHECK(IsValidManagedRegister());
   CHECK(other.IsValidManagedRegister());
@@ -60,8 +62,8 @@
   if (IsRegisterPair()) {
     Register low = AsRegisterPairLow();
     Register high = AsRegisterPairHigh();
-    return ManagedRegister::FromCpuRegister(low).Overlaps(other) ||
-        ManagedRegister::FromCpuRegister(high).Overlaps(other);
+    return X86ManagedRegister::FromCpuRegister(low).Overlaps(other) ||
+        X86ManagedRegister::FromCpuRegister(high).Overlaps(other);
   }
   if (other.IsRegisterPair()) {
     return other.Overlaps(*this);
@@ -70,7 +72,7 @@
 }
 
 
-int ManagedRegister::AllocIdLow() const {
+int X86ManagedRegister::AllocIdLow() const {
   CHECK(IsRegisterPair());
   const int r = RegId() - (kNumberOfCpuRegIds + kNumberOfXmmRegIds +
                            kNumberOfX87RegIds);
@@ -79,7 +81,7 @@
 }
 
 
-int ManagedRegister::AllocIdHigh() const {
+int X86ManagedRegister::AllocIdHigh() const {
   CHECK(IsRegisterPair());
   const int r = RegId() - (kNumberOfCpuRegIds + kNumberOfXmmRegIds +
                            kNumberOfX87RegIds);
@@ -88,7 +90,7 @@
 }
 
 
-void ManagedRegister::Print(std::ostream& os) const {
+void X86ManagedRegister::Print(std::ostream& os) const {
   if (!IsValidManagedRegister()) {
     os << "No Register";
   } else if (IsXmmRegister()) {
@@ -104,9 +106,10 @@
   }
 }
 
-std::ostream& operator<<(std::ostream& os, const ManagedRegister& reg) {
+std::ostream& operator<<(std::ostream& os, const X86ManagedRegister& reg) {
   reg.Print(os);
   return os;
 }
 
+}  // namespace x86
 }  // namespace art
diff --git a/src/managed_register_x86.h b/src/managed_register_x86.h
index 1d38d7f..7c1f916 100644
--- a/src/managed_register_x86.h
+++ b/src/managed_register_x86.h
@@ -4,8 +4,10 @@
 #define ART_SRC_MANAGED_REGISTER_X86_H_
 
 #include "constants_x86.h"
+#include "managed_register.h"
 
 namespace art {
+namespace x86 {
 
 // Values for register pairs.
 // The registers in kReservedCpuRegistersArray in x86.cc are not used in pairs.
@@ -69,18 +71,8 @@
 // (enum RegisterPair).
 // 'ManagedRegister::NoRegister()' provides an invalid register.
 // There is a one-to-one mapping between ManagedRegister and register id.
-class ManagedRegister {
+class X86ManagedRegister : public ManagedRegister {
  public:
-  // ManagedRegister is a value class. There exists no method to change the
-  // internal state. We therefore allow a copy constructor and an
-  // assignment-operator.
-  ManagedRegister(const ManagedRegister& other) : id_(other.id_) { }
-
-  ManagedRegister& operator=(const ManagedRegister& other) {
-    id_ = other.id_;
-    return *this;
-  }
-
   Register AsCpuRegister() const {
     CHECK(IsCpuRegister());
     return static_cast<Register>(id_);
@@ -133,52 +125,35 @@
     return (0 <= test) && (test < kNumberOfPairRegIds);
   }
 
-  bool IsNoRegister() const {
-    return id_ == kNoRegister;
-  }
-
   void Print(std::ostream& os) const;
 
-  // It is valid to invoke Equals on and with a NoRegister.
-  bool Equals(const ManagedRegister& other) const {
-    return id_ == other.id_;
-  }
-
   // Returns true if the two managed-registers ('this' and 'other') overlap.
   // Either managed-register may be the NoRegister. If both are the NoRegister
   // then false is returned.
-  bool Overlaps(const ManagedRegister& other) const;
+  bool Overlaps(const X86ManagedRegister& other) const;
 
-  static ManagedRegister NoRegister() {
-    return ManagedRegister();
-  }
-
-  static ManagedRegister FromCpuRegister(Register r) {
+  static X86ManagedRegister FromCpuRegister(Register r) {
     CHECK_NE(r, kNoRegister);
     return FromRegId(r);
   }
 
-  static ManagedRegister FromXmmRegister(XmmRegister r) {
+  static X86ManagedRegister FromXmmRegister(XmmRegister r) {
     CHECK_NE(r, kNoXmmRegister);
     return FromRegId(r + kNumberOfCpuRegIds);
   }
 
-  static ManagedRegister FromX87Register(X87Register r) {
+  static X86ManagedRegister FromX87Register(X87Register r) {
     CHECK_NE(r, kNoX87Register);
     return FromRegId(r + kNumberOfCpuRegIds + kNumberOfXmmRegIds);
   }
 
-  static ManagedRegister FromRegisterPair(RegisterPair r) {
+  static X86ManagedRegister FromRegisterPair(RegisterPair r) {
     CHECK_NE(r, kNoRegisterPair);
     return FromRegId(r + (kNumberOfCpuRegIds + kNumberOfXmmRegIds +
                           kNumberOfX87RegIds));
   }
 
  private:
-  static const int kNoRegister = -1;
-
-  ManagedRegister() : id_(kNoRegister) { }
-
   bool IsValidManagedRegister() const {
     return (0 <= id_) && (id_ < kNumberOfRegIds);
   }
@@ -197,17 +172,26 @@
   int AllocIdLow() const;
   int AllocIdHigh() const;
 
-  static ManagedRegister FromRegId(int reg_id) {
-    ManagedRegister reg;
-    reg.id_ = reg_id;
+  friend class ManagedRegister;
+
+  X86ManagedRegister(int reg_id) : ManagedRegister(reg_id) {}
+
+  static X86ManagedRegister FromRegId(int reg_id) {
+    X86ManagedRegister reg(reg_id);
     CHECK(reg.IsValidManagedRegister());
     return reg;
   }
-
-  int id_;
 };
 
-std::ostream& operator<<(std::ostream& os, const ManagedRegister& reg);
+std::ostream& operator<<(std::ostream& os, const X86ManagedRegister& reg);
+
+}  // namespace x86
+
+inline x86::X86ManagedRegister ManagedRegister::AsX86() const {
+  x86::X86ManagedRegister reg(id_);
+  CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister());
+  return reg;
+}
 
 }  // namespace art
 
diff --git a/src/managed_register_x86_test.cc b/src/managed_register_x86_test.cc
index 2059f65..6121e26 100644
--- a/src/managed_register_x86_test.cc
+++ b/src/managed_register_x86_test.cc
@@ -1,19 +1,20 @@
 // Copyright 2011 Google Inc. All Rights Reserved.
 
 #include "globals.h"
-#include "managed_register.h"
+#include "managed_register_x86.h"
 #include "gtest/gtest.h"
 
 namespace art {
+namespace x86 {
 
-TEST(ManagedRegister, NoRegister) {
-  ManagedRegister reg = ManagedRegister::NoRegister();
+TEST(X86ManagedRegister, NoRegister) {
+  X86ManagedRegister reg = ManagedRegister::NoRegister().AsX86();
   EXPECT_TRUE(reg.IsNoRegister());
   EXPECT_TRUE(!reg.Overlaps(reg));
 }
 
-TEST(ManagedRegister, CpuRegister) {
-  ManagedRegister reg = ManagedRegister::FromCpuRegister(EAX);
+TEST(X86ManagedRegister, CpuRegister) {
+  X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(reg.IsCpuRegister());
   EXPECT_TRUE(!reg.IsXmmRegister());
@@ -21,7 +22,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(EAX, reg.AsCpuRegister());
 
-  reg = ManagedRegister::FromCpuRegister(EBX);
+  reg = X86ManagedRegister::FromCpuRegister(EBX);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(reg.IsCpuRegister());
   EXPECT_TRUE(!reg.IsXmmRegister());
@@ -29,7 +30,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(EBX, reg.AsCpuRegister());
 
-  reg = ManagedRegister::FromCpuRegister(ECX);
+  reg = X86ManagedRegister::FromCpuRegister(ECX);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(reg.IsCpuRegister());
   EXPECT_TRUE(!reg.IsXmmRegister());
@@ -37,7 +38,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(ECX, reg.AsCpuRegister());
 
-  reg = ManagedRegister::FromCpuRegister(EDI);
+  reg = X86ManagedRegister::FromCpuRegister(EDI);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(reg.IsCpuRegister());
   EXPECT_TRUE(!reg.IsXmmRegister());
@@ -46,8 +47,8 @@
   EXPECT_EQ(EDI, reg.AsCpuRegister());
 }
 
-TEST(ManagedRegister, XmmRegister) {
-  ManagedRegister reg = ManagedRegister::FromXmmRegister(XMM0);
+TEST(X86ManagedRegister, XmmRegister) {
+  X86ManagedRegister reg = X86ManagedRegister::FromXmmRegister(XMM0);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCpuRegister());
   EXPECT_TRUE(reg.IsXmmRegister());
@@ -55,7 +56,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(XMM0, reg.AsXmmRegister());
 
-  reg = ManagedRegister::FromXmmRegister(XMM1);
+  reg = X86ManagedRegister::FromXmmRegister(XMM1);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCpuRegister());
   EXPECT_TRUE(reg.IsXmmRegister());
@@ -63,7 +64,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(XMM1, reg.AsXmmRegister());
 
-  reg = ManagedRegister::FromXmmRegister(XMM7);
+  reg = X86ManagedRegister::FromXmmRegister(XMM7);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCpuRegister());
   EXPECT_TRUE(reg.IsXmmRegister());
@@ -72,8 +73,8 @@
   EXPECT_EQ(XMM7, reg.AsXmmRegister());
 }
 
-TEST(ManagedRegister, X87Register) {
-  ManagedRegister reg = ManagedRegister::FromX87Register(ST0);
+TEST(X86ManagedRegister, X87Register) {
+  X86ManagedRegister reg = X86ManagedRegister::FromX87Register(ST0);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCpuRegister());
   EXPECT_TRUE(!reg.IsXmmRegister());
@@ -81,7 +82,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(ST0, reg.AsX87Register());
 
-  reg = ManagedRegister::FromX87Register(ST1);
+  reg = X86ManagedRegister::FromX87Register(ST1);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCpuRegister());
   EXPECT_TRUE(!reg.IsXmmRegister());
@@ -89,7 +90,7 @@
   EXPECT_TRUE(!reg.IsRegisterPair());
   EXPECT_EQ(ST1, reg.AsX87Register());
 
-  reg = ManagedRegister::FromX87Register(ST7);
+  reg = X86ManagedRegister::FromX87Register(ST7);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCpuRegister());
   EXPECT_TRUE(!reg.IsXmmRegister());
@@ -98,8 +99,8 @@
   EXPECT_EQ(ST7, reg.AsX87Register());
 }
 
-TEST(ManagedRegister, RegisterPair) {
-  ManagedRegister reg = ManagedRegister::FromRegisterPair(EAX_EDX);
+TEST(X86ManagedRegister, RegisterPair) {
+  X86ManagedRegister reg = X86ManagedRegister::FromRegisterPair(EAX_EDX);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCpuRegister());
   EXPECT_TRUE(!reg.IsXmmRegister());
@@ -108,7 +109,7 @@
   EXPECT_EQ(EAX, reg.AsRegisterPairLow());
   EXPECT_EQ(EDX, reg.AsRegisterPairHigh());
 
-  reg = ManagedRegister::FromRegisterPair(EAX_ECX);
+  reg = X86ManagedRegister::FromRegisterPair(EAX_ECX);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCpuRegister());
   EXPECT_TRUE(!reg.IsXmmRegister());
@@ -117,7 +118,7 @@
   EXPECT_EQ(EAX, reg.AsRegisterPairLow());
   EXPECT_EQ(ECX, reg.AsRegisterPairHigh());
 
-  reg = ManagedRegister::FromRegisterPair(EAX_EBX);
+  reg = X86ManagedRegister::FromRegisterPair(EAX_EBX);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCpuRegister());
   EXPECT_TRUE(!reg.IsXmmRegister());
@@ -126,7 +127,7 @@
   EXPECT_EQ(EAX, reg.AsRegisterPairLow());
   EXPECT_EQ(EBX, reg.AsRegisterPairHigh());
 
-  reg = ManagedRegister::FromRegisterPair(EAX_EDI);
+  reg = X86ManagedRegister::FromRegisterPair(EAX_EDI);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCpuRegister());
   EXPECT_TRUE(!reg.IsXmmRegister());
@@ -135,7 +136,7 @@
   EXPECT_EQ(EAX, reg.AsRegisterPairLow());
   EXPECT_EQ(EDI, reg.AsRegisterPairHigh());
 
-  reg = ManagedRegister::FromRegisterPair(EDX_ECX);
+  reg = X86ManagedRegister::FromRegisterPair(EDX_ECX);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCpuRegister());
   EXPECT_TRUE(!reg.IsXmmRegister());
@@ -144,7 +145,7 @@
   EXPECT_EQ(EDX, reg.AsRegisterPairLow());
   EXPECT_EQ(ECX, reg.AsRegisterPairHigh());
 
-  reg = ManagedRegister::FromRegisterPair(EDX_EBX);
+  reg = X86ManagedRegister::FromRegisterPair(EDX_EBX);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCpuRegister());
   EXPECT_TRUE(!reg.IsXmmRegister());
@@ -153,7 +154,7 @@
   EXPECT_EQ(EDX, reg.AsRegisterPairLow());
   EXPECT_EQ(EBX, reg.AsRegisterPairHigh());
 
-  reg = ManagedRegister::FromRegisterPair(EDX_EDI);
+  reg = X86ManagedRegister::FromRegisterPair(EDX_EDI);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCpuRegister());
   EXPECT_TRUE(!reg.IsXmmRegister());
@@ -162,7 +163,7 @@
   EXPECT_EQ(EDX, reg.AsRegisterPairLow());
   EXPECT_EQ(EDI, reg.AsRegisterPairHigh());
 
-  reg = ManagedRegister::FromRegisterPair(ECX_EBX);
+  reg = X86ManagedRegister::FromRegisterPair(ECX_EBX);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCpuRegister());
   EXPECT_TRUE(!reg.IsXmmRegister());
@@ -171,7 +172,7 @@
   EXPECT_EQ(ECX, reg.AsRegisterPairLow());
   EXPECT_EQ(EBX, reg.AsRegisterPairHigh());
 
-  reg = ManagedRegister::FromRegisterPair(ECX_EDI);
+  reg = X86ManagedRegister::FromRegisterPair(ECX_EDI);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCpuRegister());
   EXPECT_TRUE(!reg.IsXmmRegister());
@@ -180,7 +181,7 @@
   EXPECT_EQ(ECX, reg.AsRegisterPairLow());
   EXPECT_EQ(EDI, reg.AsRegisterPairHigh());
 
-  reg = ManagedRegister::FromRegisterPair(EBX_EDI);
+  reg = X86ManagedRegister::FromRegisterPair(EBX_EDI);
   EXPECT_TRUE(!reg.IsNoRegister());
   EXPECT_TRUE(!reg.IsCpuRegister());
   EXPECT_TRUE(!reg.IsXmmRegister());
@@ -190,154 +191,155 @@
   EXPECT_EQ(EDI, reg.AsRegisterPairHigh());
 }
 
-TEST(ManagedRegister, Equals) {
-  ManagedRegister reg_eax = ManagedRegister::FromCpuRegister(EAX);
-  EXPECT_TRUE(reg_eax.Equals(ManagedRegister::FromCpuRegister(EAX)));
-  EXPECT_TRUE(!reg_eax.Equals(ManagedRegister::FromCpuRegister(EBX)));
-  EXPECT_TRUE(!reg_eax.Equals(ManagedRegister::FromCpuRegister(EDI)));
-  EXPECT_TRUE(!reg_eax.Equals(ManagedRegister::FromXmmRegister(XMM0)));
-  EXPECT_TRUE(!reg_eax.Equals(ManagedRegister::FromXmmRegister(XMM7)));
-  EXPECT_TRUE(!reg_eax.Equals(ManagedRegister::FromX87Register(ST0)));
-  EXPECT_TRUE(!reg_eax.Equals(ManagedRegister::FromX87Register(ST7)));
-  EXPECT_TRUE(!reg_eax.Equals(ManagedRegister::FromRegisterPair(EAX_EDX)));
-  EXPECT_TRUE(!reg_eax.Equals(ManagedRegister::FromRegisterPair(EBX_EDI)));
+TEST(X86ManagedRegister, Equals) {
+  X86ManagedRegister reg_eax = X86ManagedRegister::FromCpuRegister(EAX);
+  EXPECT_TRUE(reg_eax.Equals(X86ManagedRegister::FromCpuRegister(EAX)));
+  EXPECT_TRUE(!reg_eax.Equals(X86ManagedRegister::FromCpuRegister(EBX)));
+  EXPECT_TRUE(!reg_eax.Equals(X86ManagedRegister::FromCpuRegister(EDI)));
+  EXPECT_TRUE(!reg_eax.Equals(X86ManagedRegister::FromXmmRegister(XMM0)));
+  EXPECT_TRUE(!reg_eax.Equals(X86ManagedRegister::FromXmmRegister(XMM7)));
+  EXPECT_TRUE(!reg_eax.Equals(X86ManagedRegister::FromX87Register(ST0)));
+  EXPECT_TRUE(!reg_eax.Equals(X86ManagedRegister::FromX87Register(ST7)));
+  EXPECT_TRUE(!reg_eax.Equals(X86ManagedRegister::FromRegisterPair(EAX_EDX)));
+  EXPECT_TRUE(!reg_eax.Equals(X86ManagedRegister::FromRegisterPair(EBX_EDI)));
 
-  ManagedRegister reg_xmm0 = ManagedRegister::FromXmmRegister(XMM0);
-  EXPECT_TRUE(!reg_xmm0.Equals(ManagedRegister::FromCpuRegister(EAX)));
-  EXPECT_TRUE(!reg_xmm0.Equals(ManagedRegister::FromCpuRegister(EBX)));
-  EXPECT_TRUE(!reg_xmm0.Equals(ManagedRegister::FromCpuRegister(EDI)));
-  EXPECT_TRUE(reg_xmm0.Equals(ManagedRegister::FromXmmRegister(XMM0)));
-  EXPECT_TRUE(!reg_xmm0.Equals(ManagedRegister::FromXmmRegister(XMM7)));
-  EXPECT_TRUE(!reg_xmm0.Equals(ManagedRegister::FromX87Register(ST0)));
-  EXPECT_TRUE(!reg_xmm0.Equals(ManagedRegister::FromX87Register(ST7)));
-  EXPECT_TRUE(!reg_xmm0.Equals(ManagedRegister::FromRegisterPair(EAX_EDX)));
-  EXPECT_TRUE(!reg_xmm0.Equals(ManagedRegister::FromRegisterPair(EBX_EDI)));
+  X86ManagedRegister reg_xmm0 = X86ManagedRegister::FromXmmRegister(XMM0);
+  EXPECT_TRUE(!reg_xmm0.Equals(X86ManagedRegister::FromCpuRegister(EAX)));
+  EXPECT_TRUE(!reg_xmm0.Equals(X86ManagedRegister::FromCpuRegister(EBX)));
+  EXPECT_TRUE(!reg_xmm0.Equals(X86ManagedRegister::FromCpuRegister(EDI)));
+  EXPECT_TRUE(reg_xmm0.Equals(X86ManagedRegister::FromXmmRegister(XMM0)));
+  EXPECT_TRUE(!reg_xmm0.Equals(X86ManagedRegister::FromXmmRegister(XMM7)));
+  EXPECT_TRUE(!reg_xmm0.Equals(X86ManagedRegister::FromX87Register(ST0)));
+  EXPECT_TRUE(!reg_xmm0.Equals(X86ManagedRegister::FromX87Register(ST7)));
+  EXPECT_TRUE(!reg_xmm0.Equals(X86ManagedRegister::FromRegisterPair(EAX_EDX)));
+  EXPECT_TRUE(!reg_xmm0.Equals(X86ManagedRegister::FromRegisterPair(EBX_EDI)));
 
-  ManagedRegister reg_st0 = ManagedRegister::FromX87Register(ST0);
-  EXPECT_TRUE(!reg_st0.Equals(ManagedRegister::FromCpuRegister(EAX)));
-  EXPECT_TRUE(!reg_st0.Equals(ManagedRegister::FromCpuRegister(EBX)));
-  EXPECT_TRUE(!reg_st0.Equals(ManagedRegister::FromCpuRegister(EDI)));
-  EXPECT_TRUE(!reg_st0.Equals(ManagedRegister::FromXmmRegister(XMM0)));
-  EXPECT_TRUE(!reg_st0.Equals(ManagedRegister::FromXmmRegister(XMM7)));
-  EXPECT_TRUE(reg_st0.Equals(ManagedRegister::FromX87Register(ST0)));
-  EXPECT_TRUE(!reg_st0.Equals(ManagedRegister::FromX87Register(ST7)));
-  EXPECT_TRUE(!reg_st0.Equals(ManagedRegister::FromRegisterPair(EAX_EDX)));
-  EXPECT_TRUE(!reg_st0.Equals(ManagedRegister::FromRegisterPair(EBX_EDI)));
+  X86ManagedRegister reg_st0 = X86ManagedRegister::FromX87Register(ST0);
+  EXPECT_TRUE(!reg_st0.Equals(X86ManagedRegister::FromCpuRegister(EAX)));
+  EXPECT_TRUE(!reg_st0.Equals(X86ManagedRegister::FromCpuRegister(EBX)));
+  EXPECT_TRUE(!reg_st0.Equals(X86ManagedRegister::FromCpuRegister(EDI)));
+  EXPECT_TRUE(!reg_st0.Equals(X86ManagedRegister::FromXmmRegister(XMM0)));
+  EXPECT_TRUE(!reg_st0.Equals(X86ManagedRegister::FromXmmRegister(XMM7)));
+  EXPECT_TRUE(reg_st0.Equals(X86ManagedRegister::FromX87Register(ST0)));
+  EXPECT_TRUE(!reg_st0.Equals(X86ManagedRegister::FromX87Register(ST7)));
+  EXPECT_TRUE(!reg_st0.Equals(X86ManagedRegister::FromRegisterPair(EAX_EDX)));
+  EXPECT_TRUE(!reg_st0.Equals(X86ManagedRegister::FromRegisterPair(EBX_EDI)));
 
-  ManagedRegister reg_pair = ManagedRegister::FromRegisterPair(EAX_EDX);
-  EXPECT_TRUE(!reg_pair.Equals(ManagedRegister::FromCpuRegister(EAX)));
-  EXPECT_TRUE(!reg_pair.Equals(ManagedRegister::FromCpuRegister(EBX)));
-  EXPECT_TRUE(!reg_pair.Equals(ManagedRegister::FromCpuRegister(EDI)));
-  EXPECT_TRUE(!reg_pair.Equals(ManagedRegister::FromXmmRegister(XMM0)));
-  EXPECT_TRUE(!reg_pair.Equals(ManagedRegister::FromXmmRegister(XMM7)));
-  EXPECT_TRUE(!reg_pair.Equals(ManagedRegister::FromX87Register(ST0)));
-  EXPECT_TRUE(!reg_pair.Equals(ManagedRegister::FromX87Register(ST7)));
-  EXPECT_TRUE(reg_pair.Equals(ManagedRegister::FromRegisterPair(EAX_EDX)));
-  EXPECT_TRUE(!reg_pair.Equals(ManagedRegister::FromRegisterPair(EBX_EDI)));
+  X86ManagedRegister reg_pair = X86ManagedRegister::FromRegisterPair(EAX_EDX);
+  EXPECT_TRUE(!reg_pair.Equals(X86ManagedRegister::FromCpuRegister(EAX)));
+  EXPECT_TRUE(!reg_pair.Equals(X86ManagedRegister::FromCpuRegister(EBX)));
+  EXPECT_TRUE(!reg_pair.Equals(X86ManagedRegister::FromCpuRegister(EDI)));
+  EXPECT_TRUE(!reg_pair.Equals(X86ManagedRegister::FromXmmRegister(XMM0)));
+  EXPECT_TRUE(!reg_pair.Equals(X86ManagedRegister::FromXmmRegister(XMM7)));
+  EXPECT_TRUE(!reg_pair.Equals(X86ManagedRegister::FromX87Register(ST0)));
+  EXPECT_TRUE(!reg_pair.Equals(X86ManagedRegister::FromX87Register(ST7)));
+  EXPECT_TRUE(reg_pair.Equals(X86ManagedRegister::FromRegisterPair(EAX_EDX)));
+  EXPECT_TRUE(!reg_pair.Equals(X86ManagedRegister::FromRegisterPair(EBX_EDI)));
 }
 
-TEST(ManagedRegister, Overlaps) {
-  ManagedRegister reg = ManagedRegister::FromCpuRegister(EAX);
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromCpuRegister(EAX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EBX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EDI)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromXmmRegister(XMM0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromXmmRegister(XMM7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromX87Register(ST0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromX87Register(ST7)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromRegisterPair(EAX_EDX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(EBX_EDI)));
+TEST(X86ManagedRegister, Overlaps) {
+  X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX);
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromCpuRegister(EAX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EBX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EDI)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM7)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromX87Register(ST0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromX87Register(ST7)));
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromRegisterPair(EAX_EDX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromRegisterPair(EBX_EDI)));
 
-  reg = ManagedRegister::FromCpuRegister(EDX);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EAX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EBX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EDI)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromXmmRegister(XMM0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromXmmRegister(XMM7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromX87Register(ST0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromX87Register(ST7)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromRegisterPair(EAX_EDX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(EBX_EDI)));
+  reg = X86ManagedRegister::FromCpuRegister(EDX);
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EAX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EBX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EDI)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM7)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromX87Register(ST0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromX87Register(ST7)));
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromRegisterPair(EAX_EDX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromRegisterPair(EBX_EDI)));
 
-  reg = ManagedRegister::FromCpuRegister(EDI);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EAX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EBX)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromCpuRegister(EDI)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromXmmRegister(XMM0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromXmmRegister(XMM7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromX87Register(ST0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromX87Register(ST7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(EAX_EDX)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromRegisterPair(EBX_EDI)));
+  reg = X86ManagedRegister::FromCpuRegister(EDI);
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EAX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EBX)));
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromCpuRegister(EDI)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM7)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromX87Register(ST0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromX87Register(ST7)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromRegisterPair(EAX_EDX)));
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromRegisterPair(EBX_EDI)));
 
-  reg = ManagedRegister::FromCpuRegister(EBX);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EAX)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromCpuRegister(EBX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EDI)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromXmmRegister(XMM0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromXmmRegister(XMM7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromX87Register(ST0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromX87Register(ST7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(EAX_EDX)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromRegisterPair(EBX_EDI)));
+  reg = X86ManagedRegister::FromCpuRegister(EBX);
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EAX)));
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromCpuRegister(EBX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EDI)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM7)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromX87Register(ST0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromX87Register(ST7)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromRegisterPair(EAX_EDX)));
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromRegisterPair(EBX_EDI)));
 
-  reg = ManagedRegister::FromXmmRegister(XMM0);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EAX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EBX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EDI)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromXmmRegister(XMM0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromXmmRegister(XMM7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromX87Register(ST0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromX87Register(ST7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(EAX_EDX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(EBX_EDI)));
+  reg = X86ManagedRegister::FromXmmRegister(XMM0);
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EAX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EBX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EDI)));
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM7)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromX87Register(ST0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromX87Register(ST7)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromRegisterPair(EAX_EDX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromRegisterPair(EBX_EDI)));
 
-  reg = ManagedRegister::FromX87Register(ST0);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EAX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EBX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EDI)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromXmmRegister(XMM0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromXmmRegister(XMM7)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromX87Register(ST0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromX87Register(ST7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(EAX_EDX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(EBX_EDI)));
+  reg = X86ManagedRegister::FromX87Register(ST0);
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EAX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EBX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EDI)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM7)));
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromX87Register(ST0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromX87Register(ST7)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromRegisterPair(EAX_EDX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromRegisterPair(EBX_EDI)));
 
-  reg = ManagedRegister::FromRegisterPair(EAX_EDX);
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromCpuRegister(EAX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EBX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EDI)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromXmmRegister(XMM0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromXmmRegister(XMM7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromX87Register(ST0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromX87Register(ST7)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromRegisterPair(EAX_EDX)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromRegisterPair(EDX_ECX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(EBX_EDI)));
+  reg = X86ManagedRegister::FromRegisterPair(EAX_EDX);
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromCpuRegister(EAX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EBX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EDI)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM7)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromX87Register(ST0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromX87Register(ST7)));
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromRegisterPair(EAX_EDX)));
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromRegisterPair(EDX_ECX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromRegisterPair(EBX_EDI)));
 
-  reg = ManagedRegister::FromRegisterPair(EBX_EDI);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EAX)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromCpuRegister(EBX)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromCpuRegister(EDI)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromXmmRegister(XMM0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromXmmRegister(XMM7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromX87Register(ST0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromX87Register(ST7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(EAX_EDX)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromRegisterPair(EBX_EDI)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromRegisterPair(EDX_EBX)));
+  reg = X86ManagedRegister::FromRegisterPair(EBX_EDI);
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EAX)));
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromCpuRegister(EBX)));
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromCpuRegister(EDI)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM7)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromX87Register(ST0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromX87Register(ST7)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromRegisterPair(EAX_EDX)));
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromRegisterPair(EBX_EDI)));
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromRegisterPair(EDX_EBX)));
 
-  reg = ManagedRegister::FromRegisterPair(EDX_ECX);
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EAX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EBX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromCpuRegister(EDI)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromXmmRegister(XMM0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromXmmRegister(XMM7)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromX87Register(ST0)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromX87Register(ST7)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromRegisterPair(EAX_EDX)));
-  EXPECT_TRUE(!reg.Overlaps(ManagedRegister::FromRegisterPair(EBX_EDI)));
-  EXPECT_TRUE(reg.Overlaps(ManagedRegister::FromRegisterPair(EDX_EBX)));
+  reg = X86ManagedRegister::FromRegisterPair(EDX_ECX);
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EAX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EBX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromCpuRegister(EDI)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromXmmRegister(XMM7)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromX87Register(ST0)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromX87Register(ST7)));
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromRegisterPair(EAX_EDX)));
+  EXPECT_TRUE(!reg.Overlaps(X86ManagedRegister::FromRegisterPair(EBX_EDI)));
+  EXPECT_TRUE(reg.Overlaps(X86ManagedRegister::FromRegisterPair(EDX_EBX)));
 }
 
+}  // namespace x86
 }  // namespace art