Quick compiler, fix wide bug
In Dalvik, 64-bit data items are represented as a pair of 32-bit
registers. The Art compiler maintained this notation, while llvm
expects properly typed data. During the conversion to bitcode, we
must drop the high word of pairs, while correctly typing the low.
This CL fixes several bugs related to this. "Placeholder" llvm
Values are created only for the low word of pairs, and we now skip
Phi node generation for high words. Doing this required a bit
of tightening up of the size & type inference code (which previously
was able to get away with ignoring high words).
Also, I've moved shift operations into intrinics because Dalvik
and llvm have different ideas about what a shift means.
Bitcode generation is only supported for the Arm target at the
moment. With this CL, all target tests pass and the phone boots.
o Performance data is not yet meaningful, either compile or
o When configured for Quick, we run single-threaded.
o In a small percentage of methods, we generate invalid llvm
bitcode (missing exception edges). As-checked-in, llvm
function generation is turned off to avoid missing edge
complaints (to enable testing of the Quick backend).
8 files changed