commit 1ca98499b837491f2519ca7d7d42354a0dbd45a2
author Elliott Hughes <enh@google.com> Thu Apr 12 17:21:02 2012 -0700
committer Elliott Hughes <enh@google.com> Thu Apr 12 17:29:48 2012 -0700
tree 3dc254a33a6052478101f50500e07d7f90adcc6c
parent a47468765b3c314b4b76959e3976af4f012bc533

Fix ARM disassembly of LDR/STR offsets, always include the sign in branch offsets.

Examples:

            0x60cdd80c: e599c1e4    ldr     r12, [r9, #484]  ; pDeliverException

            0x60cdd7c4: 1a00000b    bne     +44 (0x60cdd7f8)
            0x60cdd804: eaffffef    b       -68 (0x60cdd7c8)

I now believe the entire disassembly of our JNI stubs.

Change-Id: Ibf4ae7e767054e78b8e763cb20eea6b73fb6f0e7

src/disassembler_arm.cc

diff --git a/src/disassembler_arm.cc b/src/disassembler_arm.cc
index 18bd0f4..b5ef6a5 100644
--- a/src/disassembler_arm.cc
+++ b/src/disassembler_arm.cc
@@ -71,7 +71,7 @@
 }
 
 void DisassemblerArm::DumpBranchTarget(std::ostream& os, const uint8_t* instr_ptr, int32_t imm32) {
-  os << imm32 << " (" << reinterpret_cast<const void*>(instr_ptr + imm32) << ")";
+  os << StringPrintf("%+d (%p)", imm32, instr_ptr + imm32);
 }
 
 static uint32_t ReadU16(const uint8_t* ptr) {
@@ -127,15 +127,15 @@
   return os;
 }
 
-struct Imm12 {
-  Imm12(uint32_t instruction) {
+struct ShiftedImmediate {
+  ShiftedImmediate(uint32_t instruction) {
     uint32_t rotate = ((instruction >> 8) & 0xf);
     uint32_t imm = (instruction & 0xff);
     value = (imm >> (2 * rotate)) | (imm << (32 - (2 * rotate)));
   }
   uint32_t value;
 };
-std::ostream& operator<<(std::ostream& os, const Imm12& rhs) {
+std::ostream& operator<<(std::ostream& os, const ShiftedImmediate& rhs) {
   os << "#" << rhs.value;
   return os;
 }
@@ -202,7 +202,7 @@
           args << ArmRegister(instruction, 12) << ", ";
         }
         if (i) {
-          args << ArmRegister(instruction, 16) << ", " << Imm12(instruction);
+          args << ArmRegister(instruction, 16) << ", " << ShiftedImmediate(instruction);
         } else {
           args << Rm(instruction);
         }
@@ -221,18 +221,19 @@
           UNIMPLEMENTED(FATAL) << "literals";
         } else {
           bool wback = !p || w;
+          uint32_t offset = (instruction & 0xfff);
           if (p && !wback) {
-            args << "[" << rn << ", " << Imm12(instruction) << "]";
+            args << "[" << rn << ", #" << offset << "]";
           } else if (p && wback) {
-            args << "[" << rn << ", " << Imm12(instruction) << "]!";
+            args << "[" << rn << ", #" << offset << "]!";
           } else if (!p && wback) {
-            args << "[" << rn << "], " << Imm12(instruction);
+            args << "[" << rn << "], #" << offset;
           } else {
             LOG(FATAL) << p << " " << w;
           }
           if (rn.r == 9) {
             args << "  ; ";
-            Thread::DumpThreadOffset(args, Imm12(instruction).value, 4);
+            Thread::DumpThreadOffset(args, offset, 4);
           }
         }
       }