[Sim] Add a restricted mode setup
This CL introduces a special ART setup for all modes (host, target),
which is going to be a base for VIXL Simulator Stage 1 setup. This
setup can be enabled by exporting ART_USE_RESTRICTED_MODE=true to the
environment before building ART. The setup limits ART by doing the
following:
- Limits the GC to only non-concurent Mark&Sweep.
- Turns off the Nterp (so only switch C++ intepreter to be used).
- Turns off the JNI compiler (GenericJNITrampoline to be used).
- Rejects the compilation of all method (except for the allow list).
- Turns off compilation and support of intrinsics.
- Turns off implicit null checks.
- Turns off implicit suspend checks.
- Turns off introspection entrypoints.
- Turns off special behavior for critical native methods.
- Turns off compiler CHECKER tool.
With these limitations it will be easier to start off an initial
Simulator Stage 1 setup. As the limitations are set for all the modes,
it will be easy to compare/debug the workflow for the simulator mode
and to compare it to host and target runs.
The CL also adds sections in knownfailures.json for tests that fail
in this special setup.
Also cleanup some read barrier entrypoint declarations in
entrypoints_init_arm64.cc to match the definitions in
quick_entrypoints_arm64.S and slightly refactor Runtime::Init to stay
below the 500 line limit.
Author: Artem Serov <artem.serov@linaro.org>
Artem Serov <artem.serov@arm.com>
Chris Jones <christopher.jones@arm.com>
Test: export ART_USE_RESTRICTED_MODE=true
test.py --host --target
Change-Id: I87319cf339646dc13b9086b00af08882b01603c8
22 files changed
