commit 09cd727b48560836b7cc1341c00e980fae71ebc8
author jeffhao <jeffhao@google.com> Mon Oct 29 16:37:01 2012 -0700
committer jeffhao <jeffhao@google.com> Mon Oct 29 16:37:01 2012 -0700
tree 84af874eca6e1b1049a32a9b57c101509d19b36e
parent 2a85d8d034863df3c5ee156a140d0bd88b2b9224

Fix for MIPS long subtraction when source and destination are same.

MIPS emulator boots and works now, passing all vm-tests except one
invoke-super test.

Change-Id: I3bd27f9a582412900c08f5771d5dd76749d9de89

src/compiler/codegen/mips/ArchFactory.cc

diff --git a/src/compiler/codegen/mips/ArchFactory.cc b/src/compiler/codegen/mips/ArchFactory.cc
index f51e722..e2d9e91 100644
--- a/src/compiler/codegen/mips/ArchFactory.cc
+++ b/src/compiler/codegen/mips/ArchFactory.cc
@@ -58,16 +58,16 @@
   RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
   /*
    *  [v1 v0] =  [a1 a0] - [a3 a2];
+   *  sltu  t1,a0,a2
    *  subu  v0,a0,a2
    *  subu  v1,a1,a3
-   *  sltu  t1,a0,v0
    *  subu  v1,v1,t1
    */
 
+  int tReg = oatAllocTemp(cUnit);
+  newLIR3(cUnit, kMipsSltu, tReg, rlSrc1.lowReg, rlSrc2.lowReg);
   opRegRegReg(cUnit, kOpSub, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
   opRegRegReg(cUnit, kOpSub, rlResult.highReg, rlSrc1.highReg, rlSrc2.highReg);
-  int tReg = oatAllocTemp(cUnit);
-  newLIR3(cUnit, kMipsSltu, tReg, rlSrc1.lowReg, rlResult.lowReg);
   opRegRegReg(cUnit, kOpSub, rlResult.highReg, rlResult.highReg, tReg);
   oatFreeTemp(cUnit, tReg);
   storeValueWide(cUnit, rlDest, rlResult);