| ArmConditionCode ArmConditionEncoding(ConditionCode code); |
| AssemblerStatus AssembleInstructions(CompilationUnit* cu, uintptr_t start_addr); |
| bool DoubleReg(int reg); |
| bool FpReg(int reg); |
| bool GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
| bool GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
| bool GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
| bool GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
| bool GenArithOpFloat(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
| bool GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
| bool GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); |
| bool GenInlinedCas32(CompilationUnit* cu, CallInfo* info, bool need_write_barrier); |
| bool GenInlinedMinMaxInt(CompilationUnit *cu, CallInfo* info, bool is_min); |
| bool GenInlinedSqrt(CompilationUnit* cu, CallInfo* info); |
| bool GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src); |
| bool GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
| bool GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
| bool GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
| bool ArchInit(); |
| bool ArchVariantInit(void); |
| bool IsFpReg(int reg); |
| bool SameRegType(int reg1, int reg2); |
| bool SingleReg(int reg); |
| bool SmallLiteralDivide(CompilationUnit* cu, Instruction::Code dalvik_opcode, RegLocation rl_src, RegLocation rl_dest, int lit); |
| RegisterInfo* GetRegInfo(CompilationUnit* cu, int reg); |
| RegLocation GetReturnAlt(CompilationUnit* cu); |
| RegLocation GetReturnWideAlt(CompilationUnit* cu); |
| void ClobberCalleeSave(CompilationUnit *cu); |
| void FreeCallTemps(CompilationUnit* cu); |
| void LockCallTemps(CompilationUnit* cu); |
| InstructionSet InstructionSet(); |
| int EncodeShift(int code, int amount); |
| int LoadHelper(CompilationUnit* cu, int offset); |
| int ModifiedImmediate(uint32_t value); |
| int AllocTypedTemp(CompilationUnit* cu, bool fp_hint, int reg_class); |
| int AllocTypedTempPair(CompilationUnit* cu, bool fp_hint, int reg_class); |
| int AssignInsnOffsets(CompilationUnit* cu); |
| int GetInsnSize(LIR* lir); |
| int S2d(int low_reg, int high_reg); |
| int TargetReg(SpecialTargetRegister reg); |
| LIR* FpRegCopy(CompilationUnit* cu, int r_dest, int r_src); |
| LIR* GenRegMemCheck(CompilationUnit* cu, ConditionCode c_code, int reg1, int base, int offset, ThrowKind kind); |
| LIR* LoadBaseDispBody(CompilationUnit* cu, int rBase, int displacement, int r_dest, int r_dest_hi, OpSize size, int s_reg); |
| LIR* LoadBaseDisp(CompilationUnit* cu, int rBase, int displacement, int r_dest, OpSize size, int s_reg); |
| LIR* LoadBaseDispWide(CompilationUnit* cu, int rBase, int displacement, int r_dest_lo, int r_dest_hi, int s_reg); |
| LIR* LoadBaseIndexed(CompilationUnit* cu, int rBase, int r_index, int r_dest, int scale, OpSize size); |
| LIR* LoadBaseIndexedDisp(CompilationUnit *cu, int rBase, int r_index, int scale, int displacement, int r_dest, int r_dest_hi, OpSize size, int s_reg); |
| LIR* LoadConstantNoClobber(CompilationUnit* cu, int r_dest, int value); |
| LIR* LoadConstantValueWide(CompilationUnit* cu, int r_dest_lo, int r_dest_hi, int val_lo, int val_hi); |
| LIR* LoadMultiple(CompilationUnit *cu, int rBase, int r_mask); |
| LIR* OpBranchUnconditional(CompilationUnit* cu, OpKind op); |
| LIR* OpCmpBranch(CompilationUnit* cu, ConditionCode cond, int src1, int src2, LIR* target); |
| LIR* OpCmpImmBranch(CompilationUnit* cu, ConditionCode cond, int reg, int check_value, LIR* target); |
| LIR* OpCondBranch(CompilationUnit* cu, ConditionCode cc, LIR* target); |
| LIR* OpDecAndBranch(CompilationUnit* cu, ConditionCode c_code, int reg, LIR* target); |
| LIR* OpIT(CompilationUnit* cu, ArmConditionCode cond, const char* guide); |
| LIR* OpMem(CompilationUnit* cu, OpKind op, int rBase, int disp); |
| LIR* OpPcRelLoad(CompilationUnit* cu, int reg, LIR* target); |
| LIR* OpReg(CompilationUnit* cu, OpKind op, int r_dest_src); |
| LIR* OpRegCopy(CompilationUnit* cu, int r_dest, int r_src); |
| LIR* OpRegCopyNoInsert(CompilationUnit* cu, int r_dest, int r_src); |
| LIR* OpRegImm(CompilationUnit* cu, OpKind op, int r_dest_src1, int value); |
| LIR* OpRegMem(CompilationUnit* cu, OpKind op, int r_dest, int rBase, int offset); |
| LIR* OpRegReg(CompilationUnit* cu, OpKind op, int r_dest_src1, int r_src2); |
| LIR* OpRegRegImm(CompilationUnit* cu, OpKind op, int r_dest, int r_src1, int value); |
| LIR* OpRegRegReg(CompilationUnit* cu, OpKind op, int r_dest, int r_src1, int r_src2); |
| LIR* OpRegRegRegShift(CompilationUnit* cu, OpKind op, int r_dest, int r_src1, int r_src2, int shift); |
| LIR* OpRegRegShift(CompilationUnit* cu, OpKind op, int r_dest_src1, int r_src2, int shift); |
| LIR* OpTestSuspend(CompilationUnit* cu, LIR* target); |
| LIR* OpThreadMem(CompilationUnit* cu, OpKind op, int thread_offset); |
| LIR* OpVldm(CompilationUnit* cu, int rBase, int count); |
| LIR* OpVstm(CompilationUnit* cu, int rBase, int count); |
| LIR* StoreBaseDispBody(CompilationUnit* cu, int rBase, int displacement, int r_src, int r_src_hi, OpSize size); |
| LIR* StoreBaseDisp(CompilationUnit* cu, int rBase, int displacement, int r_src, OpSize size); |
| LIR* StoreBaseDispWide(CompilationUnit* cu, int rBase, int displacement, int r_src_lo, int r_src_hi); |
| LIR* StoreBaseIndexed(CompilationUnit* cu, int rBase, int r_index, int r_src, int scale, OpSize size); |
| LIR* StoreBaseIndexedDisp(CompilationUnit *cu, int rBase, int r_index, int scale, int displacement, int r_src, int r_src_hi, OpSize size, int s_reg); |
| LIR* StoreMultiple(CompilationUnit *cu, int rBase, int r_mask); |
| RegLocation ArgLoc(CompilationUnit* cu, RegLocation loc); |
| RegLocation GenDivRem(CompilationUnit* cu, RegLocation rl_dest, int reg_lo, int reg_hi, bool is_div); |
| RegLocation GenDivRemLit(CompilationUnit* cu, RegLocation rl_dest, int reg_lo, int lit, bool is_div); |
| RegLocation LoadArg(CompilationUnit* cu, RegLocation loc); |
| RegLocation LocCReturn(); |
| RegLocation LocCReturnDouble(); |
| RegLocation LocCReturnFloat(); |
| RegLocation LocCReturnWide(); |
| std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); |
| uint64_t GetRegMaskCommon(CompilationUnit* cu, int reg); |
| uint32_t FpRegMask(); |
| uint32_t FpRegMask(); |
| uint64_t GetPCUseDefEncoding(); |
| void FreeRegLocTemps(CompilationUnit* cu, RegLocation rl_keep, RegLocation rl_free); |
| void GenCmpLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
| void GenDivZeroCheck(CompilationUnit* cu, int reg_lo, int reg_hi); |
| void GenEntrySequence(CompilationUnit* cu, RegLocation* ArgLocs, RegLocation rl_method); |
| void GenExitSequence(CompilationUnit* cu); |
| void GenFillArrayData(CompilationUnit* cu, uint32_t table_offset, RegLocation rl_src); |
| void GenFusedFPCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); |
| void GenFusedLongCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir); |
| void GenMonitorEnter(CompilationUnit* cu, int opt_flags, RegLocation rl_src); |
| void GenMonitorExit(CompilationUnit* cu, int opt_flags, RegLocation rl_src); |
| void GenMultiplyByTwoBitMultiplier(CompilationUnit* cu, RegLocation rl_src, RegLocation rl_result, int lit, int first_bit, int second_bit); |
| void GenNegDouble(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src); |
| void GenNegFloat(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src); |
| void GenPackedSwitch(CompilationUnit* cu, uint32_t table_offset, RegLocation rl_src); |
| void GenPrintLabel(CompilationUnit *cu, MIR* mir); |
| void GenSparseSwitch(CompilationUnit* cu, uint32_t table_offset, RegLocation rl_src); |
| void GenSpecialCase(CompilationUnit* cu, BasicBlock* bb, MIR* mir, SpecialCaseHandler special_case); |
| void LoadPair(CompilationUnit* cu, int base, int low_reg, int high_reg); |
| void MarkGCCard(CompilationUnit* cu, int val_reg, int tgt_addr_reg); |
| void AdjustSpillMask(CompilationUnit* cu); |
| void ClobberCalleeSave(CompilationUnit *cu); |
| void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix); |
| void FlushReg(CompilationUnit* cu, int reg); |
| void FlushRegWide(CompilationUnit* cu, int reg1, int reg2); |
| void GenMemBarrier(CompilationUnit* cu, MemBarrierKind barrier_kind); |
| void CompilerInitializeRegAlloc(CompilationUnit* cu); |
| void MarkPreservedSingle(CompilationUnit* cu, int v_reg, int reg); |
| void NopLIR( LIR* lir); |
| void OpLea(CompilationUnit* cu, int rBase, int reg1, int reg2, int scale, int offset); |
| void OpRegCopyWide(CompilationUnit* cu, int dest_lo, int dest_hi, int src_lo, int src_hi); |
| void OpRegThreadMem(CompilationUnit* cu, OpKind op, int r_dest, int thread_offset); |
| void OpTlsCmp(CompilationUnit* cu, int offset, int val); |
| bool BranchUnconditional(LIR* lir); |
| void SetupTargetResourceMasks(CompilationUnit* cu, LIR* lir); |
| void SpillCoreRegs(CompilationUnit* cu); |
| void UnSpillCoreRegs(CompilationUnit* cu); |
| X86ConditionCode X86ConditionEncoding(ConditionCode cond); |
| uint64_t GetTargetInstFlags(int opcode); |
| const char* GetTargetInstName(int opcode); |
| const char* GetTargetInstFmt(int opcode); |
