| NVIDIA TEGRA124 High Definition Multimedia Interface |
| ==================================================== |
| |
| 1) The hdmi node: |
| hdmi node must be contained in host1x parent node. This node represents NVIDIA TEGRA124 |
| High Definition Multimedia Interface. |
| |
| Required properties |
| - name: hdmi |
| - compatible: Should contain "nvidia,tegra124-hdmi". |
| - reg: Physical base address and length of the controller's registers. |
| - interrupts: The interrupt outputs from the controller. |
| |
| Optional properties: |
| - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing |
| - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection |
| - nvidia,edid: supplies a binary EDID blob |
| - nvidia,hotplug-report: With 1, it will have optional hotplug report callback |
| which does only set DDC_SDA and DDC_SCL pull downs to be active when hotplug |
| is detected, otherwise keep them disabled. |
| |
| 1.A) The hdmi-display node: |
| hdmi-display must be contained in hdmi parent node. This node represents hdmi display node. |
| |
| Required properties |
| - name: hdmi-display |
| |
| - Child nodes represent tmds configurations, node of modes, output settings, |
| smart dimmer settings, color management unit settings. |
| |
| 1.A.i) NVIDIA Display Controller Modes |
| This must be contained in hdmi-display parent node. This contains supported modes. |
| |
| Required properties: |
| - name: Should be "display-timings" |
| |
| - Child nodes represent modes. Several modes can be prepared. |
| |
| 1.A.i.x) NVIDIA Display Controller Mode timing |
| This must be contained in display-timings parent node. This contains mode settings, including |
| display timings. For hdmi out-type case, display-timings properties are only valid in case of |
| hdmi fb console mode. |
| |
| Required properties: |
| - name: Can be arbitrary, but each sibling node should have unique name. |
| - hactive, vactive: display resolution. |
| - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters |
| in pixels. |
| - vfront-porch, vback-porch, vsync-len: vertical display timing parameters in |
| lines. |
| - clock-frequency: display clock in Hz. |
| - nvidia,h-ref-to-sync: H reference to HSYNC. This specifies the start position of HSYNC |
| with respect to H reference point. |
| - nvidia,v-ref-to-sync: V reference to VSYNC. This specifies the start position of VSYNC |
| with respect to V reference point. |
| |
| 1.A.j) NVIDIA Display Default Output Settings |
| This must be contained in hdmi-display parent node. This is default output settings. |
| |
| Required properties: |
| - name: Should be "disp-default-out". |
| - nvidia,out-width: Width in struct fb_var_screeninfo. width of picture in mm. |
| - nvidia,out-height: Height in struct fb_var_screeninfo. height of picture in mm. |
| - nvidia,out-flags: One item or an array of several tuples items can be chosen. |
| List of items is TEGRA_DC_OUT_HOTPLUG_HIGH, TEGRA_DC_OUT_HOTPLUG_LOW, |
| TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND, TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON, |
| TEGRA_DC_OUT_CONTINUOUS_MODE, TEGRA_DC_OUT_ONE_SHOT_MODE, |
| TEGRA_DC_OUT_N_SHOT_MODE, TEGRA_DC_OUT_ONE_SHOT_LP_MODE, |
| TEGRA_DC_OUT_INITIALIZED_MODE and TEGRA_DC_OUT_HOTPLUG_WAKE_LP0. |
| If several items are written, bitwise OR is operated for them, internally. |
| - nvidia,out-parent-clk: Parent clk for display controller. |
| - nvidia,out-max-pixclk: Maximum pixel clock in pico-seconds. |
| - nvidia,out-align: Display data alignment. Should be TEGRA_DC_ALIGN_MSB or TEGRA_DC_ALIGN_LSB. |
| - nvidia,out-order: Display data order. Should be TEGRA_DC_ORDER_RED_BLUE or |
| TEGRA_DC_ORDER_BLUE_RED. |
| - nvidia,out-depth: Display base color size. 3, 6, 8, 9, 12, 15, 16, 18 and 24 for |
| BASE_COLOR_SIZE111, BASE_COLOR_SIZE222, BASE_COLOR_SIZE332, BASE_COLOR_SIZE333, |
| BASE_COLOR_SIZE444, BASE_COLOR_SIZE555, BASE_COLOR_SIZE565, BASE_COLOR_SIZE666, |
| and BASE_COLOR_SIZE888, respectively. In default, BASE_COLOR_SIZE888 is chosen. |
| For hdmi out-type case, depth selection is only valid for hdmi fb console mode, |
| otherwise, BASE_COLOR_SIZE888 is chosen as a default. |
| - nvidia,out-xres: Visible resolution for width. |
| - nvidia,out-yres: Visible resolution for height. |
| |
| 1.A.k) NVIDIA Display Controller Smart Dimmer Settings |
| This must be contained in hdmi-display parent node. This is smart dimmer settings. |
| |
| Required properties: |
| - name: Should be "smartdimmer". |
| - nvidia,use-auto-pwm: With enabled, hardware adjust the backlight PWM control |
| signal directly. |
| - nvidia,hw-update-delay: It determines the delay of the update of the hardware |
| enhancement value (K) that is applied to the pixels. |
| - nvidia,bin-width: It is the width of the histogram bins, in quantisation level. |
| 0xffffffff, 1, 2, 4 or 8 can be written, 0xffffffff, which means 2's compliment |
| of -1, indicates automatic based on aggressiveness. |
| - nvidia,aggressiveness: The aggressiveness level of the smart dimmer algorithm. |
| - nvidia,use-vid-luma: With enabled, it uses video luminance control of luminance. |
| - nvidia,phase-in-adjustments: Software backlight phase-in |
| - nvidia,k-limit-enable: When enabled, Max.K is taken from K_LIMIT register (nvidia,k-limit) |
| rather than computed from nvidia,aggressiveness. |
| - nvidia,k-limit: When nvidia,k-limit-enable is enabled, limits raw K independently of |
| aggressiveness. |
| - nvidia,sd-window-enable: When enabled, constrain histogram (and therefore backlight) |
| to a rectangular subset of display. |
| - nvidia,soft-clipping-enable: When enabled, enhancement gain (K) is reduced for pixels |
| above nvidia,soft-clipping-threshold level to avoid saturation. |
| - nvidia,soft-clipping-threshold: Threshold at which pixel enhancement gain is reduced. |
| - nvidia,smooth-k-enable: When enabled, max raw K change per frame is limited to |
| nvidia,smooth-k-incr. |
| - nvidia,smooth-k-incr: When nvidia,smooth-k-enable is enabled, the raw K is changed |
| at most by smooth-k-incr per frame. |
| - nvidia,coeff: Luminance calculation coefficients used to convert the red green and |
| blue color components into a luminance value. The conversion is performed according to |
| the following equation: Luminance = (R*R_COEFF + G*G_COEFF + B*B_COEFF) >> 4. |
| Need to write blue, green, red coefficient for luminance calculation in sequence. |
| - nvidia,fc: Flicker control that prevents rapid and frequent changes |
| in the enhancement value. Need to write time_limit, threshold in sequence. |
| - nvidia,blp: Defines the parameters for the backlight temporal response model. Need to |
| write time_constant for the response curve and step that determines the instantaneous |
| portion of the target value of enhancement that is applied: <time_constant, step>. |
| - nvidia,bltf: Backlight transfer function. Each points on the transfer function curve |
| defines how the backlight output changes with respect to the control input. The 17th point |
| is defined to be the maximum value. |
| - nvidia,lut: Enhancement value (K) look up table. each LUT entry contains the value of k |
| for each of the three color components (R_LUT, G_LUT, B_LUT in sequence). |
| There are nine entries in total. |
| - nvidia,use-vpulse2: With enabled, run histogram on vpulse2 rather than vsync. |
| - nvidia,bl-device-name: Backlight device name. |
| |
| 1.A.l) NVIDIA Display Controller Color Management Unit Settings |
| This must be contained in hdmi-display node. This is color management unit settings. |
| |
| Required properties: |
| - name: Should be "cmu". |
| - nvidia,cmu-csc: CMU color space conversion matrix. It is 3X3 matrix. |
| - nvidia,cmu-lut2: CMU LUT2. Should be 960 u8 arrays. |
| |
| 1.A.m) NVIDIA HDMI TMDS configurations |
| This must be contained in hdmi-display parent node. This includes tmds configurations. |
| |
| Required properties: |
| - name: Should be "tmds-config" |
| |
| - Child nodes represent tmds configurations. Several configurations can be prepared. |
| |
| 1.A.m.x) NVIDIA HDMI TMDS configuration |
| This must be contained in tmds-config parent node. This includes tmds configuration. |
| |
| Required properties: |
| - name: Can be arbitrary, but each sibling node should have unique name. |
| - version: tmds configuration version. two tuples items needs to be written.: <major minor> |
| - pclk: pixel clk required in tmds table for each mode. |
| - pll0: See HDMI_NV_PDISP_SOR_PLL0_0 in Tegra TRM. |
| - pll1: See HDMI_NV_PDISP_SOR_PLL1_0 in Tegra TRM. |
| - pe-current: Individual lane pre-emphasis current control (4bits per lane) |
| See HDMI_NV_PDISP_PE_CURRENT_0 in Tegra TRM. |
| - drive-current: TMDS per-lane I/O current control. |
| See HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_0 in Tegra TRM. |
| - peak-current: New pad controls for 28nm macro TMDS_X4_HP 8 bits per lane. |
| See HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_0 in Tegra TRM. |
| - pad-ctls0-mask: HDMI_NV_PDISP_SOR_PAD_CTLS0_0 register and mask. |
| - pad-ctls0-setting: HDMI_NV_PDISP_SOR_PAD_CTLS0_0 register or mask. |
| |
| Example |
| |
| host1x { |
| hdmi { |
| status = "okay"; |
| compatible = "nvidia,tegra124-hdmi"; |
| reg = <0x54280000 0x00040000>; |
| interrupts = <0 75 0x04>; |
| nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
| nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 1>; /* PN7 */ |
| hdmi-display { |
| status = "okay"; |
| disp-default-out { |
| nvidia,out-flags = <TEGRA_DC_OUT_HOTPLUG_HIGH>; |
| nvidia,out-parent-clk = "pll_d2"; |
| nvidia,out-max-pixclk = <3367>; /* KHZ2PICOS(297000) */ |
| nvidia,out-align = <TEGRA_DC_ALIGN_MSB>; |
| nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>; |
| nvidia,out-xres = <1920>; |
| nvidia,out-yres = <1080>; |
| }; |
| tmds-config { |
| tmds-cfg@0 { |
| version = <1 0>; |
| pclk = <27000000>; |
| pll0 = <0x01003010>; |
| pll1 = <0x00301b00>; |
| pe-current = <0x00000000>; |
| drive-current = <0x1f1f1f1f>; |
| peak-current = <0x03030303>; |
| pad-ctls0-mask = <0xfffff0ff>; |
| pad-ctls0-setting = <0x00000400>; |
| }; |
| tmds-cfg@1 { |
| version = <1 0>; |
| pclk = <74250000>; |
| pll0 = <0x01003110>; |
| pll1 = <0x00301500>; |
| pe-current = <0x00000000>; |
| drive-current = <0x2c2c2c2c>; |
| peak-current = <0x07070707>; |
| pad-ctls0-mask = <0xfffff0ff>; |
| pad-ctls0-setting = <0x00000400>; |
| }; |
| tmds-cfg@2 { |
| version = <1 0>; |
| pclk = <148500000>; |
| pll0 = <0x01003310>; |
| pll1 = <0x00301500>; |
| pe-current = <0x00000000>; |
| drive-current = <0x33333333>; |
| peak-current = <0x0c0c0c0c>; |
| pad-ctls0-mask = <0xfffff0ff>; |
| pad-ctls0-setting = <0x00000400>; |
| }; |
| tmds-cfg@3 { |
| version = <1 0>; |
| pclk = <0x7fffffff>; |
| pll0 = <0x01003f10>; |
| pll1 = <0x00300f00>; |
| pe-current = <0x00000000>; |
| drive-current = <0x37373737>; |
| peak-current = <0x17171717>; |
| pad-ctls0-mask = <0xfffff0ff>; |
| pad-ctls0-setting = <0x00000600>; |
| }; |
| }; |
| }; |
| }; |
| }; |
| hdmi_ddc: i2c@7000c700 { |
| clock-frequency = <100000>; |
| }; |