ARM: tegra: power: Add read fences in power gating
To assure post of the previous writes through Tegra interconnect
added read fences in the following power gating code paths:
- Seconadry CPU boot ungating (path taken on Tegra11, Tegra14, Tegra12)
- GPU rail clamps gating/ungating (path taken on Tegra12, Tegra13)
- MC client ungating flush done (path taken on all platforms)
Bug 1484343
Change-Id: Ie09ef37135beae0ed0beb1cd4d7e96187ba9be26
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/385403
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 50659ca..f755f93 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -269,6 +269,7 @@
reg = PMC_TOGGLE_START | TEGRA_CPU_POWERGATE_ID(cpu);
pmc_writel(reg, PWRGATE_TOGGLE);
+ pmc_readl(PWRGATE_TOGGLE);
}
return 0;
diff --git a/arch/arm/mach-tegra/powergate-t11x.c b/arch/arm/mach-tegra/powergate-t11x.c
index b846660..954d3a3 100644
--- a/arch/arm/mach-tegra/powergate-t11x.c
+++ b/arch/arm/mach-tegra/powergate-t11x.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -505,6 +505,7 @@
rst_ctrl = mc_read(MC_CLIENT_HOTRESET_CTRL);
rst_ctrl &= ~(1 << mcClientBit);
mc_write(rst_ctrl, MC_CLIENT_HOTRESET_CTRL);
+ mc_read(MC_CLIENT_HOTRESET_CTRL);
spin_unlock_irqrestore(&tegra11x_powergate_lock, flags);
}
diff --git a/arch/arm/mach-tegra/powergate-t12x.c b/arch/arm/mach-tegra/powergate-t12x.c
index 4998e2c..05764cc 100644
--- a/arch/arm/mach-tegra/powergate-t12x.c
+++ b/arch/arm/mach-tegra/powergate-t12x.c
@@ -393,6 +393,7 @@
rst_ctrl = mc_read(rst_ctrl_reg);
rst_ctrl &= ~(1 << mcClientBit);
mc_write(rst_ctrl, rst_ctrl_reg);
+ mc_read(rst_ctrl_reg);
spin_unlock_irqrestore(&tegra12x_powergate_lock, flags);
}
@@ -416,6 +417,7 @@
/* enable clamp */
pmc_write(0x1, PMC_GPU_RG_CNTRL_0);
+ pmc_read(PMC_GPU_RG_CNTRL_0);
udelay(10);
@@ -488,6 +490,7 @@
/* disable clamp */
pmc_write(0, PMC_GPU_RG_CNTRL_0);
+ pmc_read(PMC_GPU_RG_CNTRL_0);
udelay(10);
diff --git a/arch/arm/mach-tegra/powergate-t14x.c b/arch/arm/mach-tegra/powergate-t14x.c
index cb1e1e2..2ee85b5 100644
--- a/arch/arm/mach-tegra/powergate-t14x.c
+++ b/arch/arm/mach-tegra/powergate-t14x.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -459,6 +459,7 @@
rst_ctrl = mc_read(MC_CLIENT_HOTRESET_CTRL);
rst_ctrl &= ~(1 << mcClientBit);
mc_write(rst_ctrl, MC_CLIENT_HOTRESET_CTRL);
+ mc_read(MC_CLIENT_HOTRESET_CTRL);
spin_unlock_irqrestore(&tegra14x_powergate_lock, flags);
}
diff --git a/arch/arm/mach-tegra/powergate-t30.c b/arch/arm/mach-tegra/powergate-t30.c
index 14a5f75..8612873 100644
--- a/arch/arm/mach-tegra/powergate-t30.c
+++ b/arch/arm/mach-tegra/powergate-t30.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2012-214, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -308,7 +308,7 @@
rst_ctrl = mc_read(MC_CLIENT_HOTRESET_CTRL);
rst_ctrl &= ~(1 << mcClientBit);
mc_write(rst_ctrl, MC_CLIENT_HOTRESET_CTRL);
-
+ mc_read(MC_CLIENT_HOTRESET_CTRL);
spin_unlock_irqrestore(&tegra3_powergate_lock, flags);
}
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index cf576fc..1c41ae3 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -85,6 +85,7 @@
/* CPU ungated in s/w only during boot/resume with outer
waiting loop and no contention from other CPUs */
pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
+ pmc_read(PWRGATE_TOGGLE);
spin_unlock_irqrestore(lock, flags);
return 0;
}
