blob: 4635c4ab2a3c4972d9cdf0a908b684a29d50517d [file] [log] [blame]
/*
* IOMMU API for ARM architected SMMU implementations.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2013 ARM Limited
*
* Author: Will Deacon <will.deacon@arm.com>
*
* This driver currently supports:
* - SMMUv1 and v2 implementations
* - Stream-matching and stream-indexing
* - v7/v8 long-descriptor format
* - Non-secure access to the SMMU
* - Context fault reporting
* - Extended Stream ID (16 bit)
*/
#define pr_fmt(fmt) "arm-smmu: " fmt
#include <linux/acpi.h>
#include <linux/acpi_iort.h>
#include <linux/atomic.h>
#include <linux/delay.h>
#include <linux/dma-iommu.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/io-64-nonatomic-hi-lo.h>
#include <linux/iommu.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_iommu.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <soc/qcom/secure_buffer.h>
#include <linux/of_platform.h>
#include <linux/msm-bus.h>
#include <trace/events/iommu.h>
#include <dt-bindings/msm/msm-bus-ids.h>
#include <linux/irq.h>
#include <linux/wait.h>
#include <linux/amba/bus.h>
#include <soc/qcom/msm_tz_smmu.h>
#include <soc/qcom/scm.h>
#include "io-pgtable.h"
#include "arm-smmu-regs.h"
/*
* Apparently, some Qualcomm arm64 platforms which appear to expose their SMMU
* global register space are still, in fact, using a hypervisor to mediate it
* by trapping and emulating register accesses. Sadly, some deployed versions
* of said trapping code have bugs wherein they go horribly wrong for stores
* using r31 (i.e. XZR/WZR) as the source register.
*/
#define QCOM_DUMMY_VAL -1
#define ARM_MMU500_ACTLR_CPRE (1 << 1)
#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
#define ARM_MMU500_ACR_SMTNMB_TLBEN (1 << 8)
#define TLB_LOOP_TIMEOUT 500000 /* 500ms */
#define TLB_SPIN_COUNT 10
#define ARM_SMMU_IMPL_DEF0(smmu) \
((smmu)->base + (2 * (1 << (smmu)->pgshift)))
#define ARM_SMMU_IMPL_DEF1(smmu) \
((smmu)->base + (6 * (1 << (smmu)->pgshift)))
/* Maximum number of context banks per SMMU */
#define ARM_SMMU_MAX_CBS 128
/* SMMU global address space */
#define ARM_SMMU_GR0(smmu) ((smmu)->base)
#define ARM_SMMU_GR1(smmu) ((smmu)->base + (1 << (smmu)->pgshift))
/*
* SMMU global address space with conditional offset to access secure
* aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
* nsGFSYNR0: 0x450)
*/
#define ARM_SMMU_GR0_NS(smmu) \
((smmu)->base + \
((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \
? 0x400 : 0))
/*
* Some 64-bit registers only make sense to write atomically, but in such
* cases all the data relevant to AArch32 formats lies within the lower word,
* therefore this actually makes more sense than it might first appear.
*/
#ifdef CONFIG_64BIT
#define smmu_write_atomic_lq writeq_relaxed
#else
#define smmu_write_atomic_lq writel_relaxed
#endif
/* Translation context bank */
#define ARM_SMMU_CB(smmu, n) ((smmu)->cb_base + ((n) << (smmu)->pgshift))
#define MSI_IOVA_BASE 0x8000000
#define MSI_IOVA_LENGTH 0x100000
static int force_stage;
module_param(force_stage, int, S_IRUGO);
MODULE_PARM_DESC(force_stage,
"Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.");
static bool disable_bypass = true;
module_param(disable_bypass, bool, S_IRUGO);
MODULE_PARM_DESC(disable_bypass,
"Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
enum arm_smmu_arch_version {
ARM_SMMU_V1,
ARM_SMMU_V1_64K,
ARM_SMMU_V2,
};
enum arm_smmu_implementation {
GENERIC_SMMU,
ARM_MMU500,
CAVIUM_SMMUV2,
QCOM_SMMUV2,
QCOM_SMMUV500,
};
struct arm_smmu_impl_def_reg {
u32 offset;
u32 value;
};
/* Until ACPICA headers cover IORT rev. C */
#ifndef ACPI_IORT_SMMU_CORELINK_MMU401
#define ACPI_IORT_SMMU_CORELINK_MMU401 0x4
#endif
#ifndef ACPI_IORT_SMMU_CAVIUM_THUNDERX
#define ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x5
#endif
/*
* attach_count
* The SMR and S2CR registers are only programmed when the number of
* devices attached to the iommu using these registers is > 0. This
* is required for the "SID switch" use case for secure display.
* Protected by stream_map_mutex.
*/
struct arm_smmu_s2cr {
struct iommu_group *group;
int count;
int attach_count;
enum arm_smmu_s2cr_type type;
enum arm_smmu_s2cr_privcfg privcfg;
u8 cbndx;
bool cb_handoff;
};
#define s2cr_init_val (struct arm_smmu_s2cr){ \
.type = disable_bypass ? S2CR_TYPE_FAULT : S2CR_TYPE_BYPASS, \
.cb_handoff = false, \
}
struct arm_smmu_smr {
u16 mask;
u16 id;
bool valid;
};
struct arm_smmu_cb {
u64 ttbr[2];
u32 tcr[2];
u32 mair[2];
struct arm_smmu_cfg *cfg;
u32 actlr;
};
struct arm_smmu_master_cfg {
struct arm_smmu_device *smmu;
s16 smendx[];
};
#define INVALID_SMENDX -1
#define __fwspec_cfg(fw) ((struct arm_smmu_master_cfg *)fw->iommu_priv)
#define fwspec_smmu(fw) (__fwspec_cfg(fw)->smmu)
#define fwspec_smendx(fw, i) \
(i >= fw->num_ids ? INVALID_SMENDX : __fwspec_cfg(fw)->smendx[i])
#define for_each_cfg_sme(fw, i, idx) \
for (i = 0; idx = fwspec_smendx(fw, i), i < fw->num_ids; ++i)
/*
* Describes resources required for on/off power operation.
* Separate reference count is provided for atomic/nonatomic
* operations.
*/
struct arm_smmu_power_resources {
struct platform_device *pdev;
struct device *dev;
struct clk **clocks;
int num_clocks;
struct regulator_bulk_data *gdscs;
int num_gdscs;
uint32_t bus_client;
struct msm_bus_scale_pdata *bus_dt_data;
/* Protects power_count */
struct mutex power_lock;
int power_count;
/* Protects clock_refs_count */
spinlock_t clock_refs_lock;
int clock_refs_count;
int regulator_defer;
};
struct arm_smmu_arch_ops;
struct arm_smmu_device {
struct device *dev;
void __iomem *base;
void __iomem *cb_base;
unsigned long size;
phys_addr_t phys_addr;
unsigned long pgshift;
#define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0)
#define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1)
#define ARM_SMMU_FEAT_TRANS_S1 (1 << 2)
#define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
#define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
#define ARM_SMMU_FEAT_TRANS_OPS (1 << 5)
#define ARM_SMMU_FEAT_VMID16 (1 << 6)
#define ARM_SMMU_FEAT_FMT_AARCH64_4K (1 << 7)
#define ARM_SMMU_FEAT_FMT_AARCH64_16K (1 << 8)
#define ARM_SMMU_FEAT_FMT_AARCH64_64K (1 << 9)
#define ARM_SMMU_FEAT_FMT_AARCH32_L (1 << 10)
#define ARM_SMMU_FEAT_FMT_AARCH32_S (1 << 11)
#define ARM_SMMU_FEAT_EXIDS (1 << 12)
u32 features;
#define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
#define ARM_SMMU_OPT_FATAL_ASF (1 << 1)
#define ARM_SMMU_OPT_SKIP_INIT (1 << 2)
#define ARM_SMMU_OPT_DYNAMIC (1 << 3)
#define ARM_SMMU_OPT_3LVL_TABLES (1 << 4)
#define ARM_SMMU_OPT_NO_ASID_RETENTION (1 << 5)
#define ARM_SMMU_OPT_STATIC_CB (1 << 6)
#define ARM_SMMU_OPT_DISABLE_ATOS (1 << 7)
#define ARM_SMMU_OPT_MIN_IOVA_ALIGN (1 << 8)
#define ARM_SMMU_OPT_NO_DYNAMIC_ASID (1 << 9)
u32 options;
enum arm_smmu_arch_version version;
enum arm_smmu_implementation model;
u32 num_context_banks;
u32 num_s2_context_banks;
DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
struct arm_smmu_cb *cbs;
atomic_t irptndx;
u32 num_mapping_groups;
u16 streamid_mask;
u16 smr_mask_mask;
struct arm_smmu_smr *smrs;
struct arm_smmu_s2cr *s2crs;
struct mutex stream_map_mutex;
struct mutex iommu_group_mutex;
unsigned long va_size;
unsigned long ipa_size;
unsigned long pa_size;
unsigned long pgsize_bitmap;
u32 num_global_irqs;
u32 num_context_irqs;
unsigned int *irqs;
struct list_head list;
u32 cavium_id_base; /* Specific to Cavium */
spinlock_t global_sync_lock;
/* IOMMU core code handle */
struct iommu_device iommu;
/* Specific to QCOM */
struct arm_smmu_impl_def_reg *impl_def_attach_registers;
unsigned int num_impl_def_attach_registers;
struct arm_smmu_power_resources *pwr;
spinlock_t atos_lock;
/* protects idr */
struct mutex idr_mutex;
struct idr asid_idr;
struct arm_smmu_arch_ops *arch_ops;
void *archdata;
enum tz_smmu_device_id sec_id;
};
enum arm_smmu_context_fmt {
ARM_SMMU_CTX_FMT_NONE,
ARM_SMMU_CTX_FMT_AARCH64,
ARM_SMMU_CTX_FMT_AARCH32_L,
ARM_SMMU_CTX_FMT_AARCH32_S,
};
struct arm_smmu_cfg {
u8 cbndx;
u8 irptndx;
union {
u16 asid;
u16 vmid;
};
u32 cbar;
u32 procid;
enum arm_smmu_context_fmt fmt;
};
#define INVALID_IRPTNDX 0xff
#define INVALID_CBNDX 0xff
#define INVALID_ASID 0xffff
/*
* In V7L and V8L with TTBCR2.AS == 0, ASID is 8 bits.
* V8L 16 with TTBCR2.AS == 1 (16 bit ASID) isn't supported yet.
*/
#define MAX_ASID 0xff
#define ARM_SMMU_CB_ASID(smmu, cfg) ((cfg)->asid)
#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base + \
(cfg)->cbndx + 1)
enum arm_smmu_domain_stage {
ARM_SMMU_DOMAIN_S1 = 0,
ARM_SMMU_DOMAIN_S2,
ARM_SMMU_DOMAIN_NESTED,
ARM_SMMU_DOMAIN_BYPASS,
};
struct arm_smmu_pte_info {
void *virt_addr;
size_t size;
struct list_head entry;
};
struct arm_smmu_domain {
struct arm_smmu_device *smmu;
struct device *dev;
struct io_pgtable_ops *pgtbl_ops;
struct arm_smmu_cfg cfg;
enum arm_smmu_domain_stage stage;
struct mutex init_mutex; /* Protects smmu pointer */
spinlock_t cb_lock; /* Serialises ATS1* ops */
spinlock_t sync_lock; /* Serialises TLB syncs */
struct io_pgtable_cfg pgtbl_cfg;
u32 attributes;
bool slave_side_secure;
u32 secure_vmid;
struct list_head pte_info_list;
struct list_head unassign_list;
struct mutex assign_lock;
struct list_head secure_pool_list;
/* nonsecure pool protected by pgtbl_lock */
struct list_head nonsecure_pool;
struct iommu_domain domain;
bool qsmmuv500_errata1_min_iova_align;
};
struct arm_smmu_option_prop {
u32 opt;
const char *prop;
};
static atomic_t cavium_smmu_context_count = ATOMIC_INIT(0);
static bool using_legacy_binding, using_generic_binding;
static struct arm_smmu_option_prop arm_smmu_options[] = {
{ ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
{ ARM_SMMU_OPT_FATAL_ASF, "qcom,fatal-asf" },
{ ARM_SMMU_OPT_SKIP_INIT, "qcom,skip-init" },
{ ARM_SMMU_OPT_DYNAMIC, "qcom,dynamic" },
{ ARM_SMMU_OPT_3LVL_TABLES, "qcom,use-3-lvl-tables" },
{ ARM_SMMU_OPT_NO_ASID_RETENTION, "qcom,no-asid-retention" },
{ ARM_SMMU_OPT_STATIC_CB, "qcom,enable-static-cb"},
{ ARM_SMMU_OPT_DISABLE_ATOS, "qcom,disable-atos" },
{ ARM_SMMU_OPT_MIN_IOVA_ALIGN, "qcom,min-iova-align" },
{ ARM_SMMU_OPT_NO_DYNAMIC_ASID, "qcom,no-dynamic-asid" },
{ 0, NULL},
};
static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
dma_addr_t iova);
static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
dma_addr_t iova);
static void arm_smmu_destroy_domain_context(struct iommu_domain *domain);
static int arm_smmu_prepare_pgtable(void *addr, void *cookie);
static void arm_smmu_unprepare_pgtable(void *cookie, void *addr, size_t size);
static int arm_smmu_assign_table(struct arm_smmu_domain *smmu_domain);
static void arm_smmu_unassign_table(struct arm_smmu_domain *smmu_domain);
static uint64_t arm_smmu_iova_to_pte(struct iommu_domain *domain,
dma_addr_t iova);
static int arm_smmu_enable_s1_translations(struct arm_smmu_domain *smmu_domain);
static int arm_smmu_alloc_cb(struct iommu_domain *domain,
struct arm_smmu_device *smmu,
struct device *dev);
static bool arm_smmu_is_static_cb(struct arm_smmu_device *smmu);
static bool arm_smmu_is_master_side_secure(struct arm_smmu_domain *smmu_domain);
static bool arm_smmu_is_slave_side_secure(struct arm_smmu_domain *smmu_domain);
static int msm_secure_smmu_map(struct iommu_domain *domain, unsigned long iova,
phys_addr_t paddr, size_t size, int prot);
static size_t msm_secure_smmu_unmap(struct iommu_domain *domain,
unsigned long iova,
size_t size);
static size_t msm_secure_smmu_map_sg(struct iommu_domain *domain,
unsigned long iova,
struct scatterlist *sg,
unsigned int nents, int prot);
static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
{
return container_of(dom, struct arm_smmu_domain, domain);
}
static void parse_driver_options(struct arm_smmu_device *smmu)
{
int i = 0;
do {
if (of_property_read_bool(smmu->dev->of_node,
arm_smmu_options[i].prop)) {
smmu->options |= arm_smmu_options[i].opt;
dev_dbg(smmu->dev, "option %s\n",
arm_smmu_options[i].prop);
}
} while (arm_smmu_options[++i].opt);
}
static bool is_dynamic_domain(struct iommu_domain *domain)
{
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
return !!(smmu_domain->attributes & (1 << DOMAIN_ATTR_DYNAMIC));
}
static int arm_smmu_restore_sec_cfg(struct arm_smmu_device *smmu, u32 cb)
{
int ret;
int scm_ret = 0;
if (!arm_smmu_is_static_cb(smmu))
return 0;
ret = scm_restore_sec_cfg(smmu->sec_id, cb, &scm_ret);
if (ret || scm_ret) {
pr_err("scm call IOMMU_SECURE_CFG failed\n");
return -EINVAL;
}
return 0;
}
static bool is_iommu_pt_coherent(struct arm_smmu_domain *smmu_domain)
{
if (smmu_domain->attributes &
(1 << DOMAIN_ATTR_PAGE_TABLE_FORCE_COHERENT))
return true;
else if (smmu_domain->smmu && smmu_domain->smmu->dev)
return smmu_domain->smmu->dev->archdata.dma_coherent;
else
return false;
}
static bool arm_smmu_is_static_cb(struct arm_smmu_device *smmu)
{
return smmu->options & ARM_SMMU_OPT_STATIC_CB;
}
static bool arm_smmu_has_secure_vmid(struct arm_smmu_domain *smmu_domain)
{
return (smmu_domain->secure_vmid != VMID_INVAL);
}
static bool arm_smmu_is_slave_side_secure(struct arm_smmu_domain *smmu_domain)
{
return arm_smmu_has_secure_vmid(smmu_domain) &&
smmu_domain->slave_side_secure;
}
static bool arm_smmu_is_master_side_secure(struct arm_smmu_domain *smmu_domain)
{
return arm_smmu_has_secure_vmid(smmu_domain)
&& !smmu_domain->slave_side_secure;
}
static void arm_smmu_secure_domain_lock(struct arm_smmu_domain *smmu_domain)
{
if (arm_smmu_is_master_side_secure(smmu_domain))
mutex_lock(&smmu_domain->assign_lock);
}
static void arm_smmu_secure_domain_unlock(struct arm_smmu_domain *smmu_domain)
{
if (arm_smmu_is_master_side_secure(smmu_domain))
mutex_unlock(&smmu_domain->assign_lock);
}
static bool arm_smmu_opt_hibernation(struct arm_smmu_device *smmu)
{
return IS_ENABLED(CONFIG_HIBERNATION);
}
#ifdef CONFIG_ARM_SMMU_SELFTEST
static int selftest;
module_param_named(selftest, selftest, int, 0644);
static int irq_count;
static DECLARE_WAIT_QUEUE_HEAD(wait_int);
static irqreturn_t arm_smmu_cf_selftest(int irq, void *cb_base)
{
u32 fsr;
struct irq_data *irq_data = irq_get_irq_data(irq);
unsigned long hwirq = ULONG_MAX;
fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
irq_count++;
if (irq_data)
hwirq = irq_data->hwirq;
pr_info("Interrupt (irq:%d hwirq:%ld) received, fsr:0x%x\n",
irq, hwirq, fsr);
writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR);
wake_up(&wait_int);
return IRQ_HANDLED;
}
static void arm_smmu_interrupt_selftest(struct arm_smmu_device *smmu)
{
int cb;
int cb_count = 0;
if (!selftest)
return;
if (arm_smmu_is_static_cb(smmu))
return;
cb = smmu->num_s2_context_banks;
if (smmu->version < ARM_SMMU_V2)
return;
for_each_clear_bit_from(cb, smmu->context_map,
smmu->num_context_banks) {
int irq;
int ret;
void *cb_base;
u32 reg;
u32 reg_orig;
int irq_cnt;
irq = smmu->irqs[smmu->num_global_irqs + cb];
cb_base = ARM_SMMU_CB(smmu, cb);
ret = devm_request_threaded_irq(smmu->dev, irq, NULL,
arm_smmu_cf_selftest,
IRQF_ONESHOT | IRQF_SHARED,
"arm-smmu-context-fault", cb_base);
if (ret < 0) {
dev_err(smmu->dev,
"Failed to request cntx IRQ %d (%u)\n",
cb, irq);
continue;
}
cb_count++;
irq_cnt = irq_count;
reg_orig = readl_relaxed(cb_base + ARM_SMMU_CB_SCTLR);
reg = reg_orig | SCTLR_CFIE | SCTLR_CFRE;
writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
dev_info(smmu->dev, "Testing cntx %d irq %d\n", cb, irq);
/* Make sure ARM_SMMU_CB_SCTLR is configured */
wmb();
writel_relaxed(FSR_TF, cb_base + ARM_SMMU_CB_FSRRESTORE);
wait_event_timeout(wait_int, (irq_count > irq_cnt),
msecs_to_jiffies(1000));
/* Make sure ARM_SMMU_CB_FSRRESTORE is written to */
wmb();
writel_relaxed(reg_orig, cb_base + ARM_SMMU_CB_SCTLR);
devm_free_irq(smmu->dev, irq, cb_base);
}
dev_info(smmu->dev,
"Interrupt selftest completed...\n");
dev_info(smmu->dev,
"Tested %d contexts, received %d interrupts\n",
cb_count, irq_count);
WARN_ON(cb_count != irq_count);
irq_count = 0;
}
#else
static void arm_smmu_interrupt_selftest(struct arm_smmu_device *smmu)
{
}
#endif
/*
* init()
* Hook for additional device tree parsing at probe time.
*
* device_reset()
* Hook for one-time architecture-specific register settings.
*
* iova_to_phys_hard()
* Provides debug information. May be called from the context fault irq handler.
*
* init_context_bank()
* Hook for architecture-specific settings which require knowledge of the
* dynamically allocated context bank number.
*
* device_group()
* Hook for checking whether a device is compatible with a said group.
*/
struct arm_smmu_arch_ops {
int (*init)(struct arm_smmu_device *smmu);
void (*device_reset)(struct arm_smmu_device *smmu);
phys_addr_t (*iova_to_phys_hard)(struct iommu_domain *domain,
dma_addr_t iova);
void (*init_context_bank)(struct arm_smmu_domain *smmu_domain,
struct device *dev);
int (*device_group)(struct device *dev, struct iommu_group *group);
};
static int arm_smmu_arch_init(struct arm_smmu_device *smmu)
{
if (!smmu->arch_ops)
return 0;
if (!smmu->arch_ops->init)
return 0;
return smmu->arch_ops->init(smmu);
}
static void arm_smmu_arch_device_reset(struct arm_smmu_device *smmu)
{
if (!smmu->arch_ops)
return;
if (!smmu->arch_ops->device_reset)
return;
return smmu->arch_ops->device_reset(smmu);
}
static void arm_smmu_arch_init_context_bank(
struct arm_smmu_domain *smmu_domain, struct device *dev)
{
struct arm_smmu_device *smmu = smmu_domain->smmu;
if (!smmu->arch_ops)
return;
if (!smmu->arch_ops->init_context_bank)
return;
return smmu->arch_ops->init_context_bank(smmu_domain, dev);
}
static int arm_smmu_arch_device_group(struct device *dev,
struct iommu_group *group)
{
struct iommu_fwspec *fwspec = dev->iommu_fwspec;
struct arm_smmu_device *smmu = fwspec_smmu(fwspec);
if (!smmu->arch_ops)
return 0;
if (!smmu->arch_ops->device_group)
return 0;
return smmu->arch_ops->device_group(dev, group);
}
static void arm_smmu_arch_write_sync(struct arm_smmu_device *smmu)
{
u32 id;
if (!smmu)
return;
/* Read to complete prior write transcations */
id = readl_relaxed(ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_ID0);
/* Wait for read to complete before off */
rmb();
}
static struct device_node *dev_get_dev_node(struct device *dev)
{
if (dev_is_pci(dev)) {
struct pci_bus *bus = to_pci_dev(dev)->bus;
while (!pci_is_root_bus(bus))
bus = bus->parent;
return of_node_get(bus->bridge->parent->of_node);
}
return of_node_get(dev->of_node);
}
static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)
{
*((__be32 *)data) = cpu_to_be32(alias);
return 0; /* Continue walking */
}
static int __find_legacy_master_phandle(struct device *dev, void *data)
{
struct of_phandle_iterator *it = *(void **)data;
struct device_node *np = it->node;
int err;
of_for_each_phandle(it, err, dev->of_node, "mmu-masters",
"#stream-id-cells", 0)
if (it->node == np) {
*(void **)data = dev;
return 1;
}
it->node = np;
return err == -ENOENT ? 0 : err;
}
static struct platform_driver arm_smmu_driver;
static struct iommu_ops arm_smmu_ops;
static int arm_smmu_register_legacy_master(struct device *dev,
struct arm_smmu_device **smmu)
{
struct device *smmu_dev;
struct device_node *np;
struct of_phandle_iterator it;
void *data = &it;
u32 *sids;
__be32 pci_sid;
int err = 0;
memset(&it, 0, sizeof(it));
np = dev_get_dev_node(dev);
if (!np || !of_find_property(np, "#stream-id-cells", NULL)) {
of_node_put(np);
return -ENODEV;
}
it.node = np;
err = driver_for_each_device(&arm_smmu_driver.driver, NULL, &data,
__find_legacy_master_phandle);
smmu_dev = data;
of_node_put(np);
if (err == 0)
return -ENODEV;
if (err < 0)
return err;
if (dev_is_pci(dev)) {
/* "mmu-masters" assumes Stream ID == Requester ID */
pci_for_each_dma_alias(to_pci_dev(dev), __arm_smmu_get_pci_sid,
&pci_sid);
it.cur = &pci_sid;
it.cur_count = 1;
}
err = iommu_fwspec_init(dev, &smmu_dev->of_node->fwnode,
&arm_smmu_ops);
if (err)
return err;
sids = kcalloc(it.cur_count, sizeof(*sids), GFP_KERNEL);
if (!sids)
return -ENOMEM;
*smmu = dev_get_drvdata(smmu_dev);
of_phandle_iterator_args(&it, sids, it.cur_count);
err = iommu_fwspec_add_ids(dev, sids, it.cur_count);
kfree(sids);
return err;
}
static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
{
int idx;
do {
idx = find_next_zero_bit(map, end, start);
if (idx == end)
return -ENOSPC;
} while (test_and_set_bit(idx, map));
return idx;
}
static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
{
clear_bit(idx, map);
}
static int arm_smmu_prepare_clocks(struct arm_smmu_power_resources *pwr)
{
int i, ret = 0;
for (i = 0; i < pwr->num_clocks; ++i) {
ret = clk_prepare(pwr->clocks[i]);
if (ret) {
dev_err(pwr->dev, "Couldn't prepare clock #%d\n", i);
while (i--)
clk_unprepare(pwr->clocks[i]);
break;
}
}
return ret;
}
static void arm_smmu_unprepare_clocks(struct arm_smmu_power_resources *pwr)
{
int i;
for (i = pwr->num_clocks; i; --i)
clk_unprepare(pwr->clocks[i - 1]);
}
static int arm_smmu_enable_clocks(struct arm_smmu_power_resources *pwr)
{
int i, ret = 0;
for (i = 0; i < pwr->num_clocks; ++i) {
ret = clk_enable(pwr->clocks[i]);
if (ret) {
dev_err(pwr->dev, "Couldn't enable clock #%d\n", i);
while (i--)
clk_disable(pwr->clocks[i]);
break;
}
}
return ret;
}
static void arm_smmu_disable_clocks(struct arm_smmu_power_resources *pwr)
{
int i;
for (i = pwr->num_clocks; i; --i)
clk_disable(pwr->clocks[i - 1]);
}
static int arm_smmu_request_bus(struct arm_smmu_power_resources *pwr)
{
if (!pwr->bus_client)
return 0;
return msm_bus_scale_client_update_request(pwr->bus_client, 1);
}
static void arm_smmu_unrequest_bus(struct arm_smmu_power_resources *pwr)
{
if (!pwr->bus_client)
return;
WARN_ON(msm_bus_scale_client_update_request(pwr->bus_client, 0));
}
static int arm_smmu_enable_regulators(struct arm_smmu_power_resources *pwr)
{
struct regulator_bulk_data *consumers;
int num_consumers, ret;
int i;
num_consumers = pwr->num_gdscs;
consumers = pwr->gdscs;
for (i = 0; i < num_consumers; i++) {
ret = regulator_enable(consumers[i].consumer);
if (ret)
goto out;
}
return 0;
out:
i -= 1;
for (; i >= 0; i--)
regulator_disable(consumers[i].consumer);
return ret;
}
static int arm_smmu_disable_regulators(struct arm_smmu_power_resources *pwr)
{
struct regulator_bulk_data *consumers;
int i;
int num_consumers, ret, r;
num_consumers = pwr->num_gdscs;
consumers = pwr->gdscs;
for (i = num_consumers - 1; i >= 0; --i) {
ret = regulator_disable_deferred(consumers[i].consumer,
pwr->regulator_defer);
if (ret != 0)
goto err;
}
return 0;
err:
pr_err("Failed to disable %s: %d\n", consumers[i].supply, ret);
for (++i; i < num_consumers; ++i) {
r = regulator_enable(consumers[i].consumer);
if (r != 0)
pr_err("Failed to rename %s: %d\n",
consumers[i].supply, r);
}
return ret;
}
/* Clocks must be prepared before this (arm_smmu_prepare_clocks) */
static int arm_smmu_power_on_atomic(struct arm_smmu_power_resources *pwr)
{
int ret = 0;
unsigned long flags;
spin_lock_irqsave(&pwr->clock_refs_lock, flags);
if (pwr->clock_refs_count > 0) {
pwr->clock_refs_count++;
spin_unlock_irqrestore(&pwr->clock_refs_lock, flags);
return 0;
}
ret = arm_smmu_enable_clocks(pwr);
if (!ret)
pwr->clock_refs_count = 1;
spin_unlock_irqrestore(&pwr->clock_refs_lock, flags);
return ret;
}
/* Clocks should be unprepared after this (arm_smmu_unprepare_clocks) */
static void arm_smmu_power_off_atomic(struct arm_smmu_power_resources *pwr)
{
unsigned long flags;
struct arm_smmu_device *smmu = pwr->dev->driver_data;
arm_smmu_arch_write_sync(smmu);
spin_lock_irqsave(&pwr->clock_refs_lock, flags);
if (pwr->clock_refs_count == 0) {
WARN(1, "%s: bad clock_ref_count\n", dev_name(pwr->dev));
spin_unlock_irqrestore(&pwr->clock_refs_lock, flags);
return;
} else if (pwr->clock_refs_count > 1) {
pwr->clock_refs_count--;
spin_unlock_irqrestore(&pwr->clock_refs_lock, flags);
return;
}
arm_smmu_disable_clocks(pwr);
pwr->clock_refs_count = 0;
spin_unlock_irqrestore(&pwr->clock_refs_lock, flags);
}
static int arm_smmu_power_on_slow(struct arm_smmu_power_resources *pwr)
{
int ret;
mutex_lock(&pwr->power_lock);
if (pwr->power_count > 0) {
pwr->power_count += 1;
mutex_unlock(&pwr->power_lock);
return 0;
}
ret = arm_smmu_request_bus(pwr);
if (ret)
goto out_unlock;
ret = arm_smmu_enable_regulators(pwr);
if (ret)
goto out_disable_bus;
ret = arm_smmu_prepare_clocks(pwr);
if (ret)
goto out_disable_regulators;
pwr->power_count = 1;
mutex_unlock(&pwr->power_lock);
return 0;
out_disable_regulators:
regulator_bulk_disable(pwr->num_gdscs, pwr->gdscs);
out_disable_bus:
arm_smmu_unrequest_bus(pwr);
out_unlock:
mutex_unlock(&pwr->power_lock);
return ret;
}
static void arm_smmu_power_off_slow(struct arm_smmu_power_resources *pwr)
{
mutex_lock(&pwr->power_lock);
if (pwr->power_count == 0) {
WARN(1, "%s: Bad power count\n", dev_name(pwr->dev));
mutex_unlock(&pwr->power_lock);
return;
} else if (pwr->power_count > 1) {
pwr->power_count--;
mutex_unlock(&pwr->power_lock);
return;
}
arm_smmu_unprepare_clocks(pwr);
arm_smmu_disable_regulators(pwr);
arm_smmu_unrequest_bus(pwr);
pwr->power_count = 0;
mutex_unlock(&pwr->power_lock);
}
static int arm_smmu_power_on(struct arm_smmu_power_resources *pwr)
{
int ret;
ret = arm_smmu_power_on_slow(pwr);
if (ret)
return ret;
ret = arm_smmu_power_on_atomic(pwr);
if (ret)
goto out_disable;
return 0;
out_disable:
arm_smmu_power_off_slow(pwr);
return ret;
}
static void arm_smmu_power_off(struct arm_smmu_power_resources *pwr)
{
arm_smmu_power_off_atomic(pwr);
arm_smmu_power_off_slow(pwr);
}
/*
* Must be used instead of arm_smmu_power_on if it may be called from
* atomic context
*/
static int arm_smmu_domain_power_on(struct iommu_domain *domain,
struct arm_smmu_device *smmu)
{
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
int atomic_domain = smmu_domain->attributes & (1 << DOMAIN_ATTR_ATOMIC);
if (atomic_domain)
return arm_smmu_power_on_atomic(smmu->pwr);
return arm_smmu_power_on(smmu->pwr);
}
/*
* Must be used instead of arm_smmu_power_on if it may be called from
* atomic context
*/
static void arm_smmu_domain_power_off(struct iommu_domain *domain,
struct arm_smmu_device *smmu)
{
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
int atomic_domain = smmu_domain->attributes & (1 << DOMAIN_ATTR_ATOMIC);
if (atomic_domain) {
arm_smmu_power_off_atomic(smmu->pwr);
return;
}
arm_smmu_power_off(smmu->pwr);
}
/* Wait for any pending TLB invalidations to complete */
static int __arm_smmu_tlb_sync(struct arm_smmu_device *smmu,
void __iomem *sync, void __iomem *status)
{
unsigned int spin_cnt, delay;
u32 sync_inv_ack, tbu_pwr_status, sync_inv_progress;
writel_relaxed(QCOM_DUMMY_VAL, sync);
for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) {
for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) {
if (!(readl_relaxed(status) & sTLBGSTATUS_GSACTIVE))
return 0;
cpu_relax();
}
udelay(delay);
}
sync_inv_ack = scm_io_read((unsigned long)(smmu->phys_addr +
ARM_SMMU_STATS_SYNC_INV_TBU_ACK));
tbu_pwr_status = scm_io_read((unsigned long)(smmu->phys_addr +
ARM_SMMU_TBU_PWR_STATUS));
sync_inv_progress = scm_io_read((unsigned long)(smmu->phys_addr +
ARM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR));
trace_tlbsync_timeout(smmu->dev, 0);
dev_err_ratelimited(smmu->dev,
"TLB sync timed out -- SMMU may be deadlocked ack 0x%x pwr 0x%x sync and invalidation progress 0x%x\n",
sync_inv_ack, tbu_pwr_status, sync_inv_progress);
BUG_ON(IS_ENABLED(CONFIG_IOMMU_TLBSYNC_DEBUG));
return -EINVAL;
}
static void arm_smmu_tlb_sync_global(struct arm_smmu_device *smmu)
{
void __iomem *base = ARM_SMMU_GR0(smmu);
unsigned long flags;
spin_lock_irqsave(&smmu->global_sync_lock, flags);
if (__arm_smmu_tlb_sync(smmu, base + ARM_SMMU_GR0_sTLBGSYNC,
base + ARM_SMMU_GR0_sTLBGSTATUS))
dev_err_ratelimited(smmu->dev,
"TLB global sync failed!\n");
spin_unlock_irqrestore(&smmu->global_sync_lock, flags);
}
static void arm_smmu_tlb_sync_context(void *cookie)
{
struct arm_smmu_domain *smmu_domain = cookie;
struct arm_smmu_device *smmu = smmu_domain->smmu;
void __iomem *base = ARM_SMMU_CB(smmu, smmu_domain->cfg.cbndx);
unsigned long flags;
spin_lock_irqsave(&smmu_domain->sync_lock, flags);
if (__arm_smmu_tlb_sync(smmu, base + ARM_SMMU_CB_TLBSYNC,
base + ARM_SMMU_CB_TLBSTATUS))
dev_err_ratelimited(smmu->dev,
"TLB sync on cb%d failed for device %s\n",
smmu_domain->cfg.cbndx,
dev_name(smmu_domain->dev));
spin_unlock_irqrestore(&smmu_domain->sync_lock, flags);
}
static void arm_smmu_tlb_sync_vmid(void *cookie)
{
struct arm_smmu_domain *smmu_domain = cookie;
arm_smmu_tlb_sync_global(smmu_domain->smmu);
}
static void arm_smmu_tlb_inv_context_s1(void *cookie)
{
struct arm_smmu_domain *smmu_domain = cookie;
struct device *dev = smmu_domain->dev;
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
struct arm_smmu_device *smmu = smmu_domain->smmu;
void __iomem *base = ARM_SMMU_CB(smmu_domain->smmu, cfg->cbndx);
bool use_tlbiall = smmu->options & ARM_SMMU_OPT_NO_ASID_RETENTION;
ktime_t cur = ktime_get();
trace_tlbi_start(dev, 0);
if (!use_tlbiall)
writel_relaxed(cfg->asid, base + ARM_SMMU_CB_S1_TLBIASID);
else
writel_relaxed(0, base + ARM_SMMU_CB_S1_TLBIALL);
arm_smmu_tlb_sync_context(cookie);
trace_tlbi_end(dev, ktime_us_delta(ktime_get(), cur));
}
static void arm_smmu_tlb_inv_context_s2(void *cookie)
{
struct arm_smmu_domain *smmu_domain = cookie;
struct arm_smmu_device *smmu = smmu_domain->smmu;
void __iomem *base = ARM_SMMU_GR0(smmu);
writel_relaxed(smmu_domain->cfg.vmid, base + ARM_SMMU_GR0_TLBIVMID);
arm_smmu_tlb_sync_global(smmu);
}
static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
size_t granule, bool leaf, void *cookie)
{
struct arm_smmu_domain *smmu_domain = cookie;
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
struct arm_smmu_device *smmu = smmu_domain->smmu;
bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
void __iomem *reg = ARM_SMMU_CB(smmu_domain->smmu, cfg->cbndx);
bool use_tlbiall = smmu->options & ARM_SMMU_OPT_NO_ASID_RETENTION;
if (smmu_domain->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
wmb();
if (stage1 && !use_tlbiall) {
reg += leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
if (cfg->fmt != ARM_SMMU_CTX_FMT_AARCH64) {
iova &= ~12UL;
iova |= cfg->asid;
do {
writel_relaxed(iova, reg);
iova += granule;
} while (size -= granule);
} else {
iova >>= 12;
iova |= (u64)cfg->asid << 48;
do {
writeq_relaxed(iova, reg);
iova += granule >> 12;
} while (size -= granule);
}
} else if (stage1 && use_tlbiall) {
reg += ARM_SMMU_CB_S1_TLBIALL;
writel_relaxed(0, reg);
} else {
reg += leaf ? ARM_SMMU_CB_S2_TLBIIPAS2L :
ARM_SMMU_CB_S2_TLBIIPAS2;
iova >>= 12;
do {
smmu_write_atomic_lq(iova, reg);
iova += granule >> 12;
} while (size -= granule);
}
}
/*
* On MMU-401 at least, the cost of firing off multiple TLBIVMIDs appears
* almost negligible, but the benefit of getting the first one in as far ahead
* of the sync as possible is significant, hence we don't just make this a
* no-op and set .tlb_sync to arm_smmu_inv_context_s2() as you might think.
*/
static void arm_smmu_tlb_inv_vmid_nosync(unsigned long iova, size_t size,
size_t granule, bool leaf, void *cookie)
{
struct arm_smmu_domain *smmu_domain = cookie;
void __iomem *base = ARM_SMMU_GR0(smmu_domain->smmu);
if (smmu_domain->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
wmb();
writel_relaxed(smmu_domain->cfg.vmid, base + ARM_SMMU_GR0_TLBIVMID);
}
struct arm_smmu_secure_pool_chunk {
void *addr;
size_t size;
struct list_head list;
};
static void *arm_smmu_secure_pool_remove(struct arm_smmu_domain *smmu_domain,
size_t size)
{
struct arm_smmu_secure_pool_chunk *it;
list_for_each_entry(it, &smmu_domain->secure_pool_list, list) {
if (it->size == size) {
void *addr = it->addr;
list_del(&it->list);
kfree(it);
return addr;
}
}
return NULL;
}
static int arm_smmu_secure_pool_add(struct arm_smmu_domain *smmu_domain,
void *addr, size_t size)
{
struct arm_smmu_secure_pool_chunk *chunk;
chunk = kmalloc(sizeof(*chunk), GFP_ATOMIC);
if (!chunk)
return -ENOMEM;
chunk->addr = addr;
chunk->size = size;
memset(addr, 0, size);
list_add(&chunk->list, &smmu_domain->secure_pool_list);
return 0;
}
static void arm_smmu_secure_pool_destroy(struct arm_smmu_domain *smmu_domain)
{
struct arm_smmu_secure_pool_chunk *it, *i;
list_for_each_entry_safe(it, i, &smmu_domain->secure_pool_list, list) {
arm_smmu_unprepare_pgtable(smmu_domain, it->addr, it->size);
/* pages will be freed later (after being unassigned) */
list_del(&it->list);
kfree(it);
}
}
static void *arm_smmu_alloc_pages_exact(void *cookie,
size_t size, gfp_t gfp_mask)
{
int ret;
void *page;
struct arm_smmu_domain *smmu_domain = cookie;
if (!arm_smmu_is_master_side_secure(smmu_domain)) {
struct page *pg;
/* size is expected to be 4K with current configuration */
if (size == PAGE_SIZE) {
pg = list_first_entry_or_null(
&smmu_domain->nonsecure_pool, struct page, lru);
if (pg) {
list_del_init(&pg->lru);
return page_address(pg);
}
}
return alloc_pages_exact(size, gfp_mask);
}
page = arm_smmu_secure_pool_remove(smmu_domain, size);
if (page)
return page;
page = alloc_pages_exact(size, gfp_mask);
if (page) {
ret = arm_smmu_prepare_pgtable(page, cookie);
if (ret) {
free_pages_exact(page, size);
return NULL;
}
}
return page;
}
static void arm_smmu_free_pages_exact(void *cookie, void *virt, size_t size)
{
struct arm_smmu_domain *smmu_domain = cookie;
if (!arm_smmu_is_master_side_secure(smmu_domain)) {
free_pages_exact(virt, size);
return;
}
if (arm_smmu_secure_pool_add(smmu_domain, virt, size))
arm_smmu_unprepare_pgtable(smmu_domain, virt, size);
}
static const struct iommu_gather_ops arm_smmu_s1_tlb_ops = {
.tlb_flush_all = arm_smmu_tlb_inv_context_s1,
.tlb_add_flush = arm_smmu_tlb_inv_range_nosync,
.tlb_sync = arm_smmu_tlb_sync_context,
.alloc_pages_exact = arm_smmu_alloc_pages_exact,
.free_pages_exact = arm_smmu_free_pages_exact,
};
static const struct iommu_gather_ops arm_smmu_s2_tlb_ops_v2 = {
.tlb_flush_all = arm_smmu_tlb_inv_context_s2,
.tlb_add_flush = arm_smmu_tlb_inv_range_nosync,
.tlb_sync = arm_smmu_tlb_sync_context,
.alloc_pages_exact = arm_smmu_alloc_pages_exact,
.free_pages_exact = arm_smmu_free_pages_exact,
};
static const struct iommu_gather_ops arm_smmu_s2_tlb_ops_v1 = {
.tlb_flush_all = arm_smmu_tlb_inv_context_s2,
.tlb_add_flush = arm_smmu_tlb_inv_vmid_nosync,
.tlb_sync = arm_smmu_tlb_sync_vmid,
.alloc_pages_exact = arm_smmu_alloc_pages_exact,
.free_pages_exact = arm_smmu_free_pages_exact,
};
static void msm_smmu_tlb_inv_context(void *cookie)
{
}
static void msm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
size_t granule, bool leaf,
void *cookie)
{
}
static void msm_smmu_tlb_sync(void *cookie)
{
}
static struct iommu_gather_ops msm_smmu_gather_ops = {
.tlb_flush_all = msm_smmu_tlb_inv_context,
.tlb_add_flush = msm_smmu_tlb_inv_range_nosync,
.tlb_sync = msm_smmu_tlb_sync,
.alloc_pages_exact = arm_smmu_alloc_pages_exact,
.free_pages_exact = arm_smmu_free_pages_exact,
};
static void print_ctx_regs(struct arm_smmu_device *smmu, struct arm_smmu_cfg
*cfg, unsigned int fsr)
{
u32 fsynr0;
void __iomem *cb_base = ARM_SMMU_CB(smmu, cfg->cbndx);
void __iomem *gr1_base = ARM_SMMU_GR1(smmu);
bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
fsynr0 = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
dev_err(smmu->dev, "FAR = 0x%016llx\n",
readq_relaxed(cb_base + ARM_SMMU_CB_FAR));
dev_err(smmu->dev, "PAR = 0x%pK\n",
readq_relaxed(cb_base + ARM_SMMU_CB_PAR));
dev_err(smmu->dev,
"FSR = 0x%08x [%s%s%s%s%s%s%s%s%s%s]\n",
fsr,
(fsr & 0x02) ? (fsynr0 & 0x10 ?
"TF W " : "TF R ") : "",
(fsr & 0x04) ? "AFF " : "",
(fsr & 0x08) ? (fsynr0 & 0x10 ?
"PF W " : "PF R ") : "",
(fsr & 0x10) ? "EF " : "",
(fsr & 0x20) ? "TLBMCF " : "",
(fsr & 0x40) ? "TLBLKF " : "",
(fsr & 0x80) ? "MHF " : "",
(fsr & 0x100) ? "UUT " : "",
(fsr & 0x40000000) ? "SS " : "",
(fsr & 0x80000000) ? "MULTI " : "");
if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
dev_err(smmu->dev, "TTBR0 = 0x%pK\n",
readl_relaxed(cb_base + ARM_SMMU_CB_TTBR0));
dev_err(smmu->dev, "TTBR1 = 0x%pK\n",
readl_relaxed(cb_base + ARM_SMMU_CB_TTBR1));
} else {
dev_err(smmu->dev, "TTBR0 = 0x%pK\n",
readq_relaxed(cb_base + ARM_SMMU_CB_TTBR0));
if (stage1)
dev_err(smmu->dev, "TTBR1 = 0x%pK\n",
readq_relaxed(cb_base + ARM_SMMU_CB_TTBR1));
}
dev_err(smmu->dev, "SCTLR = 0x%08x ACTLR = 0x%08x\n",
readl_relaxed(cb_base + ARM_SMMU_CB_SCTLR),
readl_relaxed(cb_base + ARM_SMMU_CB_ACTLR));
dev_err(smmu->dev, "CBAR = 0x%08x\n",
readl_relaxed(gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)));
dev_err(smmu->dev, "MAIR0 = 0x%08x MAIR1 = 0x%08x\n",
readl_relaxed(cb_base + ARM_SMMU_CB_S1_MAIR0),
readl_relaxed(cb_base + ARM_SMMU_CB_S1_MAIR1));
}
static phys_addr_t arm_smmu_verify_fault(struct iommu_domain *domain,
dma_addr_t iova, u32 fsr)
{
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
struct arm_smmu_device *smmu = smmu_domain->smmu;
phys_addr_t phys;
phys_addr_t phys_post_tlbiall;
phys = arm_smmu_iova_to_phys_hard(domain, iova);
smmu_domain->pgtbl_cfg.tlb->tlb_flush_all(smmu_domain);
phys_post_tlbiall = arm_smmu_iova_to_phys_hard(domain, iova);
if (phys != phys_post_tlbiall) {
dev_err(smmu->dev,
"ATOS results differed across TLBIALL...\n"
"Before: %pa After: %pa\n", &phys, &phys_post_tlbiall);
}
return (phys == 0 ? phys_post_tlbiall : phys);
}
static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
{
int flags, ret, tmp;
u32 fsr, fsynr0, fsynr1, frsynra, resume;
unsigned long iova;
struct iommu_domain *domain = dev;
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
struct arm_smmu_device *smmu = smmu_domain->smmu;
void __iomem *cb_base;
void __iomem *gr1_base;
bool fatal_asf = smmu->options & ARM_SMMU_OPT_FATAL_ASF;
phys_addr_t phys_soft;
uint64_t pte;
bool non_fatal_fault = !!(smmu_domain->attributes &
(1 << DOMAIN_ATTR_NON_FATAL_FAULTS));
static DEFINE_RATELIMIT_STATE(_rs,
DEFAULT_RATELIMIT_INTERVAL,
DEFAULT_RATELIMIT_BURST);
ret = arm_smmu_power_on(smmu->pwr);
if (ret)
return IRQ_NONE;
gr1_base = ARM_SMMU_GR1(smmu);
cb_base = ARM_SMMU_CB(smmu, cfg->cbndx);
fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
if (!(fsr & FSR_FAULT)) {
ret = IRQ_NONE;
goto out_power_off;
}
if (fatal_asf && (fsr & FSR_ASF)) {
dev_err(smmu->dev,
"Took an address size fault. Refusing to recover.\n");
BUG();
}
fsynr0 = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
fsynr1 = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR1);
flags = fsynr0 & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
if (fsr & FSR_TF)
flags |= IOMMU_FAULT_TRANSLATION;
if (fsr & FSR_PF)
flags |= IOMMU_FAULT_PERMISSION;
if (fsr & FSR_EF)
flags |= IOMMU_FAULT_EXTERNAL;
if (fsr & FSR_SS)
flags |= IOMMU_FAULT_TRANSACTION_STALLED;
iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);
phys_soft = arm_smmu_iova_to_phys(domain, iova);
frsynra = readl_relaxed(gr1_base + ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));
frsynra &= CBFRSYNRA_SID_MASK;
tmp = report_iommu_fault(domain, smmu->dev, iova, flags);
if (!tmp || (tmp == -EBUSY)) {
dev_dbg(smmu->dev,
"Context fault handled by client: iova=0x%08lx, cb=%d, fsr=0x%x, fsynr0=0x%x, fsynr1=0x%x\n",
iova, cfg->cbndx, fsr, fsynr0, fsynr1);
dev_dbg(smmu->dev,
"soft iova-to-phys=%pa\n", &phys_soft);
ret = IRQ_HANDLED;
resume = RESUME_TERMINATE;
} else {
if (__ratelimit(&_rs)) {
phys_addr_t phys_atos;
print_ctx_regs(smmu, cfg, fsr);
phys_atos = arm_smmu_verify_fault(domain, iova, fsr);
dev_err(smmu->dev,
"Unhandled context fault: iova=0x%08lx, cb=%d, fsr=0x%x, fsynr0=0x%x, fsynr1=0x%x\n",
iova, cfg->cbndx, fsr, fsynr0, fsynr1);
dev_err(smmu->dev,
"soft iova-to-phys=%pa\n", &phys_soft);
if (!phys_soft)
dev_err(smmu->dev,
"SOFTWARE TABLE WALK FAILED! Looks like %s accessed an unmapped address!\n",
dev_name(smmu->dev));
else {
pte = arm_smmu_iova_to_pte(domain, iova);
dev_err(smmu->dev, "PTE = %016llx\n", pte);
}
if (phys_atos)
dev_err(smmu->dev, "hard iova-to-phys (ATOS)=%pa\n",
&phys_atos);
else
dev_err(smmu->dev, "hard iova-to-phys (ATOS) failed\n");
dev_err(smmu->dev, "SID=0x%x\n", frsynra);
}
ret = IRQ_NONE;
resume = RESUME_TERMINATE;
if (!non_fatal_fault) {
dev_err(smmu->dev,
"Unhandled arm-smmu context fault!\n");
BUG();
}
}
/*
* If the client returns -EBUSY, do not clear FSR and do not RESUME
* if stalled. This is required to keep the IOMMU client stalled on
* the outstanding fault. This gives the client a chance to take any
* debug action and then terminate the stalled transaction.
* So, the sequence in case of stall on fault should be:
* 1) Do not clear FSR or write to RESUME here
* 2) Client takes any debug action
* 3) Client terminates the stalled transaction and resumes the IOMMU
* 4) Client clears FSR. The FSR should only be cleared after 3) and
* not before so that the fault remains outstanding. This ensures
* SCTLR.HUPCF has the desired effect if subsequent transactions also
* need to be terminated.
*/
if (tmp != -EBUSY) {
/* Clear the faulting FSR */
writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR);
/*
* Barrier required to ensure that the FSR is cleared
* before resuming SMMU operation
*/
wmb();
/* Retry or terminate any stalled transactions */
if (fsr & FSR_SS)
writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
}
out_power_off:
arm_smmu_power_off(smmu->pwr);
return ret;
}
static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
{
u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
struct arm_smmu_device *smmu = dev;
void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
if (arm_smmu_power_on(smmu->pwr))
return IRQ_NONE;
gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
if (!gfsr) {
arm_smmu_power_off(smmu->pwr);
return IRQ_NONE;
}
dev_err_ratelimited(smmu->dev,
"Unexpected global fault, this could be serious\n");
dev_err_ratelimited(smmu->dev,
"\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
gfsr, gfsynr0, gfsynr1, gfsynr2);
writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
arm_smmu_power_off(smmu->pwr);
return IRQ_HANDLED;
}
static bool arm_smmu_master_attached(struct arm_smmu_device *smmu,
struct iommu_fwspec *fwspec)
{
int i, idx;
for_each_cfg_sme(fwspec, i, idx) {
if (smmu->s2crs[idx].attach_count)
return true;
}
return false;
}
static int arm_smmu_set_pt_format(struct arm_smmu_domain *smmu_domain,
struct io_pgtable_cfg *pgtbl_cfg)
{
struct arm_smmu_device *smmu = smmu_domain->smmu;
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
int ret = 0;
if ((smmu->version > ARM_SMMU_V1) &&
(cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) &&
!arm_smmu_has_secure_vmid(smmu_domain) &&
arm_smmu_is_static_cb(smmu)) {
ret = msm_tz_set_cb_format(smmu->sec_id, cfg->cbndx);
}
return ret;
}
static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
struct io_pgtable_cfg *pgtbl_cfg)
{
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];
bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
cb->cfg = cfg;
/* TTBCR */
if (stage1) {
if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
cb->tcr[0] = pgtbl_cfg->arm_v7s_cfg.tcr;
} else {
cb->tcr[0] = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
cb->tcr[1] = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
cb->tcr[1] |= TTBCR2_SEP_UPSTREAM;
if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64)
cb->tcr[1] |= TTBCR2_AS;
}
} else {
cb->tcr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
}
/* TTBRs */
if (stage1) {
if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr[0];
cb->ttbr[1] = pgtbl_cfg->arm_v7s_cfg.ttbr[1];
} else {
cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
cb->ttbr[0] |= (u64)cfg->asid << TTBRn_ASID_SHIFT;
cb->ttbr[1] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
cb->ttbr[1] |= (u64)cfg->asid << TTBRn_ASID_SHIFT;
}
} else {
cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
}
/* MAIRs (stage-1 only) */
if (stage1) {
if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
cb->mair[0] = pgtbl_cfg->arm_v7s_cfg.prrr;
cb->mair[1] = pgtbl_cfg->arm_v7s_cfg.nmrr;
} else {
cb->mair[0] = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
cb->mair[1] = pgtbl_cfg->arm_lpae_s1_cfg.mair[1];
}
}
}
static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx,
u32 attributes)
{
u32 reg;
bool stage1;
struct arm_smmu_cb *cb = &smmu->cbs[idx];
struct arm_smmu_cfg *cfg = cb->cfg;
void __iomem *cb_base, *gr1_base;
cb_base = ARM_SMMU_CB(smmu, idx);
/* Unassigned context banks only need disabling */
if (!cfg) {
writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
return;
}
gr1_base = ARM_SMMU_GR1(smmu);
stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
/* CBA2R */
if (smmu->version > ARM_SMMU_V1) {
if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64)
reg = CBA2R_RW64_64BIT;
else
reg = CBA2R_RW64_32BIT;
/* 16-bit VMIDs live in CBA2R */
if (smmu->features & ARM_SMMU_FEAT_VMID16)
reg |= cfg->vmid << CBA2R_VMID_SHIFT;
writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(idx));
}
/* CBAR */
reg = cfg->cbar;
if (smmu->version < ARM_SMMU_V2)
reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
/*
* Use the weakest shareability/memory types, so they are
* overridden by the ttbcr/pte.
*/
if (stage1) {
reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
(CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
} else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) {
/* 8-bit VMIDs live in CBAR */
reg |= cfg->vmid << CBAR_VMID_SHIFT;
}
writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(idx));
/*
* TTBCR
* We must write this before the TTBRs, since it determines the
* access behaviour of some fields (in particular, ASID[15:8]).
*/
if (stage1 && smmu->version > ARM_SMMU_V1)
writel_relaxed(cb->tcr[1], cb_base + ARM_SMMU_CB_TTBCR2);
writel_relaxed(cb->tcr[0], cb_base + ARM_SMMU_CB_TTBCR);
/* TTBRs */
if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) {
writel_relaxed(cfg->asid, cb_base + ARM_SMMU_CB_CONTEXTIDR);
writel_relaxed(cb->ttbr[0], cb_base + ARM_SMMU_CB_TTBR0);
writel_relaxed(cb->ttbr[1], cb_base + ARM_SMMU_CB_TTBR1);
} else {
writeq_relaxed(cb->ttbr[0], cb_base + ARM_SMMU_CB_TTBR0);
if (stage1)
writeq_relaxed(cb->ttbr[1], cb_base + ARM_SMMU_CB_TTBR1);
}
/* MAIRs (stage-1 only) */
if (stage1) {
writel_relaxed(cb->mair[0], cb_base + ARM_SMMU_CB_S1_MAIR0);
writel_relaxed(cb->mair[1], cb_base + ARM_SMMU_CB_S1_MAIR1);
}
/* ACTLR (implementation defined) */
writel_relaxed(cb->actlr, cb_base + ARM_SMMU_CB_ACTLR);
/* SCTLR */
reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE;
/* Ensure bypass transactions are Non-shareable */
reg |= SCTLR_SHCFG_NSH << SCTLR_SHCFG_SHIFT;
if (attributes & (1 << DOMAIN_ATTR_CB_STALL_DISABLE)) {
reg &= ~SCTLR_CFCFG;
reg |= SCTLR_HUPCF;
}
if (attributes & (1 << DOMAIN_ATTR_NO_CFRE))
reg &= ~SCTLR_CFRE;
if ((!(attributes & (1 << DOMAIN_ATTR_S1_BYPASS)) &&
!(attributes & (1 << DOMAIN_ATTR_EARLY_MAP))) || !stage1)
reg |= SCTLR_M;
if (stage1)
reg |= SCTLR_S1_ASIDPNE;
if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
reg |= SCTLR_E;
writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
}
static int arm_smmu_init_asid(struct iommu_domain *domain,
struct arm_smmu_device *smmu)
{
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
bool dynamic = is_dynamic_domain(domain);
int ret;
if (!dynamic || (smmu->options & ARM_SMMU_OPT_NO_DYNAMIC_ASID)) {
cfg->asid = cfg->cbndx + 1;
} else {
mutex_lock(&smmu->idr_mutex);
ret = idr_alloc_cyclic(&smmu->asid_idr, domain,
smmu->num_context_banks + 2,
MAX_ASID + 1, GFP_KERNEL);
mutex_unlock(&smmu->idr_mutex);
if (ret < 0) {
dev_err(smmu->dev, "dynamic ASID allocation failed: %d\n",
ret);
return ret;
}
cfg->asid = ret;
}
return 0;
}
static void arm_smmu_free_asid(struct iommu_domain *domain)
{
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
struct arm_smmu_device *smmu = smmu_domain->smmu;
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
bool dynamic = is_dynamic_domain(domain);
if (cfg->asid == INVALID_ASID || !dynamic)
return;
mutex_lock(&smmu->idr_mutex);
idr_remove(&smmu->asid_idr, cfg->asid);
mutex_unlock(&smmu->idr_mutex);
}
static int arm_smmu_init_domain_context(struct iommu_domain *domain,
struct arm_smmu_device *smmu,
struct device *dev)
{
int irq, start, ret = 0;
unsigned long ias, oas;
struct io_pgtable_ops *pgtbl_ops;
enum io_pgtable_fmt fmt;
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
const struct iommu_gather_ops *tlb_ops;
bool is_fast = smmu_domain->attributes & (1 << DOMAIN_ATTR_FAST);
unsigned long quirks = 0;
bool dynamic;
mutex_lock(&smmu_domain->init_mutex);
if (smmu_domain->smmu)
goto out_unlock;
if (domain->type == IOMMU_DOMAIN_IDENTITY) {
smmu_domain->stage = ARM_SMMU_DOMAIN_BYPASS;
smmu_domain->smmu = smmu;
smmu_domain->cfg.irptndx = INVALID_IRPTNDX;
smmu_domain->cfg.asid = INVALID_ASID;
}
dynamic = is_dynamic_domain(domain);
if (dynamic && !(smmu->options & ARM_SMMU_OPT_DYNAMIC)) {
dev_err(smmu->dev, "dynamic domains not supported\n");
ret = -EPERM;
goto out_unlock;
}
if (arm_smmu_has_secure_vmid(smmu_domain) &&
arm_smmu_opt_hibernation(smmu)) {
dev_err(smmu->dev,
"Secure usecases not supported with hibernation\n");
ret = -EPERM;
goto out_unlock;
}
/*
* Mapping the requested stage onto what we support is surprisingly
* complicated, mainly because the spec allows S1+S2 SMMUs without
* support for nested translation. That means we end up with the
* following table:
*
* Requested Supported Actual
* S1 N S1
* S1 S1+S2 S1
* S1 S2 S2
* S1 S1 S1
* N N N
* N S1+S2 S2
* N S2 S2
* N S1 S1
*
* Note that you can't actually request stage-2 mappings.
*/
if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1))
smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2))
smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
/*
* Choosing a suitable context format is even more fiddly. Until we
* grow some way for the caller to express a preference, and/or move
* the decision into the io-pgtable code where it arguably belongs,
* just aim for the closest thing to the rest of the system, and hope
* that the hardware isn't esoteric enough that we can't assume AArch64
* support to be a superset of AArch32 support...
*/
if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_L)
cfg->fmt = ARM_SMMU_CTX_FMT_AARCH32_L;
if (IS_ENABLED(CONFIG_IOMMU_IO_PGTABLE_ARMV7S) &&
!IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_ARM_LPAE) &&
(smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) &&
(smmu_domain->stage == ARM_SMMU_DOMAIN_S1))
cfg->fmt = ARM_SMMU_CTX_FMT_AARCH32_S;
if ((IS_ENABLED(CONFIG_64BIT) || cfg->fmt == ARM_SMMU_CTX_FMT_NONE) &&
(smmu->features & (ARM_SMMU_FEAT_FMT_AARCH64_64K |
ARM_SMMU_FEAT_FMT_AARCH64_16K |
ARM_SMMU_FEAT_FMT_AARCH64_4K)))
cfg->fmt = ARM_SMMU_CTX_FMT_AARCH64;
if (cfg->fmt == ARM_SMMU_CTX_FMT_NONE) {
ret = -EINVAL;
goto out_unlock;
}
switch (smmu_domain->stage) {
case ARM_SMMU_DOMAIN_S1:
cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
start = smmu->num_s2_context_banks;
ias = smmu->va_size;
oas = smmu->ipa_size;
if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) {
fmt = ARM_64_LPAE_S1;
if (smmu->options & ARM_SMMU_OPT_3LVL_TABLES)
ias = min(ias, 39UL);
} else if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_L) {
fmt = ARM_32_LPAE_S1;
ias = min(ias, 32UL);
oas = min(oas, 40UL);
} else {
fmt = ARM_V7S;
ias = min(ias, 32UL);
oas = min(oas, 32UL);
}
tlb_ops = &arm_smmu_s1_tlb_ops;
break;
case ARM_SMMU_DOMAIN_NESTED:
/*
* We will likely want to change this if/when KVM gets
* involved.
*/
case ARM_SMMU_DOMAIN_S2:
cfg->cbar = CBAR_TYPE_S2_TRANS;
start = 0;
ias = smmu->ipa_size;
oas = smmu->pa_size;
if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) {
fmt = ARM_64_LPAE_S2;
} else {
fmt = ARM_32_LPAE_S2;
ias = min(ias, 40UL);
oas = min(oas, 40UL);
}
if (smmu->version == ARM_SMMU_V2)
tlb_ops = &arm_smmu_s2_tlb_ops_v2;
else
tlb_ops = &arm_smmu_s2_tlb_ops_v1;
break;
default:
ret = -EINVAL;
goto out_unlock;
}
if (is_fast)
fmt = ARM_V8L_FAST;
if (smmu_domain->attributes & (1 << DOMAIN_ATTR_USE_UPSTREAM_HINT))
quirks |= IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT;
if (is_iommu_pt_coherent(smmu_domain))
quirks |= IO_PGTABLE_QUIRK_NO_DMA;
if (smmu_domain->attributes & (1 << DOMAIN_ATTR_USE_LLC_NWA))
quirks |= IO_PGTABLE_QUIRK_QCOM_USE_LLC_NWA;
if (((quirks & IO_PGTABLE_QUIRK_QCOM_USE_UPSTREAM_HINT) ||
(quirks & IO_PGTABLE_QUIRK_QCOM_USE_LLC_NWA)) &&
(smmu->model == QCOM_SMMUV500))
quirks |= IO_PGTABLE_QUIRK_QSMMUV500_NON_SHAREABLE;
if (arm_smmu_is_slave_side_secure(smmu_domain))
tlb_ops = &msm_smmu_gather_ops;
ret = arm_smmu_alloc_cb(domain, smmu, dev);
if (ret < 0)
goto out_unlock;
cfg->cbndx = ret;
if (arm_smmu_is_slave_side_secure(smmu_domain)) {
smmu_domain->pgtbl_cfg = (struct io_pgtable_cfg) {
.quirks = quirks,
.pgsize_bitmap = smmu->pgsize_bitmap,
.arm_msm_secure_cfg = {
.sec_id = smmu->sec_id,
.cbndx = cfg->cbndx,
},
.tlb = tlb_ops,
.iommu_dev = smmu->dev,
};
fmt = ARM_MSM_SECURE;
} else {
smmu_domain->pgtbl_cfg = (struct io_pgtable_cfg) {
.quirks = quirks,
.pgsize_bitmap = smmu->pgsize_bitmap,
.ias = ias,
.oas = oas,
.tlb = tlb_ops,
.iommu_dev = smmu->dev,
};
}
smmu_domain->smmu = smmu;
smmu_domain->dev = dev;
pgtbl_ops = alloc_io_pgtable_ops(fmt, &smmu_domain->pgtbl_cfg,
smmu_domain);
if (!pgtbl_ops) {
ret = -ENOMEM;
goto out_clear_smmu;
}
/*
* assign any page table memory that might have been allocated
* during alloc_io_pgtable_ops
*/
arm_smmu_secure_domain_lock(smmu_domain);
arm_smmu_assign_table(smmu_domain);
arm_smmu_secure_domain_unlock(smmu_domain);
/* Update the domain's page sizes to reflect the page table format */
domain->pgsize_bitmap = smmu_domain->pgtbl_cfg.pgsize_bitmap;
domain->geometry.aperture_end = (1UL << ias) - 1;
domain->geometry.force_aperture = true;
/* Assign an asid */
ret = arm_smmu_init_asid(domain, smmu);
if (ret)
goto out_clear_smmu;
if (!dynamic) {
/* Initialise the context bank with our page table cfg */
arm_smmu_init_context_bank(smmu_domain,
&smmu_domain->pgtbl_cfg);
arm_smmu_arch_init_context_bank(smmu_domain, dev);
arm_smmu_write_context_bank(smmu, cfg->cbndx,
smmu_domain->attributes );
/* for slave side secure, we may have to force the pagetable
* format to V8L.
*/
ret = arm_smmu_set_pt_format(smmu_domain,
&smmu_domain->pgtbl_cfg);
if (ret)
goto out_clear_smmu;
if (smmu->version < ARM_SMMU_V2) {
cfg->irptndx = atomic_inc_return(&smmu->irptndx);
cfg->irptndx %= smmu->num_context_irqs;
} else {
cfg->irptndx = cfg->cbndx;
}
/*
* Request context fault interrupt. Do this last to avoid the
* handler seeing a half-initialised domain state.
*/
irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
ret = devm_request_threaded_irq(smmu->dev, irq, NULL,
arm_smmu_context_fault, IRQF_ONESHOT | IRQF_SHARED,
"arm-smmu-context-fault", domain);
if (ret < 0) {
dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
cfg->irptndx, irq);
cfg->irptndx = INVALID_IRPTNDX;
goto out_clear_smmu;
}
} else {
cfg->irptndx = INVALID_IRPTNDX;
}
mutex_unlock(&smmu_domain->init_mutex);
/* Publish page table ops for map/unmap */
smmu_domain->pgtbl_ops = pgtbl_ops;
if (arm_smmu_is_slave_side_secure(smmu_domain) &&
!arm_smmu_master_attached(smmu, dev->iommu_fwspec))
arm_smmu_restore_sec_cfg(smmu, cfg->cbndx);
return 0;
out_clear_smmu:
arm_smmu_destroy_domain_context(domain);
smmu_domain->smmu = NULL;
out_unlock:
mutex_unlock(&smmu_domain->init_mutex);
return ret;
}
static void arm_smmu_domain_reinit(struct arm_smmu_domain *smmu_domain)
{
smmu_domain->cfg.irptndx = INVALID_IRPTNDX;
smmu_domain->cfg.cbndx = INVALID_CBNDX;
smmu_domain->secure_vmid = VMID_INVAL;
}
static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
{
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
struct arm_smmu_device *smmu = smmu_domain->smmu;
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
void __iomem *cb_base;
int irq;
bool dynamic;
int ret;
if (!smmu || domain->type == IOMMU_DOMAIN_IDENTITY)
return;
ret = arm_smmu_power_on(smmu->pwr);
if (ret) {
WARN_ONCE(ret, "Woops, powering on smmu %p failed. Leaking context bank\n",
smmu);
return;
}
dynamic = is_dynamic_domain(domain);
if (dynamic) {
arm_smmu_free_asid(domain);
free_io_pgtable_ops(smmu_domain->pgtbl_ops);
arm_smmu_power_off(smmu->pwr);
arm_smmu_secure_domain_lock(smmu_domain);
arm_smmu_secure_pool_destroy(smmu_domain);
arm_smmu_unassign_table(smmu_domain);
arm_smmu_secure_domain_unlock(smmu_domain);
arm_smmu_domain_reinit(smmu_domain);
return;
}
/*
* Disable the context bank and free the page tables before freeing
* it.
*/
smmu->cbs[cfg->cbndx].cfg = NULL;
cb_base = ARM_SMMU_CB(smmu, cfg->cbndx);
writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
if (cfg->irptndx != INVALID_IRPTNDX) {
irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
devm_free_irq(smmu->dev, irq, domain);
}
free_io_pgtable_ops(smmu_domain->pgtbl_ops);
arm_smmu_secure_domain_lock(smmu_domain);
arm_smmu_secure_pool_destroy(smmu_domain);
arm_smmu_unassign_table(smmu_domain);
arm_smmu_secure_domain_unlock(smmu_domain);
__arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
arm_smmu_power_off(smmu->pwr);
arm_smmu_domain_reinit(smmu_domain);
}
static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
{
struct arm_smmu_domain *smmu_domain;
/* Do not support DOMAIN_DMA for now */
if (type != IOMMU_DOMAIN_UNMANAGED &&
type != IOMMU_DOMAIN_IDENTITY)
return NULL;
/*
* Allocate the domain and initialise some of its data structures.
* We can't really do anything meaningful until we've added a
* master.
*/
smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
if (!smmu_domain)
return NULL;
if (type == IOMMU_DOMAIN_DMA && (using_legacy_binding ||
iommu_get_dma_cookie(&smmu_domain->domain))) {
kfree(smmu_domain);
return NULL;
}
mutex_init(&smmu_domain->init_mutex);
spin_lock_init(&smmu_domain->cb_lock);
spin_lock_init(&smmu_domain->sync_lock);
INIT_LIST_HEAD(&smmu_domain->pte_info_list);
INIT_LIST_HEAD(&smmu_domain->unassign_list);
mutex_init(&smmu_domain->assign_lock);
INIT_LIST_HEAD(&smmu_domain->secure_pool_list);
INIT_LIST_HEAD(&smmu_domain->nonsecure_pool);
arm_smmu_domain_reinit(smmu_domain);
return &smmu_domain->domain;
}
static void arm_smmu_domain_free(struct iommu_domain *domain)
{
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
/*
* Free the domain resources. We assume that all devices have
* already been detached.
*/
iommu_put_dma_cookie(domain);
arm_smmu_destroy_domain_context(domain);
kfree(smmu_domain);
}
static void arm_smmu_write_smr(struct arm_smmu_device *smmu, int idx)
{
struct arm_smmu_smr *smr = smmu->smrs + idx;
u32 reg = smr->id << SMR_ID_SHIFT | smr->mask << SMR_MASK_SHIFT;
if (!(smmu->features & ARM_SMMU_FEAT_EXIDS) && smr->valid)
reg |= SMR_VALID;
writel_relaxed(reg, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_SMR(idx));
}
static void arm_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
{
struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
u32 reg = (s2cr->type & S2CR_TYPE_MASK) << S2CR_TYPE_SHIFT |
(s2cr->cbndx & S2CR_CBNDX_MASK) << S2CR_CBNDX_SHIFT |
(s2cr->privcfg & S2CR_PRIVCFG_MASK) << S2CR_PRIVCFG_SHIFT |
S2CR_SHCFG_NSH << S2CR_SHCFG_SHIFT;
if (smmu->features & ARM_SMMU_FEAT_EXIDS && smmu->smrs &&
smmu->smrs[idx].valid)
reg |= S2CR_EXIDVALID;
writel_relaxed(reg, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_S2CR(idx));
}
static void arm_smmu_write_sme(struct arm_smmu_device *smmu, int idx)
{
arm_smmu_write_s2cr(smmu, idx);
if (smmu->smrs)
arm_smmu_write_smr(smmu, idx);
}
/*
* The width of SMR's mask field depends on sCR0_EXIDENABLE, so this function
* should be called after sCR0 is written.
*/
static void arm_smmu_test_smr_masks(struct arm_smmu_device *smmu)
{
unsigned long size;
void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
u32 smr, id;
int idx;
/* Check if Stream Match Register support is included */
if (!smmu->smrs)
return;
/* For slave side secure targets, as we can't write to the
* global space, set the sme mask values to default.
*/
if (arm_smmu_is_static_cb(smmu)) {
smmu->streamid_mask = SID_MASK;
smmu->smr_mask_mask = SMR_MASK_MASK;
return;
}
/* ID0 */
id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
size = (id >> ID0_NUMSMRG_SHIFT) & ID0_NUMSMRG_MASK;
/*
* Few SMR registers may be inuse before the smmu driver
* probes(say by the bootloader). Find a SMR register
* which is not inuse.
*/
for (idx = 0; idx < size; idx++) {
smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(idx));
if (!(smr & SMR_VALID))
break;
}
if (idx == size) {
dev_err(smmu->dev,
"Unable to compute streamid_masks\n");
return;
}
/*
* SMR.ID bits may not be preserved if the corresponding MASK
* bits are set, so check each one separately. We can reject
* masters later if they try to claim IDs outside these masks.
*/
smr = smmu->streamid_mask << SMR_ID_SHIFT;
writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(idx));
smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(idx));
smmu->streamid_mask = smr >> SMR_ID_SHIFT;
smr = smmu->streamid_mask << SMR_MASK_SHIFT;
writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(idx));
smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(idx));
smmu->smr_mask_mask = smr >> SMR_MASK_SHIFT;
}
static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask)
{
struct arm_smmu_smr *smrs = smmu->smrs;
int i, free_idx = -ENOSPC;
/* Stream indexing is blissfully easy */
if (!smrs)
return id;
/* Validating SMRs is... less so */
for (i = 0; i < smmu->num_mapping_groups; ++i) {
if (!smrs[i].valid) {
/*
* Note the first free entry we come across, which
* we'll claim in the end if nothing else matches.
*/
if (free_idx < 0)
free_idx = i;
continue;
}
/*
* If the new entry is _entirely_ matched by an existing entry,
* then reuse that, with the guarantee that there also cannot
* be any subsequent conflicting entries. In normal use we'd
* expect simply identical entries for this case, but there's
* no harm in accommodating the generalisation.
*/
if ((mask & smrs[i].mask) == mask &&
!((id ^ smrs[i].id) & ~smrs[i].mask))
return i;
/*
* If the new entry has any other overlap with an existing one,
* though, then there always exists at least one stream ID
* which would cause a conflict, and we can't allow that risk.
*/
if (!((id ^ smrs[i].id) & ~(smrs[i].mask | mask)))
return -EINVAL;
}
return free_idx;
}
static bool arm_smmu_free_sme(struct arm_smmu_device *smmu, int idx)
{
if (--smmu->s2crs[idx].count)
return false;
smmu->s2crs[idx] = s2cr_init_val;
if (smmu->smrs)
smmu->smrs[idx].valid = false;
return true;
}
static int arm_smmu_master_alloc_smes(struct device *dev)
{
struct iommu_fwspec *fwspec = dev->iommu_fwspec;
struct arm_smmu_master_cfg *cfg = fwspec->iommu_priv;
struct arm_smmu_device *smmu = cfg->smmu;
struct arm_smmu_smr *smrs = smmu->smrs;
struct iommu_group *group;
int i, idx, ret;
mutex_lock(&smmu->iommu_group_mutex);
mutex_lock(&smmu->stream_map_mutex);
/* Figure out a viable stream map entry allocation */
for_each_cfg_sme(fwspec, i, idx) {
u16 sid = fwspec->ids[i];
u16 mask = fwspec->ids[i] >> SMR_MASK_SHIFT;
if (idx != INVALID_SMENDX) {
ret = -EEXIST;
goto sme_err;
}
ret = arm_smmu_find_sme(smmu, sid, mask);
if (ret < 0)
goto sme_err;
idx = ret;
if (smrs && smmu->s2crs[idx].count == 0) {
smrs[idx].id = sid;
smrs[idx].mask = mask;
smrs[idx].valid = true;
}
smmu->s2crs[idx].count++;
cfg->smendx[i] = (s16)idx;
}
mutex_unlock(&smmu->stream_map_mutex);
group = iommu_group_get_for_dev(dev);
if (!group)
group = ERR_PTR(-ENOMEM);
if (IS_ERR(group)) {
ret = PTR_ERR(group);
goto iommu_group_err;
}
iommu_group_put(group);
/* It worked! Don't poke the actual hardware until we've attached */
for_each_cfg_sme(fwspec, i, idx)
smmu->s2crs[idx].group = group;
mutex_unlock(&smmu->iommu_group_mutex);
return 0;
iommu_group_err:
mutex_lock(&smmu->stream_map_mutex);
sme_err:
while (i--) {
arm_smmu_free_sme(smmu, cfg->smendx[i]);
cfg->smendx[i] = INVALID_SMENDX;
}
mutex_unlock(&smmu->stream_map_mutex);
mutex_unlock(&smmu->iommu_group_mutex);
return ret;
}
static void arm_smmu_master_free_smes(struct iommu_fwspec *fwspec)
{
struct arm_smmu_device *smmu = fwspec_smmu(fwspec);
struct arm_smmu_master_cfg *cfg = fwspec->iommu_priv;
int i, idx;
mutex_lock(&smmu->stream_map_mutex);
for_each_cfg_sme(fwspec, i, idx) {
if (arm_smmu_free_sme(smmu, idx))
arm_smmu_write_sme(smmu, idx);
cfg->smendx[i] = INVALID_SMENDX;
}
mutex_unlock(&smmu->stream_map_mutex);
}
static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
struct iommu_fwspec *fwspec)
{
struct arm_smmu_device *smmu = smmu_domain->smmu;
struct arm_smmu_s2cr *s2cr = smmu->s2crs;
int i, idx;
const struct iommu_gather_ops *tlb;
tlb = smmu_domain->pgtbl_cfg.tlb;
mutex_lock(&smmu->stream_map_mutex);
for_each_cfg_sme(fwspec, i, idx) {
if (WARN_ON(s2cr[idx].attach_count == 0)) {
mutex_unlock(&smmu->stream_map_mutex);
return;
}
s2cr[idx].attach_count -= 1;
if (s2cr[idx].attach_count > 0)
continue;
writel_relaxed(0, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_SMR(idx));
writel_relaxed(0, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_S2CR(idx));
}
mutex_unlock(&smmu->stream_map_mutex);
/* Ensure there are no stale mappings for this context bank */
tlb->tlb_flush_all(smmu_domain);
}
static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
struct iommu_fwspec *fwspec)
{
struct arm_smmu_device *smmu = smmu_domain->smmu;
struct arm_smmu_s2cr *s2cr = smmu->s2crs;
u8 cbndx = smmu_domain->cfg.cbndx;
enum arm_smmu_s2cr_type type;
int i, idx;
if (smmu_domain->stage == ARM_SMMU_DOMAIN_BYPASS)
type = S2CR_TYPE_BYPASS;
else
type = S2CR_TYPE_TRANS;
mutex_lock(&smmu->stream_map_mutex);
for_each_cfg_sme(fwspec, i, idx) {
if (s2cr[idx].attach_count++ > 0)
continue;
s2cr[idx].type = type;
s2cr[idx].privcfg = S2CR_PRIVCFG_DEFAULT;
s2cr[idx].cbndx = cbndx;
arm_smmu_write_sme(smmu, idx);
}
mutex_unlock(&smmu->stream_map_mutex);
return 0;
}
static void arm_smmu_detach_dev(struct iommu_domain *domain,
struct device *dev)
{
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
struct arm_smmu_device *smmu = smmu_domain->smmu;
struct iommu_fwspec *fwspec = dev->iommu_fwspec;
int dynamic = smmu_domain->attributes & (1 << DOMAIN_ATTR_DYNAMIC);
int atomic_domain = smmu_domain->attributes & (1 << DOMAIN_ATTR_ATOMIC);
if (dynamic)
return;
if (!smmu) {
dev_err(dev, "Domain not attached; cannot detach!\n");
return;
}
if (atomic_domain)
arm_smmu_power_on_atomic(smmu->pwr);
else
arm_smmu_power_on(smmu->pwr);
arm_smmu_domain_remove_master(smmu_domain, fwspec);
arm_smmu_power_off(smmu->pwr);
}
static int arm_smmu_assign_table(struct arm_smmu_domain *smmu_domain)
{
int ret = 0;
int dest_vmids[2] = {VMID_HLOS, smmu_domain->secure_vmid};
int dest_perms[2] = {PERM_READ | PERM_WRITE, PERM_READ};
int source_vmid = VMID_HLOS;
struct arm_smmu_pte_info *pte_info, *temp;
if (!arm_smmu_is_master_side_secure(smmu_domain))
return ret;
list_for_each_entry(pte_info, &smmu_domain->pte_info_list, entry) {
ret = hyp_assign_phys(virt_to_phys(pte_info->virt_addr),
PAGE_SIZE, &source_vmid, 1,
dest_vmids, dest_perms, 2);
if (WARN_ON(ret))
break;
}
list_for_each_entry_safe(pte_info, temp, &smmu_domain->pte_info_list,
entry) {
list_del(&pte_info->entry);
kfree(pte_info);
}
return ret;
}
static void arm_smmu_unassign_table(struct arm_smmu_domain *smmu_domain)
{
int ret;
int dest_vmids = VMID_HLOS;
int dest_perms = PERM_READ | PERM_WRITE | PERM_EXEC;
int source_vmlist[2] = {VMID_HLOS, smmu_domain->secure_vmid};
struct arm_smmu_pte_info *pte_info, *temp;
if (!arm_smmu_is_master_side_secure(smmu_domain))
return;
list_for_each_entry(pte_info, &smmu_domain->unassign_list, entry) {
ret = hyp_assign_phys(virt_to_phys(pte_info->virt_addr),
PAGE_SIZE, source_vmlist, 2,
&dest_vmids, &dest_perms, 1);
if (WARN_ON(ret))
break;
free_pages_exact(pte_info->virt_addr, pte_info->size);
}
list_for_each_entry_safe(pte_info, temp, &smmu_domain->unassign_list,
entry) {
list_del(&pte_info->entry);
kfree(pte_info);
}
}
static void arm_smmu_unprepare_pgtable(void *cookie, void *addr, size_t size)
{
struct arm_smmu_domain *smmu_domain = cookie;
struct arm_smmu_pte_info *pte_info;
if (smmu_domain->slave_side_secure ||
!arm_smmu_has_secure_vmid(smmu_domain)) {
if (smmu_domain->slave_side_secure)
WARN(1, "slave side secure is enforced\n");
else
WARN(1, "Invalid VMID is set !!\n");
return;
}
pte_info = kzalloc(sizeof(struct arm_smmu_pte_info), GFP_ATOMIC);
if (!pte_info)
return;
pte_info->virt_addr = addr;
pte_info->size = size;
list_add_tail(&pte_info->entry, &smmu_domain->unassign_list);
}
static int arm_smmu_prepare_pgtable(void *addr, void *cookie)
{
struct arm_smmu_domain *smmu_domain = cookie;
struct arm_smmu_pte_info *pte_info;
if (smmu_domain->slave_side_secure ||
!arm_smmu_has_secure_vmid(smmu_domain)) {
if (smmu_domain->slave_side_secure)
WARN(1, "slave side secure is enforced\n");
else
WARN(1, "Invalid VMID is set !!\n");
return -EINVAL;
}
pte_info = kzalloc(sizeof(struct arm_smmu_pte_info), GFP_ATOMIC);
if (!pte_info)
return -ENOMEM;
pte_info->virt_addr = addr;
list_add_tail(&pte_info->entry, &smmu_domain->pte_info_list);
return 0;
}
static void arm_smmu_prealloc_memory(struct arm_smmu_domain *smmu_domain,
size_t size, struct list_head *pool)
{
int i;
u32 nr = 0;
struct page *page;
if ((smmu_domain->attributes & (1 << DOMAIN_ATTR_ATOMIC)) ||
arm_smmu_has_secure_vmid(smmu_domain))
return;
/* number of 2nd level pagetable entries */
nr += round_up(size, SZ_1G) >> 30;
/* number of 3rd level pagetabel entries */
nr += round_up(size, SZ_2M) >> 21;
/* Retry later with atomic allocation on error */
for (i = 0; i < nr; i++) {
page = alloc_pages(GFP_KERNEL | __GFP_ZERO, 0);
if (!page)
break;
list_add(&page->lru, pool);
}
}
static void arm_smmu_prealloc_memory_sg(struct arm_smmu_domain *smmu_domain,
struct scatterlist *sgl, int nents,
struct list_head *pool)
{
int i;
size_t size = 0;
struct scatterlist *sg;
if ((smmu_domain->attributes & (1 << DOMAIN_ATTR_ATOMIC)) ||
arm_smmu_has_secure_vmid(smmu_domain))
return;
for_each_sg(sgl, sg, nents, i)
size += sg->length;
arm_smmu_prealloc_memory(smmu_domain, size, pool);
}
static void arm_smmu_release_prealloc_memory(
struct arm_smmu_domain *smmu_domain, struct list_head *list)
{
struct page *page, *tmp;
list_for_each_entry_safe(page, tmp, list, lru) {
list_del(&page->lru);
__free_pages(page, 0);
}
}
static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
{
int ret;
struct iommu_fwspec *fwspec = dev->iommu_fwspec;
struct arm_smmu_device *smmu;
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);