Merge "msm: ep_pcie: update pcie parameters"
diff --git a/Documentation/devicetree/bindings/pci/msm_ep_pcie.txt b/Documentation/devicetree/bindings/pci/msm_ep_pcie.txt
index faf56c2..3e265a1 100644
--- a/Documentation/devicetree/bindings/pci/msm_ep_pcie.txt
+++ b/Documentation/devicetree/bindings/pci/msm_ep_pcie.txt
@@ -33,10 +33,10 @@
- qcom,<supply-name>-voltage-level: specifies voltage levels for supply.
Should be specified in pairs (max, min, optimal), units uV.
- clock-names: list of names of clock inputs.
- Should be "pcie_0_pipe_clk",
- "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
- "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
- "pcie_0_ldo";
+ Should be "pcie_pipe_clk",
+ "pcie_aux_clk", "pcie_cfg_ahb_clk",
+ "pcie_mstr_axi_clk", "pcie_slv_axi_clk",
+ "pcie_ldo";
- max-clock-frequency-hz: list of the maximum operating frequencies stored
in the same order of clock names;
- resets: reset specifier pair consists of phandle for the reset controller
@@ -105,17 +105,17 @@
qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>;
qcom,vreg-0.9-voltage-level = <950000 950000 24000>;
- clock-names = "pcie_0_pipe_clk",
- "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
- "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
- "pcie_0_ldo";
+ clock-names = "pcie_pipe_clk",
+ "pcie_aux_clk", "pcie_cfg_ahb_clk",
+ "pcie_mstr_axi_clk", "pcie_slv_axi_clk",
+ "pcie_ldo";
max-clock-frequency-hz = <62500000>, <1000000>,
<0>, <0>, <0>, <0>;
resets = <&clock_gcc GCC_PCIE_BCR>,
<&clock_gcc GCC_PCIE_PHY_BCR>;
- reset-names = "pcie_0_core_reset", "pcie_0_phy_reset";
+ reset-names = "pcie_core_reset", "pcie_phy_reset";
qcom,msm-bus,name = "pcie-ep";
qcom,msm-bus,num-cases = <2>;
diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_com.h b/drivers/platform/msm/ep_pcie/ep_pcie_com.h
index 36d49e4..9a5877e 100644
--- a/drivers/platform/msm/ep_pcie/ep_pcie_com.h
+++ b/drivers/platform/msm/ep_pcie/ep_pcie_com.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -154,7 +154,7 @@
#define MAX_IATU_ENTRY_NUM 2
#define EP_PCIE_LOG_PAGES 50
-#define EP_PCIE_MAX_VREG 2
+#define EP_PCIE_MAX_VREG 3
#define EP_PCIE_MAX_CLK 7
#define EP_PCIE_MAX_PIPE_CLK 1
#define EP_PCIE_MAX_RESET 2
diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c
index a676f4e..3a9e168 100644
--- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c
+++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -52,6 +52,7 @@ struct ep_pcie_dev_t ep_pcie_dev = {0};
static struct ep_pcie_vreg_info_t ep_pcie_vreg_info[EP_PCIE_MAX_VREG] = {
{NULL, "vreg-1.8", 1800000, 1800000, 14000, true},
{NULL, "vreg-0.9", 1000000, 1000000, 40000, true},
+ {NULL, "vreg-cx", 0, 0, 0, false}
};
static struct ep_pcie_gpio_info_t ep_pcie_gpio_info[EP_PCIE_MAX_GPIO] = {
@@ -63,24 +64,24 @@ static struct ep_pcie_gpio_info_t ep_pcie_gpio_info[EP_PCIE_MAX_GPIO] = {
static struct ep_pcie_clk_info_t
ep_pcie_clk_info[EP_PCIE_MAX_CLK] = {
- {NULL, "pcie_0_cfg_ahb_clk", 0, true},
- {NULL, "pcie_0_mstr_axi_clk", 0, true},
- {NULL, "pcie_0_slv_axi_clk", 0, true},
- {NULL, "pcie_0_aux_clk", 1000000, true},
- {NULL, "pcie_0_ldo", 0, true},
- {NULL, "pcie_0_sleep_clk", 0, false},
- {NULL, "pcie_0_slv_q2a_axi_clk", 0, false},
+ {NULL, "pcie_cfg_ahb_clk", 0, true},
+ {NULL, "pcie_mstr_axi_clk", 0, true},
+ {NULL, "pcie_slv_axi_clk", 0, true},
+ {NULL, "pcie_aux_clk", 1000000, true},
+ {NULL, "pcie_ldo", 0, true},
+ {NULL, "pcie_sleep_clk", 0, false},
+ {NULL, "pcie_slv_q2a_axi_clk", 0, false},
};
static struct ep_pcie_clk_info_t
ep_pcie_pipe_clk_info[EP_PCIE_MAX_PIPE_CLK] = {
- {NULL, "pcie_0_pipe_clk", 62500000, true},
+ {NULL, "pcie_pipe_clk", 62500000, true},
};
static struct ep_pcie_reset_info_t
ep_pcie_reset_info[EP_PCIE_MAX_RESET] = {
- {NULL, "pcie_0_core_reset", false},
- {NULL, "pcie_0_phy_reset", false},
+ {NULL, "pcie_core_reset", false},
+ {NULL, "pcie_phy_reset", false},
};
static const struct ep_pcie_res_info_t ep_pcie_res_info[EP_PCIE_MAX_RES] = {
@@ -1280,15 +1281,6 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt)
goto clk_fail;
}
- /* enable pipe clock */
- ret = ep_pcie_pipe_clk_init(dev);
- if (ret) {
- EP_PCIE_ERR(dev,
- "PCIe V%d: failed to enable pipe clock\n",
- dev->rev);
- goto pipe_clk_fail;
- }
-
dev->power_on = true;
}
@@ -1381,7 +1373,16 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt)
/* init PCIe PHY */
ep_pcie_phy_init(dev);
- EP_PCIE_DBG(dev, "PCIe V%d: waiting for phy ready\n", dev->rev);
+ /* enable pipe clock */
+ ret = ep_pcie_pipe_clk_init(dev);
+ if (ret) {
+ EP_PCIE_ERR(dev,
+ "PCIe V%d: failed to enable pipe clock\n",
+ dev->rev);
+ goto pipe_clk_fail;
+ }
+
+ EP_PCIE_DBG(dev, "PCIe V%d: waiting for phy ready...\n", dev->rev);
retries = 0;
do {
if (ep_pcie_phy_is_ready(dev))
@@ -1966,7 +1967,6 @@ int32_t ep_pcie_irq_init(struct ep_pcie_dev_t *dev)
EP_PCIE_ERR(dev,
"PCIe V%d: Unable to enable wake for Global interrupt\n",
dev->rev);
- return ret;
}
EP_PCIE_DBG(dev,
