blob: 53ff99a3f58aad7ab0b6c4c79f10176c7f6890d6 [file] [log] [blame]
/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "skeleton64.dtsi"
#include <dt-bindings/clock/qcom,gcc-sdm660.h>
#include <dt-bindings/clock/qcom,gpu-sdm660.h>
#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/audio-ext-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
#include <dt-bindings/clock/qcom,cpu-osm.h>
/ {
model = "Qualcomm Technologies, Inc. SDM 660";
compatible = "qcom,sdm660";
qcom,msm-id = <317 0x0>;
interrupt-parent = <&intc>;
aliases {
serial0 = &uartblsp1dm1;
sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
sdhc2 = &sdhc_2; /* SDC2 for SD card */
};
chosen {
stdout-path = "serial0";
bootargs = "rcupdate.rcu_expedited=1";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
qcom,ea = <&ea0>;
efficiency = <1024>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
/* A53 L2 dump not supported */
qcom,dump-size = <0x0>;
};
L1_I_0: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9040>;
};
L1_D_0: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9040>;
};
L1_TLB_0: l1-tlb {
qcom,dump-size = <0x2800>;
};
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
qcom,ea = <&ea1>;
efficiency = <1024>;
next-level-cache = <&L2_0>;
L1_I_1: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9040>;
};
L1_D_1: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9040>;
};
L1_TLB_1: l1-tlb {
qcom,dump-size = <0x2800>;
};
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
qcom,ea = <&ea2>;
efficiency = <1024>;
next-level-cache = <&L2_0>;
L1_I_2: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9040>;
};
L1_D_2: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9040>;
};
L1_TLB_2: l1-tlb {
qcom,dump-size = <0x2800>;
};
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
qcom,ea = <&ea3>;
efficiency = <1024>;
next-level-cache = <&L2_0>;
L1_I_3: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9040>;
};
L1_D_3: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9040>;
};
L1_TLB_3: l1-tlb {
qcom,dump-size = <0x2800>;
};
};
CPU4: cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile1>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
qcom,ea = <&ea4>;
efficiency = <1638>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
};
L1_I_100: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x12000>;
};
L1_D_100: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x12000>;
};
L1_TLB_100: l1-tlb {
qcom,dump-size = <0x4800>;
};
};
CPU5: cpu@101 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile2>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
qcom,ea = <&ea5>;
efficiency = <1638>;
next-level-cache = <&L2_1>;
L1_I_101: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x12000>;
};
L1_D_101: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x12000>;
};
L1_TLB_101: l1-tlb {
qcom,dump-size = <0x4800>;
};
};
CPU6: cpu@102 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile3>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
qcom,ea = <&ea6>;
efficiency = <1638>;
next-level-cache = <&L2_1>;
L1_I_102: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x12000>;
};
L1_D_102: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x12000>;
};
L1_TLB_102: l1-tlb {
qcom,dump-size = <0x4800>;
};
};
CPU7: cpu@103 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile4>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
qcom,ea = <&ea7>;
efficiency = <1638>;
next-level-cache = <&L2_1>;
L1_I_103: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x12000>;
};
L1_D_103: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x12000>;
};
L1_TLB_103: l1-tlb {
qcom,dump-size = <0x4800>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
};
};
clocks {
xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
clock-output-names = "xo_board";
};
sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32764>;
clock-output-names = "sleep_clk";
};
};
soc: soc { };
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
removed_regions: removed_regions@85800000 {
compatible = "removed-dma-pool";
no-map;
reg = <0x0 0x85800000 0x0 0x3700000>;
};
modem_fw_mem: modem_fw_region@8ac00000 {
compatible = "removed-dma-pool";
no-map;
reg = <0x0 0x8ac00000 0x0 0x7e00000>;
};
adsp_fw_mem: adsp_fw_region@92a00000 {
compatible = "removed-dma-pool";
no-map;
reg = <0x0 0x92a00000 0x0 0x1e00000>;
};
pil_mba_mem: pil_mba_region@94800000 {
compatible = "removed-dma-pool";
no-map;
reg = <0x0 0x94800000 0x0 0x200000>;
};
cdsp_fw_mem: cdsp_fw_region@94a00000 {
compatible = "removed-dma-pool";
no-map;
reg = <0x0 0x94a00000 0x0 0x600000>;
};
venus_fw_mem: venus_fw_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x80000000 0x0 0x20000000>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x800000>;
};
adsp_mem: adsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x800000>;
};
qseecom_mem: qseecom_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
secure_display_memory: secure_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x5c00000>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0x2c00000>;
linux,cma-default;
};
cont_splash_mem: splash_region@9d400000 {
reg = <0x0 0x9d400000 0x0 0x02400000>;
label = "cont_splash_mem";
};
};
bluetooth: bt_wcn3990 {
compatible = "qca,wcn3990";
qca,bt-vdd-core-supply = <&pm660_l9>;
qca,bt-vdd-pa-supply = <&pm660_l6>;
qca,bt-vdd-ldo-supply = <&pm660_l19>;
qca,bt-chip-pwd-supply = <&pm660l_bob_pin1>;
clocks = <&clock_rpmcc RPM_RF_CLK1_PIN>;
clock-names = "rf_clk1";
qca,bt-vdd-core-voltage-level = <1800000 1900000>;
qca,bt-vdd-pa-voltage-level = <1304000 1370000>;
qca,bt-vdd-ldo-voltage-level = <3312000 3400000>;
qca,bt-chip-pwd-voltage-level = <3600000 3600000>;
qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */
};
};
#include "sdm660-smp2p.dtsi"
#include "sdm660-coresight.dtsi"
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
reg = <0x17a00000 0x10000>, /* GICD */
<0x17b00000 0x100000>; /* GICR * 8 */
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
interrupts = <1 9 4>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 1 0xf08>,
<1 2 0xf08>,
<1 3 0xf08>,
<1 0 0xf08>;
clock-frequency = <19200000>;
};
dma_blsp1: qcom,sps-dma@0xc144000{ /* BLSP1 */
#dma-cells = <4>;
compatible = "qcom,sps-dma";
reg = <0xc144000 0x1F000>;
interrupts = <0 238 0>;
qcom,summing-threshold = <0x10>;
};
dma_blsp2: qcom,sps-dma@0xc184000{ /* BLSP2 */
#dma-cells = <4>;
compatible = "qcom,sps-dma";
reg = <0xc184000 0x1F000>;
interrupts = <0 239 0>;
qcom,summing-threshold = <0x10>;
};
restart@10ac000 {
compatible = "qcom,pshold";
reg = <0x10ac000 0x4>,
<0x1fd3000 0x4>;
reg-names = "pshold-base", "tcsr-boot-misc-detect";
};
spmi_bus: qcom,spmi@800f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x800f000 0x1000>,
<0x8400000 0x1000000>,
<0x9400000 0x1000000>,
<0xa400000 0x220000>,
<0x800a000 0x3000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;
status = "ok";
};
cpuss_dump {
compatible = "qcom,cpuss-dump";
qcom,l1_i_cache0 {
qcom,dump-node = <&L1_I_0>;
qcom,dump-id = <0x60>;
};
qcom,l1_i_cache1 {
qcom,dump-node = <&L1_I_1>;
qcom,dump-id = <0x61>;
};
qcom,l1_i_cache2 {
qcom,dump-node = <&L1_I_2>;
qcom,dump-id = <0x62>;
};
qcom,l1_i_cache3 {
qcom,dump-node = <&L1_I_3>;
qcom,dump-id = <0x63>;
};
qcom,l1_i_cache100 {
qcom,dump-node = <&L1_I_100>;
qcom,dump-id = <0x64>;
};
qcom,l1_i_cache101 {
qcom,dump-node = <&L1_I_101>;
qcom,dump-id = <0x65>;
};
qcom,l1_i_cache102 {
qcom,dump-node = <&L1_I_102>;
qcom,dump-id = <0x66>;
};
qcom,l1_i_cache103 {
qcom,dump-node = <&L1_I_103>;
qcom,dump-id = <0x67>;
};
qcom,l1_d_cache0 {
qcom,dump-node = <&L1_D_0>;
qcom,dump-id = <0x80>;
};
qcom,l1_d_cache1 {
qcom,dump-node = <&L1_D_1>;
qcom,dump-id = <0x81>;
};
qcom,l1_d_cache2 {
qcom,dump-node = <&L1_D_2>;
qcom,dump-id = <0x82>;
};
qcom,l1_d_cache3 {
qcom,dump-node = <&L1_D_3>;
qcom,dump-id = <0x83>;
};
qcom,l1_d_cache100 {
qcom,dump-node = <&L1_D_100>;
qcom,dump-id = <0x84>;
};
qcom,l1_d_cache101 {
qcom,dump-node = <&L1_D_101>;
qcom,dump-id = <0x85>;
};
qcom,l1_d_cache102 {
qcom,dump-node = <&L1_D_102>;
qcom,dump-id = <0x86>;
};
qcom,l1_d_cache103 {
qcom,dump-node = <&L1_D_103>;
qcom,dump-id = <0x87>;
};
qcom,l1_tlb_dump0 {
qcom,dump-node = <&L1_TLB_0>;
qcom,dump-id = <0x20>;
};
qcom,l1_tlb_dump1 {
qcom,dump-node = <&L1_TLB_1>;
qcom,dump-id = <0x21>;
};
qcom,l1_tlb_dump2 {
qcom,dump-node = <&L1_TLB_2>;
qcom,dump-id = <0x22>;
};
qcom,l1_tlb_dump3 {
qcom,dump-node = <&L1_TLB_3>;
qcom,dump-id = <0x23>;
};
qcom,l1_tlb_dump100 {
qcom,dump-node = <&L1_TLB_100>;
qcom,dump-id = <0x24>;
};
qcom,l1_tlb_dump101 {
qcom,dump-node = <&L1_TLB_101>;
qcom,dump-id = <0x25>;
};
qcom,l1_tlb_dump102 {
qcom,dump-node = <&L1_TLB_102>;
qcom,dump-id = <0x26>;
};
qcom,l1_tlb_dump103 {
qcom,dump-node = <&L1_TLB_103>;
qcom,dump-id = <0x27>;
};
};
wdog: qcom,wdt@17817000 {
compatible = "qcom,msm-watchdog";
reg = <0x17817000 0x1000>;
reg-names = "wdt-base";
interrupts = <0 3 0>, <0 4 0>;
qcom,bark-time = <11000>;
qcom,pet-time = <10000>;
qcom,ipi-ping;
qcom,wakeup-enable;
qcom,scandump-size = <0x40000>;
};
qcom,sps {
compatible = "qcom,msm_sps_4k";
qcom,pipe-attr-ee;
};
qcom,memshare {
compatible = "qcom,memshare";
qcom,client_1 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x200000>;
qcom,client-id = <0>;
qcom,allocate-boot-time;
label = "modem";
};
qcom,client_2 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x300000>;
qcom,client-id = <2>;
label = "modem";
};
mem_client_3_size: qcom,client_3 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x0>;
qcom,client-id = <1>;
qcom,allocate-boot-time;
label = "modem";
};
};
tsens: tsens@10ad000 {
compatible = "qcom,sdm660-tsens";
reg = <0x10ad000 0x2000>,
<0x784240 0x1000>;
reg-names = "tsens_physical", "tsens_eeprom_physical";
interrupts = <0 184 0>, <0 430 0>;
interrupt-names = "tsens-upper-lower", "tsens-critical";
qcom,client-id = <0 1 2 3 4 5 6 7 8 9 10 11 12 13>;
qcom,sensor-id = <0 10 11 4 5 6 7 8 13 2 3 12 9 1>;
qcom,sensors = <14>;
qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200
3200 3200 3200 3200 3200 3200>;
};
uartblsp1dm1: serial@0c170000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xc170000 0x1000>;
interrupts = <0 108 0>;
status = "disabled";
clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
<&clock_gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
};
qcom,sensor-information {
compatible = "qcom,sensor-information";
sensor_information0: qcom,sensor-information-0 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor0";
qcom,scaling-factor = <10>;
};
sensor_information1: qcom,sensor-information-1 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor1";
qcom,scaling-factor = <10>;
};
sensor_information2: qcom,sensor-information-2 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor2";
qcom,scaling-factor = <10>;
};
sensor_information3: qcom,sensor-information-3 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor3";
qcom,scaling-factor = <10>;
};
sensor_information4: qcom,sensor-information-4 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor4";
qcom,scaling-factor = <10>;
};
sensor_information5: qcom,sensor-information-5 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor5";
qcom,scaling-factor = <10>;
};
sensor_information6: qcom,sensor-information-6 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor6";
qcom,scaling-factor = <10>;
};
sensor_information7: qcom,sensor-information-7 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor7";
qcom,scaling-factor = <10>;
};
sensor_information8: qcom,sensor-information-8 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor8";
qcom,scaling-factor = <10>;
qcom,alias-name = "gpu";
};
sensor_information9: qcom,sensor-information-9 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor9";
qcom,scaling-factor = <10>;
};
sensor_information10: qcom,sensor-information-10 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor10";
qcom,scaling-factor = <10>;
};
sensor_information11: qcom,sensor-information-11 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor11";
qcom,scaling-factor = <10>;
};
sensor_information12: qcom,sensor-information-12 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor12";
qcom,scaling-factor = <10>;
};
sensor_information13: qcom,sensor-information-13 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor13";
qcom,scaling-factor = <10>;
};
sensor_information14: qcom,sensor-information-14 {
qcom,sensor-type = "alarm";
qcom,sensor-name = "pm660_tz";
qcom,scaling-factor = <1000>;
};
sensor_information15: qcom,sensor-information-15 {
qcom,sensor-type = "adc";
qcom,sensor-name = "msm_therm";
};
sensor_information16: qcom,sensor-information-16 {
qcom,sensor-type = "adc";
qcom,sensor-name = "xo_therm";
};
sensor_information17: qcom,sensor-information-17 {
qcom,sensor-type = "adc";
qcom,sensor-name = "pa_therm0";
};
sensor_information18: qcom,sensor-information-18 {
qcom,sensor-type = "adc";
qcom,sensor-name = "pa_therm1";
};
sensor_information19: qcom,sensor-information-19 {
qcom,sensor-type = "adc";
qcom,sensor-name = "quiet_therm";
};
sensor_information20: qcom,sensor-information-20 {
qcom,sensor-type = "llm";
qcom,sensor-name = "limits_sensor-00";
};
sensor_information21: qcom,sensor-information-21 {
qcom,sensor-type = "llm";
qcom,sensor-name = "limits_sensor-01";
};
};
mitigation_profile0: qcom,limit_info-0 {
qcom,temperature-sensor = <&sensor_information1>;
qcom,hotplug-mitigation-enable;
};
mitigation_profile1: qcom,limit_info-1 {
qcom,temperature-sensor = <&sensor_information3>;
qcom,hotplug-mitigation-enable;
};
mitigation_profile2: qcom,limit_info-2 {
qcom,temperature-sensor = <&sensor_information4>;
qcom,hotplug-mitigation-enable;
};
mitigation_profile3: qcom,limit_info-3 {
qcom,temperature-sensor = <&sensor_information5>;
qcom,hotplug-mitigation-enable;
};
mitigation_profile4: qcom,limit_info-4 {
qcom,temperature-sensor = <&sensor_information6>;
qcom,hotplug-mitigation-enable;
};
qcom,msm-thermal {
compatible = "qcom,msm-thermal";
qcom,sensor-id = <1>;
qcom,poll-ms = <100>;
qcom,therm-reset-temp = <115>;
qcom,core-limit-temp = <70>;
qcom,core-temp-hysteresis = <10>;
qcom,hotplug-temp = <105>;
qcom,hotplug-temp-hysteresis = <20>;
qcom,online-hotplug-core;
qcom,synchronous-cluster-id = <0 1>;
qcom,synchronous-cluster-map = <0 4 &CPU0 &CPU1 &CPU2 &CPU3>,
<1 4 &CPU4 &CPU5 &CPU6 &CPU7>;
clock-names = "osm";
clocks = <&clock_cpu PWRCL_CLK>;
qcom,cxip-lm-enable = <1>;
qcom,vdd-restriction-temp = <5>;
qcom,vdd-restriction-temp-hysteresis = <10>;
vdd-dig-supply = <&pm660l_s3_floor_level>;
vdd-gfx-supply = <&gfx_vreg_corner>;
qcom,vdd-dig-rstr{
qcom,vdd-rstr-reg = "vdd-dig";
qcom,levels = <RPM_SMD_REGULATOR_LEVEL_NOM
RPM_SMD_REGULATOR_LEVEL_TURBO
RPM_SMD_REGULATOR_LEVEL_TURBO>;
qcom,min-level = <RPM_SMD_REGULATOR_LEVEL_NONE>;
};
qcom,vdd-gfx-rstr{
qcom,vdd-rstr-reg = "vdd-gfx";
qcom,levels = <5 6 6>; /* Nominal, Turbo, Turbo */
qcom,min-level = <1>; /* No Request */
};
msm_thermal_freq: qcom,vdd-apps-rstr{
qcom,vdd-rstr-reg = "vdd-apps";
qcom,levels = <1248000>;
qcom,freq-req;
};
};
cx_ipeak_lm: cx_ipeak@1fe5040 {
compatible = "qcom,cx-ipeak-sdm660";
reg = <0x1fe5040 0x28>;
};
qcom,bcl {
compatible = "qcom,bcl";
qcom,bcl-enable;
qcom,bcl-framework-interface;
qcom,bcl-hotplug-list = <&CPU6 &CPU7>;
qcom,bcl-soc-hotplug-list = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,ibat-monitor {
qcom,low-threshold-uamp = <3400000>;
qcom,high-threshold-uamp = <4200000>;
qcom,vph-high-threshold-uv = <3500000>;
qcom,vph-low-threshold-uv = <3300000>;
qcom,soc-low-threshold = <10>;
};
};
qcom,lmh {
compatible = "qcom,lmh_v1";
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
};
qcom,msm-core@780000 {
compatible = "qcom,apss-core-ea";
reg = <0x780000 0x1000>;
qcom,low-hyst-temp = <100>;
qcom,high-hyst-temp = <100>;
ea0: ea0 {
sensor = <&sensor_information1>;
};
ea1: ea1 {
sensor = <&sensor_information1>;
};
ea2: ea2 {
sensor = <&sensor_information1>;
};
ea3: ea3 {
sensor = <&sensor_information1>;
};
ea4: ea4 {
sensor = <&sensor_information3>;
};
ea5: ea5 {
sensor = <&sensor_information4>;
};
ea6: ea6 {
sensor = <&sensor_information5>;
};
ea7: ea7 {
sensor = <&sensor_information6>;
};
};
uartblsp2dm1: serial@0c1b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xc1b0000 0x1000>;
interrupts = <0 114 0>;
status = "disabled";
clocks = <&clock_gcc GCC_BLSP2_UART2_APPS_CLK>,
<&clock_gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
};
slim_aud: slim@151c0000 {
cell-index = <1>;
compatible = "qcom,slim-ngd";
reg = <0x151c0000 0x2c000>,
<0x15184000 0x2a000>;
reg-names = "slimbus_physical", "slimbus_bam_physical";
interrupts = <0 163 0>, <0 164 0>;
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
qcom,apps-ch-pipes = <0x7e0000>;
qcom,ea-pc = <0x260>;
status = "disabled";
};
slim_qca: slim@15240000 {
cell-index = <3>;
compatible = "qcom,slim-ngd";
reg = <0x15240000 0x2c000>,
<0x15204000 0x20000>;
reg-names = "slimbus_physical", "slimbus_bam_physical";
interrupts = <0 291 0>, <0 292 0>;
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
qcom,apps-ch-pipes = <0x1800>;
/* Slimbus Slave DT for WCN3990 */
btfmslim_codec: wcn3990 {
compatible = "qcom,btfmslim_slave";
elemental-addr = [00 01 20 02 17 02];
qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
};
};
timer@17920000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17920000 0x1000>;
clock-frequency = <19200000>;
frame@17921000 {
frame-number = <0>;
interrupts = <0 8 0x4>,
<0 7 0x4>;
reg = <0x17921000 0x1000>,
<0x17922000 0x1000>;
};
frame@17923000 {
frame-number = <1>;
interrupts = <0 9 0x4>;
reg = <0x17923000 0x1000>;
status = "disabled";
};
frame@17924000 {
frame-number = <2>;
interrupts = <0 10 0x4>;
reg = <0x17924000 0x1000>;
status = "disabled";
};
frame@17925000 {
frame-number = <3>;
interrupts = <0 11 0x4>;
reg = <0x17925000 0x1000>;
status = "disabled";
};
frame@17926000 {
frame-number = <4>;
interrupts = <0 12 0x4>;
reg = <0x17926000 0x1000>;
status = "disabled";
};
frame@17927000 {
frame-number = <5>;
interrupts = <0 13 0x4>;
reg = <0x17927000 0x1000>;
status = "disabled";
};
frame@17928000 {
frame-number = <6>;
interrupts = <0 14 0x4>;
reg = <0x17928000 0x1000>;
status = "disabled";
};
};
arm64-cpu-erp {
compatible = "arm,arm64-cpu-erp";
interrupts = <0 43 4>,
<0 44 4>,
<0 41 4>,
<0 42 4>;
interrupt-names = "pri-dbe-irq",
"sec-dbe-irq",
"pri-ext-irq",
"sec-ext-irq";
poll-delay-ms = <5000>;
};
clock_rpmcc: qcom,rpmcc {
compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
#clock-cells = <1>;
};
clock_gcc: clock-controller@100000 {
compatible = "qcom,gcc-sdm660", "syscon";
reg = <0x100000 0x94000>;
vdd_dig-supply = <&pm660l_s3_level>;
vdd_dig_ao-supply = <&pm660l_s3_level_ao>;
#clock-cells = <1>;
#reset-cells = <1>;
};
clock_mmss: clock-controller@c8c0000 {
compatible = "qcom,mmcc-sdm660";
reg = <0xc8c0000 0x40000>;
vdd_mx_mmss-supply = <&pm660l_s5_level>;
vdd_dig_mmss-supply = <&pm660l_s3_level>;
vdda-supply = <&pm660_l10>;
#clock-cells = <1>;
#reset-cells = <1>;
};
clock_gpu: clock-controller@5065000 {
compatible = "qcom,gpu-sdm660";
reg = <0x5065000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
clock_gfx: gfx@5065000 {
compatible = "qcom,gpucc-sdm660";
reg = <0x5065000 0x10000>;
vdd_dig_gfx-supply = <&pm660l_s3_level>;
vdd_mx_gfx-supply = <&pm660l_s5_level>;
vdd_gfx-supply = <&gfx_vreg_corner>;
qcom,gfxfreq-corner =
< 0 0>,
< 160000000 1>, /* MinSVS */
< 266000000 2>, /* LowSVS */
< 370000000 3>, /* SVS */
< 465000000 4>, /* SVS_L1 */
< 588000000 5>, /* NOM */
< 647000000 6>, /* NOM_L1 */
< 700000000 7>, /* TURBO */
< 750000000 7>; /* TURBO */
#clock-cells = <1>;
#reset-cells = <1>;
};
cpu_debug: syscon@1791101c {
compatible = "syscon";
reg = <0x1791101c 0x4>;
};
gpu_debug: syscon@05065120 {
compatible = "syscon";
reg = <0x05065120 0x4>;
};
mmss_debug: syscon@c8c0900 {
compatible = "syscon";
reg = <0xc8c0900 0x4>;
};
clock_debug: qcom,cc-debug@62000 {
compatible = "qcom,gcc-debug-sdm660";
reg = <0x62000 0x4>;
reg-names = "dbg_offset";
clocks = <&clock_rpmcc RPM_XO_CLK_SRC>;
clock-names = "xo_clk_src";
qcom,cc-count = <4>;
qcom,gcc = <&clock_gcc>;
qcom,cpu = <&cpu_debug>;
qcom,mmss = <&mmss_debug>;
qcom,gpu = <&gpu_debug>;
#clock-cells = <1>;
};
cpubw: qcom,cpubw {
compatible = "qcom,devbw";
governor = "performance";
qcom,src-dst-ports = <1 512>;
qcom,active-only;
qcom,bw-tbl =
< 381 /* 100 MHz */ >,
< 572 /* 150 MHz */ >,
< 762 /* 200 MHz */ >,
< 1144 /* 300 MHz */ >,
< 1571 /* 412 MHz */ >,
< 2086 /* 547 MHz */ >,
< 2597 /* 681 MHz */ >,
< 2929 /* 768 MHz */ >,
< 3879 /* 1017 MHz */ >,
< 4943 /* 1296 MHz */ >,
< 5163 /* 1353 MHz */ >,
< 5931 /* 1555 MHz */ >,
< 6881 /* 1804 MHz */ >;
};
bwmon: qcom,cpu-bwmon {
compatible = "qcom,bimc-bwmon4";
reg = <0x01008000 0x300>, <0x01001000 0x200>;
reg-names = "base", "global_base";
interrupts = <0 183 4>;
qcom,mport = <0>;
qcom,hw-timer-hz = <19200000>;
qcom,target-dev = <&cpubw>;
};
mincpubw: qcom,mincpubw {
compatible = "qcom,devbw";
governor = "powersave";
qcom,src-dst-ports = <1 512>;
qcom,active-only;
qcom,bw-tbl =
< 381 /* 100 MHz */ >,
< 572 /* 150 MHz */ >,
< 762 /* 200 MHz */ >,
< 1144 /* 300 MHz */ >,
< 1571 /* 412 MHz */ >,
< 2086 /* 547 MHz */ >,
< 2597 /* 681 MHz */ >,
< 2929 /* 768 MHz */ >,
< 3879 /* 1017 MHz */ >,
< 4943 /* 1296 MHz */ >,
< 5163 /* 1353 MHz */ >,
< 5931 /* 1555 MHz */ >,
< 6881 /* 1804 MHz */ >;
};
memlat_cpu0: qcom,memlat-cpu0 {
compatible = "qcom,devbw";
governor = "powersave";
qcom,src-dst-ports = <1 512>;
qcom,active-only;
qcom,bw-tbl =
< 381 /* 100 MHz */ >,
< 572 /* 150 MHz */ >,
< 762 /* 200 MHz */ >,
< 1144 /* 300 MHz */ >,
< 1571 /* 412 MHz */ >,
< 2086 /* 547 MHz */ >,
< 2597 /* 681 MHz */ >,
< 2929 /* 768 MHz */ >,
< 3879 /* 1017 MHz */ >,
< 4943 /* 1296 MHz */ >,
< 5163 /* 1353 MHz */ >,
< 5931 /* 1555 MHz */ >,
< 6881 /* 1804 MHz */ >;
};
memlat_cpu4: qcom,memlat-cpu4 {
compatible = "qcom,devbw";
governor = "powersave";
qcom,src-dst-ports = <1 512>;
qcom,active-only;
qcom,bw-tbl =
< 381 /* 100 MHz */ >,
< 572 /* 150 MHz */ >,
< 762 /* 200 MHz */ >,
< 1144 /* 300 MHz */ >,
< 1571 /* 412 MHz */ >,
< 2086 /* 547 MHz */ >,
< 2597 /* 681 MHz */ >,
< 2929 /* 768 MHz */ >,
< 3879 /* 1017 MHz */ >,
< 4943 /* 1296 MHz */ >,
< 5163 /* 1353 MHz */ >,
< 5931 /* 1555 MHz */ >,
< 6881 /* 1804 MHz */ >;
};
devfreq_memlat_0: qcom,arm-memlat-mon-0 {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,target-dev = <&memlat_cpu0>;
qcom,core-dev-table =
< 902400 762 >,
< 1401600 2086 >,
< 1881600 3879 >;
};
devfreq_memlat_4: qcom,arm-memlat-mon-4 {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,target-dev = <&memlat_cpu4>;
qcom,core-dev-table =
< 1113600 762 >,
< 1401600 3879 >,
< 2150400 5931 >,
< 2457600 6881 >;
};
devfreq_cpufreq: devfreq-cpufreq {
mincpubw-cpufreq {
target-dev = <&mincpubw>;
cpu-to-dev-map-0 =
< 633600 762 >,
< 1401600 1571 >,
< 1881600 2929 >;
cpu-to-dev-map-4 =
< 1113600 762 >,
< 1401600 2086 >,
< 1747200 2929 >,
< 2150400 3879 >,
< 2457600 6881 >;
};
};
clock_cpu: qcom,clk-cpu-660@179c0000 {
compatible = "qcom,clk-cpu-osm";
reg = <0x179c0000 0x4000>, <0x17916000 0x1000>,
<0x17816000 0x1000>, <0x179d1000 0x1000>,
<0x00784130 0x8>;
reg-names = "osm", "pwrcl_pll", "perfcl_pll",
"apcs_common", "perfcl_efuse";
vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
vdd-perfcl-supply = <&apc1_perfcl_vreg>;
interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "pwrcl-irq", "perfcl-irq";
qcom,pwrcl-speedbin0-v0 =
< 300000000 0x0004000f 0x01200020 0x1 1 >,
< 633600000 0x05040021 0x03200020 0x1 2 >,
< 902400000 0x0404002f 0x04260026 0x1 3 >,
< 1113600000 0x0404003a 0x052e002e 0x2 4 >,
< 1401600000 0x04040049 0x073a003a 0x2 5 >,
< 1536000000 0x04040050 0x08400040 0x2 6 >,
< 1747200000 0x0404005b 0x09480048 0x2 7 >,
< 1843200000 0x04040060 0x094c004c 0x3 8 >;
qcom,perfcl-speedbin0-v0 =
< 300000000 0x0004000f 0x01200020 0x1 1 >,
< 1113600000 0x0404003a 0x052e002e 0x1 2 >,
< 1401600000 0x04040049 0x073a003a 0x2 3 >,
< 1747200000 0x0404005b 0x09480048 0x2 4 >,
< 1958400000 0x04040066 0x0a510051 0x2 5 >,
< 2150400000 0x04040070 0x0b590059 0x2 6 >,
< 2457600000 0x04040080 0x0c660066 0x3 7 >;
qcom,perfcl-speedbin1-v0 =
< 300000000 0x0004000f 0x01200020 0x1 1 >,
< 1113600000 0x0404003a 0x052e002e 0x1 2 >,
< 1401600000 0x04040049 0x073a003a 0x2 3 >,
< 1747200000 0x0404005b 0x09480048 0x2 4 >,
< 1958400000 0x04040066 0x0a510051 0x2 5 >,
< 2150400000 0x04040070 0x0b590059 0x2 6 >,
< 2208000000 0x04040073 0x0b5c005c 0x3 7 >;
qcom,up-timer = <1000 1000>;
qcom,down-timer = <1000 1000>;
qcom,pc-override-index = <0 0>;
qcom,set-ret-inactive;
qcom,enable-llm-freq-vote;
qcom,llm-freq-up-timer = <327675 327675>;
qcom,llm-freq-down-timer = <327675 327675>;
qcom,enable-llm-volt-vote;
qcom,llm-volt-up-timer = <327675 327675>;
qcom,llm-volt-down-timer = <327675 327675>;
qcom,cc-reads = <10>;
qcom,cc-delay = <5>;
qcom,cc-factor = <100>;
qcom,osm-clk-rate = <200000000>;
qcom,xo-clk-rate = <19200000>;
qcom,l-val-base = <0x17916004 0x17816004>;
qcom,apcs-itm-present = <0x179d143c 0x179d143c>;
qcom,apcs-pll-user-ctl = <0x1791600c 0x1781600c>;
qcom,apcs-cfg-rcgr = <0x17911054 0x17811054>;
qcom,apcs-cmd-rcgr = <0x17911050 0x17811050>;
qcom,apm-mode-ctl = <0x179d0004 0x179d0010>;
qcom,apm-ctrl-status = <0x179d000c 0x179d0018>;
qcom,apm-threshold-voltage = <872000>;
qcom,boost-fsm-en;
qcom,safe-fsm-en;
qcom,ps-fsm-en;
qcom,droop-fsm-en;
qcom,wfx-fsm-en;
qcom,pc-fsm-en;
clock-names = "aux_clk", "xo_a";
clocks = <&clock_gcc HMSS_GPLL0_CLK_SRC>,
<&clock_rpmcc RPM_XO_A_CLK_SRC>;
#clock-cells = <1>;
};
msm_cpufreq: qcom,msm-cpufreq {
compatible = "qcom,msm-cpufreq";
clock-names = "cpu0_clk", "cpu4_clk";
clocks = <&clock_cpu PWRCL_CLK>,
<&clock_cpu PERFCL_CLK>;
qcom,governor-per-policy;
qcom,cpufreq-table-0 =
< 633600 >,
< 902400 >,
< 1113600 >,
< 1401600 >,
< 1536000 >,
< 1747200 >,
< 1843200 >;
qcom,cpufreq-table-4 =
< 1113600 >,
< 1401600 >,
< 1747200 >,
< 1958400 >,
< 2150400 >,
< 2208000 >,
< 2457600 >;
};
sdhc_1: sdhci@c0c4000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>;
reg-names = "hc_mem", "cmdq_mem";
interrupts = <0 110 0>, <0 112 0>;
interrupt-names = "hc_irq", "pwr_irq";
qcom,bus-width = <8>;
qcom,large-address-bus;
sdhc-msm-crypto = <&sdcc1_ice>;
qcom,devfreq,freq-table = <50000000 200000000>;
qcom,msm-bus,name = "sdhc1";
qcom,msm-bus,num-cases = <9>;
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-KBps =
/* No vote */
<78 512 0 0>, <1 606 0 0>,
/* 400 KB/s*/
<78 512 1046 1600>,
<1 606 1600 1600>,
/* 20 MB/s */
<78 512 52286 80000>,
<1 606 80000 80000>,
/* 25 MB/s */
<78 512 65360 100000>,
<1 606 100000 100000>,
/* 50 MB/s */
<78 512 130718 200000>,
<1 606 133320 133320>,
/* 100 MB/s */
<78 512 130718 200000>,
<1 606 150000 150000>,
/* 200 MB/s */
<78 512 261438 400000>,
<1 606 300000 300000>,
/* 400 MB/s */
<78 512 261438 400000>,
<1 606 300000 300000>,
/* Max. bandwidth */
<78 512 1338562 4096000>,
<1 606 1338562 4096000>;
qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
100000000 200000000 400000000 4294967295>;
clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,
<&clock_gcc GCC_SDCC1_APPS_CLK>,
<&clock_gcc GCC_SDCC1_ICE_CORE_CLK>;
clock-names = "iface_clk", "core_clk", "ice_core_clk";
qcom,ice-clk-rates = <300000000 75000000>;
status = "disabled";
};
sdhc_2: sdhci@c084000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0xc084000 0x1000>;
reg-names = "hc_mem";
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
qcom,bus-width = <4>;
qcom,large-address-bus;
qcom,msm-bus,name = "sdhc2";
qcom,msm-bus,num-cases = <8>;
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-KBps =
/* No vote */
<81 512 0 0>, <1 608 0 0>,
/* 400 KB/s*/
<81 512 1046 1600>,
<1 608 1600 1600>,
/* 20 MB/s */
<81 512 52286 80000>,
<1 608 80000 80000>,
/* 25 MB/s */
<81 512 65360 100000>,
<1 608 100000 100000>,
/* 50 MB/s */
<81 512 130718 200000>,
<1 608 133320 133320>,
/* 100 MB/s */
<81 512 261438 200000>,
<1 608 150000 150000>,
/* 200 MB/s */
<81 512 261438 400000>,
<1 608 300000 300000>,
/* Max. bandwidth */
<81 512 1338562 4096000>,
<1 608 1338562 4096000>;
qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
100000000 200000000 4294967295>;
qcom,devfreq,freq-table = <50000000 200000000>;
clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
<&clock_gcc GCC_SDCC2_APPS_CLK>;
clock-names = "iface_clk", "core_clk";
status = "disabled";
};
ipa_hw: qcom,ipa@14780000 {
compatible = "qcom,ipa";
reg = <0x14780000 0x4effc>, <0x14784000 0x26934>;
reg-names = "ipa-base", "bam-base";
interrupts = <0 333 0>,
<0 432 0>;
interrupt-names = "ipa-irq", "bam-irq";
qcom,ipa-hw-ver = <6>; /* IPA core version = IPAv2.6L */
qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */
qcom,wan-rx-ring-size = <192>; /* IPA WAN-rx-ring-size*/
qcom,lan-rx-ring-size = <192>; /* IPA LAN-rx-ring-size*/
clocks = <&clock_rpmcc RPM_IPA_CLK>,
<&clock_rpmcc AGGR2_NOC_SMMU_CLK>;
clock-names = "core_clk", "smmu_clk";
qcom,arm-smmu;
qcom,smmu-disable-htw;
qcom,smmu-s1-bypass;
qcom,ee = <0>;
qcom,use-ipa-tethering-bridge;
qcom,modem-cfg-emb-pipe-flt;
qcom,ipa-wdi2;
qcom,use-dma-zone;
qcom,msm-bus,name = "ipa";
qcom,msm-bus,num-cases = <4>;
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-KBps =
/* No vote */
<90 512 0 0>,
<1 676 0 0>,
/* SVS */
<90 512 80000 640000>,
<1 676 80000 80000>,
/* NOMINAL */
<90 512 206000 960000>,
<1 676 206000 160000>,
/* TURBO */
<90 512 206000 960000>,
<1 676 206000 160000>;
qcom,bus-vector-names = "MIN", "SVS", "PERF", "TURBO";
qcom,rx-polling-sleep-ms = <1>; /* Polling sleep interval */
qcom,ipa-polling-iteration = <40>; /* Polling Iteration */
ipa_smmu_ap: ipa_smmu_ap {
compatible = "qcom,ipa-smmu-ap-cb";
iommus = <&anoc2_smmu 0x19C0>;
qcom,iova-mapping = <0x10000000 0x40000000>;
};
ipa_smmu_wlan: ipa_smmu_wlan {
status = "disabled";
compatible = "qcom,ipa-smmu-wlan-cb";
iommus = <&anoc2_smmu 0x19C1>;
};
ipa_smmu_uc: ipa_smmu_uc {
compatible = "qcom,ipa-smmu-uc-cb";
iommus = <&anoc2_smmu 0x19C2>;
qcom,iova-mapping = <0x40000000 0x20000000>;
};
};
qcom,rmtfs_sharedmem@0 {
compatible = "qcom,sharedmem-uio";
reg = <0x0 0x200000>;
reg-names = "rmtfs";
qcom,client-id = <0x00000001>;
};
qcom,rmnet-ipa {
compatible = "qcom,rmnet-ipa";
qcom,rmnet-ipa-ssr;
qcom,ipa-loaduC;
qcom,ipa-advertise-sg-support;
};
qcom,ipc-spinlock@1f40000 {
compatible = "qcom,ipc-spinlock-sfpb";
reg = <0x1f40000 0x8000>;
qcom,num-locks = <8>;
};
qcom,smem@86000000 {
compatible = "qcom,smem";
reg = <0x86000000 0x200000>,
<0x17911008 0x4>,
<0x778000 0x7000>,
<0x1fd4000 0x8>;
reg-names = "smem", "irq-reg-base", "aux-mem1",
"smem_targ_info_reg";
qcom,mpu-enabled;
};
qcom,msm-cdsp-loader {
compatible = "qcom,cdsp-loader";
qcom,proc-img-to-load = "cdsp";
};
qcom,msm-adsprpc-mem {
compatible = "qcom,msm-adsprpc-mem-region";
memory-region = <&adsp_mem>;
};
qcom,msm_fastrpc {
compatible = "qcom,msm-fastrpc-adsp";
qcom,fastrpc-glink;
qcom,msm_fastrpc_compute_cb1 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <&lpass_q6_smmu 3>;
dma-coherent;
};
qcom,msm_fastrpc_compute_cb2 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <&lpass_q6_smmu 7>;
dma-coherent;
};
qcom,msm_fastrpc_compute_cb3 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <&lpass_q6_smmu 8>;
dma-coherent;
};
qcom,msm_fastrpc_compute_cb4 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <&lpass_q6_smmu 9>;
dma-coherent;
};
qcom,msm_fastrpc_compute_cb5 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&turing_q6_smmu 3>;
dma-coherent;
};
qcom,msm_fastrpc_compute_cb6 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&turing_q6_smmu 4>;
dma-coherent;
};
qcom,msm_fastrpc_compute_cb7 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&turing_q6_smmu 5>;
dma-coherent;
};
qcom,msm_fastrpc_compute_cb8 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&turing_q6_smmu 6>;
dma-coherent;
};
qcom,msm_fastrpc_compute_cb9 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&turing_q6_smmu 7>;
dma-coherent;
};
qcom,msm_fastrpc_compute_cb10 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&turing_q6_smmu 8>;
dma-coherent;
};
qcom,msm_fastrpc_compute_cb11 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&turing_q6_smmu 9>;
dma-coherent;
};
qcom,msm_fastrpc_compute_cb12 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&turing_q6_smmu 10>;
dma-coherent;
};
qcom,msm_fastrpc_compute_cb13 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&turing_q6_smmu 11>;
dma-coherent;
};
};
dcc: dcc@10b3000 {
compatible = "qcom,dcc";
reg = <0x10b3000 0x1000>,
<0x10b4000 0x2000>;
reg-names = "dcc-base", "dcc-ram-base";
clocks = <&clock_gcc GCC_DCC_AHB_CLK>;
clock-names = "dcc_clk";
};
qcom,glink-smem-native-xprt-modem@86000000 {
compatible = "qcom,glink-smem-native-xprt";
reg = <0x86000000 0x200000>,
<0x17911008 0x4>;
reg-names = "smem", "irq-reg-base";
qcom,irq-mask = <0x8000>;
interrupts = <0 452 1>;
label = "mpss";
};
qcom,glink-smem-native-xprt-adsp@86000000 {
compatible = "qcom,glink-smem-native-xprt";
reg = <0x86000000 0x200000>,
<0x17911008 0x4>;
reg-names = "smem", "irq-reg-base";
qcom,irq-mask = <0x200>;
interrupts = <0 157 1>;
label = "lpass";
qcom,qos-config = <&glink_qos_adsp>;
qcom,ramp-time = <0xaf>;
};
glink_qos_adsp: qcom,glink-qos-config-adsp {
compatible = "qcom,glink-qos-config";
qcom,flow-info = <0x3c 0x0>,
<0x3c 0x0>,
<0x3c 0x0>,
<0x3c 0x0>;
qcom,mtu-size = <0x800>;
qcom,tput-stats-cycle = <0xa>;
};
qcom,glink-smem-native-xprt-cdsp@86000000 {
compatible = "qcom,glink-smem-native-xprt";
reg = <0x86000000 0x200000>,
<0x17911008 0x4>;
reg-names = "smem", "irq-reg-base";
qcom,irq-mask = <0x20000000>;
interrupts = <0 513 1>;
label = "cdsp";
};
qcom,glink-smem-native-xprt-rpm@778000 {
compatible = "qcom,glink-rpm-native-xprt";
reg = <0x778000 0x7000>,
<0x17911008 0x4>;
reg-names = "msgram", "irq-reg-base";
qcom,irq-mask = <0x1>;
interrupts = <0 168 1>;
label = "rpm";
};
glink_mpss: qcom,glink-ssr-modem {
compatible = "qcom,glink_ssr";
label = "modem";
qcom,edge = "mpss";
qcom,notify-edges = <&glink_lpass>, <&glink_rpm>,
<&glink_cdsp>;
qcom,xprt = "smem";
};
glink_lpass: qcom,glink-ssr-adsp {
compatible = "qcom,glink_ssr";
label = "adsp";
qcom,edge = "lpass";
qcom,notify-edges = <&glink_mpss>, <&glink_rpm>,
<&glink_cdsp>;
qcom,xprt = "smem";
};
glink_rpm: qcom,glink-ssr-rpm {
compatible = "qcom,glink_ssr";
label = "rpm";
qcom,edge = "rpm";
qcom,notify-edges = <&glink_lpass>, <&glink_mpss>,
<&glink_cdsp>;
qcom,xprt = "smem";
};
glink_cdsp: qcom,glink-ssr-cdsp {
compatible = "qcom,glink_ssr";
label = "cdsp";
qcom,edge = "cdsp";
qcom,notify-edges = <&glink_lpass>, <&glink_mpss>,
<&glink_rpm>;
qcom,xprt = "smem";
};
glink_spi_xprt_wdsp: qcom,glink-spi-xprt-wdsp {
compatible = "qcom,glink-spi-xprt";
label = "wdsp";
qcom,remote-fifo-config = <&glink_fifo_wdsp>;
qcom,qos-config = <&glink_qos_wdsp>;
qcom,ramp-time = <0x10>,
<0x20>,
<0x30>,
<0x40>;
};
glink_fifo_wdsp: qcom,glink-fifo-config-wdsp {
compatible = "qcom,glink-fifo-config";
qcom,out-read-idx-reg = <0x12000>;
qcom,out-write-idx-reg = <0x12004>;
qcom,in-read-idx-reg = <0x1200c>;
qcom,in-write-idx-reg = <0x12010>;
};
glink_qos_wdsp: qcom,glink-qos-config-wdsp {
compatible = "qcom,glink-qos-config";
qcom,flow-info = <0x80 0x0>,
<0x70 0x1>,
<0x60 0x2>,
<0x50 0x3>;
qcom,mtu-size = <0x800>;
qcom,tput-stats-cycle = <0xa>;
};
qcom,glink_pkt {
compatible = "qcom,glinkpkt";
qcom,glinkpkt-at-mdm0 {
qcom,glinkpkt-transport = "smem";
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DS";
qcom,glinkpkt-dev-name = "at_mdm0";
};
qcom,glinkpkt-loopback_cntl {
qcom,glinkpkt-transport = "lloop";
qcom,glinkpkt-edge = "local";
qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT";
qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl";
};
qcom,glinkpkt-loopback_data {
qcom,glinkpkt-transport = "lloop";
qcom,glinkpkt-edge = "local";
qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT";
qcom,glinkpkt-dev-name = "glink_pkt_loopback";
};
qcom,glinkpkt-apr-apps2 {
qcom,glinkpkt-transport = "smem";
qcom,glinkpkt-edge = "adsp";
qcom,glinkpkt-ch-name = "apr_apps2";
qcom,glinkpkt-dev-name = "apr_apps2";
};
qcom,glinkpkt-data40-cntl {
qcom,glinkpkt-transport = "smem";
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA40_CNTL";
qcom,glinkpkt-dev-name = "smdcntl8";
};
qcom,glinkpkt-data1 {
qcom,glinkpkt-transport = "smem";
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA1";
qcom,glinkpkt-dev-name = "smd7";
};
qcom,glinkpkt-data4 {
qcom,glinkpkt-transport = "smem";
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA4";
qcom,glinkpkt-dev-name = "smd8";
};
qcom,glinkpkt-data11 {
qcom,glinkpkt-transport = "smem";
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA11";
qcom,glinkpkt-dev-name = "smd11";
};
};
rpm_bus: qcom,rpm-smd {
compatible = "qcom,rpm-glink";
qcom,glink-edge = "rpm";
rpm-channel-name = "rpm_requests";
};
qcom,ipc_router {
compatible = "qcom,ipc_router";
qcom,node-id = <1>;
};
qcom,ipc_router_modem_xprt {
compatible = "qcom,ipc_router_glink_xprt";
qcom,ch-name = "IPCRTR";
qcom,xprt-remote = "mpss";
qcom,glink-xprt = "smem";
qcom,xprt-linkid = <1>;
qcom,xprt-version = <1>;
qcom,fragmented-data;
};
qcom,ipc_router_q6_xprt {
compatible = "qcom,ipc_router_glink_xprt";
qcom,ch-name = "IPCRTR";
qcom,xprt-remote = "lpass";
qcom,glink-xprt = "smem";
qcom,xprt-linkid = <1>;
qcom,xprt-version = <1>;
qcom,fragmented-data;
};
qcom,ipc_router_cdsp_xprt {
compatible = "qcom,ipc_router_glink_xprt";
qcom,ch-name = "IPCRTR";
qcom,xprt-remote = "cdsp";
qcom,glink-xprt = "smem";
qcom,xprt-linkid = <1>;
qcom,xprt-version = <1>;
qcom,fragmented-data;
};
qcom,venus@cce0000 {
compatible = "qcom,pil-tz-generic";
reg = <0xcce0000 0x4000>;
vdd-supply = <&gdsc_venus>;
qcom,proxy-reg-names = "vdd";
clocks = <&clock_mmss MMSS_VIDEO_CORE_CLK>,
<&clock_mmss MMSS_MNOC_AHB_CLK>,
<&clock_mmss MMSS_VIDEO_AHB_CLK>,
<&clock_rpmcc MMSSNOC_AXI_CLK>,
<&clock_mmss MMSS_VIDEO_AXI_CLK>;
clock-names = "core_clk", "mnoc_ahb_clk", "iface_clk",
"noc_axi_clk", "bus_clk";
qcom,proxy-clock-names = "core_clk", "mnoc_ahb_clk",
"iface_clk", "noc_axi_clk", "bus_clk";
qcom,msm-bus,name = "pil-venus";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<63 512 0 0>,
<63 512 0 304000>;
qcom,pas-id = <9>;
qcom,proxy-timeout-ms = <100>;
qcom,firmware-name = "venus";
memory-region = <&venus_fw_mem>;
status = "ok";
};
qcom,icnss@18800000 {
compatible = "qcom,icnss";
reg = <0x18800000 0x800000>,
<0xa0000000 0x10000000>,
<0xb0000000 0x10000>;
reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa";
iommus = <&anoc2_smmu 0x1a00>,
<&anoc2_smmu 0x1a01>;
clocks = <&clock_rpmcc RPM_RF_CLK1_PIN>;
clock-names = "cxo_ref_clk_pin";
interrupts = <0 413 0>, /* CE0 */
<0 414 0>, /* CE1 */
<0 415 0>, /* CE2 */
<0 416 0>, /* CE3 */
<0 417 0>, /* CE4 */
<0 418 0>, /* CE5 */
<0 420 0>, /* CE6 */
<0 421 0>, /* CE7 */
<0 422 0>, /* CE8 */
<0 423 0>, /* CE9 */
<0 424 0>, /* CE10 */
<0 425 0>; /* CE11 */
vdd-0.8-cx-mx-supply = <&pm660_l5>;
vdd-1.8-xo-supply = <&pm660_l9_pin_ctrl>;
vdd-1.3-rfa-supply = <&pm660_l6_pin_ctrl>;
vdd-3.3-ch0-supply = <&pm660_l19_pin_ctrl>;
qcom,vdd-0.8-cx-mx-config = <525000 950000>;
qcom,vdd-1.8-xo-config = <1750000 1900000>;
qcom,vdd-1.3-rfa-config = <1200000 1370000>;
qcom,vdd-3.3-ch0-config = <3200000 3400000>;
qcom,wlan-msa-memory = <0x100000>;
qcom,smmu-s1-bypass;
};
qcom,lpass@15700000 {
compatible = "qcom,pil-tz-generic";
reg = <0x15700000 0x00100>;
interrupts = <0 162 1>;
vdd_cx-supply = <&pm660l_l9_level>;
qcom,proxy-reg-names = "vdd_cx";
qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
clocks = <&clock_rpmcc CXO_PIL_LPASS_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
qcom,pas-id = <1>;
qcom,proxy-timeout-ms = <10000>;
qcom,smem-id = <423>;
qcom,sysmon-id = <1>;
qcom,ssctl-instance-id = <0x14>;
qcom,firmware-name = "adsp";
memory-region = <&adsp_fw_mem>;
/* GPIO inputs from lpass */
qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;
/* GPIO output to lpass */
qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
status = "ok";
};
qcom,turing@1a300000 {
compatible = "qcom,pil-tz-generic";
reg = <0x1a300000 0x00100>;
interrupts = <0 518 1>;
vdd_cx-supply = <&pm660l_s3_level>;
qcom,proxy-reg-names = "vdd_cx";
qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
clocks = <&clock_rpmcc CXO_PIL_CDSP_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
qcom,pas-id = <18>;
qcom,proxy-timeout-ms = <10000>;
qcom,smem-id = <601>;
qcom,sysmon-id = <7>;
qcom,ssctl-instance-id = <0x17>;
qcom,firmware-name = "cdsp";
memory-region = <&cdsp_fw_mem>;
/* GPIO inputs from turing */
qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_5_in 0 0>;
qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_5_in 2 0>;
qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_5_in 1 0>;
qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_5_in 3 0>;
/* GPIO output to turing*/
qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_5_out 0 0>;
status = "ok";
};
pil_modem: qcom,mss@4080000 {
compatible = "qcom,pil-q6v55-mss";
reg = <0x4080000 0x100>,
<0x1f63000 0x008>,
<0x1f65000 0x008>,
<0x1f64000 0x008>,
<0x4180000 0x040>,
<0x00179000 0x004>,
<0x01fe5048 0x004>;
reg-names = "qdsp6_base", "halt_q6", "halt_modem",
"halt_nc", "rmb_base", "restart_reg",
"cxip_lm_vote_clear";
clocks = <&clock_rpmcc RPM_XO_CLK_SRC>,
<&clock_gcc GCC_MSS_CFG_AHB_CLK>,
<&clock_gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
<&clock_gcc GCC_BOOT_ROM_AHB_CLK>,
<&clock_gcc GPLL0_OUT_MSSCC>,
<&clock_gcc GCC_MSS_SNOC_AXI_CLK>,
<&clock_gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
<&clock_rpmcc RPM_QDSS_CLK>;
clock-names = "xo", "iface_clk", "bus_clk",
"mem_clk", "gpll0_mss_clk", "snoc_axi_clk",
"mnoc_axi_clk", "qdss_clk";
qcom,proxy-clock-names = "xo", "qdss_clk";
qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
"gpll0_mss_clk", "snoc_axi_clk",
"mnoc_axi_clk";
interrupts = <0 448 1>;
vdd_cx-supply = <&pm660l_s3_level>;
vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
vdd_mx-supply = <&pm660l_s5_level>;
vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
qcom,firmware-name = "modem";
qcom,pil-self-auth;
qcom,sysmon-id = <0>;
qcom,ssctl-instance-id = <0x12>;
qcom,qdsp6v62-1-5;
memory-region = <&modem_fw_mem>;
qcom,mem-protect-id = <0xF>;
qcom,cx-ipeak-vote;
/* GPIO inputs from mss */
qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>;
/* GPIO output to mss */
qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
status = "ok";
qcom,mba-mem@0 {
compatible = "qcom,pil-mba-mem";
memory-region = <&pil_mba_mem>;
};
};
qcom,msm-rtb {
compatible = "qcom,msm-rtb";
qcom,rtb-size = <0x100000>;
};
qcom,mpm2-sleep-counter@10a3000 {
compatible = "qcom,mpm2-sleep-counter";
reg = <0x10a3000 0x1000>;
clock-frequency = <32768>;
};
qcom,msm-imem@146bf000 {
compatible = "qcom,msm-imem";
reg = <0x146bf000 0x1000>;
ranges = <0x0 0x146bf000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 8>;
};
dload_type@1c {
compatible = "qcom,msm-imem-dload-type";
reg = <0x1c 4>;
};
restart_reason@65c {
compatible = "qcom,msm-imem-restart_reason";
reg = <0x65c 4>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 32>;
};
kaslr_offset@6d0 {
compatible = "qcom,msm-imem-kaslr_offset";
reg = <0x6d0 12>;
};
pil@94c {
compatible = "qcom,msm-imem-pil";
reg = <0x94c 200>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 200>;
};
};
qcom,ghd {
compatible = "qcom,gladiator-hang-detect";
qcom,threshold-arr = <0x179d141c 0x179d1420
0x179d1424 0x179d1428
0x179d142c 0x179d1430>;
qcom,config-reg = <0x179d1434>;
};
qcom,msm-gladiator-v2@17900000 {
compatible = "qcom,msm-gladiator-v2";
reg = <0x17900000 0xe000>;
reg-names = "gladiator_base";
interrupts = <0 22 0>;
clock-names = "atb_clk";
clocks = <&clock_rpmcc RPM_QDSS_CLK>;
};
cpu_pmu: cpu-pmu {
compatible = "arm,armv8-pmuv3";
qcom,irq-is-percpu;
interrupts = <1 6 4>;
};
qcom_seecom: qseecom@86d00000 {
compatible = "qcom,qseecom";
reg = <0x86d00000 0x2200000>;
reg-names = "secapp-region";
qcom,hlos-num-ce-hw-instances = <1>;
qcom,hlos-ce-hw-instance = <0>;
qcom,qsee-ce-hw-instance = <0>;
qcom,disk-encrypt-pipe-pair = <2>;
qcom,support-fde;
qcom,no-clock-support;
qcom,msm-bus,name = "qseecom-noc";
qcom,msm-bus,num-cases = <4>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<55 512 0 0>,
<55 512 200000 400000>,
<55 512 300000 800000>,
<55 512 400000 1000000>;
clock-names = "core_clk_src", "core_clk",
"iface_clk", "bus_clk";
clocks = <&clock_rpmcc QSEECOM_CE1_CLK>,
<&clock_rpmcc QSEECOM_CE1_CLK>,
<&clock_rpmcc QSEECOM_CE1_CLK>,
<&clock_rpmcc QSEECOM_CE1_CLK>;
qcom,ce-opp-freq = <171430000>;
qcom,qsee-reentrancy-support = <2>;
};
qcom_cedev: qcedev@1de0000{
compatible = "qcom,qcedev";
reg = <0x1de0000 0x20000>,
<0x1dc4000 0x24000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <0 206 0>;
qcom,bam-pipe-pair = <1>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,ce-hw-shared;
qcom,bam-ee = <0>;
qcom,msm-bus,name = "qcedev-noc";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<55 512 0 0>,
<55 512 393600 393600>;
clock-names = "core_clk_src", "core_clk",
"iface_clk", "bus_clk";
clocks = <&clock_rpmcc QCEDEV_CE1_CLK>,
<&clock_rpmcc QCEDEV_CE1_CLK>,
<&clock_rpmcc QCEDEV_CE1_CLK>,
<&clock_rpmcc QCEDEV_CE1_CLK>;
qcom,ce-opp-freq = <171430000>;
};
qcom_crypto: qcrypto@1de0000 {
compatible = "qcom,qcrypto";
reg = <0x1de0000 0x20000>,
<0x1dc4000 0x24000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <0 206 0>;
qcom,bam-pipe-pair = <2>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,bam-ee = <0>;
qcom,ce-hw-shared;
qcom,clk-mgmt-sus-res;
qcom,msm-bus,name = "qcrypto-noc";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<55 512 0 0>,
<55 512 393600 393600>;
clock-names = "core_clk_src", "core_clk",
"iface_clk", "bus_clk";
clocks = <&clock_rpmcc QCRYPTO_CE1_CLK>,
<&clock_rpmcc QCRYPTO_CE1_CLK>,
<&clock_rpmcc QCRYPTO_CE1_CLK>,
<&clock_rpmcc QCRYPTO_CE1_CLK>;
qcom,ce-opp-freq = <171430000>;
qcom,use-sw-aes-cbc-ecb-ctr-algo;
qcom,use-sw-aes-xts-algo;
qcom,use-sw-aes-ccm-algo;
qcom,use-sw-ahash-algo;
qcom,use-sw-aead-algo;
qcom,use-sw-hmac-algo;
};
qcom_tzlog: tz-log@146bf720 {
compatible = "qcom,tz-log";
reg = <0x146bf720 0x3000>;
qcom,hyplog-enabled;
hyplog-address-offset = <0x410>;
hyplog-size-offset = <0x414>;
};
qcom_rng: qrng@793000 {
compatible = "qcom,msm-rng";
reg = <0x793000 0x1000>;
qcom,msm-rng-iface-clk;
qcom,no-qrng-config;
qcom,msm-bus,name = "msm-rng-noc";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<1 618 0 0>, /* No vote */
<1 618 0 800>; /* 100 KHz */
clocks = <&clock_gcc GCC_PRNG_AHB_CLK>;
clock-names = "iface_clk";
};
qcom,chd_silver {
compatible = "qcom,core-hang-detect";
label = "silver";
qcom,threshold-arr = <0x179880b0 0x179980b0
0x179a80b0 0x179b80b0>;
qcom,config-arr = <0x179880b8 0x179980b8
0x179a80b8 0x179b80b8>;
};
qcom,chd_gold {
compatible = "qcom,core-hang-detect";
label = "gold";
qcom,threshold-arr = <0x178880b0 0x178980b0
0x178a80b0 0x178b80b0>;
qcom,config-arr = <0x178880b8 0x178980b8
0x178a80b8 0x178b80b8>;
};
ufsphy1: ufsphy@1da7000 {
compatible = "qcom,ufs-phy-qmp-v3-660";
reg = <0x1da7000 0xdb8>;
reg-names = "phy_mem";
#phy-cells = <0>;
clock-names = "ref_clk_src",
"ref_clk",
"ref_aux_clk";
clocks = <&clock_rpmcc RPM_LN_BB_CLK1>,
<&clock_gcc GCC_UFS_CLKREF_CLK>,
<&clock_gcc GCC_UFS_PHY_AUX_CLK>;
status = "disabled";
};
ufs1: ufshc@1da4000 {
compatible = "qcom,ufshc";
reg = <0x1da4000 0x3000>;
interrupts = <0 265 0>;
phys = <&ufsphy1>;
phy-names = "ufsphy";
ufs-qcom-crypto = <&ufs_ice>;
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk";
clocks =
<&clock_gcc GCC_UFS_AXI_CLK>,
<&clock_gcc GCC_AGGRE2_UFS_AXI_CLK>,
<&clock_gcc GCC_UFS_AHB_CLK>,
<&clock_gcc GCC_UFS_UNIPRO_CORE_CLK>,
<&clock_gcc GCC_UFS_ICE_CORE_CLK>,
<&clock_rpmcc RPM_LN_BB_CLK1>,
<&clock_gcc GCC_UFS_TX_SYMBOL_0_CLK>,
<&clock_gcc GCC_UFS_RX_SYMBOL_0_CLK>;
freq-table-hz =
<50000000 200000000>,
<0 0>,
<0 0>,
<37500000 150000000>,
<75000000 300000000>,
<0 0>,
<0 0>,
<0 0>;
lanes-per-direction = <1>;
spm-level = <5>;
qcom,msm-bus,name = "ufs1";
qcom,msm-bus,num-cases = <12>;
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-KBps =
<95 512 0 0>, <1 650 0 0>, /* No vote */
<95 512 922 0>, <1 650 1000 0>, /* PWM G1 */
<95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */
<95 512 3688 0>, <1 650 1000 0>, /* PWM G3 */
<95 512 7376 0>, <1 650 1000 0>, /* PWM G4 */
<95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */
<95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */
<95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RA */
<95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */
<95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */
<95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RB */
<95 512 7643136 0>, <1 650 307200 0>; /* Max. bandwidth */
qcom,bus-vector-names = "MIN",
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
"MAX";
resets = <&clock_gcc GCC_UFS_BCR>;
reset-names = "core_reset";
status = "disabled";
};
jtag_fuse: jtagfuse@786040 {
compatible = "qcom,jtag-fuse-v4";
reg = <0x786040 0x8>;
reg-names = "fuse-base";
};
jtag_mm0: jtagmm@7840000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7840000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_rpmcc RPM_QDSS_CLK>,
<&clock_rpmcc RPM_QDSS_A_CLK>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU0>;
};
jtag_mm1: jtagmm@7940000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7940000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_rpmcc RPM_QDSS_CLK>,
<&clock_rpmcc RPM_QDSS_A_CLK>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU1>;
};
jtag_mm2: jtagmm@7a40000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7a40000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_rpmcc RPM_QDSS_CLK>,
<&clock_rpmcc RPM_QDSS_A_CLK>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU2>;
};
jtag_mm3: jtagmm@7b40000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7b40000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_rpmcc RPM_QDSS_CLK>,
<&clock_rpmcc RPM_QDSS_A_CLK>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU3>;
};
jtag_mm4: jtagmm@7c40000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7c40000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_rpmcc RPM_QDSS_CLK>,
<&clock_rpmcc RPM_QDSS_A_CLK>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU4>;
};
jtag_mm5: jtagmm@7d40000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7d40000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_rpmcc RPM_QDSS_CLK>,
<&clock_rpmcc RPM_QDSS_A_CLK>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU5>;
};
jtag_mm6: jtagmm@7e40000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7e40000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_rpmcc RPM_QDSS_CLK>,
<&clock_rpmcc RPM_QDSS_A_CLK>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU6>;
};
jtag_mm7: jtagmm@7f40000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7f40000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_rpmcc RPM_QDSS_CLK>,
<&clock_rpmcc RPM_QDSS_A_CLK>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU7>;
};
};
#include "sdm660-ion.dtsi"
#include "sdm660-bus.dtsi"
#include "msm-pm660.dtsi"
#include "msm-pm660l.dtsi"
#include "msm-pm660-rpm-regulator.dtsi"
#include "msm-pm660l-rpm-regulator.dtsi"
#include "sdm660-regulator.dtsi"
#include "msm-gdsc-660.dtsi"
#include "sdm660-gpu.dtsi"
#include "sdm660-pm.dtsi"
&gdsc_usb30 {
status = "ok";
};
&gdsc_ufs {
status = "ok";
};
&gdsc_bimc_smmu {
clock-names = "bus_clk";
clocks = <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
proxy-supply = <&gdsc_bimc_smmu>;
qcom,proxy-consumer-enable;
status = "ok";
};
&gdsc_hlos1_vote_lpass_adsp {
status = "ok";
};
&gdsc_hlos1_vote_turing_adsp {
status = "ok";
};
&gdsc_hlos2_vote_turing_adsp {
status = "ok";
};
&gdsc_venus {
status = "ok";
};
&gdsc_venus_core0 {
qcom,support-hw-trigger;
status = "ok";
};
&gdsc_camss_top {
status = "ok";
};
&gdsc_vfe0 {
parent-supply = <&gdsc_camss_top>;
status = "ok";
};
&gdsc_vfe1 {
parent-supply = <&gdsc_camss_top>;
status = "ok";
};
&gdsc_cpp {
parent-supply = <&gdsc_camss_top>;
qcom,support-hw-trigger;
status = "ok";
};
&gdsc_mdss {
proxy-supply = <&gdsc_mdss>;
qcom,proxy-consumer-enable;
status = "ok";
};
&gdsc_gpu_gx {
clock-names = "core_root_clk";
clocks = <&clock_gfx GFX3D_CLK_SRC>;
qcom,force-enable-root-clk;
parent-supply = <&gfx_vreg_corner>;
status = "ok";
};
&gdsc_gpu_cx {
status = "ok";
};
&clock_cpu {
lmh_dcvs0: qcom,limits-dcvs@0 {
compatible = "qcom,msm-hw-limits";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
};
lmh_dcvs1: qcom,limits-dcvs@1 {
compatible = "qcom,msm-hw-limits";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
};
};
#include "msm-arm-smmu-660.dtsi"
#include "msm-arm-smmu-impl-defs-660.dtsi"
#include "sdm660-common.dtsi"
#include "sdm660-blsp.dtsi"
#include "sdm660-camera.dtsi"
#include "sdm660-vidc.dtsi"
#include "msm-audio.dtsi"
#include "sdm660-audio.dtsi"
&pm660l_gpios {
/* GPIO 7 for VOL_UP */
gpio@c600 {
status = "okay";
qcom,mode = <0>;
qcom,pull = <0>;
qcom,vin-sel =