| Qualcomm MSM Ethernet Controller (EMAC) |
| |
| Required properties: |
| - cell-index : EMAC controller instance number. |
| - compatible : Should be "qcom,mdm9607-emac" for mdm9607 based EMAC driver |
| Should be "qcom,emac" for other targets based EMAC driver |
| |
| - reg : Offset and length of the register regions for the device |
| - reg-names : Register region names referenced in 'reg' above. |
| Required register resource entries are: |
| "emac" : EMAC controller register block. |
| "emac_csr" : EMAC wrapper register block. |
| Optional register resource entries are: |
| "emac_1588" : EMAC 1588 (PTP) register block. |
| Required if 'qcom,emac-tstamp-en' is present. |
| "emac_sgmii" : EMAC SGMII PHY register block. |
| Required if 'phy-mode' is "sgmii". |
| - interrupts : Interrupt numbers used by this controller |
| - interrupt-names : Interrupt resource names referenced in 'interrupts' above. |
| Required interrupt resource entries are: |
| "emac_core0_irq" : EMAC core0 interrupt. |
| "emac_core1_irq" : EMAC core1 interrupt. |
| "emac_core2_irq" : EMAC core2 interrupt. |
| "emac_core3_irq" : EMAC core3 interrupt. |
| Optional interrupt resource entries are: |
| "emac_sgmii_irq" : EMAC SGMII interrupt. |
| Required if 'phy-mode' is "sgmii". |
| "emac_wol_irq" : EMAC Wake-On-LAN (WOL) interrupt. |
| Required if WOL is supported. |
| - qcom,emac-gpio-mdc : GPIO pin number of the MDC line of MDIO bus. |
| - qcom,emac-gpio-mdio : GPIO pin number of the MDIO line of MDIO bus. |
| - phy-mode: String, operation mode of the PHY interface. See ethernet.txt in the |
| same directory. |
| - phy-addr : Specifies phy address on MDIO bus. |
| Required if the optional property "qcom,no-external-phy" |
| is not specified. |
| - phy-channel : Phy address for internal phy in ACPI mode. |
| - phy-mode : Specifies PHY type being used (eg., "sgmii", "rgmii", "gmii" etc). |
| For "sgmii", the "emac_sgmii" register base and |
| "emac_sgmii_irq" interrupt must be specified. |
| |
| Optional properties: |
| - qcom,emac-tstamp-en : Enables the PTP (1588) timestamping feature. |
| Include this only if PTP (1588) timestamping |
| feature is needed. If included, "emac_1588" register |
| base should be specified. |
| - local-mac-address : The 6-byte MAC address. |
| This field is optional. If present, it is only a |
| placeholder for the MAC address. The correct MAC |
| address is populated in device tree during platform |
| initialization. |
| - mac-address : 6- bytes MAC address in ACPI mode. |
| This field is optional. If present, it is only a placeholder |
| for the MAC address. The correct MAC address is populated in |
| device tree during platform initialization. |
| - qcom,no-external-phy : Indicates there is no external PHY connected to EMAC. |
| Include this only if the EMAC is directly connected to |
| the peer end without EPHY. |
| - qcom,emac-ptp-grandmaster : Enable the PTP (1588) grandmaster mode. |
| Include this only if PTP (1588) is configured as |
| grandmaster. |
| - qcom,emac-ptp-frac-ns-adj : The vector table to adjust the fractional ns per |
| RTC clock cycle. |
| Include this only if there is accuracy loss of |
| fractional ns per RTC clock cycle. For individual |
| table entry, the first field indicates the RTC |
| reference clock rate. The second field indicates |
| the number of adjustment in 2 ^ -26 ns. |
| - no-ephy : Specifies in case there is no external phy present in ACPI mode. |
| - tstamp-eble : Enables the PTP (1588) timestamping feature in ACPI mode. |
| - <supply-name>-supply: phandle to the regulator device tree node |
| Required "supply-name" are "emac_vreg*" |
| - qcom,vdd-voltage-level: This property must be a list of five integer |
| values (max voltage value for supply 1/2/3/4/5) where each value |
| represents a voltage in microvolts. |
| |
| Example1: |
| emac0: qcom,emac@feb20000 { |
| cell-index = <0>; |
| compatible = "qcom,emac"; |
| reg-names = "emac", "emac_csr", "emac_1588", "emac_sgmii"; |
| reg = <0xfeb20000 0x10000>, |
| <0xfeb36000 0x1000>, |
| <0xfeb3c000 0x4000>, |
| <0xfeb13800 0x400>; |
| interrupts = <0 76 0>, <0 77 0>, <0 78 0>, <0 79 0>; |
| interrupt-names = "emac_core0_irq", "emac_core1_irq", |
| "emac_core2_irq", "emac_core3_irq"; |
| qcom,emac-gpio-mdc = <&msmgpio 123 0>; |
| qcom,emac-gpio-mdio = <&msmgpio 124 0>; |
| qcom,emac-tstamp-en; |
| phy-mode = "sgmii"; |
| phy-addr = <0>; |
| }; |
| |
| Example2: |
| emac0: qcom,emac@7c40000 { |
| cell-index = <0>; |
| compatible = "qcom,mdm9607-emac"; |
| reg-names = "emac", "emac_csr", "emac_1588", "emac_sgmii"; |
| reg = <0x7c40000 0x10000>, |
| <0x7c56000 0x1000>, |
| <0x7c5C000 0x4000>, |
| <0x7c58000 0x400>; |
| #address-cells = <0>; |
| interrupt-parent = <&emac0>; |
| #interrupt-cells = <1>; |
| interrupts = <0 1 2>; |
| interrupt-map-mask = <0xffffffff>; |
| interrupt-map = <0 &intc 0 76 0 |
| 1 &intc 0 80 0 |
| 2 &tlmm_pinmux 30 0x8>; |
| interrupt-names = "emac_core0_irq", |
| "emac_sgmii_irq", |
| "emac_wol_irq"; |
| emac_vreg1-supply = <&mdm9607_l1>; |
| emac_vreg2-supply = <&mdm9607_l3>; |
| emac_vreg3-supply = <&mdm9607_l5>; |
| emac_vreg4-supply = <&mdm9607_l11>; |
| emac_vreg5-supply = <&emac_lan_vreg>; |
| qcom,vdd-voltage-level = <1250000 1800000 2850000 1800000 0>; |
| clocks = <&clock_gcc clk_gcc_emac_0_axi_clk>, |
| <&clock_gcc clk_gcc_emac_0_ahb_clk>, |
| <&clock_gcc clk_gcc_emac_0_125m_clk>, |
| <&clock_gcc clk_gcc_emac_0_sys_25m_clk>, |
| <&clock_gcc clk_gcc_emac_0_tx_clk>, |
| <&clock_gcc clk_gcc_emac_0_rx_clk>, |
| <&clock_gcc clk_gcc_emac_0_sys_clk>; |
| clock-names = "axi_clk", "cfg_ahb_clk", "125m_clk", |
| "25m_clk", "tx_clk", "rx_clk", "sys_clk"; |
| pinctrl-names = "emac_mdio_active", "emac_mdio_sleep", |
| "emac_ephy_active", "emac_ephy_sleep"; |
| pinctrl-0 = <&emac0_mdio_active>; |
| pinctrl-1 = <&emac0_mdio_sleep>; |
| pinctrl-2 = <&emac0_ephy_active>; |
| pinctrl-3 = <&emac0_ephy_sleep>; |
| qcom,emac-tstamp-en; |
| qcom,emac-ptp-frac-ns-adj = <125000000 1>; |
| phy-mode = "sgmii"; |
| phy-addr = <0>; |
| status = "disable"; |
| }; |
