blob: c6a12a34f58888ef95e707e3ea7ad104cc8102fb [file] [log] [blame]
/* Copyright (c) 2009-2014, Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <linux/uaccess.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/dma-mapping.h>
#include <linux/clk/msm-clk.h>
#include <linux/irqchip/msm-mpm-irq.h>
#include <soc/qcom/scm.h>
#include <linux/usb.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/usb/gadget.h>
#include <linux/usb/hcd.h>
#include <linux/usb/quirks.h>
#include <linux/usb/msm_hsusb.h>
#include <linux/usb/msm_hsusb_hw.h>
#include <linux/usb/msm_ext_chg.h>
#include <linux/regulator/consumer.h>
#include <linux/mfd/pm8xxx/pm8921-charger.h>
#include <linux/mfd/pm8xxx/misc.h>
#include <linux/mhl_8334.h>
#include <mach/msm_xo.h>
#include <mach/msm_bus.h>
#include <mach/rpm-regulator.h>
#define MSM_USB_BASE (motg->regs)
#define DRIVER_NAME "msm_otg"
#define ID_TIMER_FREQ (jiffies + msecs_to_jiffies(500))
#define CHG_RECHECK_DELAY (jiffies + msecs_to_jiffies(2000))
#define ULPI_IO_TIMEOUT_USEC (10 * 1000)
#define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
#define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
#define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
#define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
#define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
#define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
#define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
#define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
#define USB_PHY_VDD_DIG_VOL_NONE 0 /*uV */
#define USB_PHY_VDD_DIG_VOL_MIN 1045000 /* uV */
#define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
#define USB_SUSPEND_DELAY_TIME (500 * HZ/1000) /* 500 msec */
enum msm_otg_phy_reg_mode {
USB_PHY_REG_OFF,
USB_PHY_REG_ON,
USB_PHY_REG_LPM_ON,
USB_PHY_REG_LPM_OFF,
};
static char *override_phy_init;
module_param(override_phy_init, charp, S_IRUGO|S_IWUSR);
MODULE_PARM_DESC(override_phy_init,
"Override HSUSB PHY Init Settings");
unsigned int lpm_disconnect_thresh = 1000;
module_param(lpm_disconnect_thresh , uint, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(lpm_disconnect_thresh,
"Delay before entering LPM on USB disconnect");
static bool floated_charger_enable;
module_param(floated_charger_enable , bool, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(floated_charger_enable,
"Whether to enable floated charger");
static DECLARE_COMPLETION(pmic_vbus_init);
static struct msm_otg *the_msm_otg;
static bool debug_aca_enabled;
static bool debug_bus_voting_enabled;
static bool mhl_det_in_progress;
static struct regulator *hsusb_3p3;
static struct regulator *hsusb_1p8;
static struct regulator *hsusb_vdd;
static struct regulator *vbus_otg;
static struct regulator *mhl_usb_hs_switch;
static struct power_supply *psy;
static bool aca_id_turned_on;
static bool legacy_power_supply;
static inline bool aca_enabled(void)
{
#ifdef CONFIG_USB_MSM_ACA
return true;
#else
return debug_aca_enabled;
#endif
}
static int vdd_val[VDD_TYPE_MAX][VDD_VAL_MAX] = {
{ /* VDD_CX CORNER Voting */
[VDD_NONE] = RPM_VREG_CORNER_NONE,
[VDD_MIN] = RPM_VREG_CORNER_NOMINAL,
[VDD_MAX] = RPM_VREG_CORNER_HIGH,
},
{ /* VDD_CX Voltage Voting */
[VDD_NONE] = USB_PHY_VDD_DIG_VOL_NONE,
[VDD_MIN] = USB_PHY_VDD_DIG_VOL_MIN,
[VDD_MAX] = USB_PHY_VDD_DIG_VOL_MAX,
},
};
static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
{
int rc = 0;
if (init) {
hsusb_3p3 = devm_regulator_get(motg->phy.dev, "HSUSB_3p3");
if (IS_ERR(hsusb_3p3)) {
dev_err(motg->phy.dev, "unable to get hsusb 3p3\n");
return PTR_ERR(hsusb_3p3);
}
rc = regulator_set_voltage(hsusb_3p3, USB_PHY_3P3_VOL_MIN,
USB_PHY_3P3_VOL_MAX);
if (rc) {
dev_err(motg->phy.dev, "unable to set voltage level for"
"hsusb 3p3\n");
return rc;
}
hsusb_1p8 = devm_regulator_get(motg->phy.dev, "HSUSB_1p8");
if (IS_ERR(hsusb_1p8)) {
dev_err(motg->phy.dev, "unable to get hsusb 1p8\n");
rc = PTR_ERR(hsusb_1p8);
goto put_3p3_lpm;
}
rc = regulator_set_voltage(hsusb_1p8, USB_PHY_1P8_VOL_MIN,
USB_PHY_1P8_VOL_MAX);
if (rc) {
dev_err(motg->phy.dev, "unable to set voltage level "
"for hsusb 1p8\n");
goto put_1p8;
}
return 0;
}
put_1p8:
regulator_set_voltage(hsusb_1p8, 0, USB_PHY_1P8_VOL_MAX);
put_3p3_lpm:
regulator_set_voltage(hsusb_3p3, 0, USB_PHY_3P3_VOL_MAX);
return rc;
}
static int msm_hsusb_config_vddcx(int high)
{
struct msm_otg *motg = the_msm_otg;
enum usb_vdd_type vdd_type = motg->vdd_type;
int max_vol = vdd_val[vdd_type][VDD_MAX];
int min_vol;
int ret;
min_vol = vdd_val[vdd_type][!!high];
ret = regulator_set_voltage(hsusb_vdd, min_vol, max_vol);
if (ret) {
pr_err("%s: unable to set the voltage for regulator "
"HSUSB_VDDCX\n", __func__);
return ret;
}
pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
return ret;
}
static int msm_hsusb_ldo_enable(struct msm_otg *motg,
enum msm_otg_phy_reg_mode mode)
{
int ret = 0;
if (IS_ERR(hsusb_1p8)) {
pr_err("%s: HSUSB_1p8 is not initialized\n", __func__);
return -ENODEV;
}
if (IS_ERR(hsusb_3p3)) {
pr_err("%s: HSUSB_3p3 is not initialized\n", __func__);
return -ENODEV;
}
switch (mode) {
case USB_PHY_REG_ON:
ret = regulator_set_optimum_mode(hsusb_1p8,
USB_PHY_1P8_HPM_LOAD);
if (ret < 0) {
pr_err("%s: Unable to set HPM of the regulator "
"HSUSB_1p8\n", __func__);
return ret;
}
ret = regulator_enable(hsusb_1p8);
if (ret) {
dev_err(motg->phy.dev, "%s: unable to enable the hsusb 1p8\n",
__func__);
regulator_set_optimum_mode(hsusb_1p8, 0);
return ret;
}
ret = regulator_set_optimum_mode(hsusb_3p3,
USB_PHY_3P3_HPM_LOAD);
if (ret < 0) {
pr_err("%s: Unable to set HPM of the regulator "
"HSUSB_3p3\n", __func__);
regulator_set_optimum_mode(hsusb_1p8, 0);
regulator_disable(hsusb_1p8);
return ret;
}
ret = regulator_enable(hsusb_3p3);
if (ret) {
dev_err(motg->phy.dev, "%s: unable to enable the hsusb 3p3\n",
__func__);
regulator_set_optimum_mode(hsusb_3p3, 0);
regulator_set_optimum_mode(hsusb_1p8, 0);
regulator_disable(hsusb_1p8);
return ret;
}
break;
case USB_PHY_REG_OFF:
ret = regulator_disable(hsusb_1p8);
if (ret) {
dev_err(motg->phy.dev, "%s: unable to disable the hsusb 1p8\n",
__func__);
return ret;
}
ret = regulator_set_optimum_mode(hsusb_1p8, 0);
if (ret < 0)
pr_err("%s: Unable to set LPM of the regulator "
"HSUSB_1p8\n", __func__);
ret = regulator_disable(hsusb_3p3);
if (ret) {
dev_err(motg->phy.dev, "%s: unable to disable the hsusb 3p3\n",
__func__);
return ret;
}
ret = regulator_set_optimum_mode(hsusb_3p3, 0);
if (ret < 0)
pr_err("%s: Unable to set LPM of the regulator "
"HSUSB_3p3\n", __func__);
break;
case USB_PHY_REG_LPM_ON:
ret = regulator_set_optimum_mode(hsusb_1p8,
USB_PHY_1P8_LPM_LOAD);
if (ret < 0) {
pr_err("%s: Unable to set LPM of the regulator: HSUSB_1p8\n",
__func__);
return ret;
}
ret = regulator_set_optimum_mode(hsusb_3p3,
USB_PHY_3P3_LPM_LOAD);
if (ret < 0) {
pr_err("%s: Unable to set LPM of the regulator: HSUSB_3p3\n",
__func__);
regulator_set_optimum_mode(hsusb_1p8, USB_PHY_REG_ON);
return ret;
}
break;
case USB_PHY_REG_LPM_OFF:
ret = regulator_set_optimum_mode(hsusb_1p8,
USB_PHY_1P8_HPM_LOAD);
if (ret < 0) {
pr_err("%s: Unable to set HPM of the regulator: HSUSB_1p8\n",
__func__);
return ret;
}
ret = regulator_set_optimum_mode(hsusb_3p3,
USB_PHY_3P3_HPM_LOAD);
if (ret < 0) {
pr_err("%s: Unable to set HPM of the regulator: HSUSB_3p3\n",
__func__);
regulator_set_optimum_mode(hsusb_1p8, USB_PHY_REG_ON);
return ret;
}
break;
default:
pr_err("%s: Unsupported mode (%d).", __func__, mode);
return -ENOTSUPP;
}
pr_debug("%s: USB reg mode (%d) (OFF/HPM/LPM)\n", __func__, mode);
return ret < 0 ? ret : 0;
}
static void msm_hsusb_mhl_switch_enable(struct msm_otg *motg, bool on)
{
struct msm_otg_platform_data *pdata = motg->pdata;
if (!pdata->mhl_enable)
return;
if (!mhl_usb_hs_switch) {
pr_err("%s: mhl_usb_hs_switch is NULL.\n", __func__);
return;
}
if (on) {
if (regulator_enable(mhl_usb_hs_switch))
pr_err("unable to enable mhl_usb_hs_switch\n");
} else {
regulator_disable(mhl_usb_hs_switch);
}
}
static int ulpi_read(struct usb_phy *phy, u32 reg)
{
struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
int cnt = 0;
/* initiate read operation */
writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
USB_ULPI_VIEWPORT);
/* wait for completion */
while (cnt < ULPI_IO_TIMEOUT_USEC) {
if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
break;
udelay(1);
cnt++;
}
if (cnt >= ULPI_IO_TIMEOUT_USEC) {
dev_err(phy->dev, "ulpi_read: timeout %08x\n",
readl(USB_ULPI_VIEWPORT));
dev_err(phy->dev, "PORTSC: %08x USBCMD: %08x\n",
readl_relaxed(USB_PORTSC), readl_relaxed(USB_USBCMD));
return -ETIMEDOUT;
}
return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
}
static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
{
struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
int cnt = 0;
/* initiate write operation */
writel(ULPI_RUN | ULPI_WRITE |
ULPI_ADDR(reg) | ULPI_DATA(val),
USB_ULPI_VIEWPORT);
/* wait for completion */
while (cnt < ULPI_IO_TIMEOUT_USEC) {
if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
break;
udelay(1);
cnt++;
}
if (cnt >= ULPI_IO_TIMEOUT_USEC) {
dev_err(phy->dev, "ulpi_write: timeout\n");
dev_err(phy->dev, "PORTSC: %08x USBCMD: %08x\n",
readl_relaxed(USB_PORTSC), readl_relaxed(USB_USBCMD));
return -ETIMEDOUT;
}
return 0;
}
static struct usb_phy_io_ops msm_otg_io_ops = {
.read = ulpi_read,
.write = ulpi_write,
};
static void ulpi_init(struct msm_otg *motg)
{
struct msm_otg_platform_data *pdata = motg->pdata;
int aseq[10];
int *seq = NULL;
if (override_phy_init) {
pr_debug("%s(): HUSB PHY Init:%s\n", __func__,
override_phy_init);
get_options(override_phy_init, ARRAY_SIZE(aseq), aseq);
seq = &aseq[1];
} else {
seq = pdata->phy_init_seq;
}
if (!seq)
return;
while (seq[0] >= 0) {
if (override_phy_init)
pr_debug("ulpi: write 0x%02x to 0x%02x\n",
seq[0], seq[1]);
dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
seq[0], seq[1]);
ulpi_write(&motg->phy, seq[0], seq[1]);
seq += 2;
}
}
static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
{
int ret;
if (assert) {
if (motg->clk) {
ret = clk_reset(motg->clk, CLK_RESET_ASSERT);
} else {
/* Using asynchronous block reset to the hardware */
dev_dbg(motg->phy.dev, "block_reset ASSERT\n");
clk_disable_unprepare(motg->pclk);
clk_disable_unprepare(motg->core_clk);
ret = clk_reset(motg->core_clk, CLK_RESET_ASSERT);
}
if (ret)
dev_err(motg->phy.dev, "usb hs_clk assert failed\n");
} else {
if (motg->clk) {
ret = clk_reset(motg->clk, CLK_RESET_DEASSERT);
} else {
dev_dbg(motg->phy.dev, "block_reset DEASSERT\n");
ret = clk_reset(motg->core_clk, CLK_RESET_DEASSERT);
ndelay(200);
ret = clk_prepare_enable(motg->core_clk);
WARN(ret, "USB core_clk enable failed\n");
ret = clk_prepare_enable(motg->pclk);
WARN(ret, "USB pclk enable failed\n");
}
if (ret)
dev_err(motg->phy.dev, "usb hs_clk deassert failed\n");
}
return ret;
}
static int msm_otg_phy_reset(struct msm_otg *motg)
{
u32 val;
int ret;
struct msm_otg_platform_data *pdata = motg->pdata;
/*
* AHB2AHB Bypass mode shouldn't be enable before doing
* async clock reset. If it is enable, disable the same.
*/
val = readl_relaxed(USB_AHBMODE);
if (val & AHB2AHB_BYPASS) {
pr_err("%s(): AHB2AHB_BYPASS SET: AHBMODE:%x\n",
__func__, val);
val &= ~AHB2AHB_BYPASS_BIT_MASK;
writel_relaxed(val | AHB2AHB_BYPASS_CLEAR, USB_AHBMODE);
pr_err("%s(): AHBMODE: %x\n", __func__,
readl_relaxed(USB_AHBMODE));
}
ret = msm_otg_link_clk_reset(motg, 1);
if (ret)
return ret;
/* wait for 1ms delay as suggested in HPG. */
usleep_range(1000, 1200);
ret = msm_otg_link_clk_reset(motg, 0);
if (ret)
return ret;
if (pdata && pdata->enable_sec_phy)
writel_relaxed(readl_relaxed(USB_PHY_CTRL2) | (1<<16),
USB_PHY_CTRL2);
val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
writel(val | PORTSC_PTS_ULPI, USB_PORTSC);
dev_info(motg->phy.dev, "phy_reset: success\n");
return 0;
}
#define LINK_RESET_TIMEOUT_USEC (250 * 1000)
static int msm_otg_link_reset(struct msm_otg *motg)
{
int cnt = 0;
struct msm_otg_platform_data *pdata = motg->pdata;
writel_relaxed(USBCMD_RESET, USB_USBCMD);
while (cnt < LINK_RESET_TIMEOUT_USEC) {
if (!(readl_relaxed(USB_USBCMD) & USBCMD_RESET))
break;
udelay(1);
cnt++;
}
if (cnt >= LINK_RESET_TIMEOUT_USEC)
return -ETIMEDOUT;
/* select ULPI phy */
writel_relaxed(0x80000000, USB_PORTSC);
writel_relaxed(0x0, USB_AHBBURST);
writel_relaxed(0x08, USB_AHBMODE);
if (pdata && pdata->enable_sec_phy)
writel_relaxed(readl_relaxed(USB_PHY_CTRL2) | (1<<16),
USB_PHY_CTRL2);
return 0;
}
static void msm_usb_phy_reset(struct msm_otg *motg)
{
u32 val;
if (motg->pdata->phy_type != SNPS_28NM_INTEGRATED_PHY)
return;
/* Assert USB PHY_PON */
val = readl_relaxed(motg->usb_phy_ctrl_reg);
val &= ~PHY_POR_BIT_MASK;
val |= PHY_POR_ASSERT;
writel_relaxed(val, motg->usb_phy_ctrl_reg);
/* wait for minimum 10 microseconds as suggested in HPG. */
usleep_range(10, 15);
/* Deassert USB PHY_PON */
val = readl_relaxed(motg->usb_phy_ctrl_reg);
val &= ~PHY_POR_BIT_MASK;
val |= PHY_POR_DEASSERT;
writel_relaxed(val, motg->usb_phy_ctrl_reg);
/* Ensure that RESET operation is completed. */
mb();
}
static int msm_otg_reset(struct usb_phy *phy)
{
struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
struct msm_otg_platform_data *pdata = motg->pdata;
int ret;
u32 val = 0;
u32 ulpi_val = 0;
/*
* USB PHY and Link reset also reset the USB BAM.
* Thus perform reset operation only once to avoid
* USB BAM reset on other cases e.g. USB cable disconnections.
*/
if (pdata->disable_reset_on_disconnect) {
if (motg->reset_counter)
return 0;
else
motg->reset_counter++;
}
if (motg->clk)
clk_prepare_enable(motg->clk);
ret = msm_otg_phy_reset(motg);
if (ret) {
dev_err(phy->dev, "phy_reset failed\n");
return ret;
}
aca_id_turned_on = false;
ret = msm_otg_link_reset(motg);
if (ret) {
dev_err(phy->dev, "link reset failed\n");
return ret;
}
msleep(100);
/* Reset USB PHY after performing USB Link RESET */
msm_usb_phy_reset(motg);
/* Program USB PHY Override registers. */
ulpi_init(motg);
/*
* It is recommended in HPG to reset USB PHY after programming
* USB PHY Override registers.
*/
msm_usb_phy_reset(motg);
if (motg->clk)
clk_disable_unprepare(motg->clk);
if (pdata->otg_control == OTG_PHY_CONTROL) {
val = readl_relaxed(USB_OTGSC);
if (pdata->mode == USB_OTG) {
ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
val |= OTGSC_IDIE | OTGSC_BSVIE;
} else if (pdata->mode == USB_PERIPHERAL) {
ulpi_val = ULPI_INT_SESS_VALID;
val |= OTGSC_BSVIE;
}
writel_relaxed(val, USB_OTGSC);
ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
} else if (pdata->otg_control == OTG_PMIC_CONTROL) {
ulpi_write(phy, OTG_COMP_DISABLE,
ULPI_SET(ULPI_PWR_CLK_MNG_REG));
/* Enable PMIC pull-up */
pm8xxx_usb_id_pullup(1);
}
if (motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED)
writel_relaxed(readl_relaxed(USB_OTGSC) & ~(OTGSC_IDPU),
USB_OTGSC);
return 0;
}
static const char *timer_string(int bit)
{
switch (bit) {
case A_WAIT_VRISE: return "a_wait_vrise";
case A_WAIT_VFALL: return "a_wait_vfall";
case B_SRP_FAIL: return "b_srp_fail";
case A_WAIT_BCON: return "a_wait_bcon";
case A_AIDL_BDIS: return "a_aidl_bdis";
case A_BIDL_ADIS: return "a_bidl_adis";
case B_ASE0_BRST: return "b_ase0_brst";
case A_TST_MAINT: return "a_tst_maint";
case B_TST_SRP: return "b_tst_srp";
case B_TST_CONFIG: return "b_tst_config";
default: return "UNDEFINED";
}
}
static enum hrtimer_restart msm_otg_timer_func(struct hrtimer *hrtimer)
{
struct msm_otg *motg = container_of(hrtimer, struct msm_otg, timer);
switch (motg->active_tmout) {
case A_WAIT_VRISE:
/* TODO: use vbus_vld interrupt */
set_bit(A_VBUS_VLD, &motg->inputs);
break;
case A_TST_MAINT:
/* OTG PET: End session after TA_TST_MAINT */
set_bit(A_BUS_DROP, &motg->inputs);
break;
case B_TST_SRP:
/*
* OTG PET: Initiate SRP after TB_TST_SRP of
* previous session end.
*/
set_bit(B_BUS_REQ, &motg->inputs);
break;
case B_TST_CONFIG:
clear_bit(A_CONN, &motg->inputs);
break;
default:
set_bit(motg->active_tmout, &motg->tmouts);
}
pr_debug("expired %s timer\n", timer_string(motg->active_tmout));
queue_work(system_nrt_wq, &motg->sm_work);
return HRTIMER_NORESTART;
}
static void msm_otg_del_timer(struct msm_otg *motg)
{
int bit = motg->active_tmout;
pr_debug("deleting %s timer. remaining %lld msec\n", timer_string(bit),
div_s64(ktime_to_us(hrtimer_get_remaining(
&motg->timer)), 1000));
hrtimer_cancel(&motg->timer);
clear_bit(bit, &motg->tmouts);
}
static void msm_otg_start_timer(struct msm_otg *motg, int time, int bit)
{
clear_bit(bit, &motg->tmouts);
motg->active_tmout = bit;
pr_debug("starting %s timer\n", timer_string(bit));
hrtimer_start(&motg->timer,
ktime_set(time / 1000, (time % 1000) * 1000000),
HRTIMER_MODE_REL);
}
static void msm_otg_init_timer(struct msm_otg *motg)
{
hrtimer_init(&motg->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
motg->timer.function = msm_otg_timer_func;
}
static int msm_otg_start_hnp(struct usb_otg *otg)
{
struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
if (otg->phy->state != OTG_STATE_A_HOST) {
pr_err("HNP can not be initiated in %s state\n",
usb_otg_state_string(otg->phy->state));
return -EINVAL;
}
pr_debug("A-Host: HNP initiated\n");
clear_bit(A_BUS_REQ, &motg->inputs);
queue_work(system_nrt_wq, &motg->sm_work);
return 0;
}
static int msm_otg_start_srp(struct usb_otg *otg)
{
struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
u32 val;
int ret = 0;
if (otg->phy->state != OTG_STATE_B_IDLE) {
pr_err("SRP can not be initiated in %s state\n",
usb_otg_state_string(otg->phy->state));
ret = -EINVAL;
goto out;
}
if ((jiffies - motg->b_last_se0_sess) < msecs_to_jiffies(TB_SRP_INIT)) {
pr_debug("initial conditions of SRP are not met. Try again"
"after some time\n");
ret = -EAGAIN;
goto out;
}
pr_debug("B-Device SRP started\n");
/*
* PHY won't pull D+ high unless it detects Vbus valid.
* Since by definition, SRP is only done when Vbus is not valid,
* software work-around needs to be used to spoof the PHY into
* thinking it is valid. This can be done using the VBUSVLDEXTSEL and
* VBUSVLDEXT register bits.
*/
ulpi_write(otg->phy, 0x03, 0x97);
/*
* Harware auto assist data pulsing: Data pulse is given
* for 7msec; wait for vbus
*/
val = readl_relaxed(USB_OTGSC);
writel_relaxed((val & ~OTGSC_INTSTS_MASK) | OTGSC_HADP, USB_OTGSC);
/* VBUS plusing is obsoleted in OTG 2.0 supplement */
out:
return ret;
}
static void msm_otg_host_hnp_enable(struct usb_otg *otg, bool enable)
{
struct usb_hcd *hcd = bus_to_hcd(otg->host);
struct usb_device *rhub = otg->host->root_hub;
if (enable) {
pm_runtime_disable(&rhub->dev);
rhub->state = USB_STATE_NOTATTACHED;
hcd->driver->bus_suspend(hcd);
clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
} else {
usb_remove_hcd(hcd);
msm_otg_reset(otg->phy);
usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
}
}
static int msm_otg_set_suspend(struct usb_phy *phy, int suspend)
{
struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
if (aca_enabled())
return 0;
/*
* UDC and HCD call usb_phy_set_suspend() to enter/exit LPM
* during bus suspend/resume. Update the relevant state
* machine inputs and trigger LPM entry/exit. Checking
* in_lpm flag would avoid unnecessary work scheduling.
*/
if (suspend) {
switch (phy->state) {
case OTG_STATE_A_WAIT_BCON:
if (TA_WAIT_BCON > 0)
break;
/* fall through */
case OTG_STATE_A_HOST:
pr_debug("host bus suspend\n");
clear_bit(A_BUS_REQ, &motg->inputs);
if (!atomic_read(&motg->in_lpm))
queue_work(system_nrt_wq, &motg->sm_work);
break;
case OTG_STATE_B_PERIPHERAL:
pr_debug("peripheral bus suspend\n");
if (!(motg->caps & ALLOW_LPM_ON_DEV_SUSPEND))
break;
set_bit(A_BUS_SUSPEND, &motg->inputs);
if (!atomic_read(&motg->in_lpm))
queue_delayed_work(system_nrt_wq,
&motg->suspend_work,
USB_SUSPEND_DELAY_TIME);
break;
default:
break;
}
} else {
switch (phy->state) {
case OTG_STATE_A_WAIT_BCON:
/* Remote wakeup or resume */
set_bit(A_BUS_REQ, &motg->inputs);
/* ensure hardware is not in low power mode */
if (atomic_read(&motg->in_lpm))
pm_runtime_resume(phy->dev);
break;
case OTG_STATE_A_SUSPEND:
/* Remote wakeup or resume */
set_bit(A_BUS_REQ, &motg->inputs);
phy->state = OTG_STATE_A_HOST;
/* ensure hardware is not in low power mode */
if (atomic_read(&motg->in_lpm))
pm_runtime_resume(phy->dev);
break;
case OTG_STATE_B_PERIPHERAL:
pr_debug("peripheral bus resume\n");
if (!(motg->caps & ALLOW_LPM_ON_DEV_SUSPEND))
break;
clear_bit(A_BUS_SUSPEND, &motg->inputs);
if (atomic_read(&motg->in_lpm))
queue_work(system_nrt_wq, &motg->sm_work);
break;
default:
break;
}
}
return 0;
}
static void msm_otg_bus_vote(struct msm_otg *motg, enum usb_bus_vote vote)
{
int ret;
struct msm_otg_platform_data *pdata = motg->pdata;
/* Check if target allows min_vote to be same as no_vote */
if (pdata->bus_scale_table &&
vote >= pdata->bus_scale_table->num_usecases)
vote = USB_NO_PERF_VOTE;
if (motg->bus_perf_client) {
ret = msm_bus_scale_client_update_request(
motg->bus_perf_client, vote);
if (ret)
dev_err(motg->phy.dev, "%s: Failed to vote (%d)\n"
"for bus bw %d\n", __func__, vote, ret);
}
}
#define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
#define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
#ifdef CONFIG_PM_SLEEP
static int msm_otg_suspend(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
struct usb_bus *bus = phy->otg->host;
struct msm_otg_platform_data *pdata = motg->pdata;
int cnt = 0;
bool host_bus_suspend, device_bus_suspend, dcp, prop_charger;
bool floated_charger, sm_work_busy;
u32 phy_ctrl_val = 0, cmd_val;
unsigned ret;
u32 portsc, config2;
u32 func_ctrl;
if (atomic_read(&motg->in_lpm))
return 0;
if (motg->pdata->delay_lpm_hndshk_on_disconnect &&
!msm_bam_usb_lpm_ok())
return -EBUSY;
motg->ui_enabled = 0;
disable_irq(motg->irq);
host_bus_suspend = !test_bit(MHL, &motg->inputs) && phy->otg->host &&
!test_bit(ID, &motg->inputs);
device_bus_suspend = phy->otg->gadget && test_bit(ID, &motg->inputs) &&
test_bit(A_BUS_SUSPEND, &motg->inputs) &&
motg->caps & ALLOW_LPM_ON_DEV_SUSPEND;
dcp = motg->chg_type == USB_DCP_CHARGER;
prop_charger = motg->chg_type == USB_PROPRIETARY_CHARGER;
floated_charger = motg->chg_type == USB_FLOATED_CHARGER;
/* !BSV, but its handling is in progress by otg sm_work */
sm_work_busy = !test_bit(B_SESS_VLD, &motg->inputs) &&
phy->state == OTG_STATE_B_PERIPHERAL;
/* Enable line state difference wakeup fix for only device and host
* bus suspend scenarios. Otherwise PHY can not be suspended when
* a charger that pulls DP/DM high is connected.
*/
config2 = readl_relaxed(USB_GENCONFIG2);
if (device_bus_suspend)
config2 |= GENCFG2_LINESTATE_DIFF_WAKEUP_EN;
else
config2 &= ~GENCFG2_LINESTATE_DIFF_WAKEUP_EN;
writel_relaxed(config2, USB_GENCONFIG2);
/*
* Abort suspend when,
* 1. charging detection in progress due to cable plug-in
* 2. host mode activation in progress due to Micro-A cable insertion
* 3. !BSV, but its handling is in progress by otg sm_work
*/
if ((test_bit(B_SESS_VLD, &motg->inputs) && !device_bus_suspend &&
!dcp && !prop_charger && !floated_charger) ||
test_bit(A_BUS_REQ, &motg->inputs) || sm_work_busy) {
motg->ui_enabled = 1;
enable_irq(motg->irq);
return -EBUSY;
}
/*
* Chipidea 45-nm PHY suspend sequence:
*
* Interrupt Latch Register auto-clear feature is not present
* in all PHY versions. Latch register is clear on read type.
* Clear latch register to avoid spurious wakeup from
* low power mode (LPM).
*
* PHY comparators are disabled when PHY enters into low power
* mode (LPM). Keep PHY comparators ON in LPM only when we expect
* VBUS/Id notifications from USB PHY. Otherwise turn off USB
* PHY comparators. This save significant amount of power.
*
* PLL is not turned off when PHY enters into low power mode (LPM).
* Disable PLL for maximum power savings.
*/
if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
ulpi_read(phy, 0x14);
if (pdata->otg_control == OTG_PHY_CONTROL)
ulpi_write(phy, 0x01, 0x30);
ulpi_write(phy, 0x08, 0x09);
}
if (motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED) {
/* put the controller in non-driving mode */
func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
ulpi_write(phy, ULPI_IFC_CTRL_AUTORESUME,
ULPI_CLR(ULPI_IFC_CTRL));
}
/* Set the PHCD bit, only if it is not set by the controller.
* PHY may take some time or even fail to enter into low power
* mode (LPM). Hence poll for 500 msec and reset the PHY and link
* in failure case.
*/
portsc = readl_relaxed(USB_PORTSC);
if (!(portsc & PORTSC_PHCD)) {
writel_relaxed(portsc | PORTSC_PHCD,
USB_PORTSC);
while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
if (readl_relaxed(USB_PORTSC) & PORTSC_PHCD)
break;
udelay(1);
cnt++;
}
}
if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
dev_err(phy->dev, "Unable to suspend PHY\n");
msm_otg_reset(phy);
motg->ui_enabled = 1;
enable_irq(motg->irq);
return -ETIMEDOUT;
}
/*
* PHY has capability to generate interrupt asynchronously in low
* power mode (LPM). This interrupt is level triggered. So USB IRQ
* line must be disabled till async interrupt enable bit is cleared
* in USBCMD register. Assert STP (ULPI interface STOP signal) to
* block data communication from PHY.
*
* PHY retention mode is disallowed while entering to LPM with wall
* charger connected. But PHY is put into suspend mode. Hence
* enable asynchronous interrupt to detect charger disconnection when
* PMIC notifications are unavailable.
*/
cmd_val = readl_relaxed(USB_USBCMD);
if (host_bus_suspend || device_bus_suspend ||
(motg->pdata->otg_control == OTG_PHY_CONTROL))
cmd_val |= ASYNC_INTR_CTRL | ULPI_STP_CTRL;
else
cmd_val |= ULPI_STP_CTRL;
writel_relaxed(cmd_val, USB_USBCMD);
/*
* BC1.2 spec mandates PD to enable VDP_SRC when charging from DCP.
* PHY retention and collapse can not happen with VDP_SRC enabled.
*/
if (motg->caps & ALLOW_PHY_RETENTION && !device_bus_suspend && !dcp &&
(!host_bus_suspend || ((motg->caps & ALLOW_HOST_PHY_RETENTION)
&& (pdata->dpdm_pulldown_added || !(portsc & PORTSC_CCS))))) {
phy_ctrl_val = readl_relaxed(motg->usb_phy_ctrl_reg);
if (motg->pdata->otg_control == OTG_PHY_CONTROL) {
/* Enable PHY HV interrupts to wake MPM/Link */
if ((motg->pdata->mode == USB_OTG) ||
(motg->pdata->mode == USB_HOST))
phy_ctrl_val |= (PHY_IDHV_INTEN |
PHY_OTGSESSVLDHV_INTEN);
else
phy_ctrl_val |= PHY_OTGSESSVLDHV_INTEN;
}
if (host_bus_suspend)
phy_ctrl_val |= PHY_CLAMP_DPDMSE_EN;
if (!(motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED)) {
writel_relaxed(phy_ctrl_val & ~PHY_RETEN,
motg->usb_phy_ctrl_reg);
motg->lpm_flags |= PHY_RETENTIONED;
} else {
writel_relaxed(phy_ctrl_val, motg->usb_phy_ctrl_reg);
}
} else if (device_bus_suspend && !dcp &&
(pdata->mpm_dpshv_int || pdata->mpm_dmshv_int)) {
/* DP DM HV interrupts are used for bus resume from XO off */
phy_ctrl_val = readl_relaxed(motg->usb_phy_ctrl_reg);
phy_ctrl_val |= PHY_CLAMP_DPDMSE_EN;
if (motg->caps & ALLOW_PHY_RETENTION && pdata->vddmin_gpio) {
/*
* This is HW WA needed when PHY_CLAMP_DPDMSE_EN is
* enabled and we put the phy in retention mode.
* Without this WA, the async_irq will be fired right
* after suspending whithout any bus resume.
*/
config2 = readl_relaxed(USB_GENCONFIG2);
config2 &= ~GENCFG2_DPSE_DMSE_HV_INTR_EN;
writel_relaxed(config2, USB_GENCONFIG2);
phy_ctrl_val &= ~PHY_RETEN;
motg->lpm_flags |= PHY_RETENTIONED;
gpio_direction_output(pdata->vddmin_gpio, 1);
}
writel_relaxed(phy_ctrl_val, motg->usb_phy_ctrl_reg);
}
/* Ensure that above operation is completed before turning off clocks */
mb();
/* Consider clocks on workaround flag only in case of bus suspend */
if (!(phy->state == OTG_STATE_B_PERIPHERAL &&
test_bit(A_BUS_SUSPEND, &motg->inputs)) ||
!motg->pdata->core_clk_always_on_workaround) {
clk_disable_unprepare(motg->pclk);
clk_disable_unprepare(motg->core_clk);
motg->lpm_flags |= CLOCKS_DOWN;
}
/* usb phy no more require TCXO clock, hence vote for TCXO disable */
if (!host_bus_suspend || ((motg->caps & ALLOW_HOST_PHY_RETENTION) &&
(pdata->dpdm_pulldown_added || !(portsc & PORTSC_CCS)))) {
if (motg->xo_clk) {
clk_disable_unprepare(motg->xo_clk);
motg->lpm_flags |= XO_SHUTDOWN;
} else {
ret = msm_xo_mode_vote(motg->xo_handle,
MSM_XO_MODE_OFF);
if (ret)
dev_err(phy->dev, "%s fail to devote XO %d\n",
__func__, ret);
else
motg->lpm_flags |= XO_SHUTDOWN;
}
}
if (motg->caps & ALLOW_PHY_POWER_COLLAPSE &&
!host_bus_suspend && !dcp) {
msm_hsusb_ldo_enable(motg, USB_PHY_REG_OFF);
motg->lpm_flags |= PHY_PWR_COLLAPSED;
} else if (motg->caps & ALLOW_PHY_REGULATORS_LPM &&
!host_bus_suspend && !device_bus_suspend && !dcp) {
msm_hsusb_ldo_enable(motg, USB_PHY_REG_LPM_ON);
motg->lpm_flags |= PHY_REGULATORS_LPM;
}
if (motg->lpm_flags & PHY_RETENTIONED ||
(motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED)) {
msm_hsusb_config_vddcx(0);
msm_hsusb_mhl_switch_enable(motg, 0);
}
if (device_may_wakeup(phy->dev)) {
if (motg->async_irq)
enable_irq_wake(motg->async_irq);
else
enable_irq_wake(motg->irq);
if (motg->pdata->pmic_id_irq)
enable_irq_wake(motg->pdata->pmic_id_irq);
if (pdata->otg_control == OTG_PHY_CONTROL &&
pdata->mpm_otgsessvld_int)
msm_mpm_set_pin_wake(pdata->mpm_otgsessvld_int, 1);
if ((host_bus_suspend || device_bus_suspend) &&
pdata->mpm_dpshv_int)
msm_mpm_set_pin_wake(pdata->mpm_dpshv_int, 1);
if ((host_bus_suspend || device_bus_suspend) &&
pdata->mpm_dmshv_int)
msm_mpm_set_pin_wake(pdata->mpm_dmshv_int, 1);
}
if (bus)
clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
msm_otg_bus_vote(motg, USB_NO_PERF_VOTE);
motg->host_bus_suspend = host_bus_suspend;
motg->device_bus_suspend = device_bus_suspend;
atomic_set(&motg->in_lpm, 1);
/* Enable ASYNC IRQ (if present) during LPM */
if (motg->async_irq)
enable_irq(motg->async_irq);
/* XO shutdown during idle , non wakeable irqs must be disabled */
if (device_bus_suspend || host_bus_suspend || !motg->async_irq) {
motg->ui_enabled = 1;
enable_irq(motg->irq);
}
wake_unlock(&motg->wlock);
dev_info(phy->dev, "USB in low power mode\n");
return 0;
}
static int msm_otg_resume(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
struct usb_bus *bus = phy->otg->host;
struct msm_otg_platform_data *pdata = motg->pdata;
int cnt = 0;
unsigned temp;
u32 phy_ctrl_val = 0;
unsigned ret;
bool in_device_mode;
bool bus_is_suspended;
bool is_remote_wakeup;
u32 func_ctrl;
if (!atomic_read(&motg->in_lpm))
return 0;
if (motg->pdata->delay_lpm_hndshk_on_disconnect)
msm_bam_notify_lpm_resume();
if (motg->ui_enabled) {
motg->ui_enabled = 0;
disable_irq(motg->irq);
}
wake_lock(&motg->wlock);
/* Some platforms require BUS vote to enable/disable clocks */
msm_otg_bus_vote(motg, USB_MIN_PERF_VOTE);
/* Vote for TCXO when waking up the phy */
if (motg->lpm_flags & XO_SHUTDOWN) {
if (motg->xo_clk) {
clk_prepare_enable(motg->xo_clk);
} else {
ret = msm_xo_mode_vote(motg->xo_handle, MSM_XO_MODE_ON);
if (ret)
dev_err(phy->dev, "%s fail to vote for XO %d\n",
__func__, ret);
}
motg->lpm_flags &= ~XO_SHUTDOWN;
}
if (motg->lpm_flags & CLOCKS_DOWN) {
ret = clk_prepare_enable(motg->core_clk);
WARN(ret, "USB core_clk enable failed\n");
ret = clk_prepare_enable(motg->pclk);
WARN(ret, "USB pclk enable failed\n");
motg->lpm_flags &= ~CLOCKS_DOWN;
}
if (motg->lpm_flags & PHY_PWR_COLLAPSED) {
msm_hsusb_ldo_enable(motg, USB_PHY_REG_ON);
motg->lpm_flags &= ~PHY_PWR_COLLAPSED;
} else if (motg->lpm_flags & PHY_REGULATORS_LPM) {
msm_hsusb_ldo_enable(motg, USB_PHY_REG_LPM_OFF);
motg->lpm_flags &= ~PHY_REGULATORS_LPM;
}
if (motg->lpm_flags & PHY_RETENTIONED ||
(motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED)) {
msm_hsusb_mhl_switch_enable(motg, 1);
msm_hsusb_config_vddcx(1);
phy_ctrl_val = readl_relaxed(motg->usb_phy_ctrl_reg);
phy_ctrl_val |= PHY_RETEN;
if (motg->pdata->otg_control == OTG_PHY_CONTROL &&
!motg->device_bus_suspend)
/* Disable PHY HV interrupts */
phy_ctrl_val &=
~(PHY_IDHV_INTEN | PHY_OTGSESSVLDHV_INTEN);
phy_ctrl_val &= ~(PHY_CLAMP_DPDMSE_EN);
writel_relaxed(phy_ctrl_val, motg->usb_phy_ctrl_reg);
motg->lpm_flags &= ~PHY_RETENTIONED;
if (pdata->vddmin_gpio && motg->device_bus_suspend)
gpio_direction_input(pdata->vddmin_gpio);
} else if (motg->device_bus_suspend) {
phy_ctrl_val = readl_relaxed(motg->usb_phy_ctrl_reg);
phy_ctrl_val &= ~(PHY_CLAMP_DPDMSE_EN);
writel_relaxed(phy_ctrl_val, motg->usb_phy_ctrl_reg);
}
temp = readl(USB_USBCMD);
temp &= ~ASYNC_INTR_CTRL;
temp &= ~ULPI_STP_CTRL;
writel(temp, USB_USBCMD);
/*
* PHY comes out of low power mode (LPM) in case of wakeup
* from asynchronous interrupt.
*/
if (!(readl_relaxed(USB_PORTSC) & PORTSC_PHCD))
goto skip_phy_resume;
in_device_mode =
phy->otg->gadget &&
test_bit(ID, &motg->inputs);
bus_is_suspended =
readl_relaxed(USB_PORTSC) & PORTSC_SUSP_MASK;
is_remote_wakeup = in_device_mode && bus_is_suspended;
if (is_remote_wakeup &&
(atomic_read(&(motg->set_fpr_with_lpm_exit)) ||
pdata->rw_during_lpm_workaround)) {
/* In some targets there is a HW issue with remote wakeup
* during low-power mode. As a workaround, the FPR bit
* is written simultaneously with the clearing of the
* PHCD bit.
*/
writel_relaxed(
(readl_relaxed(USB_PORTSC) & ~PORTSC_PHCD) |
PORTSC_FPR_MASK,
USB_PORTSC);
atomic_set(&(motg->set_fpr_with_lpm_exit), 0);
} else {
writel_relaxed(readl_relaxed(USB_PORTSC) & ~PORTSC_PHCD,
USB_PORTSC);
}
while (cnt < PHY_RESUME_TIMEOUT_USEC) {
if (!(readl_relaxed(USB_PORTSC) & PORTSC_PHCD))
break;
udelay(1);
cnt++;
}
if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
/*
* This is a fatal error. Reset the link and
* PHY. USB state can not be restored. Re-insertion
* of USB cable is the only way to get USB working.
*/
dev_err(phy->dev, "Unable to resume USB."
"Re-plugin the cable\n");
msm_otg_reset(phy);
}
skip_phy_resume:
if (motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED) {
/* put the controller in normal mode */
func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
}
if (device_may_wakeup(phy->dev)) {
if (motg->async_irq)
disable_irq_wake(motg->async_irq);
else
disable_irq_wake(motg->irq);
if (motg->pdata->pmic_id_irq)
disable_irq_wake(motg->pdata->pmic_id_irq);
if (pdata->otg_control == OTG_PHY_CONTROL &&
pdata->mpm_otgsessvld_int)
msm_mpm_set_pin_wake(pdata->mpm_otgsessvld_int, 0);
if ((motg->host_bus_suspend || motg->device_bus_suspend) &&
pdata->mpm_dpshv_int)
msm_mpm_set_pin_wake(pdata->mpm_dpshv_int, 0);
if ((motg->host_bus_suspend || motg->device_bus_suspend) &&
pdata->mpm_dmshv_int)
msm_mpm_set_pin_wake(pdata->mpm_dmshv_int, 0);
}
if (bus)
set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
atomic_set(&motg->in_lpm, 0);
if (motg->async_int) {
/* Match the disable_irq call from ISR */
enable_irq(motg->async_int);
motg->async_int = 0;
}
motg->ui_enabled = 1;
enable_irq(motg->irq);
/* If ASYNC IRQ is present then keep it enabled only during LPM */
if (motg->async_irq)
disable_irq(motg->async_irq);
dev_info(phy->dev, "USB exited from low power mode\n");
return 0;
}
#endif
static void msm_otg_notify_host_mode(struct msm_otg *motg, bool host_mode)
{
if (!psy) {
pr_err("No USB power supply registered!\n");
return;
}
if (legacy_power_supply) {
/* legacy support */
if (host_mode) {
power_supply_set_scope(psy, POWER_SUPPLY_SCOPE_SYSTEM);
} else {
power_supply_set_scope(psy, POWER_SUPPLY_SCOPE_DEVICE);
/*
* VBUS comparator is disabled by PMIC charging driver
* when SYSTEM scope is selected. For ID_GND->ID_A
* transition, give 50 msec delay so that PMIC charger
* driver detect the VBUS and ready for accepting
* charging current value from USB.
*/
if (test_bit(ID_A, &motg->inputs))
msleep(50);
}
} else {
motg->host_mode = host_mode;
power_supply_changed(psy);
}
}
static int msm_otg_notify_chg_type(struct msm_otg *motg)
{
static int charger_type;
/*
* TODO
* Unify OTG driver charger types and power supply charger types
*/
if (charger_type == motg->chg_type)
return 0;
if (motg->chg_type == USB_SDP_CHARGER)
charger_type = POWER_SUPPLY_TYPE_USB;
else if (motg->chg_type == USB_CDP_CHARGER)
charger_type = POWER_SUPPLY_TYPE_USB_CDP;
else if (motg->chg_type == USB_DCP_CHARGER ||
motg->chg_type == USB_PROPRIETARY_CHARGER ||
motg->chg_type == USB_FLOATED_CHARGER)
charger_type = POWER_SUPPLY_TYPE_USB_DCP;
else if ((motg->chg_type == USB_ACA_DOCK_CHARGER ||
motg->chg_type == USB_ACA_A_CHARGER ||
motg->chg_type == USB_ACA_B_CHARGER ||
motg->chg_type == USB_ACA_C_CHARGER))
charger_type = POWER_SUPPLY_TYPE_USB_ACA;
else
charger_type = POWER_SUPPLY_TYPE_UNKNOWN;
if (!psy) {
pr_err("No USB power supply registered!\n");
return -EINVAL;
}
pr_debug("setting usb power supply type %d\n", charger_type);
power_supply_set_supply_type(psy, charger_type);
return 0;
}
static int msm_otg_notify_power_supply(struct msm_otg *motg, unsigned mA)
{
if (!psy) {
dev_dbg(motg->phy.dev, "no usb power supply registered\n");
goto psy_error;
}
if (motg->cur_power == 0 && mA > 2) {
/* Enable charging */
if (power_supply_set_online(psy, true))
goto psy_error;
if (power_supply_set_current_limit(psy, 1000*mA))
goto psy_error;
} else if (motg->cur_power > 0 && (mA == 0 || mA == 2)) {
/* Disable charging */
if (power_supply_set_online(psy, false))
goto psy_error;
/* Set max current limit */
if (power_supply_set_current_limit(psy, 0))
goto psy_error;
} else {
if (power_supply_set_online(psy, true))
goto psy_error;
/* Current has changed (100/2 --> 500) */
if (power_supply_set_current_limit(psy, 1000*mA))
goto psy_error;
}
power_supply_changed(psy);
return 0;
psy_error:
dev_dbg(motg->phy.dev, "power supply error when setting property\n");
return -ENXIO;
}
static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
{
struct usb_gadget *g = motg->phy.otg->gadget;
if (g && g->is_a_peripheral)
return;
if ((motg->chg_type == USB_ACA_DOCK_CHARGER ||
motg->chg_type == USB_ACA_A_CHARGER ||
motg->chg_type == USB_ACA_B_CHARGER ||
motg->chg_type == USB_ACA_C_CHARGER) &&
mA > IDEV_ACA_CHG_LIMIT)
mA = IDEV_ACA_CHG_LIMIT;
if (msm_otg_notify_chg_type(motg))
dev_err(motg->phy.dev,
"Failed notifying %d charger type to PMIC\n",
motg->chg_type);
if (motg->cur_power == mA)
return;
dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
/*
* Use Power Supply API if supported, otherwise fallback
* to legacy pm8921 API.
*/
if (msm_otg_notify_power_supply(motg, mA))
pm8921_charger_vbus_draw(mA);
motg->cur_power = mA;
}
static int msm_otg_set_power(struct usb_phy *phy, unsigned mA)
{
struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
/*
* Gadget driver uses set_power method to notify about the
* available current based on suspend/configured states.
*
* IDEV_CHG can be drawn irrespective of suspend/un-configured
* states when CDP/ACA is connected.
*/
if (motg->chg_type == USB_SDP_CHARGER)
msm_otg_notify_charger(motg, mA);
return 0;
}
static void msm_otg_start_host(struct usb_otg *otg, int on)
{
struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
struct msm_otg_platform_data *pdata = motg->pdata;
struct usb_hcd *hcd;
if (!otg->host)
return;
hcd = bus_to_hcd(otg->host);
if (on) {
dev_dbg(otg->phy->dev, "host on\n");
if (pdata->otg_control == OTG_PHY_CONTROL)
ulpi_write(otg->phy, OTG_COMP_DISABLE,
ULPI_SET(ULPI_PWR_CLK_MNG_REG));
/*
* Some boards have a switch cotrolled by gpio
* to enable/disable internal HUB. Enable internal
* HUB before kicking the host.
*/
if (pdata->setup_gpio)
pdata->setup_gpio(OTG_STATE_A_HOST);
usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
} else {
dev_dbg(otg->phy->dev, "host off\n");
usb_remove_hcd(hcd);
/* HCD core reset all bits of PORTSC. select ULPI phy */
writel_relaxed(0x80000000, USB_PORTSC);
if (pdata->setup_gpio)
pdata->setup_gpio(OTG_STATE_UNDEFINED);
if (pdata->otg_control == OTG_PHY_CONTROL)
ulpi_write(otg->phy, OTG_COMP_DISABLE,
ULPI_CLR(ULPI_PWR_CLK_MNG_REG));
}
}
static int msm_otg_usbdev_notify(struct notifier_block *self,
unsigned long action, void *priv)
{
struct msm_otg *motg = container_of(self, struct msm_otg, usbdev_nb);
struct usb_otg *otg = motg->phy.otg;
struct usb_device *udev = priv;
if (action == USB_BUS_ADD || action == USB_BUS_REMOVE)
goto out;
if (udev->bus != otg->host)
goto out;
/*
* Interested in devices connected directly to the root hub.
* ACA dock can supply IDEV_CHG irrespective devices connected
* on the accessory port.
*/
if (!udev->parent || udev->parent->parent ||
motg->chg_type == USB_ACA_DOCK_CHARGER)
goto out;
switch (action) {
case USB_DEVICE_ADD:
if (aca_enabled())
usb_disable_autosuspend(udev);
if (otg->phy->state == OTG_STATE_A_WAIT_BCON) {
pr_debug("B_CONN set\n");
set_bit(B_CONN, &motg->inputs);
msm_otg_del_timer(motg);
otg->phy->state = OTG_STATE_A_HOST;
/*
* OTG PET: A-device must end session within
* 10 sec after PET enumeration.
*/
if (udev->quirks & USB_QUIRK_OTG_PET)
msm_otg_start_timer(motg, TA_TST_MAINT,
A_TST_MAINT);
}
/* fall through */
case USB_DEVICE_CONFIG:
if (udev->actconfig)
motg->mA_port = udev->actconfig->desc.bMaxPower * 2;
else
motg->mA_port = IUNIT;
if (otg->phy->state == OTG_STATE_B_HOST)
msm_otg_del_timer(motg);
break;
case USB_DEVICE_REMOVE:
if ((otg->phy->state == OTG_STATE_A_HOST) ||
(otg->phy->state == OTG_STATE_A_SUSPEND)) {
pr_debug("B_CONN clear\n");
clear_bit(B_CONN, &motg->inputs);
/*
* OTG PET: A-device must end session after
* PET disconnection if it is enumerated
* with bcdDevice[0] = 1. USB core sets
* bus->otg_vbus_off for us. clear it here.
*/
if (udev->bus->otg_vbus_off) {
udev->bus->otg_vbus_off = 0;
set_bit(A_BUS_DROP, &motg->inputs);
}
queue_work(system_nrt_wq, &motg->sm_work);
}
default:
break;
}
if (test_bit(ID_A, &motg->inputs))
msm_otg_notify_charger(motg, IDEV_ACA_CHG_MAX -
motg->mA_port);
out:
return NOTIFY_OK;
}
static void msm_hsusb_vbus_power(struct msm_otg *motg, bool on)
{
int ret;
static bool vbus_is_on;
if (vbus_is_on == on)
return;
if (motg->pdata->vbus_power) {
ret = motg->pdata->vbus_power(on);
if (!ret)
vbus_is_on = on;
return;
}
if (!vbus_otg) {
pr_err("vbus_otg is NULL.");
return;
}
/*
* if entering host mode tell the charger to not draw any current
* from usb before turning on the boost.
* if exiting host mode disable the boost before enabling to draw
* current from the source.
*/
if (on) {
msm_otg_notify_host_mode(motg, on);
ret = regulator_enable(vbus_otg);
if (ret) {
pr_err("unable to enable vbus_otg\n");
return;
}
vbus_is_on = true;
} else {
ret = regulator_disable(vbus_otg);
if (ret) {
pr_err("unable to disable vbus_otg\n");
return;
}
msm_otg_notify_host_mode(motg, on);
vbus_is_on = false;
}
}
static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
{
struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
struct usb_hcd *hcd;
/*
* Fail host registration if this board can support
* only peripheral configuration.
*/
if (motg->pdata->mode == USB_PERIPHERAL) {
dev_info(otg->phy->dev, "Host mode is not supported\n");
return -ENODEV;
}
if (!motg->pdata->vbus_power && host) {
vbus_otg = devm_regulator_get(motg->phy.dev, "vbus_otg");
if (IS_ERR(vbus_otg)) {
pr_err("Unable to get vbus_otg\n");
return PTR_ERR(vbus_otg);
}
}
if (!host) {
if (otg->phy->state == OTG_STATE_A_HOST) {
pm_runtime_get_sync(otg->phy->dev);
usb_unregister_notify(&motg->usbdev_nb);
msm_otg_start_host(otg, 0);
msm_hsusb_vbus_power(motg, 0);
otg->host = NULL;
otg->phy->state = OTG_STATE_UNDEFINED;
queue_work(system_nrt_wq, &motg->sm_work);
} else {
otg->host = NULL;
}
return 0;
}
hcd = bus_to_hcd(host);
hcd->power_budget = motg->pdata->power_budget;
#ifdef CONFIG_USB_OTG
host->otg_port = 1;
#endif
motg->usbdev_nb.notifier_call = msm_otg_usbdev_notify;
usb_register_notify(&motg->usbdev_nb);
otg->host = host;
dev_dbg(otg->phy->dev, "host driver registered w/ tranceiver\n");
/*
* Kick the state machine work, if peripheral is not supported
* or peripheral is already registered with us.
*/
if (motg->pdata->mode == USB_HOST || otg->gadget) {
pm_runtime_get_sync(otg->phy->dev);
queue_work(system_nrt_wq, &motg->sm_work);
}
return 0;
}
static void msm_otg_start_peripheral(struct usb_otg *otg, int on)
{
struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
struct msm_otg_platform_data *pdata = motg->pdata;
int ret;
if (!otg->gadget)
return;
if (on) {
dev_dbg(otg->phy->dev, "gadget on\n");
/*
* Some boards have a switch cotrolled by gpio
* to enable/disable internal HUB. Disable internal
* HUB before kicking the gadget.
*/
if (pdata->setup_gpio)
pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
/* Configure BUS performance parameters for MAX bandwidth */
if (debug_bus_voting_enabled)
msm_otg_bus_vote(motg, USB_MAX_PERF_VOTE);
usb_gadget_vbus_connect(otg->gadget);
/*
* Request VDD min gpio, if need to support VDD
* minimazation during peripheral bus suspend.
*/
if (pdata->vddmin_gpio) {
ret = gpio_request(pdata->vddmin_gpio,
"MSM_OTG_VDD_MIN_GPIO");
if (ret < 0) {
dev_err(otg->phy->dev,
"gpio req failed for vdd min:%d\n",
ret);
pdata->vddmin_gpio = 0;
}
}
} else {
dev_dbg(otg->phy->dev, "gadget off\n");
usb_gadget_vbus_disconnect(otg->gadget);
/* Configure BUS performance parameters to default */
msm_otg_bus_vote(motg, USB_MIN_PERF_VOTE);
if (pdata->setup_gpio)
pdata->setup_gpio(OTG_STATE_UNDEFINED);
if (pdata->vddmin_gpio)
gpio_free(pdata->vddmin_gpio);
}
}
static int msm_otg_set_peripheral(struct usb_otg *otg,
struct usb_gadget *gadget)
{
struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
/*
* Fail peripheral registration if this board can support
* only host configuration.
*/
if (motg->pdata->mode == USB_HOST) {
dev_info(otg->phy->dev, "Peripheral mode is not supported\n");
return -ENODEV;
}
if (!gadget) {
if (otg->phy->state == OTG_STATE_B_PERIPHERAL) {
pm_runtime_get_sync(otg->phy->dev);
msm_otg_start_peripheral(otg, 0);
otg->gadget = NULL;
otg->phy->state = OTG_STATE_UNDEFINED;
queue_work(system_nrt_wq, &motg->sm_work);
} else {
otg->gadget = NULL;
}
return 0;
}
otg->gadget = gadget;
dev_dbg(otg->phy->dev, "peripheral driver registered w/ tranceiver\n");
/*
* Kick the state machine work, if host is not supported
* or host is already registered with us.
*/
if (motg->pdata->mode == USB_PERIPHERAL || otg->host) {
pm_runtime_get_sync(otg->phy->dev);
queue_work(system_nrt_wq, &motg->sm_work);
}
return 0;
}
static bool msm_otg_read_pmic_id_state(struct msm_otg *motg)
{
unsigned long flags;
int id;
if (!motg->pdata->pmic_id_irq)
return -ENODEV;
local_irq_save(flags);
id = irq_read_line(motg->pdata->pmic_id_irq);
local_irq_restore(flags);
/*
* If we can not read ID line state for some reason, treat
* it as float. This would prevent MHL discovery and kicking
* host mode unnecessarily.
*/
return !!id;
}
static int msm_otg_mhl_register_callback(struct msm_otg *motg,
void (*callback)(int on))
{
struct usb_phy *phy = &motg->phy;
int ret;
if (!motg->pdata->mhl_enable) {
dev_dbg(phy->dev, "MHL feature not enabled\n");
return -ENODEV;
}
if (motg->pdata->otg_control != OTG_PMIC_CONTROL ||
!motg->pdata->pmic_id_irq) {
dev_dbg(phy->dev, "MHL can not be supported without PMIC Id\n");
return -ENODEV;
}
if (!motg->pdata->mhl_dev_name) {
dev_dbg(phy->dev, "MHL device name does not exist.\n");
return -ENODEV;
}
if (callback)
ret = mhl_register_callback(motg->pdata->mhl_dev_name,
callback);
else
ret = mhl_unregister_callback(motg->pdata->mhl_dev_name);
if (ret)
dev_dbg(phy->dev, "mhl_register_callback(%s) return error=%d\n",
motg->pdata->mhl_dev_name, ret);
else
motg->mhl_enabled = true;
return ret;
}
static void msm_otg_mhl_notify_online(int on)
{
struct msm_otg *motg = the_msm_otg;
struct usb_phy *phy = &motg->phy;
bool queue = false;
dev_dbg(phy->dev, "notify MHL %s%s\n", on ? "" : "dis", "connected");
if (on) {
set_bit(MHL, &motg->inputs);
} else {
clear_bit(MHL, &motg->inputs);
queue = true;
}
if (queue && phy->state != OTG_STATE_UNDEFINED)
schedule_work(&motg->sm_work);
}
static bool msm_otg_is_mhl(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
int is_mhl, ret;
ret = mhl_device_discovery(motg->pdata->mhl_dev_name, &is_mhl);
if (ret || is_mhl != MHL_DISCOVERY_RESULT_MHL) {
/*
* MHL driver calls our callback saying that MHL connected
* if RID_GND is detected. But at later part of discovery
* it may figure out MHL is not connected and returns
* false. Hence clear MHL input here.
*/
clear_bit(MHL, &motg->inputs);
dev_dbg(phy->dev, "MHL device not found\n");
return false;
}
set_bit(MHL, &motg->inputs);
dev_dbg(phy->dev, "MHL device found\n");
return true;
}
static bool msm_chg_mhl_detect(struct msm_otg *motg)
{
bool ret, id;
if (!motg->mhl_enabled)
return false;
id = msm_otg_read_pmic_id_state(motg);
if (id)
return false;
mhl_det_in_progress = true;
ret = msm_otg_is_mhl(motg);
mhl_det_in_progress = false;
return ret;
}
static void msm_otg_chg_check_timer_func(unsigned long data)
{
struct msm_otg *motg = (struct msm_otg *) data;
struct usb_otg *otg = motg->phy.otg;
if (atomic_read(&motg->in_lpm) ||
!test_bit(B_SESS_VLD, &motg->inputs) ||
otg->phy->state != OTG_STATE_B_PERIPHERAL ||
otg->gadget->speed != USB_SPEED_UNKNOWN) {
dev_dbg(otg->phy->dev, "Nothing to do in chg_check_timer\n");
return;
}
if ((readl_relaxed(USB_PORTSC) & PORTSC_LS) == PORTSC_LS) {
dev_dbg(otg->phy->dev, "DCP is detected as SDP\n");
set_bit(B_FALSE_SDP, &motg->inputs);
queue_work(system_nrt_wq, &motg->sm_work);
}
}
static bool msm_chg_aca_detect(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
u32 int_sts;
bool ret = false;
if (!aca_enabled())
goto out;
if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY)
goto out;
int_sts = ulpi_read(phy, 0x87);
switch (int_sts & 0x1C) {
case 0x08:
if (!test_and_set_bit(ID_A, &motg->inputs)) {
dev_dbg(phy->dev, "ID_A\n");
motg->chg_type = USB_ACA_A_CHARGER;
motg->chg_state = USB_CHG_STATE_DETECTED;
clear_bit(ID_B, &motg->inputs);
clear_bit(ID_C, &motg->inputs);
set_bit(ID, &motg->inputs);
ret = true;
}
break;
case 0x0C:
if (!test_and_set_bit(ID_B, &motg->inputs)) {
dev_dbg(phy->dev, "ID_B\n");
motg->chg_type = USB_ACA_B_CHARGER;
motg->chg_state = USB_CHG_STATE_DETECTED;
clear_bit(ID_A, &motg->inputs);
clear_bit(ID_C, &motg->inputs);
set_bit(ID, &motg->inputs);
ret = true;
}
break;
case 0x10:
if (!test_and_set_bit(ID_C, &motg->inputs)) {
dev_dbg(phy->dev, "ID_C\n");
motg->chg_type = USB_ACA_C_CHARGER;
motg->chg_state = USB_CHG_STATE_DETECTED;
clear_bit(ID_A, &motg->inputs);
clear_bit(ID_B, &motg->inputs);
set_bit(ID, &motg->inputs);
ret = true;
}
break;
case 0x04:
if (test_and_clear_bit(ID, &motg->inputs)) {
dev_dbg(phy->dev, "ID_GND\n");
motg->chg_type = USB_INVALID_CHARGER;
motg->chg_state = USB_CHG_STATE_UNDEFINED;
clear_bit(ID_A, &motg->inputs);
clear_bit(ID_B, &motg->inputs);
clear_bit(ID_C, &motg->inputs);
ret = true;
}
break;
default:
ret = test_and_clear_bit(ID_A, &motg->inputs) |
test_and_clear_bit(ID_B, &motg->inputs) |
test_and_clear_bit(ID_C, &motg->inputs) |
!test_and_set_bit(ID, &motg->inputs);
if (ret) {
dev_dbg(phy->dev, "ID A/B/C/GND is no more\n");
motg->chg_type = USB_INVALID_CHARGER;
motg->chg_state = USB_CHG_STATE_UNDEFINED;
}
}
out:
return ret;
}
static void msm_chg_enable_aca_det(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
if (!aca_enabled())
return;
switch (motg->pdata->phy_type) {
case SNPS_28NM_INTEGRATED_PHY:
/* Disable ID_GND in link and PHY */
writel_relaxed(readl_relaxed(USB_OTGSC) & ~(OTGSC_IDPU |
OTGSC_IDIE), USB_OTGSC);
ulpi_write(phy, 0x01, 0x0C);
ulpi_write(phy, 0x10, 0x0F);
ulpi_write(phy, 0x10, 0x12);
/* Disable PMIC ID pull-up */
pm8xxx_usb_id_pullup(0);
/* Enable ACA ID detection */
ulpi_write(phy, 0x20, 0x85);
aca_id_turned_on = true;
break;
default:
break;
}
}
static void msm_chg_enable_aca_intr(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
if (!aca_enabled())
return;
switch (motg->pdata->phy_type) {
case SNPS_28NM_INTEGRATED_PHY:
/* Enable ACA Detection interrupt (on any RID change) */
ulpi_write(phy, 0x01, 0x94);
break;
default:
break;
}
}
static void msm_chg_disable_aca_intr(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
if (!aca_enabled())
return;
switch (motg->pdata->phy_type) {
case SNPS_28NM_INTEGRATED_PHY:
ulpi_write(phy, 0x01, 0x95);
break;
default:
break;
}
}
static bool msm_chg_check_aca_intr(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
bool ret = false;
if (!aca_enabled())
return ret;
switch (motg->pdata->phy_type) {
case SNPS_28NM_INTEGRATED_PHY:
if (ulpi_read(phy, 0x91) & 1) {
dev_dbg(phy->dev, "RID change\n");
ulpi_write(phy, 0x01, 0x92);
ret = msm_chg_aca_detect(motg);
}
default:
break;
}
return ret;
}
static void msm_otg_id_timer_func(unsigned long data)
{
struct msm_otg *motg = (struct msm_otg *) data;
if (!aca_enabled())
return;
if (atomic_read(&motg->in_lpm)) {
dev_dbg(motg->phy.dev, "timer: in lpm\n");
return;
}
if (motg->phy.state == OTG_STATE_A_SUSPEND)
goto out;
if (msm_chg_check_aca_intr(motg)) {
dev_dbg(motg->phy.dev, "timer: aca work\n");
queue_work(system_nrt_wq, &motg->sm_work);
}
out:
if (!test_bit(ID, &motg->inputs) || test_bit(ID_A, &motg->inputs))
mod_timer(&motg->id_timer, ID_TIMER_FREQ);
}
static bool msm_chg_check_secondary_det(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
u32 chg_det;
bool ret = false;
switch (motg->pdata->phy_type) {
case CI_45NM_INTEGRATED_PHY:
chg_det = ulpi_read(phy, 0x34);
ret = chg_det & (1 << 4);
break;
case SNPS_28NM_INTEGRATED_PHY:
chg_det = ulpi_read(phy, 0x87);
ret = chg_det & 1;
break;
default:
break;
}
return ret;
}
static void msm_chg_enable_secondary_det(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
u32 chg_det;
switch (motg->pdata->phy_type) {
case CI_45NM_INTEGRATED_PHY:
chg_det = ulpi_read(phy, 0x34);
/* Turn off charger block */
chg_det |= ~(1 << 1);
ulpi_write(phy, chg_det, 0x34);
udelay(20);
/* control chg block via ULPI */
chg_det &= ~(1 << 3);
ulpi_write(phy, chg_det, 0x34);
/* put it in host mode for enabling D- source */
chg_det &= ~(1 << 2);
ulpi_write(phy, chg_det, 0x34);
/* Turn on chg detect block */
chg_det &= ~(1 << 1);
ulpi_write(phy, chg_det, 0x34);
udelay(20);
/* enable chg detection */
chg_det &= ~(1 << 0);
ulpi_write(phy, chg_det, 0x34);
break;
case SNPS_28NM_INTEGRATED_PHY:
/*
* Configure DM as current source, DP as current sink
* and enable battery charging comparators.
*/
ulpi_write(phy, 0x8, 0x85);
ulpi_write(phy, 0x2, 0x85);
ulpi_write(phy, 0x1, 0x85);
break;
default:
break;
}
}
static bool msm_chg_check_primary_det(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
u32 chg_det;
bool ret = false;
switch (motg->pdata->phy_type) {
case CI_45NM_INTEGRATED_PHY:
chg_det = ulpi_read(phy, 0x34);
ret = chg_det & (1 << 4);
break;
case SNPS_28NM_INTEGRATED_PHY:
chg_det = ulpi_read(phy, 0x87);
ret = chg_det & 1;
/* Turn off VDP_SRC */
ulpi_write(phy, 0x3, 0x86);
msleep(20);
break;
default:
break;
}
return ret;
}
static void msm_chg_enable_primary_det(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
u32 chg_det;
switch (motg->pdata->phy_type) {
case CI_45NM_INTEGRATED_PHY:
chg_det = ulpi_read(phy, 0x34);
/* enable chg detection */
chg_det &= ~(1 << 0);
ulpi_write(phy, chg_det, 0x34);
break;
case SNPS_28NM_INTEGRATED_PHY:
/*
* Configure DP as current source, DM as current sink
* and enable battery charging comparators.
*/
ulpi_write(phy, 0x2, 0x85);
ulpi_write(phy, 0x1, 0x85);
break;
default:
break;
}
}
static bool msm_chg_check_dcd(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
u32 line_state;
bool ret = false;
switch (motg->pdata->phy_type) {
case CI_45NM_INTEGRATED_PHY:
line_state = ulpi_read(phy, 0x15);
ret = !(line_state & 1);
break;
case SNPS_28NM_INTEGRATED_PHY:
line_state = ulpi_read(phy, 0x87);
ret = line_state & 2;
break;
default:
break;
}
return ret;
}
static void msm_chg_disable_dcd(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
u32 chg_det;
switch (motg->pdata->phy_type) {
case CI_45NM_INTEGRATED_PHY:
chg_det = ulpi_read(phy, 0x34);
chg_det &= ~(1 << 5);
ulpi_write(phy, chg_det, 0x34);
break;
case SNPS_28NM_INTEGRATED_PHY:
ulpi_write(phy, 0x10, 0x86);
break;
default:
break;
}
}
static void msm_chg_enable_dcd(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
u32 chg_det;
switch (motg->pdata->phy_type) {
case CI_45NM_INTEGRATED_PHY:
chg_det = ulpi_read(phy, 0x34);
/* Turn on D+ current source */
chg_det |= (1 << 5);
ulpi_write(phy, chg_det, 0x34);
break;
case SNPS_28NM_INTEGRATED_PHY:
/* Data contact detection enable */
ulpi_write(phy, 0x10, 0x85);
break;
default:
break;
}
}
static void msm_chg_block_on(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
u32 func_ctrl, chg_det;
/* put the controller in non-driving mode */
func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
switch (motg->pdata->phy_type) {
case CI_45NM_INTEGRATED_PHY:
chg_det = ulpi_read(phy, 0x34);
/* control chg block via ULPI */
chg_det &= ~(1 << 3);
ulpi_write(phy, chg_det, 0x34);
/* Turn on chg detect block */
chg_det &= ~(1 << 1);
ulpi_write(phy, chg_det, 0x34);
udelay(20);
break;
case SNPS_28NM_INTEGRATED_PHY:
/* disable DP and DM pull down resistors */
ulpi_write(phy, 0x6, 0xC);
/* Clear charger detecting control bits */
ulpi_write(phy, 0x1F, 0x86);
/* Clear alt interrupt latch and enable bits */
ulpi_write(phy, 0x1F, 0x92);
ulpi_write(phy, 0x1F, 0x95);
udelay(100);
break;
default:
break;
}
}
static void msm_chg_block_off(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
u32 func_ctrl, chg_det;
switch (motg->pdata->phy_type) {
case CI_45NM_INTEGRATED_PHY:
chg_det = ulpi_read(phy, 0x34);
/* Turn off charger block */
chg_det |= ~(1 << 1);
ulpi_write(phy, chg_det, 0x34);
break;
case SNPS_28NM_INTEGRATED_PHY:
/* Clear charger detecting control bits */
ulpi_write(phy, 0x3F, 0x86);
/* Clear alt interrupt latch and enable bits */
ulpi_write(phy, 0x1F, 0x92);
ulpi_write(phy, 0x1F, 0x95);
/* re-enable DP and DM pull down resistors */
ulpi_write(phy, 0x6, 0xB);
break;
default:
break;
}
/* put the controller in normal mode */
func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
}
static const char *chg_to_string(enum usb_chg_type chg_type)
{
switch (chg_type) {
case USB_SDP_CHARGER: return "USB_SDP_CHARGER";
case USB_DCP_CHARGER: return "USB_DCP_CHARGER";
case USB_CDP_CHARGER: return "USB_CDP_CHARGER";
case USB_ACA_A_CHARGER: return "USB_ACA_A_CHARGER";
case USB_ACA_B_CHARGER: return "USB_ACA_B_CHARGER";
case USB_ACA_C_CHARGER: return "USB_ACA_C_CHARGER";
case USB_ACA_DOCK_CHARGER: return "USB_ACA_DOCK_CHARGER";
case USB_PROPRIETARY_CHARGER: return "USB_PROPRIETARY_CHARGER";
case USB_FLOATED_CHARGER: return "USB_FLOATED_CHARGER";
default: return "INVALID_CHARGER";
}
}
#define MSM_CHG_DCD_TIMEOUT (750 * HZ/1000) /* 750 msec */
#define MSM_CHG_DCD_POLL_TIME (50 * HZ/1000) /* 50 msec */
#define MSM_CHG_PRIMARY_DET_TIME (50 * HZ/1000) /* TVDPSRC_ON */
#define MSM_CHG_SECONDARY_DET_TIME (50 * HZ/1000) /* TVDMSRC_ON */
static void msm_chg_detect_work(struct work_struct *w)
{
struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
struct usb_phy *phy = &motg->phy;
bool is_dcd = false, tmout, vout, is_aca;
static bool dcd;
u32 line_state, dm_vlgc;
unsigned long delay;
dev_dbg(phy->dev, "chg detection work\n");
if (test_bit(MHL, &motg->inputs)) {
dev_dbg(phy->dev, "detected MHL, escape chg detection work\n");
return;
}
switch (motg->chg_state) {
case USB_CHG_STATE_UNDEFINED:
msm_chg_block_on(motg);
msm_chg_enable_dcd(motg);
msm_chg_enable_aca_det(motg);
motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
motg->dcd_time = 0;
delay = MSM_CHG_DCD_POLL_TIME;
break;
case USB_CHG_STATE_WAIT_FOR_DCD:
if (msm_chg_mhl_detect(motg)) {
msm_chg_block_off(motg);
motg->chg_state = USB_CHG_STATE_DETECTED;
motg->chg_type = USB_INVALID_CHARGER;
queue_work(system_nrt_wq, &motg->sm_work);
return;
}
is_aca = msm_chg_aca_detect(motg);
if (is_aca) {
/*
* ID_A can be ACA dock too. continue
* primary detection after DCD.
*/
if (test_bit(ID_A, &motg->inputs)) {
motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
} else {
delay = 0;
break;
}
}
is_dcd = msm_chg_check_dcd(motg);
motg->dcd_time += MSM_CHG_DCD_POLL_TIME;
tmout = motg->dcd_time >= MSM_CHG_DCD_TIMEOUT;
if (is_dcd || tmout) {
if (is_dcd)
dcd = true;
else
dcd = false;
msm_chg_disable_dcd(motg);
msm_chg_enable_primary_det(motg);
delay = MSM_CHG_PRIMARY_DET_TIME;
motg->chg_state = USB_CHG_STATE_DCD_DONE;
} else {
delay = MSM_CHG_DCD_POLL_TIME;
}
break;
case USB_CHG_STATE_DCD_DONE:
vout = msm_chg_check_primary_det(motg);
line_state = readl_relaxed(USB_PORTSC) & PORTSC_LS;
dm_vlgc = line_state & PORTSC_LS_DM;
if (vout && !dm_vlgc) { /* VDAT_REF < DM < VLGC */
if (test_bit(ID_A, &motg->inputs)) {
motg->chg_type = USB_ACA_DOCK_CHARGER;
motg->chg_state = USB_CHG_STATE_DETECTED;
delay = 0;
break;
}
if (line_state) { /* DP > VLGC */
motg->chg_type = USB_PROPRIETARY_CHARGER;
motg->chg_state = USB_CHG_STATE_DETECTED;
delay = 0;
} else {
msm_chg_enable_secondary_det(motg);
delay = MSM_CHG_SECONDARY_DET_TIME;
motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
}
} else { /* DM < VDAT_REF || DM > VLGC */
if (test_bit(ID_A, &motg->inputs)) {
motg->chg_type = USB_ACA_A_CHARGER;
motg->chg_state = USB_CHG_STATE_DETECTED;
delay = 0;
break;
}
if (line_state) /* DP > VLGC or/and DM > VLGC */
motg->chg_type = USB_PROPRIETARY_CHARGER;
else if (!dcd && floated_charger_enable)
motg->chg_type = USB_FLOATED_CHARGER;
else
motg->chg_type = USB_SDP_CHARGER;
motg->chg_state = USB_CHG_STATE_DETECTED;
delay = 0;
}
break;
case USB_CHG_STATE_PRIMARY_DONE:
vout = msm_chg_check_secondary_det(motg);
if (vout)
motg->chg_type = USB_DCP_CHARGER;
else
motg->chg_type = USB_CDP_CHARGER;
motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
/* fall through */
case USB_CHG_STATE_SECONDARY_DONE:
motg->chg_state = USB_CHG_STATE_DETECTED;
case USB_CHG_STATE_DETECTED:
/*
* Notify the charger type to power supply
* owner as soon as we determine the charger.
*/
msm_otg_notify_chg_type(motg);
msm_chg_block_off(motg);
msm_chg_enable_aca_det(motg);
/*
* Spurious interrupt is seen after enabling ACA detection
* due to which charger detection fails in case of PET.
* Add delay of 100 microsec to avoid that.
*/
udelay(100);
msm_chg_enable_aca_intr(motg);
dev_dbg(phy->dev, "chg_type = %s\n",
chg_to_string(motg->chg_type));
queue_work(system_nrt_wq, &motg->sm_work);
return;
default:
return;
}
queue_delayed_work(system_nrt_wq, &motg->chg_work, delay);
}
#define VBUS_INIT_TIMEOUT msecs_to_jiffies(5000)
/*
* We support OTG, Peripheral only and Host only configurations. In case
* of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
* via Id pin status or user request (debugfs). Id/BSV interrupts are not
* enabled when switch is controlled by user and default mode is supplied
* by board file, which can be changed by userspace later.
*/
static void msm_otg_init_sm(struct msm_otg *motg)
{
struct msm_otg_platform_data *pdata = motg->pdata;
u32 otgsc = readl(USB_OTGSC);
int ret;
switch (pdata->mode) {
case USB_OTG:
if (pdata->otg_control == OTG_USER_CONTROL) {
if (pdata->default_mode == USB_HOST) {
clear_bit(ID, &motg->inputs);
} else if (pdata->default_mode == USB_PERIPHERAL) {
set_bit(ID, &motg->inputs);
set_bit(B_SESS_VLD, &motg->inputs);
} else {
set_bit(ID, &motg->inputs);
clear_bit(B_SESS_VLD, &motg->inputs);
}
} else if (pdata->otg_control == OTG_PHY_CONTROL) {
if (otgsc & OTGSC_ID) {
set_bit(ID, &motg->inputs);
} else {
clear_bit(ID, &motg->inputs);
set_bit(A_BUS_REQ, &motg->inputs);
}
if (otgsc & OTGSC_BSV)
set_bit(B_SESS_VLD, &motg->inputs);
else
clear_bit(B_SESS_VLD, &motg->inputs);
} else if (pdata->otg_control == OTG_PMIC_CONTROL) {
if (pdata->pmic_id_irq) {
if (msm_otg_read_pmic_id_state(motg))
set_bit(ID, &motg->inputs);
else
clear_bit(ID, &motg->inputs);
}
/*
* VBUS initial state is reported after PMIC
* driver initialization. Wait for it.
*/
ret = wait_for_completion_timeout(&pmic_vbus_init,
VBUS_INIT_TIMEOUT);
if (!ret) {
dev_dbg(motg->phy.dev, "%s: timeout waiting for PMIC VBUS\n",
__func__);
clear_bit(B_SESS_VLD, &motg->inputs);
pmic_vbus_init.done = 1;
}
}
break;
case USB_HOST:
clear_bit(ID, &motg->inputs);
break;
case USB_PERIPHERAL:
set_bit(ID, &motg->inputs);
if (pdata->otg_control == OTG_PHY_CONTROL) {
if (otgsc & OTGSC_BSV)
set_bit(B_SESS_VLD, &motg->inputs);
else
clear_bit(B_SESS_VLD, &motg->inputs);
} else if (pdata->otg_control == OTG_PMIC_CONTROL) {
/*
* VBUS initial state is reported after PMIC
* driver initialization. Wait for it.
*/
ret = wait_for_completion_timeout(&pmic_vbus_init,
VBUS_INIT_TIMEOUT);
if (!ret) {
dev_dbg(motg->phy.dev, "%s: timeout waiting for PMIC VBUS\n",
__func__);
clear_bit(B_SESS_VLD, &motg->inputs);
pmic_vbus_init.done = 1;
}
} else if (pdata->otg_control == OTG_USER_CONTROL) {
set_bit(ID, &motg->inputs);
set_bit(B_SESS_VLD, &motg->inputs);
}
break;
default:
break;
}
}
static void msm_otg_wait_for_ext_chg_done(struct msm_otg *motg)
{
struct usb_phy *phy = &motg->phy;
unsigned long t;
/*
* Defer next cable connect event till external charger
* detection is completed.
*/
if (motg->ext_chg_active) {
pr_debug("before msm_otg ext chg wait\n");
t = wait_for_completion_timeout(&motg->ext_chg_wait,
msecs_to_jiffies(3000));
if (!t)
pr_err("msm_otg ext chg wait timeout\n");
else
pr_debug("msm_otg ext chg wait done\n");
}
if (motg->ext_chg_opened) {
if (phy->flags & ENABLE_DP_MANUAL_PULLUP) {
ulpi_write(phy, ULPI_MISC_A_VBUSVLDEXT |
ULPI_MISC_A_VBUSVLDEXTSEL,
ULPI_CLR(ULPI_MISC_A));
}
/* clear charging register bits */
ulpi_write(phy, 0x3F, 0x86);
/* re-enable DP and DM pull-down resistors*/
ulpi_write(phy, 0x6, 0xB);
}
}
static void msm_otg_sm_work(struct work_struct *w)
{
struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
struct usb_otg *otg = motg->phy.otg;
bool work = 0, srp_reqd, dcp;
pm_runtime_resume(otg->phy->dev);
if (motg->pm_done)
pm_runtime_get_sync(otg->phy->dev);
pr_debug("%s work\n", usb_otg_state_string(otg->phy->state));
switch (otg->phy->state) {
case OTG_STATE_UNDEFINED:
msm_otg_reset(otg->phy);
msm_otg_init_sm(motg);
if (!psy && legacy_power_supply) {
psy = power_supply_get_by_name("usb");
if (!psy)
pr_err("couldn't get usb power supply\n");
}
otg->phy->state = OTG_STATE_B_IDLE;
if (!test_bit(B_SESS_VLD, &motg->inputs) &&
test_bit(ID, &motg->inputs)) {
pm_runtime_put_noidle(otg->phy->dev);
pm_runtime_suspend(otg->phy->dev);
break;
}
/* FALL THROUGH */
case OTG_STATE_B_IDLE:
if (test_bit(MHL, &motg->inputs)) {
/* allow LPM */
pm_runtime_put_noidle(otg->phy->dev);
pm_runtime_suspend(otg->phy->dev);
} else if ((!test_bit(ID, &motg->inputs) ||
test_bit(ID_A, &motg->inputs)) && otg->host) {
pr_debug("!id || id_A\n");
if (msm_chg_mhl_detect(motg)) {
work = 1;
break;
}
clear_bit(B_BUS_REQ, &motg->inputs);
set_bit(A_BUS_REQ, &motg->inputs);
otg->phy->state = OTG_STATE_A_IDLE;
work = 1;
} else if (test_bit(B_SESS_VLD, &motg->inputs)) {
pr_debug("b_sess_vld\n");
switch (motg->chg_state) {
case USB_CHG_STATE_UNDEFINED:
msm_chg_detect_work(&motg->chg_work.work);
break;
case USB_CHG_STATE_DETECTED:
switch (motg->chg_type) {
case USB_DCP_CHARGER:
/* Enable VDP_SRC */
ulpi_write(otg->phy, 0x2, 0x85);
if (motg->ext_chg_opened) {
init_completion(
&motg->ext_chg_wait);
motg->ext_chg_active = true;
}
/* fall through */
case USB_PROPRIETARY_CHARGER:
msm_otg_notify_charger(motg,
IDEV_CHG_MAX);
pm_runtime_put_sync(otg->phy->dev);
break;
case USB_FLOATED_CHARGER:
msm_otg_notify_charger(motg,
IDEV_CHG_MAX);
pm_runtime_put_noidle(otg->phy->dev);
pm_runtime_suspend(otg->phy->dev);
break;
case USB_ACA_B_CHARGER: