Merge "ARM: dts: msm: update dt node to support PCIe2 on kona"
diff --git a/arch/arm64/boot/dts/qcom/kona-pcie.dtsi b/arch/arm64/boot/dts/qcom/kona-pcie.dtsi
index 2b64323..2a28bd5 100644
--- a/arch/arm64/boot/dts/qcom/kona-pcie.dtsi
+++ b/arch/arm64/boot/dts/qcom/kona-pcie.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/clock/qcom,gcc-kona.h>
@@ -9,16 +9,13 @@
pcie2: qcom,pcie@1c10000 {
compatible = "qcom,pci-msm";
- reg = <0x01c10000 0x4000>,
+ reg = <0x01c10000 0x3000>,
<0x01c16000 0x2000>,
<0x64000000 0xf1d>,
<0x64000f20 0xa8>,
<0x64001000 0x1000>,
- <0x64100000 0x100000>,
- <0x64200000 0x100000>,
- <0x64300000 0x4000000>;
- reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
- "io", "bars";
+ <0x64100000 0x100000>;
+ reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
cell-index = <2>;
linux,pci-domain = <2>;
@@ -26,20 +23,19 @@
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x64200000 0x64200000 0x0 0x100000>,
- <0x02000000 0x0 0x64300000 0x64300000 0x0 0x4000000>;
+ <0x02000000 0x0 0x64300000 0x64300000 0x0 0x3d00000>;
interrupt-parent = <&pcie2>;
- interrupts = <0 1 2 3 4 5>;
- interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",
- "int_global_int";
+ interrupts = <0 1 2 3 4>;
+ interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+ "int_d";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0xffffffff>;
- interrupt-map = <0 0 0 0 &intc GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH
+ interrupt-map = <0 0 0 0 &intc GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH
0 0 0 1 &intc GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &intc GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &intc GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
- 0 0 0 4 &intc GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
- 0 0 0 5 &intc GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+ 0 0 0 4 &intc GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
msi-parent = <&pcie2_msi>;
perst-gpio = <&tlmm 85 0>;
@@ -53,8 +49,8 @@
vreg-1p8-supply = <&pm8150_l9>;
vreg-0p9-supply = <&pm8150_l5>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
- qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>;
- qcom,vreg-0p9-voltage-level = <880000 880000 24000>;
+ qcom,vreg-1p8-voltage-level = <1200000 1200000 25500>;
+ qcom,vreg-0p9-voltage-level = <880000 880000 98800>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
@@ -75,13 +71,14 @@
<&clock_gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
<&clock_gcc GCC_PCIE2_PHY_REFGEN_CLK>,
- <&clock_gcc GCC_PCIE_PHY_AUX_CLK>;
+ <&clock_gcc GCC_PCIE_PHY_AUX_CLK>,
+ <&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
clock-names = "pcie_2_pipe_clk", "pcie_2_ref_clk_src",
"pcie_2_aux_clk", "pcie_2_cfg_ahb_clk",
"pcie_2_mstr_axi_clk", "pcie_2_slv_axi_clk",
"pcie_2_ldo", "pcie_2_slv_q2a_axi_clk",
"pcie_tbu_clk", "pcie_phy_refgen_clk",
- "pcie_phy_aux_clk";
+ "pcie_phy_aux_clk", "pcie_ddrss_sf_tbu_clk";
max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>, <0>;
@@ -97,9 +94,153 @@
qcom,boot-option = <0x1>;
qcom,use-19p2mhz-aux-clk;
qcom,no-l0s-supported;
+ qcom,no-l1-supported;
+ qcom,no-l1ss-supported;
+ qcom,no-aux-clk-sync;
qcom,slv-addr-space-size = <0x4000000>;
qcom,ep-latency = <10>;
+ qcom,pcie-phy-ver = <0x1000>;
+ qcom,phy-status-offset = <0xa14>;
+ qcom,phy-status-bit = <6>;
+ qcom,phy-power-down-offset = <0xa40>;
+ qcom,phy-sequence = <0x0a40 0x03 0x0
+ 0x0010 0x00 0x0
+ 0x001c 0x31 0x0
+ 0x0020 0x01 0x0
+ 0x0024 0xde 0x0
+ 0x0028 0x07 0x0
+ 0x0030 0x4c 0x0
+ 0x0034 0x06 0x0
+ 0x0048 0x90 0x0
+ 0x0058 0x0f 0x0
+ 0x0074 0x06 0x0
+ 0x0078 0x06 0x0
+ 0x007c 0x16 0x0
+ 0x0080 0x16 0x0
+ 0x0084 0x36 0x0
+ 0x0088 0x36 0x0
+ 0x0094 0x08 0x0
+ 0x00a4 0x42 0x0
+ 0x00ac 0x0a 0x0
+ 0x00b0 0x1a 0x0
+ 0x00b4 0x14 0x0
+ 0x00b8 0x34 0x0
+ 0x00bc 0x82 0x0
+ 0x00c4 0x68 0x0
+ 0x00cc 0x55 0x0
+ 0x00d0 0x55 0x0
+ 0x00d4 0x03 0x0
+ 0x00d8 0xab 0x0
+ 0x00dc 0xaa 0x0
+ 0x00e0 0x02 0x0
+ 0x010c 0x02 0x0
+ 0x0110 0x24 0x0
+ 0x0118 0xb4 0x0
+ 0x011c 0x03 0x0
+ 0x0154 0x34 0x0
+ 0x0158 0x01 0x0
+ 0x016c 0x08 0x0
+ 0x01ac 0xb9 0x0
+ 0x01b0 0x1e 0x0
+ 0x01b4 0x94 0x0
+ 0x01b8 0x18 0x0
+ 0x01bc 0x11 0x0
+ 0x0284 0x35 0x0
+ 0x029c 0x12 0x0
+ 0x023c 0x11 0x0
+ 0x0304 0x02 0x0
+ 0x0408 0x0c 0x0
+ 0x0414 0x03 0x0
+ 0x0434 0x7f 0x0
+ 0x0444 0x70 0x0
+ 0x0460 0x30 0x0
+ 0x0464 0x00 0x0
+ 0x04d4 0x54 0x0
+ 0x04d8 0x07 0x0
+ 0x04dc 0x0d 0x0
+ 0x04e8 0x00 0x0
+ 0x04ec 0x0e 0x0
+ 0x04f0 0x4a 0x0
+ 0x04f4 0x0f 0x0
+ 0x04f8 0xc0 0x0
+ 0x04fc 0x00 0x0
+ 0x0510 0x17 0x0
+ 0x0518 0x1c 0x0
+ 0x051c 0x03 0x0
+ 0x0524 0x1e 0x0
+ 0x0570 0xff 0x0
+ 0x0574 0xff 0x0
+ 0x0578 0xff 0x0
+ 0x057c 0x7f 0x0
+ 0x0580 0x66 0x0
+ 0x0584 0x24 0x0
+ 0x0588 0xe4 0x0
+ 0x058c 0xec 0x0
+ 0x0590 0x3b 0x0
+ 0x0594 0x36 0x0
+ 0x0598 0xd4 0x0
+ 0x059c 0x54 0x0
+ 0x05a0 0xdb 0x0
+ 0x05a4 0x3b 0x0
+ 0x05a8 0x31 0x0
+ 0x05bc 0x0c 0x0
+ 0x0684 0x35 0x0
+ 0x069c 0x12 0x0
+ 0x063c 0x11 0x0
+ 0x0704 0x20 0x0
+ 0x0808 0x0c 0x0
+ 0x0814 0x03 0x0
+ 0x0834 0x7f 0x0
+ 0x0844 0x70 0x0
+ 0x0860 0x30 0x0
+ 0x0864 0x00 0x0
+ 0x08d4 0x54 0x0
+ 0x08d8 0x07 0x0
+ 0x08dc 0x0d 0x0
+ 0x08e8 0x00 0x0
+ 0x08ec 0x0e 0x0
+ 0x08f0 0x4a 0x0
+ 0x08f4 0x0f 0x0
+ 0x08f8 0xc0 0x0
+ 0x08fc 0x00 0x0
+ 0x0910 0x17 0x0
+ 0x0918 0x1c 0x0
+ 0x091c 0x03 0x0
+ 0x0924 0x1e 0x0
+ 0x0970 0xff 0x0
+ 0x0974 0xff 0x0
+ 0x0978 0xff 0x0
+ 0x097c 0x7f 0x0
+ 0x0980 0x66 0x0
+ 0x0984 0x24 0x0
+ 0x0988 0xe4 0x0
+ 0x098c 0xec 0x0
+ 0x0990 0x3b 0x0
+ 0x0994 0x36 0x0
+ 0x0998 0xd4 0x0
+ 0x099c 0x54 0x0
+ 0x09a0 0xdb 0x0
+ 0x09a4 0x3b 0x0
+ 0x09a8 0x31 0x0
+ 0x09bc 0x0c 0x0
+ 0x0adc 0x05 0x0
+ 0x0b88 0x88 0x0
+ 0x0b98 0x0b 0x0
+ 0x0ba4 0x01 0x0
+ 0x0bec 0x01 0x0
+ 0x0e0c 0x0d 0x0
+ 0x0e14 0x07 0x0
+ 0x0e1c 0xc1 0x0
+ 0x0e40 0x01 0x0
+ 0x0e48 0x01 0x0
+ 0x0e90 0x00 0x0
+ 0x0eb4 0x33 0x0
+ 0x0ebc 0x00 0x0
+ 0x0ee0 0x58 0x0
+ 0x0a00 0x00 0x0
+ 0x0a44 0x03 0x0>;
+
pcie2_rp: pcie2_rp {
reg = <0 0 0 0 0>;
};
diff --git a/arch/arm64/boot/dts/qcom/kona-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/kona-pinctrl.dtsi
index 2146971..d6944ae 100644
--- a/arch/arm64/boot/dts/qcom/kona-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/qcom/kona-pinctrl.dtsi
@@ -528,7 +528,7 @@
pcie2_clkreq_default: pcie2_clkreq_default {
mux {
pins = "gpio86";
- function = "pci_e1";
+ function = "pci_e2";
};
config {
diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c
index fd8cc78..d25a75e 100644
--- a/drivers/pci/controller/pci-msm.c
+++ b/drivers/pci/controller/pci-msm.c
@@ -153,7 +153,7 @@
#define MAX_PROP_SIZE (32)
#define MAX_RC_NAME_LEN (15)
#define MSM_PCIE_MAX_VREG (4)
-#define MSM_PCIE_MAX_CLK (13)
+#define MSM_PCIE_MAX_CLK (14)
#define MSM_PCIE_MAX_PIPE_CLK (1)
#define MAX_RC_NUM (3)
#define MAX_DEVICE_NUM (20)
@@ -757,6 +757,7 @@ static struct msm_pcie_clk_info_t
{NULL, "pcie_0_sleep_clk", 0, false, false},
{NULL, "pcie_phy_refgen_clk", 0, false, false},
{NULL, "pcie_tbu_clk", 0, false, false},
+ {NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},
{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
{NULL, "pcie_phy_aux_clk", 0, false, false}
},
@@ -772,6 +773,7 @@ static struct msm_pcie_clk_info_t
{NULL, "pcie_1_sleep_clk", 0, false, false},
{NULL, "pcie_phy_refgen_clk", 0, false, false},
{NULL, "pcie_tbu_clk", 0, false, false},
+ {NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},
{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
{NULL, "pcie_phy_aux_clk", 0, false, false}
},
@@ -787,6 +789,7 @@ static struct msm_pcie_clk_info_t
{NULL, "pcie_2_sleep_clk", 0, false, false},
{NULL, "pcie_phy_refgen_clk", 0, false, false},
{NULL, "pcie_tbu_clk", 0, false, false},
+ {NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},
{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
{NULL, "pcie_phy_aux_clk", 0, false, false}
}
