#include <dt-bindings/clock/mdss-14nm-pll-clk.h>

&soc {
	mdss_mdp: qcom,mdss_mdp {
		compatible = "qcom,sde-kms";
		reg = <0x5e00000 0x8f030>,
		      <0x5eb0000 0x2008>,
		      <0x5e8f000 0x02c>,
		      <0xc125ba4 0x20>;

		reg-names = "mdp_phys",
			   "vbif_phys",
			   "sid_phys",
			   "sde_imem_phys";

		clocks =
			<&gcc GCC_DISP_AHB_CLK>,
			<&gcc GCC_DISP_HF_AXI_CLK>,
			<&gcc GCC_DISP_THROTTLE_CORE_CLK>,
			<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
			<&dispcc DISP_CC_MDSS_AHB_CLK>,
			<&dispcc DISP_CC_MDSS_MDP_CLK>,
			<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
			<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
			<&dispcc DISP_CC_MDSS_ROT_CLK>;
		clock-names = "gcc_iface", "gcc_bus", "throttle_clk",
				 "div_clk",
				"iface_clk", "core_clk", "vsync_clk",
				"lut_clk", "rot_clk";
		clock-rate = <0 0 0 0 0 256000000 19200000 192000000 192000000>;
		clock-max-rate = <0 0 0 0 0 384000000 19200000 384000000
							 307000000>;

		sde-vdd-supply = <&mdss_core_gdsc>;

		/* interrupt config */
		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <1>;

		#power-domain-cells = <0>;

		/* hw blocks */
		qcom,sde-off = <0x1000>;
		qcom,sde-len = <0x494>;

		qcom,sde-ctl-off = <0x2000>;
		qcom,sde-ctl-size = <0x1dc>;
		qcom,sde-ctl-display-pref = "primary";

		qcom,sde-mixer-off = <0x45000>;
		qcom,sde-mixer-size = <0x320>;
		qcom,sde-mixer-display-pref = "primary";

		qcom,sde-dspp-top-off = <0x1300>;
		qcom,sde-dspp-top-size = <0x80>;
		qcom,sde-dspp-off = <0x55000>;
		qcom,sde-dspp-size = <0xfe4>;

		qcom,sde-intf-off = <0x0 0x6b800>;
		qcom,sde-intf-size = <0x2b8>;
		qcom,sde-intf-type = "none", "dsi";

		qcom,sde-pp-off = <0x71000>;
		qcom,sde-pp-size = <0xd4>;

		qcom,sde-dither-off = <0x30e0>;
		qcom,sde-dither-version = <0x00010000>;
		qcom,sde-dither-size = <0x20>;

		qcom,sde-sspp-type = "vig", "dma";

		qcom,sde-sspp-off = <0x5000 0x25000>;
		qcom,sde-sspp-src-size = <0x1f8>;

		qcom,sde-sspp-xin-id = <0 1>;
		qcom,sde-sspp-excl-rect = <1 1>;
		qcom,sde-sspp-smart-dma-priority = <2 1>;
		qcom,sde-smart-dma-rev = "smart_dma_v2p5";

		qcom,sde-mixer-pair-mask = <0>;

		qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
						0xb0 0xc8 0xe0 0xf8 0x110>;

		qcom,sde-mixer-stage-base-layer;

		qcom,sde-max-per-pipe-bw-kbps = <2600000 2600000>;

		qcom,sde-max-per-pipe-bw-high-kbps = <2600000 2600000>;

		/* offsets are relative to "mdp_phys + qcom,sde-off */
		qcom,sde-sspp-clk-ctrl =
				<0x2ac 0>, <0x2ac 8>;
		qcom,sde-sspp-csc-off = <0x1a00>;
		qcom,sde-csc-type = "csc-10bit";
		qcom,sde-qseed-type = "qseedv3lite";
		qcom,sde-sspp-qseed-off = <0xa00>;
		qcom,sde-mixer-linewidth = <2048>;
		qcom,sde-sspp-linewidth = <2160>;
		qcom,sde-mixer-blendstages = <0x4>;
		qcom,sde-highest-bank-bit = <0x1>;
		qcom,sde-ubwc-version = <0x100>;
		qcom,sde-ubwc-swizzle = <0x7>;
		qcom,sde-ubwc-static = <0x11F>;
		qcom,sde-panic-per-pipe;
		qcom,sde-has-cdp;

		qcom,sde-has-dim-layer;
		qcom,sde-has-idle-pc;

		qcom,sde-max-bw-low-kbps = <3100000>;
		qcom,sde-max-bw-high-kbps = <4000000>;
		qcom,sde-min-core-ib-kbps = <2400000>;
		qcom,sde-min-llcc-ib-kbps = <800000>;
		qcom,sde-min-dram-ib-kbps = <800000>;
		qcom,sde-dram-channels = <1>;
		qcom,sde-num-nrt-paths = <0>;

		qcom,sde-vbif-off = <0>;
		qcom,sde-vbif-size = <0x2008>;
		qcom,sde-vbif-id = <0>;
		qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
		qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;

		qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
		qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;

		/*Pending macrotile & macrotile-qseed has the same configs */

		qcom,sde-danger-lut = <0x000000ff 0x0000ffff
			0x00000000 0x00000000 0x0000ffff>;

		qcom,sde-safe-lut-linear = <0 0xfff0>;
		qcom,sde-safe-lut-macrotile = <0 0xff00>;
		/* same as safe-lut-macrotile */
		qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>;
		qcom,sde-safe-lut-nrt = <0 0xffff>;

		qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>;
		qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>;
		qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>;
		qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>;

		qcom,sde-cdp-setting = <1 1>, <1 0>;

		qcom,sde-qos-cpu-mask = <0x3>;
		qcom,sde-qos-cpu-dma-latency = <300>;

		qcom,sde-secure-sid-mask = <0x0000421>;
		qcom,sde-num-mnoc-ports = <1>;
		qcom,sde-axi-bus-width = <16>;

		qcom,sde-sspp-vig-blocks {
			qcom,sde-vig-csc-off = <0x1a00>;
			qcom,sde-vig-qseed-off = <0xa00>;
			qcom,sde-vig-qseed-size = <0xa0>;
			qcom,sde-vig-inverse-pma;
		};

		qcom,sde-dspp-blocks {
			qcom,sde-dspp-igc = <0x0 0x00030001>;
			qcom,sde-dspp-hsic = <0x800 0x00010007>;
			qcom,sde-dspp-memcolor = <0x880 0x00010007>;
			qcom,sde-dspp-hist = <0x800 0x00010007>;
			qcom,sde-dspp-sixzone= <0x900 0x00010007>;
			qcom,sde-dspp-vlut = <0xa00 0x00010008>;
			qcom,sde-dspp-pcc = <0x1700 0x00040000>;
			qcom,sde-dspp-gc = <0x17c0 0x00010008>;
			qcom,sde-dspp-dither = <0x82c 0x00010007>;
		};

		qcom,platform-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,platform-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "sde-vdd";
				qcom,supply-min-voltage = <0>;
				qcom,supply-max-voltage = <0>;
				qcom,supply-enable-load = <0>;
				qcom,supply-disable-load = <0>;
			};
		};

		smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
			compatible = "qcom,smmu_sde_unsec";
			iommus = <&apps_smmu 0x420 0x2>;
			qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
			qcom,iommu-faults = "non-fatal";
			qcom,iommu-earlymap; /* for cont-splash */
		};

		smmu_sde_sec: qcom,smmu_sde_sec_cb {
			compatible = "qcom,smmu_sde_sec";
			iommus = <&apps_smmu 0x421 0x0>;
			qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
			qcom,iommu-faults = "non-fatal";
			qcom,iommu-vmid = <0xa>;
		};

		/* data and reg bus scale settings */
		qcom,sde-data-bus {
			qcom,msm-bus,name = "mdss_sde";
			qcom,msm-bus,num-cases = <3>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,vectors-KBps =
				<22 512 0 0>,
				<22 512 0 4800000>,
				<22 512 0 4800000>;
		};

		qcom,sde-reg-bus {
			qcom,msm-bus,name = "mdss_reg";
			qcom,msm-bus,num-cases = <4>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,vectors-KBps =
				<1 590 0 0>,
				<1 590 0 76800>,
				<1 590 0 150000>,
				<1 590 0 300000>;
		};

		qcom,sde-limits {
			qcom,sde-linewidth-limits {
				qcom,sde-limit-name = "sspp_linewidth_usecases";
				qcom,sde-limit-cases = "vig", "dma", "scale";
				qcom,sde-limit-ids= <0x1 0x2 0x4>;
				qcom,sde-limit-values = <0x1 4096>,
							<0x5 2560>,
							<0x2 2160>;
			};

			qcom,sde-bw-limits {
				qcom,sde-limit-name = "sde_bwlimit_usecases";
				qcom,sde-limit-cases = "per_vig_pipe",
							"per_dma_pipe",
							"total_max_bw",
							"camera_concurrency";
				qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>;
				qcom,sde-limit-values = <0x1 2600000>,
							<0x9 2600000>,
							<0x2 2600000>,
							<0xa 2600000>,
							<0x4 4000000>,
							<0xc 3100000>;
			};
		};
	};

	mdss_rotator: qcom,mdss_rotator {
		compatible = "qcom,sde_rotator";
		reg = <0x5e00000 0xac000>,
		      <0x5eb0000 0x2008>;
		reg-names = "mdp_phys",
			    "rot_vbif_phys";

		#list-cells = <1>;

		qcom,mdss-rot-mode = <1>;

		/* Bus Scale Settings */
		qcom,msm-bus,name = "mdss_rotator";
		qcom,msm-bus,num-cases = <3>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<22 512 0 0>,
			<22 512 0 6400000>,
			<22 512 0 6400000>;

		rot-vdd-supply = <&mdss_core_gdsc>;
		qcom,supply-names = "rot-vdd";

		clocks =
			<&gcc GCC_DISP_AHB_CLK>,
			<&dispcc DISP_CC_MDSS_AHB_CLK>,
			<&dispcc DISP_CC_MDSS_ROT_CLK>;
		clock-names = "gcc_iface",
			"iface_clk", "rot_clk";

		interrupt-parent = <&mdss_mdp>;
		interrupts = <2 0>;

		power-domains = <&mdss_mdp>;
		/*Offline rotator RT setting */
		qcom,mdss-rot-parent = <&mdss_mdp 0>;
		qcom,mdss-rot-xin-id = <10 11>;

		/* Offline rotator QoS setting */
		qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
		qcom,mdss-rot-cdp-setting = <1 1>;
		qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
		qcom,mdss-rot-danger-lut = <0x0 0x0>;
		qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;

		qcom,mdss-default-ot-rd-limit = <32>;
		qcom,mdss-default-ot-wr-limit = <32>;

		qcom,mdss-sbuf-headroom = <20>;

		/* reg bus scale settings */
		rot_reg: qcom,rot-reg-bus {
			qcom,msm-bus,name = "mdss_rot_reg";
			qcom,msm-bus,num-cases = <2>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,vectors-KBps =
				<1 590 0 0>,
				<1 590 0 76800>;
		};

		smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
			compatible = "qcom,smmu_sde_rot_unsec";
			iommus = <&apps_smmu 0x43C 0x0>;
			qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
			qcom,iommu-faults = "non-fatal";
		};

		smmu_rot_sec: qcom,smmu_rot_sec_cb {
			compatible = "qcom,smmu_sde_rot_sec";
			iommus = <&apps_smmu 0x43D 0x0>;
			qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
			qcom,iommu-faults = "non-fatal";
			qcom,iommu-vmid = <0xa>;
		};
	};

	mdss_dsi0: qcom,mdss_dsi0_ctrl {
		compatible = "qcom,dsi-ctrl-hw-v2.4";
		label = "dsi-ctrl-0";
		cell-index = <0>;
		frame-threshold-time-us = <1000>;
		reg =   <0x5e94000 0x400>,
			<0x5f08000 0x4>;
		reg-names = "dsi_ctrl", "disp_cc_base";
		interrupt-parent = <&mdss_mdp>;
		interrupts = <4 0>;
		vdda-1p2-supply = <&L18A>;
		clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
			<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
			<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
			<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
			<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
			<&dispcc DISP_CC_MDSS_ESC0_CLK>;
		clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
					"pixel_clk", "pixel_clk_rcg",
					"esc_clk";

		qcom,ctrl-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,ctrl-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "vdda-1p2";
				qcom,supply-min-voltage = <1232000>;
				qcom,supply-max-voltage = <1232000>;
				qcom,supply-enable-load = <21800>;
				qcom,supply-disable-load = <0>;
			};
		};

		qcom,core-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,core-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "refgen";
				qcom,supply-min-voltage = <0>;
				qcom,supply-max-voltage = <0>;
				qcom,supply-enable-load = <0>;
				qcom,supply-disable-load = <0>;
			};
		};
	};

	mdss_dsi_phy0: qcom,mdss_dsi_phy0 {
		compatible = "qcom,dsi-phy-v2.0";
		label = "dsi-phy-0";
		cell-index = <0>;
		reg = <0x5e94400 0x588>,
			<0x5e01400 0x100>,
			<0x5e94200 0x100>;
		reg-names = "dsi_phy", "phy_clamp_base",
			"dyn_refresh_base";
		vdda-0p9-supply = <&VDD_MX_LEVEL>;
		qcom,platform-strength-ctrl = [ff 06
						ff 06
						ff 06
						ff 06
						ff 00];
		qcom,platform-lane-config = [00 00 10 0f
						00 00 10 0f
						00 00 10 0f
						00 00 10 0f
						00 00 10 8f];
		qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
		qcom,panel-allow-phy-poweroff;
		qcom,phy-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;
			qcom,phy-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "vdda-0p9";
				qcom,supply-min-voltage =
					<RPM_SMD_REGULATOR_LEVEL_NOM>;
				qcom,supply-max-voltage =
					<RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR>;
				qcom,supply-off-min-voltage =
					<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
				qcom,supply-enable-load = <0>;
				qcom,supply-disable-load = <0>;
			};
		};
	};
};