)]}' { "log": [ { "commit": "1eb99171efae98867d4be4a5bd6479ea03f43ac9", "tree": "df82dcf2cf6c29319d9df1e2483843b1974efb65", "parents": [ "dfd9d57ca99d49f296189de8728b81b94ed2e16a" ], "author": { "name": "Dmitrii Merkurev", "email": "dimorinny@google.com", "time": "Fri May 17 13:40:06 2024 +0100" }, "committer": { "name": "Dmitrii Merkurev", "email": "dimorinny@google.com", "time": "Fri May 17 13:40:06 2024 +0100" }, "message": "use common python toolchain\n\nBug: 291553072\nTest: ./tools/bazel run //lk:qemu_riscv64_dist\nChange-Id: I2a3f2948769db8fa3cf196c6350c980b9c1f33fd\nSigned-off-by: Dmitrii Merkurev \u003cdimorinny@google.com\u003e\n" }, { "commit": "dfd9d57ca99d49f296189de8728b81b94ed2e16a", "tree": "83ea5822e941db430f471d0ad6756be0d52bd00b", "parents": [ "ba349e45de475a356e0a1bfccadd8610d49e2943" ], "author": { "name": "Dmitrii Merkurev", "email": "dimorinny@google.com", "time": "Mon Dec 18 23:09:28 2023 +0000" }, "committer": { "name": "Dmitrii Merkurev", "email": "dimorinny@google.com", "time": "Mon Dec 18 23:09:28 2023 +0000" }, "message": "add bazel targets to build riscv and arm64 lk\n\nBug: 291553072\nChange-Id: I902b835860241e258aea907aaf5daa8ad42f1e12\nSigned-off-by: Dmitrii Merkurev \u003cdimorinny@google.com\u003e\n" }, { "commit": "ba349e45de475a356e0a1bfccadd8610d49e2943", "tree": "e00fd6189485ac311ab2a4c085d5bd4f47bfd119", "parents": [ "b3a8f3b31ac5960183bec60edbb57754f426396c", "94a15119b2fe50a076f73e502566895e357b77ff" ], "author": { "name": "Dmitrii Merkurev", "email": "dimorinny@google.com", "time": "Mon Nov 27 01:23:14 2023 +0000" }, "committer": { "name": "Dmitrii Merkurev", "email": "dimorinny@google.com", "time": "Mon Nov 27 01:23:14 2023 +0000" }, "message": "Merge 11.2023 lk upstream master\n\nBug: 291553072\nChange-Id: I41c563c43e0da26d28f33ef39ef059d66b8fceb8\nSigned-off-by: Dmitrii Merkurev \u003cdimorinny@google.com\u003e\n" }, { "commit": "b3a8f3b31ac5960183bec60edbb57754f426396c", "tree": "4b825dc642cb6eb9a060e54bf8d69288fbee4904", "parents": [], "author": { "name": "Inna Palant", "email": "ipalant@google.com", "time": "Tue Nov 14 12:56:57 2023 -0800" }, "committer": { "name": "Inna Palant", "email": "ipalant@google.com", "time": "Tue Nov 14 12:56:57 2023 -0800" }, "message": "Empty commit\n" }, { "commit": "94a15119b2fe50a076f73e502566895e357b77ff", "tree": "e00fd6189485ac311ab2a4c085d5bd4f47bfd119", "parents": [ "ec261bcf45459c0f1d95151b6cfb33910098420c" ], "author": { "name": "Cody Wong", "email": "codycswong@google.com", "time": "Sun Oct 22 19:45:13 2023 +0800" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Sat Nov 04 13:16:24 2023 -0700" }, "message": "[libc][string] fix strncpy potential buffer overflow\n\nThe wrong placement of the increment for index `i` causes an unexpected\nbehavior, which the `strncpy` writes an extra \u0027\\0\u0027.\n\nFor example:\nThe `src` string is \"abc\". The buffer size of `dest` is 5.\n\nWhen we call `strncpy(dest, src, 5)`, the first `for` loop copies the\ncharacters, \u0027a\u0027, \u0027b\u0027, and \u0027c\u0027, to the `dest[0:2]`. In the 4th iteration,\nhowever, the `for` loop breaks due to the termination of `src` whereas\nthe value of `i` stays 3. At the moment, it has copied 4 bytes,\nincluding the \u0027\\0\u0027 of `src`.\n\nIn the second `for` loop, we have `i \u003d 3` and `count \u003d 5`, so the loop\ncopies two more \u0027\\0\u0027 to the `dest`. As a result, the `strncpy` copies 6\nbytes to the `dest` buffer, leading to buffer overflow.\n\nFix the issue by increasing the index `i` before every copy.\n\nSigned-off-by: Cody Wong \u003ccodycswong@google.com\u003e\n" }, { "commit": "ec261bcf45459c0f1d95151b6cfb33910098420c", "tree": "2ab208e390e4471be08a0e9a31a7a78dacabf22e", "parents": [ "58fd2c36d5dd46a7bd31e44fd59e807e9a31696d" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 15 14:32:01 2023 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 15 14:45:49 2023 -0700" }, "message": "[github][ci] switch to gcc 13.2.0 for the default build compiler\n" }, { "commit": "58fd2c36d5dd46a7bd31e44fd59e807e9a31696d", "tree": "abe9c37c8da985eb9b9089553c929386ed3b1b3b", "parents": [ "6b7d0ab627f642d55c83518c63a81ce656723d1b" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Jul 05 23:32:46 2023 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 15 14:41:30 2023 -0700" }, "message": "[platform][jh7110] Tweak logic to find the FDT from the uimage\n" }, { "commit": "6b7d0ab627f642d55c83518c63a81ce656723d1b", "tree": "5151586d6af489ad442e184d19e7f226a1cd6922", "parents": [ "284f83af11784e646492427ffd17e612018ac726" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Jul 05 23:30:52 2023 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 15 14:41:30 2023 -0700" }, "message": "[lib][fdtwalk] add code to skip a cpu if disabled\n\nSome RISC-V cpus come up disabled, skip enumerating them.\n" }, { "commit": "284f83af11784e646492427ffd17e612018ac726", "tree": "cb33370eb3c3bbdcb1490d242ddae5bd62a2c68e", "parents": [ "30dc320054f70910e1c1ee40a6948ee99672acec" ], "author": { "name": "Michael Shavit", "email": "mshavit@google.com", "time": "Wed Aug 30 17:00:34 2023 +0800" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Mon Sep 25 16:03:45 2023 -0700" }, "message": "[arch][arm64] Fix mmu_unmap issue when FEAT_TTL is implemented\n\nPrecisely set bits [55:22] of the vaddress in bits [43:0] for the vae1is\nand vaee1is TLBI commands.\n\nOn platforms where FEAT_TLL is implemented, bits [47:44] of the command\naccept a TTL parameter which can optionally be set to hint the\ntranslation table level containing the address being invalidated.\nImplementations aren\u0027t architecturally required to perform the\ninvalidation if the hint is incorrect however. Invalidations may\ntherefore fail with the current implementation if the vaddress has bits\nset in [58:55].\n\nThis is notably an issue on ARM fastmodels which doesn\u0027t perform the\ninvalidation when the TTL parameter is incorrect.\n" }, { "commit": "30dc320054f70910e1c1ee40a6948ee99672acec", "tree": "fb47ab6337a71029dee71933e449cf7f6805fc0f", "parents": [ "9325ca7f3b3025aafe61898d27f1c02b99426b82", "3b215c398e582765ea33331369250ace997dcf98" ], "author": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Wed Jun 21 15:42:35 2023 -0700" }, "committer": { "name": "GitHub", "email": "noreply@github.com", "time": "Wed Jun 21 15:42:35 2023 -0700" }, "message": "[github] Merge pull request #380 from arichardson/add-clang-ci\n\nAllow building RISCV64 and x86_64 with clang and add a Clang CI job" }, { "commit": "9325ca7f3b3025aafe61898d27f1c02b99426b82", "tree": "bab7dec2014bddafe80556e049074a8816d8e11a", "parents": [ "9cc95f1bf043042559b1ed1c10d00fa0567ce774" ], "author": { "name": "Matt Schulte", "email": "matsch@google.com", "time": "Wed Jun 14 09:52:40 2023 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Wed Jun 21 15:36:22 2023 -0700" }, "message": "Fix typo in endif comment" }, { "commit": "3b215c398e582765ea33331369250ace997dcf98", "tree": "9b98160ac3899522aae102407171e79d2f157a45", "parents": [ "bf6ab93088f7efe7c66f88b71d87b09893ee32e3" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Wed Jun 07 16:07:37 2023 -0700" }, "committer": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Jun 08 07:08:49 2023 -0700" }, "message": "[ci] Add 64-bit RISC-V to Clang CI\n" }, { "commit": "bf6ab93088f7efe7c66f88b71d87b09893ee32e3", "tree": "88e03b8b2ca2180af0060bd06c07ce438ccdac38", "parents": [ "69111c40f5fbde5ffcdcc1a3ba84789a04f260e1" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Dec 09 04:05:29 2021 -0800" }, "committer": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Jun 08 07:08:49 2023 -0700" }, "message": "[riscv] Workaround for undef-weak symbol relocations with clang+lld\n\nWhen building with clang -mcmodel\u003dmedany and linking with ld.lld, we get\nout-of-range relocation errors for undefined __start_\u003csection\u003e symbols\nsince 0 cannot be represented as a PC-relative offset). This is not a\nproblem with ld.bfd since ld.bfd rewrites the instructions to avoid the\nout-of-range PC-relative relocation. For now, the simplest workaround is\nto build with -fpie -mcmodel\u003dmedany (thus indirecting these symbols via\nthe GOT). This will be done automatically once clang includes\nhttps://reviews.llvm.org/D107280.\n\nWithout this change I get the following linker errors:\nld.lld: error: dev/driver.c:21:(.text+0x1E): relocation R_RISCV_PCREL_HI20 out of range: -524295 is not in [-524288, 524287]; references __start_devices\n\nSee https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/126 and\nhttps://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/201.\n" }, { "commit": "69111c40f5fbde5ffcdcc1a3ba84789a04f260e1", "tree": "b77e561b821506b6754da07ab7cfee92b78370f5", "parents": [ "135479c70ec6e4e3384b1bb8433a12e587667d30" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Fri Mar 10 03:55:58 2023 -0800" }, "committer": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Jun 08 07:08:49 2023 -0700" }, "message": "[make] Add a COMPILER_TYPE variable\n\nThis can be used to change compiler flags for GCC vs Clang.\n" }, { "commit": "135479c70ec6e4e3384b1bb8433a12e587667d30", "tree": "11bd7d7f8b7407b12e4b0cbaec4599c9a8b43ad3", "parents": [ "8c20e005ca0f6459670f0a7c449cc2988f3e04a6" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Dec 09 11:43:39 2021 +0000" }, "committer": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Jun 08 07:08:49 2023 -0700" }, "message": "[riscv] Disable linker relaxations when linking with ld.lld\n\nWe have to compile RISC-V code with -mno-relax when linking with ld.lld\nsince ld.lld does not yet support RISC-V linker relaxations. Without this\nchange, linking with ld.lld results in many errors such as:\n`relocation R_RISCV_ALIGN requires unimplemented linker relaxation`.\n\nThis support was implemented as part of LLVM 15, but to support older\nversions of ld.lld we add the flag unconditionally for now.\n" }, { "commit": "8c20e005ca0f6459670f0a7c449cc2988f3e04a6", "tree": "63141d9bdd9b62047e6a56713d3efc40128c5df7", "parents": [ "496e2f4b8c82f30464c3cdfa3c7a65e6e2ac55c2" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Dec 09 11:23:47 2021 +0000" }, "committer": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Jun 08 07:08:49 2023 -0700" }, "message": "[make] Set LINKER_TYPE to lld when building with ld.lld\n\nThis will be needed in a follow-up commit to disable linker relaxations\nfor RISC-V since ld.ldd does not support them yet.\n" }, { "commit": "496e2f4b8c82f30464c3cdfa3c7a65e6e2ac55c2", "tree": "145e7e51c91270c80fae3ce00ddaa8ff75c99868", "parents": [ "6025bec3a1a295deacb8e3479957176c89f5068d" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Dec 09 11:14:22 2021 +0000" }, "committer": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Jun 08 07:08:49 2023 -0700" }, "message": "[riscv][clang] Use a CSR name instead of a numeric expression\n\nClang\u0027s assembler rejects expressions containing e.g. (1u \u003c\u003c N) in the\nassembler. Instead using numeric expressions for per-privilege level\nCSRs, we can prepend `m` or `s`. This also lets the compiler assign the\nCSR encoding instead of having to hardcode it in the source code.\n" }, { "commit": "6025bec3a1a295deacb8e3479957176c89f5068d", "tree": "ffdc3afdcb858fd18dfff1e88bc0ef2cbc403f80", "parents": [ "e3a463e5857fb2ff736c21a00ab69cb6a20f9938" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Wed Jun 07 15:45:10 2023 -0700" }, "committer": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Wed Jun 07 15:55:50 2023 -0700" }, "message": "[ci] Add pc-x86-64-test to the Clang CI job\n" }, { "commit": "e3a463e5857fb2ff736c21a00ab69cb6a20f9938", "tree": "62feaeb9d13adeacb11cfd01844ead892fdcfcab", "parents": [ "c2a31bf8a6bbced04d9c63325a2de24842dbb780" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Wed Jun 07 14:31:07 2023 -0700" }, "committer": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Wed Jun 07 15:55:50 2023 -0700" }, "message": "[x86][clang] Allow clang to evaluate isr_stub_len\n\nThe current code results in\n`error: invalid reassignment of non-absolute variable \u0027isr_stub_start\u0027`.\nUse a numbered label instead (as that can be reassigned) and reference\nthe last occurrence using the b suffix.\n" }, { "commit": "c2a31bf8a6bbced04d9c63325a2de24842dbb780", "tree": "81d190137e473d1a9cdc9522c381030697cb5010", "parents": [ "4a9d0c33bd3e532aa369d8362a7faf1ba3cfd26a" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Wed Jun 07 13:30:11 2023 -0700" }, "committer": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Wed Jun 07 15:55:50 2023 -0700" }, "message": "[x86][clang] Make return mnemonic compatible with clang\n\nGCC appears to accept the Intel retf syntax in AT\u0026T mode but clang is\nstricter and requires use of lret.\n" }, { "commit": "4a9d0c33bd3e532aa369d8362a7faf1ba3cfd26a", "tree": "0203281924dfec359631df7f2d1cc9c3d5cff2f4", "parents": [ "acb933b5ac129932a37ab79b6e672b5156dd1510" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Wed Jun 07 13:25:01 2023 -0700" }, "committer": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Wed Jun 07 15:55:50 2023 -0700" }, "message": "[make] Build with -ffreestanding\n\nWe should build with -ffreestanding since we are building an OS kernel and\ncannot rely on all hosted environment functionality being present.\nSpecifically this fixes a compilation error with clang caused by the\nthe #include_next \u003climits.h\u003e:\n```\nIn file included from target/pc-x86/config.c:9:\nIn file included from dev/include/dev/driver.h:10:\nIn file included from lib/libc/include/sys/types.h:10:\nIn file included from lib/libc/include/limits.h:5:\nIn file included from /usr/lib/llvm-15/lib/clang/15.0.7/include/limits.h:21:\n/usr/include/limits.h:26:10: fatal error: \u0027bits/libc-header-start.h\u0027 file not found\n#include \u003cbits/libc-header-start.h\u003e\n```\nThe flag fixes this issue by ensuring that __STDC_HOSTED__ is no longer set\nto 1, so Clang\u0027s limits.h will not try to include the host system one.\n" }, { "commit": "acb933b5ac129932a37ab79b6e672b5156dd1510", "tree": "91765abbfceffebb1b3c1976478ab6bebf2ac34f", "parents": [ "9cc95f1bf043042559b1ed1c10d00fa0567ce774" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Wed Jun 07 11:40:08 2023 -0700" }, "committer": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Wed Jun 07 15:55:49 2023 -0700" }, "message": "[ci] Add a LLVM toolchain CI configuration file\n\nThis only builds a subset of all targets for now since the remaining\nones (32-bit targets) would require libgcc/compiler-rt for the 64-bit\ninteger and/or double-precision float helper functions.\nCurrently, only aarch64 targets build with clang, but with follow-up\nthis can be extended to include x86_64 and RISCV64.\n" }, { "commit": "9cc95f1bf043042559b1ed1c10d00fa0567ce774", "tree": "be7bc7b9e6b8c85f1ea9872d276041f0cfd97372", "parents": [ "c3a5c31aac46aa8c7f211bba2bfe516113fa849f" ], "author": { "name": "Alexander Richardson", "email": "alexrichardson@google.com", "time": "Wed Jun 07 12:00:23 2023 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Wed Jun 07 13:27:16 2023 -0700" }, "message": "Don\u0027t notify IRC on pushes to forks" }, { "commit": "c3a5c31aac46aa8c7f211bba2bfe516113fa849f", "tree": "9a9bb031a214f5e01e8ff16cb1c63ac04da3d682", "parents": [ "923541d4c23565a47d020d84202a6f77d22fc149" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Thu Jun 01 17:53:22 2023 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Thu Jun 01 17:53:22 2023 -0700" }, "message": "[make][engine] make the setting of toolchain variables conditional\n\nCC, LD, etc was already settable by the environment, but not by\nlocal.mk, since they were assigned in engine.mk as :\u003d. Change the set to\nbe conditional to fix this.\n" }, { "commit": "923541d4c23565a47d020d84202a6f77d22fc149", "tree": "de8f742da49ed5a31808037abfcb37221c82b944", "parents": [ "231f58903b6f86f8c8de33901671101152328ac8" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu May 04 13:53:48 2023 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Thu Jun 01 17:50:50 2023 -0700" }, "message": "[clang][arm64] Disable -Wasm-operand-widths warning\n\nClang incorrectly diagnoses msr operations as need a 64-bit operand even\nif the underlying register is actually 32 bits. Silence this warning.\nThere are quite a few occurrences of this warning so I opted to add the\n-Wno-flag instead of wrapping all callsites in\n`#pragma clang diagnostic ignored -Wasm-operand-widths`.\n" }, { "commit": "231f58903b6f86f8c8de33901671101152328ac8", "tree": "e486a4111f14491807a8a81225147f439ed53442", "parents": [ "06a206f44e6295695b014fd82c18487e37d6c6e7" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Dec 09 10:59:09 2021 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Thu Jun 01 17:50:50 2023 -0700" }, "message": "[make][clang] Do not add unsupported warning flags\n\nCurrently, clang does not support the -Wno-nonnull-compare and\n-Wmaybe-uninitialized warning flags so this adds lots of unknown warning\nflag output for each compile job when not using GCC.\nThis commit adds a makefile macro to check for supported warning flags\nand only adds them if the compiler actually supports them.\n" }, { "commit": "06a206f44e6295695b014fd82c18487e37d6c6e7", "tree": "27f8e1c9b53cf81acfe970fa1eb2096cb0419288", "parents": [ "82e565e232ba01b28b5dcefea0af7cdb0bbdc964" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Dec 09 11:19:20 2021 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Thu Jun 01 17:50:50 2023 -0700" }, "message": "[make] Fix linker invocation to be compatible with ld.lld\n\nThe LLD linker does not allow joined short arguments, so split -dT \u003cscript\u003e\ninto -d -T \u003cscript\u003e.\n" }, { "commit": "82e565e232ba01b28b5dcefea0af7cdb0bbdc964", "tree": "ef527c2ac6326df272868007febbda15f6d5a2ed", "parents": [ "365bb4e7a7ad8c376d5a23b06d6feac6c61c5a4d" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Dec 09 14:40:59 2021 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Thu Jun 01 17:50:50 2023 -0700" }, "message": "[arm64] Allow assembling with clang\n\nClang does not accept this .if condition since phys_offset is a register\nalias and not an absolute expression. We can keep these two instructions\nhere if the argument is zero since the result will be the same.\nAdditionally, this macro is only called once and always passes a non-zero\nargument. If more calls are added in the future and avoiding these two\ninstructions just before a loop is really important, we could use\n`.ifnc \\phys_offset,0` instead, but that looks rather obscure to me.\n" }, { "commit": "365bb4e7a7ad8c376d5a23b06d6feac6c61c5a4d", "tree": "b8a750779ce472abc78ad970b931854767a09492", "parents": [ "e40ac2a883ffcb2a17e93bfed95266321a309ea1" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Dec 09 14:35:37 2021 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Thu Jun 01 17:50:50 2023 -0700" }, "message": "[clang][compiler.h] Expose a few more macros for Clang\n\nClang sets the defines for GCC 4.2.1, so we have to check __clang__ for\nthese macros in addition to the GCC version.\n" }, { "commit": "e40ac2a883ffcb2a17e93bfed95266321a309ea1", "tree": "a18c524be58c5d5aa12efc55ed25b1c3f4cf1695", "parents": [ "28c615456c4bff815db20351790e42334ac89201" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Dec 09 11:02:59 2021 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Thu Jun 01 17:50:50 2023 -0700" }, "message": "[clang] Avoid a nested function in heap_wrapper.c\n\nThis GCC extension is not supported by clang and in this case is not\nnecessary. Move the function to the top level to avoid the syntax error.\n" }, { "commit": "28c615456c4bff815db20351790e42334ac89201", "tree": "8619ba96f44248a796a9f6393aa4e8861cb2f9ab", "parents": [ "b8e102ecb79b3a12c602d33f0cf5a41429533691" ], "author": { "name": "Akansh", "email": "7958962+AkanshDivker@users.noreply.github.com", "time": "Sat Jan 14 03:14:54 2023 -0500" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Thu Jun 01 12:43:56 2023 -0700" }, "message": "Fix CVE-2004-0230\n\nApplied patch for CVE-2004-0230 in tcp_in.c which prevents RST Spoofing Attack (Denial of Service).\n" }, { "commit": "b8e102ecb79b3a12c602d33f0cf5a41429533691", "tree": "ad821503eaa39a5c107cc4b9693e1af4072e16a6", "parents": [ "08111d4a37d72f7ae965a81095f7cbe30c7e9034" ], "author": { "name": "Aaron Odell", "email": "aaronodell@google.com", "time": "Tue Apr 04 22:14:32 2023 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Thu Jun 01 12:40:55 2023 -0700" }, "message": "[kernel][thread] Track per-thread scheduling statistics\n\nTrack per-thread runtime, last scheduled time, and count of times\nscheduled. Query via existing threadstats CLI.\n" }, { "commit": "08111d4a37d72f7ae965a81095f7cbe30c7e9034", "tree": "cbbd9903559b3a0a0e3a01259607aea8fa5ae78a", "parents": [ "957b9033fbe6a8f384a30f0b3d261442344e27e4" ], "author": { "name": "Aaron Odell", "email": "aaronodell@google.com", "time": "Tue Apr 04 20:38:32 2023 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Thu Jun 01 12:40:55 2023 -0700" }, "message": "[arch][arm-m][systick] Update for monotonicity\n\nUpdate arm-m systick current_time() and current_time_hires() to advance\nmonotonically even when interrupts are disabled.\n\nPrevious implementation relied on the systick exception triggering\nimmediately when the counter wrapped and incrementing the current_ticks\ncount. But if called when interrutps are disabled, then the systick has\nnot had a chance to trigger and increment the count, but the counter has\nalready wrapped around. This would result in the current_time() value\nmoving backwards.\n\nThe implementation in this commit is as follows:\n- Access to the systick val csr is always done in conjunction with a\n check of the COUNTFLAG bit, which indicates counter reaching zero.\n- The global current_ticks count is incremented immediately when\n wrap around is detected via COUNTFLAG, rather than waiting for the\n systick exception to run.\n- The check of the counter value, COUNTFLAG bit, and current_ticks\n global count are always done in a critical section to avoid race\n conditions between current_time and the systick handler.\n- The critical section and workarounds are consolidated into a helper\n function shared by current_time() and current_time_hires() to\n atomically get the tick count and the cycles since the last tick.\n\nThe effect should be that current_time() always returns an accurate\nmonotonically increasing value, regardless of interrupt enablement\nor not.\n" }, { "commit": "957b9033fbe6a8f384a30f0b3d261442344e27e4", "tree": "0bc426f72b52f644781271432659c398d3f63c00", "parents": [ "67a5104d23532380350f6c4079205382f9caa657" ], "author": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Thu Jun 01 12:17:37 2023 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Thu Jun 01 12:17:37 2023 -0700" }, "message": "[scripts][python] Move a few more scripts from python2 to python3\n\nTurns out they were already python3 safe, so just switch to requested\nversion over.\n" }, { "commit": "67a5104d23532380350f6c4079205382f9caa657", "tree": "df844f76b88dc670eb8b6cd8b966bd5cf0dbbaba", "parents": [ "431e409c7861baf0a37a380474f58db614ff2aa8" ], "author": { "name": "Pedro Falcato", "email": "pedro.falcato@gmail.com", "time": "Sun May 21 00:01:07 2023 +0100" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Sat May 20 17:46:24 2023 -0700" }, "message": "[arch][x86] Change the cache line size to 64 bytes\n\nAll remotely modern x86 CPUs use 64-byte cache lines. Change CACHE_LINE\nto reflect this.\n" }, { "commit": "431e409c7861baf0a37a380474f58db614ff2aa8", "tree": "7c3cb356b8351f5e2a62717afc6a3ea9672c227c", "parents": [ "9165714702beaae435f22f7ed54fa52addb36e49" ], "author": { "name": "Aaron Odell", "email": "aaronodell@google.com", "time": "Tue Apr 04 22:53:03 2023 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Apr 23 17:37:18 2023 -0700" }, "message": "[arch][arm-m] Add Cortex M55 support\n\nAdd the Cortex M55 as a supported target.\n" }, { "commit": "9165714702beaae435f22f7ed54fa52addb36e49", "tree": "fb5358ba65ac0c78e21109ff6b7055013480d342", "parents": [ "8fc673fe4a7a5d9f28077e6353621cf99fa6fd62" ], "author": { "name": "Aaron Odell", "email": "aaronodell@google.com", "time": "Tue Apr 04 21:30:57 2023 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Apr 23 17:35:03 2023 -0700" }, "message": "[inc][utils] Add a utils.h for miscellaneous helpers\n\nAdd a utils.h file containing miscellaneous convenience helpers.\n" }, { "commit": "8fc673fe4a7a5d9f28077e6353621cf99fa6fd62", "tree": "b171101d084118166fac68ed51c2691fdde43b89", "parents": [ "9ba1f165cdf947e443431a999d1943dbb94ba48e" ], "author": { "name": "Aaron Odell", "email": "aaronodell@google.com", "time": "Tue Apr 04 21:05:57 2023 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Apr 23 17:34:57 2023 -0700" }, "message": "[lib][debugcommands] Add panic command\n\nAdd a simple command to generate a test panic.\n" }, { "commit": "9ba1f165cdf947e443431a999d1943dbb94ba48e", "tree": "064f66b1a255a2d6b87dab7e2bdd998ebce2b8c4", "parents": [ "9ac5708eb5d1820efd5ace3871300b100cb6ea05" ], "author": { "name": "Aaron Odell", "email": "aaronodell@google.com", "time": "Tue Apr 04 19:18:58 2023 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Apr 23 17:34:54 2023 -0700" }, "message": "[libc][string] Add strcasecmp support\n\nAdd strcasecmp() for case insensitive string compares. There is no ISO\nstandard function for this purpose but strcasecmp() is POSIX standard.\n" }, { "commit": "9ac5708eb5d1820efd5ace3871300b100cb6ea05", "tree": "ace3eb032eefa096786de22d3fb666085fa540b7", "parents": [ "af844a2ff66e9ba619f024fff14b20c59116568a" ], "author": { "name": "Aaron Odell", "email": "aaronodell@google.com", "time": "Fri Mar 24 18:42:40 2023 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Apr 23 17:34:51 2023 -0700" }, "message": "[lib][debugcommands] Add commands to display current time\n\nAdd debug commands \"time\" and \"timeh\" to display current_time() and\ncurrent_time_hires() respectively.\n" }, { "commit": "af844a2ff66e9ba619f024fff14b20c59116568a", "tree": "a96b8b5a3516c16f239555d6c8837061539c27ed", "parents": [ "47c8b9a711cd595a4e25d0167edb859554d18d25" ], "author": { "name": "Aaron Odell", "email": "aaronodell@google.com", "time": "Fri Mar 24 18:23:47 2023 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Apr 23 17:34:49 2023 -0700" }, "message": "[lib][console] Add an unsigned long long to console_cmd_args\n\nAdd and populate an unsigned long long element in the console_cmd_args\nstruct. This enables handling of 64 bit values on 32 bit targets.\n" }, { "commit": "47c8b9a711cd595a4e25d0167edb859554d18d25", "tree": "9813205910c6fd0804da763ddc935cf3b1850358", "parents": [ "6bbdcd5a0936d5a24394c102dd3109564edf312c" ], "author": { "name": "Aaron Odell", "email": "aaronodell@google.com", "time": "Tue Apr 04 15:46:11 2023 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Apr 23 17:34:45 2023 -0700" }, "message": "[scripts][buildall] Propogate logged error status through pipe tee\n\nIn the non-QUIET case, the log function pipes output to the tee command.\nWithout the pipefail option, if a make command fails, but the tee exits\nsuccesfully, the overall status is 0 and the failed project doesn\u0027t get\nadded to the FAILED list and reported. Adding the pipefail option\npropagates the make failure appropriately and adds the target to the\nFAILED list.\n" }, { "commit": "6bbdcd5a0936d5a24394c102dd3109564edf312c", "tree": "5a9224423f53d1b39739778c638d4e923c09cb44", "parents": [ "6b29ec9223d6237005a55b41db0255b90cfe59b4" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Dec 09 10:04:15 2021 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Sun Apr 23 17:23:31 2023 -0700" }, "message": "[arm64][clang] Silence a register size mismatch warning\n\nEven though we only need 32 bits here, clang warns that we should be\nusing a \"w\" register in the inline assembly (which is not legal with\nmrs/msr). Silence the warning by declaring the value as unsigned long.\n\n(cherry picked from commit a0de5d88dfc67b3ba34c0455b1619e12e6cfccae)\n" }, { "commit": "6b29ec9223d6237005a55b41db0255b90cfe59b4", "tree": "1d6669447e28dc14ea70deffca1fddf148e667df", "parents": [ "b8ae41a295cffd3fa96293a7ec12547df714ab28" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Fri Mar 10 14:27:01 2023 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Sun Apr 23 17:23:31 2023 -0700" }, "message": "[clang] Silence unused private member warning\n\nWe could also remove this variable, but it seems best to keep it to\nretain the same struct layout.\n" }, { "commit": "b8ae41a295cffd3fa96293a7ec12547df714ab28", "tree": "8c392b0b812dd19e10d099c593a53cce0bff8466", "parents": [ "8f3537d7b89ea3c14016b8a49f5b9ac620bdab4b" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Fri Mar 10 14:25:00 2023 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Sun Apr 23 17:23:31 2023 -0700" }, "message": "[float_test_vec] Fix -Wdouble-promotion warnings\n" }, { "commit": "8f3537d7b89ea3c14016b8a49f5b9ac620bdab4b", "tree": "e4e945649288c562d697dd5fc7dbc483ca578127", "parents": [ "00f7060ba990ed991b7653d9f643d53f6ab02ce8" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Fri Mar 10 14:24:13 2023 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Sun Apr 23 17:23:31 2023 -0700" }, "message": "[benchmarks] Fix -Wdouble-promotion warnings\n" }, { "commit": "00f7060ba990ed991b7653d9f643d53f6ab02ce8", "tree": "4096ff316263b61ae531d9e13180ad89880b3d8a", "parents": [ "99bf8f9c412aeef08255899efc55c24a3eac3c5e" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Fri Mar 10 14:23:46 2023 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Sun Apr 23 17:23:31 2023 -0700" }, "message": "[benchmarks] Use volatile variables in bench_sincos\n\nIn addition to fixing -Wdouble-promition issues in bench_sincos, this also\nensures that the compiler can\u0027t replace the calls to sin/cos/sqrt with a\ncompile-time constant.\n" }, { "commit": "99bf8f9c412aeef08255899efc55c24a3eac3c5e", "tree": "931421c05a437ded29bde5e91f3073f554e379e5", "parents": [ "7c7612225aeb8c7d95a2fd0c117537b1ffab5d16" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Fri Mar 10 14:17:23 2023 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Sun Apr 23 17:23:31 2023 -0700" }, "message": "[clang] Fix -Wformat warnings\n\nUse %hx for uint16_t instead of %hhx.\n" }, { "commit": "7c7612225aeb8c7d95a2fd0c117537b1ffab5d16", "tree": "e7e8e351755dffaa98185a160228a5194a00799a", "parents": [ "7b12b201fde1b2abd526aeea138fb932b79c631b" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Dec 09 14:31:38 2021 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Sun Apr 23 17:23:31 2023 -0700" }, "message": "[libc] Fix -Wincompatible-library-redeclaration for strerror\n\nReturn a char * instead of a const char * to silence this Clang warning.\n" }, { "commit": "7b12b201fde1b2abd526aeea138fb932b79c631b", "tree": "5b786f97882fe95541e0c602a48b654389ecbb6e", "parents": [ "a1eb850079f4059ee0c22a7da07c473a423ec1c1" ], "author": { "name": "Alex Richardson", "email": "alexrichardson@google.com", "time": "Thu Dec 09 14:37:45 2021 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Sun Apr 23 17:23:31 2023 -0700" }, "message": "[dlmalloc] Fix -Wnull-pointer-arithmetic\n\nArithmetic on a NULL pointer is undefined behaviour and could be used by\nthe compiler to optimize out the arithmetic. Use the integer expansion of\nchunk2mem(0) instead to silence this warning:\n`arithmetic on a null pointer treated as a cast from integer to pointer is a GNU extension [-Wnull-pointer-arithmetic]`\n" }, { "commit": "a1eb850079f4059ee0c22a7da07c473a423ec1c1", "tree": "f7048a9228ef580150c9b7c91797235126768f27", "parents": [ "7c2c8d8e564bdd9f5026cc2d986f9aaecf703de5" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Thu Mar 09 23:20:18 2023 -0800" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Thu Mar 09 23:20:18 2023 -0800" }, "message": "[target][visionfive2] set the time base properly\n\nSeems to be running at 4Mhz according to the device tree.\n" }, { "commit": "7c2c8d8e564bdd9f5026cc2d986f9aaecf703de5", "tree": "34eb2ead5068a981e4f0621caeb318d49e92e360", "parents": [ "c66ad44efae39a386da42f2ca2952cf7f32104c6" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Thu Mar 09 23:09:32 2023 -0800" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Thu Mar 09 23:09:32 2023 -0800" }, "message": "[dev][interrupt][riscv_plic] merge now 3 implementations of the same plic driver into one\n\nMove a copy of the PLIC driver out of one of the platforms and make the\nsetup of the interrupt controller a bit more dynamic.\n" }, { "commit": "c66ad44efae39a386da42f2ca2952cf7f32104c6", "tree": "9e6e207ea94beb16c9982138b28556acf3e45e44", "parents": [ "ca633e2cb2e8029cc0312829a39ef6b1c31b65f1" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Mon Mar 06 01:06:27 2023 -0800" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Mon Mar 06 01:06:27 2023 -0800" }, "message": "WIP [target][visionfive2] Add initial support for a VisionFive 2 RISC-V board\n\nStill TODO:\n-Set the timer rate properly\n-Fix nonzero based hart secondary cpu boot\n-Try to parse the device tree for some information\n" }, { "commit": "ca633e2cb2e8029cc0312829a39ef6b1c31b65f1", "tree": "5c325e7656bf317c5940a873a1f10c94c0789e19", "parents": [ "36fd884faae0216a7a683257f785c3d0de51f1ee" ], "author": { "name": "Pedro Falcato", "email": "pedro.falcato@gmail.com", "time": "Sun Feb 19 02:13:17 2023 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Sat Feb 18 23:13:23 2023 -0800" }, "message": "[ubsan] Improve printing of value in shift_out_of_bounds\n\nPrint it according to the type information we\u0027re given.\n" }, { "commit": "36fd884faae0216a7a683257f785c3d0de51f1ee", "tree": "be58d0f7d3791524440c5d818e8fddf90ecf818c", "parents": [ "34d1bf4e42fadbf1e3c16ebdc34786882661e961" ], "author": { "name": "Pedro Falcato", "email": "pedro.falcato@gmail.com", "time": "Sun Feb 19 02:08:37 2023 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Sat Feb 18 23:13:23 2023 -0800" }, "message": "[ubsan] Fix minor copy-paste bugs\n\nTwo handlers accidentally had the wrong prototype, called the wrong\nthing and/or had the wrong name.\n\nShould only affect divrem_overflow_abort, negate_overflow_abort.\n" }, { "commit": "34d1bf4e42fadbf1e3c16ebdc34786882661e961", "tree": "98d71ac20279a0d37fd5d00912912ac00f7d5eae", "parents": [ "8ebbcea5ed556dface771fdaff5af50e9a4e8ef6" ], "author": { "name": "Pedro Falcato", "email": "pedro.falcato@gmail.com", "time": "Sat Feb 18 23:50:59 2023 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Sat Feb 18 16:47:16 2023 -0800" }, "message": "[github][CI] Add UBSAN variants to CI\n" }, { "commit": "8ebbcea5ed556dface771fdaff5af50e9a4e8ef6", "tree": "6d51c09655680155ea3e9564758de263d127dd9d", "parents": [ "bf2e94c2f8ede8b409f9c5836c04de6efbface34" ], "author": { "name": "Pedro Falcato", "email": "pedro.falcato@gmail.com", "time": "Sat Feb 18 23:42:53 2023 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Sat Feb 18 16:47:16 2023 -0800" }, "message": "[ubsan] Add UBSAN implementation\n\nAdd an UBSAN implementation and a new UBSAN switch to the make build.\nThe implementation is taken from Onyx and handles most of the cases\nthat should be needed for a kernel build. Floating point and fancy\nC++ CFI features are not supported yet.\n\nTo build with UBSAN, pass UBSAN\u003d1 to make such as:\nPROJECT\u003dpc-x86-64-test make -jN UBSAN\u003d1\n" }, { "commit": "bf2e94c2f8ede8b409f9c5836c04de6efbface34", "tree": "6c3948d691cfab2c866b2ffcc1a42e25a760f73d", "parents": [ "81d6014493a3fe9f6f2bee3f8a316a95f83ee3dd" ], "author": { "name": "Pedro Falcato", "email": "pedro.falcato@gmail.com", "time": "Sat Feb 18 23:22:38 2023 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Sat Feb 18 16:47:16 2023 -0800" }, "message": "[minip] Fix undefined behavior in mac_addr_copy\n\nThere was a possibly unaligned store in mac_addr_copy.\nReplace it with a memcpy call that should generate equivalent,\nwell defined code.\n" }, { "commit": "81d6014493a3fe9f6f2bee3f8a316a95f83ee3dd", "tree": "2537365c401713bc7e8df0eb86b4697d34e518b5", "parents": [ "92505637e8608cc7330bfa82a04c71ccabe809fa" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sat Feb 18 16:39:45 2023 -0800" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sat Feb 18 16:39:45 2023 -0800" }, "message": "[arch][riscv] Add more defines and optimize fpu context switch\n\nAdd a few more #defines for the status register\nTweak the FPU context switch to not rewrite the entire status register,\n which may not be a generally safe thing to do.\n" }, { "commit": "92505637e8608cc7330bfa82a04c71ccabe809fa", "tree": "e5b26634200b70f93e7235a2c38c09162fdac23b", "parents": [ "3dd8a32e92e00f47cdecee5958f4f7121c92d917" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sat Feb 18 16:39:13 2023 -0800" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sat Feb 18 16:39:13 2023 -0800" }, "message": "[app][tests][float] generally spiff up the test\n\nStill doesn\u0027t seem to work right on some arches, will need\nto debug whats going on.\n" }, { "commit": "3dd8a32e92e00f47cdecee5958f4f7121c92d917", "tree": "931637191aec45c44d533de690cb58b8a9768523", "parents": [ "415096a2bfcc5b297dfff671c70d17bcc1023430" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sat Feb 18 14:42:59 2023 -0800" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sat Feb 18 14:42:59 2023 -0800" }, "message": "[arch][riscv] a few small tweaks\n\nUpdated comment regarding clobbers on the SBI call.\nTweak a boot time print of SBI version.\nAdd a commented out line to the do-qemuriscv to assist in dumping future\ndevice trees.\n" }, { "commit": "415096a2bfcc5b297dfff671c70d17bcc1023430", "tree": "3cadb88cd0660c228c74e0049c2d1498f0d9eda0", "parents": [ "93a8b45adad260715d924da2afa4f56dae5e0518" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Jan 15 19:02:30 2023 -0800" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Jan 15 19:02:30 2023 -0800" }, "message": "[external][lib][fdt] update libfdt to newest version\n\nUpdate libfdt from https://github.com/dgibson/dtc at revision\n73590342fc85ca207ca1e6cbc110179873a96962\n\nSource is verbatim except moving headers into an include directory added\nto the path.\n\nUsing 2-clause BSD option.\n" }, { "commit": "93a8b45adad260715d924da2afa4f56dae5e0518", "tree": "aa216ac30f007585646e09d31e57bce2e6b7138b", "parents": [ "3b4dade91fc2e604d071c756e64cf428193b312e" ], "author": { "name": "Pedro Falcato", "email": "pedro.falcato@gmail.com", "time": "Sat Dec 31 03:14:45 2022 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Sun Jan 15 18:35:49 2023 -0800" }, "message": "[bus][pci] Clarify device::assign_resource\n\nThe previous XXX comments were unnecessary as the spec defines the\nbottom 3 bits as being hardwired and read-only.\n" }, { "commit": "3b4dade91fc2e604d071c756e64cf428193b312e", "tree": "a0493e8110f0b55e70d9bf74812ec4f3d1f1da5e", "parents": [ "91d0a5f7d1eb739f2df977e05dcda96d8f470f7b" ], "author": { "name": "Pedro Falcato", "email": "pedro.falcato@gmail.com", "time": "Sat Dec 31 03:12:16 2022 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Sun Jan 15 18:35:49 2023 -0800" }, "message": "[bus][pci] Disable IO and mem decoding around BAR enumeration\n\nDisable IO and mem decoding around BAR enumation as described in the PCI\nLocal Bus specification. This behavior should be safer when messing\naround BARs for BAR lengths.\n" }, { "commit": "91d0a5f7d1eb739f2df977e05dcda96d8f470f7b", "tree": "a3d51d33b7d747a1405ee23b386d488628992340", "parents": [ "2d561b4fcf228accd74cbf085017e2daeb9adb25" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sat Dec 17 17:12:35 2022 -0800" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sat Dec 17 17:12:35 2022 -0800" }, "message": "[lib][fdtwalk] add routine to find and parse /reserved-memory node\n\nAdd logic to the riscv virt platform to properly mark off memory\nclaimed by OpenSBI.\n" }, { "commit": "2d561b4fcf228accd74cbf085017e2daeb9adb25", "tree": "da9d7ed889cec67e7a300b38e915bf63804b15f6", "parents": [ "8b1335ea7e35fe21a2ca3c40516d2561d2e73f7d" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sat Dec 17 00:49:37 2022 -0800" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sat Dec 17 00:57:37 2022 -0800" }, "message": "[platform][qemu-virt-riscv] seems the first 512K are now used by opensbi 1.1\n\nLooks like this is described in /reserved_memory/mmode_resv@\u003caddress\u003e as\npatched by opensbi on top of the existing qemu provided dtb.\n\nFuture patch should parse this instead of hard coding it.\n" }, { "commit": "8b1335ea7e35fe21a2ca3c40516d2561d2e73f7d", "tree": "637baf914ba3a473634873aa84877c4f22a7d97e", "parents": [ "bcfad2558736b123cea7fa14d7b1f05aaae1fde5" ], "author": { "name": "gvk51", "email": "vamshi.g51@gmail.com", "time": "Tue Nov 01 12:35:35 2022 +0530" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Thu Nov 03 00:04:30 2022 -0700" }, "message": "[lib][debugcommands] sanity check address is mapped before display/modify\n\nAccessing un-mapped address/address-range results in data abort. Ensure\nthe address and all the pages in the requested range are mapped. Mapping\nis checked at page size, also adjusts the stop address to the nearest valid\naddress mapped.\n" }, { "commit": "bcfad2558736b123cea7fa14d7b1f05aaae1fde5", "tree": "25535504dc4def534c91a50aff44382d1306db25", "parents": [ "7742bd021bf444833f16d0a8b6ea862b733e1c51" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Nov 02 23:48:49 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Nov 02 23:48:49 2022 -0700" }, "message": "[arch][x86][mmu] update how mmu code accesses physical pages\n\nMove the mmu_initial_mapping from platform into arch/x86. For this\narchitecture the default mappings are basically hard coded in arch/x86\nanyway, so move ownership of this data there, closer to where it\u0027s\nactually initialized.\nUpdate the 32 and 64bit paging code to properly use the paddr_to_kvaddr\nand vice versa routines.\nUpdate to allocate page tables directly from the pmm instead of the heap\n(on 32bit code).\n" }, { "commit": "7742bd021bf444833f16d0a8b6ea862b733e1c51", "tree": "9cbeb8930daf0b5d22e5d99dda5596ceff05e1b0", "parents": [ "0d0568612a8113e512f83012f930bd73e878809f" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Nov 02 22:22:19 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Nov 02 23:02:24 2022 -0700" }, "message": "[arch][x86] general cleanup\n\nClean up the x86.h file a bit with how constants are defined\nSwitch rdtsc to builtin\nAdded all of the known bits for the main CR registers.\nMove the invlpg macro over to the common header.\nUpdate comments in start.S\n" }, { "commit": "0d0568612a8113e512f83012f930bd73e878809f", "tree": "b1fe9f5aff016612c10def129d89796693414e89", "parents": [ "7ddde308a3cddcd5d0f53748760dd700353e9afa" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Nov 02 02:26:06 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Nov 02 21:44:15 2022 -0700" }, "message": "[lib][acpi_lite] update to use the VMM to map acpi tables in\n\nThe old method assumed that all of the tables were mapped within the\nkmap area of the kernel. This basically works on 64bit machines but on a\n32bit x86 its entirely likely the ACPI tables are at higher physical\naddresses that can be reached, which is currently limited to 1GB.\n\nBy using the VM it means it can individually map the headers and each\nindividual table.\n" }, { "commit": "7ddde308a3cddcd5d0f53748760dd700353e9afa", "tree": "b59d013ce28f0ce5a63d8d7bae460d1f6fae3fd6", "parents": [ "b990ad7999807bcd66d930f00f302cf20ad91402" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Nov 02 02:09:46 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Nov 02 02:09:46 2022 -0700" }, "message": "[arch][x86][mmu] fix unmap routines to actually work\n\nalso additionally invlpg the address.\n" }, { "commit": "b990ad7999807bcd66d930f00f302cf20ad91402", "tree": "3b73536b7fae521c26188e45706d91c43dd2cbcc", "parents": [ "236768685463df9a9580377b96eec21abb63be9d" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Nov 02 00:28:36 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Nov 02 00:28:36 2022 -0700" }, "message": "[dev][net][e1000] just added a few comments with device ids\n\nWas fiddling with making it work on i219 based e1000s, which was not\neasily fruitful. However, may as well check in some comments with some\nids.\n" }, { "commit": "236768685463df9a9580377b96eec21abb63be9d", "tree": "d22e7de9f6a878d7cb5282ea6b3ae0b5fb5fb8ef", "parents": [ "4ce2e6a35d3bcb4495b9b54c76c8a4f0e4678b64" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 23 23:16:48 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 23 23:16:48 2022 -0700" }, "message": "[make] add a way for a module to opt into additional warnings\n\nMove -Wmissing-declarations and -Wmissing-prototypes into this bucket.\nOpt in most of the core top level modules in the system. More to follow.\n" }, { "commit": "4ce2e6a35d3bcb4495b9b54c76c8a4f0e4678b64", "tree": "b7cfc7b03a7050c004f0f2e488c471e8c5cc5ae1", "parents": [ "7017a8fff9cba27843ba96cfb583af642dd3bc60" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 23 22:58:24 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 23 23:03:17 2022 -0700" }, "message": "[libc] fix a warning squelch for some locally defined routines\n" }, { "commit": "7017a8fff9cba27843ba96cfb583af642dd3bc60", "tree": "33dcfbcf1066e704d5d3eab72d26df981bd5ab00", "parents": [ "550256d6bca5c23d76f4bfea1c798704bee656ab" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 23 22:40:00 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 23 22:40:00 2022 -0700" }, "message": "[arch][mmu] add another routine to query if the arch supports user aspaces\n\nTrim the arch mmu unit tests accordingly.\n\nShould probably switch this to a #define, but it\u0027s possible some of\nthese queries could be dynamically detected (XN for example). May\nrevisit at some point.\n" }, { "commit": "550256d6bca5c23d76f4bfea1c798704bee656ab", "tree": "811eac6543d6fb2241ef0079f52abf8203466668", "parents": [ "ee880bad58ae0f28c156e630b640c1daa9d45f5e" ], "author": { "name": "Chintan Pandya", "email": "chintanpandya@google.com", "time": "Wed Sep 14 11:33:01 2022 +0000" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 23 21:40:18 2022 -0700" }, "message": "kernel: vm: Fix incorrect argument passing in \u0027vm map\u0027 test\n\nvm map takes arg 3 as virtual address. And same needs\nto be passed to retrieve aspace. Fix this by passing\nright arg.\n\nTest: Ran \u0027vm map\u0027 test\n ] vm map 0xc0000000 0xffff000ff0000000 1 0x0\n arch_mmu_map returns 0\n\nSigned-off-by: Chintan Pandya \u003cchintanpandya@google.com\u003e\n" }, { "commit": "ee880bad58ae0f28c156e630b640c1daa9d45f5e", "tree": "0aa5d6443ca4207730e3ae6993f26ab19d9e06db", "parents": [ "45e864d0c6df415f079f9a72bd5af1d86347673a" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 23 21:26:04 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 23 21:26:04 2022 -0700" }, "message": "[ci][gcc] update main toolchain to gcc 12.2.0\n" }, { "commit": "45e864d0c6df415f079f9a72bd5af1d86347673a", "tree": "9570ebc9c8204168107981aa0bdaf5acef2bf9d4", "parents": [ "8cc5b06eebe282b9c11eea0c2898a2109d82a42d" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 23 21:20:15 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 23 21:25:12 2022 -0700" }, "message": "[ci] update github cache to v3\n" }, { "commit": "8cc5b06eebe282b9c11eea0c2898a2109d82a42d", "tree": "cd9a62fb8e14ee0c024d3c3700199f143d1e5f2d", "parents": [ "5377fcbd121c1a3a6420a46d5505eb26c21578db" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 23 21:21:16 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 23 21:25:12 2022 -0700" }, "message": "[ci] update github checkout action to v3\n" }, { "commit": "5377fcbd121c1a3a6420a46d5505eb26c21578db", "tree": "277fc95188982722f181806a36a63febf75cf764", "parents": [ "2e81bfd55f25d2ed48a9061338fc777e81a07a5a" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Fri Oct 21 22:34:38 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 23 21:02:22 2022 -0700" }, "message": "[kernel][vm] add error handling with failed arch mmu mappings\n\nIn the 3 places in the upper VMM where it calls arch_mmu_map, try to\ngracefully handle errors by unwinding the region creation.\n" }, { "commit": "2e81bfd55f25d2ed48a9061338fc777e81a07a5a", "tree": "4fc600948a571176e3b54f56e11cb971eaf22336", "parents": [ "08b32389528a15e8ae5115d0081b73d919791e91" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 23 20:59:53 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 23 21:00:15 2022 -0700" }, "message": "[arch][x86] remove an extra printf left in the x86 mmu code\n" }, { "commit": "08b32389528a15e8ae5115d0081b73d919791e91", "tree": "c8546634561d9c1ac43a5e5e450c143774447d4b", "parents": [ "611bd1cba04602d5d7b807e1d80b13e994d80653" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Fri Oct 21 01:37:01 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Sun Oct 23 20:37:33 2022 -0700" }, "message": "[arch][x86] clean up of mmu code\n\n-Large cleanup of both the 32 and 64bit mmu code. Still the same general\nflow but tighten up usage of mixing physical addresses with virtual\naddresses.\n-Remove the PAE code path from 32bit mmu, which was unused.\n" }, { "commit": "611bd1cba04602d5d7b807e1d80b13e994d80653", "tree": "894bbb92f975fe09aa952bc4244b18d23653f757", "parents": [ "3a6b43cb320cdff0fcaac200be820f6e9a490a32" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Fri Oct 21 23:45:42 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Fri Oct 21 23:47:47 2022 -0700" }, "message": "[bus][pci] ask for 4MB alignment when mapping the ecam\n\nThis helps any architecture that might have a better chance with using\nlarge pages.\n" }, { "commit": "3a6b43cb320cdff0fcaac200be820f6e9a490a32", "tree": "c9a9587fbad6b1a571df3df5f7681aa7d8a8711d", "parents": [ "d5451cc8e6d4b5457be7d78a25c4743200a4afd6" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Fri Oct 21 01:35:28 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Fri Oct 21 01:35:28 2022 -0700" }, "message": "[arch][mmu][tests] slight tweaks\n" }, { "commit": "d5451cc8e6d4b5457be7d78a25c4743200a4afd6", "tree": "21d3904d3cfb8ece0311a1dfaacf67d84c4239b3", "parents": [ "f1dad5f4c82f24f496b4cf76327eb26ecb3967dd" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Fri Oct 21 00:00:49 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Fri Oct 21 00:00:49 2022 -0700" }, "message": "[arch][tests] add a way to query some arch mmu features\n\nAllow asking the arch layer if it supports NX pages or NS pages.\nHave the arch mmu test code test accordingly.\nAlso tweak the tests to pass on arm32 mmu, which does not precisely\nmatch the return semantics of the rest of the mmu routines on map/unmap.\n" }, { "commit": "f1dad5f4c82f24f496b4cf76327eb26ecb3967dd", "tree": "aac124a225775e364ecf23c41d2e765a58d98ce9", "parents": [ "0b5202362d8b820152d737e6d8d189d27924d680" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Thu Oct 20 23:26:45 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Thu Oct 20 23:26:45 2022 -0700" }, "message": "[arch][mmu] remove arch_mmu_disable which is currently unused\n" }, { "commit": "0b5202362d8b820152d737e6d8d189d27924d680", "tree": "43784aa08f1b4750d4026b503f3ea48b1d5bd80f", "parents": [ "f6a2610aef078a90a3e13b8267ec5e664e6b4792" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Thu Oct 20 23:24:02 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Thu Oct 20 23:24:33 2022 -0700" }, "message": "[arch][mmu][test] change the arch mmu test file to c++\n\nThis lets us more easily use some C++ for test cleanup.\nUpdated the arch mmu flags to be explicitly unsigned to make C++\nhappier.\n" }, { "commit": "f6a2610aef078a90a3e13b8267ec5e664e6b4792", "tree": "51a9b2c16c4d82e943183ea89108d4a5ee8bd6c3", "parents": [ "d36f5ab8d8c76213c6a994bc4fd8564118e5e60d" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Oct 19 21:02:06 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Oct 19 21:02:06 2022 -0700" }, "message": "[arch][mmu][test] update a few of the expects to asserts in these tests\n\nIn a few places where it\u0027s dangerous to proceed, raise to an assert so the\ntest stops.\n" }, { "commit": "d36f5ab8d8c76213c6a994bc4fd8564118e5e60d", "tree": "f981bad651908e3ab1ae0641a4e5dd24aed4093d", "parents": [ "318673348ff69eee9d090af4e1121048be83e2a5" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Oct 19 20:58:32 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Oct 19 20:58:32 2022 -0700" }, "message": "[arch][x86] fix a bug in the unmap routine on 32bit mmu code\n\nWas apparently already fixed on the 64bit side, but never rolled back.\n" }, { "commit": "318673348ff69eee9d090af4e1121048be83e2a5", "tree": "c02dfe0e3d0dddf82073397aaa95a7cc595eb947", "parents": [ "b7d721503058eefca399bac72ef12a76c8187058" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Oct 19 20:22:10 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Oct 19 20:22:10 2022 -0700" }, "message": "[arch][x86][32] fix a bug in the exception report\n\nSome of the 16 bit values the cpu pushes on the stack are aligned to\n32bit offsets but actually only 16 bits were pushed. Make sure printf\nmasks off the top 16 bits when printing these fields out.\n" }, { "commit": "b7d721503058eefca399bac72ef12a76c8187058", "tree": "6de76b02d4e99f9056df6cf79f4ef238c93bcd93", "parents": [ "77d8622268212bfb51831d2f6f8295ae38524b27" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Oct 19 20:16:06 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Oct 19 20:17:05 2022 -0700" }, "message": "[arch][x86][fpu] clean up the fpu init code to print info later\n" }, { "commit": "77d8622268212bfb51831d2f6f8295ae38524b27", "tree": "bcdebbfd00b977fcb5e572c9f2cc8bdf35f95f25", "parents": [ "2ac68a56a817d3d6744eaa90edf109c00f358371" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Oct 19 19:57:39 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Oct 19 20:03:49 2022 -0700" }, "message": "[arch][x86] clean up a bit of the cpuid detection\n\nSave the model/family information in a new structure.\nMove the printing portion of the detection to the arch_init runtime\nso it gets a chance to print after the uart is initialized.\n" }, { "commit": "2ac68a56a817d3d6744eaa90edf109c00f358371", "tree": "a84882bfa1d93b8b8941141b13668b3786d29c6e", "parents": [ "96231b132f3b52cb8579e04429a10cea443f63a3" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Oct 19 19:27:57 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Oct 19 19:27:57 2022 -0700" }, "message": "[arch][x86] no need to \"memory\" clobber simple in instructions\n\nThey only read data into the eax register instead of memory.\n" }, { "commit": "96231b132f3b52cb8579e04429a10cea443f63a3", "tree": "8e6fe1acd5294b2682cf5b8d6bab2b8838fc1136", "parents": [ "208bae5feb2d4a3ee4115475ad01b66dc8a214a2" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Oct 19 00:21:57 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Wed Oct 19 00:24:10 2022 -0700" }, "message": "[bus][pci] make the pci bus dump on bootup use a little less horizontal space\n\nShould fit better on an 80 column display\n" }, { "commit": "208bae5feb2d4a3ee4115475ad01b66dc8a214a2", "tree": "d04318b0d319dbc3bc71a9dbdb5c294aec989e31", "parents": [ "3a6c4aed8f2a74c5167f5b3732837dbf6a727251" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Tue Oct 18 23:59:15 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Tue Oct 18 23:59:15 2022 -0700" }, "message": "[scripts][do-qemux86] use the older \u0027pc\u0027 machine model when selecting x86-32\n\nThis gets a bit more coverage of hardware. In general if using 32bit LK\nit\u0027s for running on older hardware anyway.\n" }, { "commit": "3a6c4aed8f2a74c5167f5b3732837dbf6a727251", "tree": "8150b2b20323ae91b07d1f8832aa25308be3d086", "parents": [ "5f9e6fdefc6a05655157b1f6d2e2a12fde614254" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Tue Oct 18 23:58:18 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Tue Oct 18 23:58:18 2022 -0700" }, "message": "[bus][pci] do not automatically initialize the bus manager in pci_init_legacy\n\nThis lets the caller do any last minute resource set up before starting\nthe bus manager. Is consistent with the way pci_init_ecam() works.\n" }, { "commit": "5f9e6fdefc6a05655157b1f6d2e2a12fde614254", "tree": "33e364f89fc09e4327e006cc2487669113b0dfeb", "parents": [ "e02401e4bfff10b8779aff1dca55f7fc5a59bbd0" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Tue Oct 18 23:56:52 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Tue Oct 18 23:56:52 2022 -0700" }, "message": "[arch][x86][cpuid] clamp number of cpuid entries to read at boot\n\nMake sure we only read up to the max amount of cpuid values we have\npreallocated in our static array.\n" }, { "commit": "e02401e4bfff10b8779aff1dca55f7fc5a59bbd0", "tree": "cefe147cb7402860a827eceea55879d871abd5be", "parents": [ "165f826ca3400c0ff83b4c641752c1b4846ea7e4" ], "author": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Tue Oct 18 23:07:32 2022 -0700" }, "committer": { "name": "Travis Geiselbrecht", "email": "geist@foobox.com", "time": "Tue Oct 18 23:07:32 2022 -0700" }, "message": "[arch][x86] fix up some in instruction macros\n\nTurns out all of the in and rep ins/outs instruction macros have been wrong\nsince they were first added.\n\n-Make sure they clobber memory\n-Make sure edi/esi/ecx registers are marked as both read and written by\nthe instruction.\n\nThe latter was causing a codegen problem in the ide driver where the\npointer was pushed forward by a rep ins but the compiler didn\u0027t know the\nregister was modified.\n" }, { "commit": "165f826ca3400c0ff83b4c641752c1b4846ea7e4", "tree": "a3b887202a3365f36fe368d4d25bcfb27d243e12", "parents": [ "2550f205b861efd8bfa0cc0a917aa816b4ea3a19" ], "author": { "name": "Pedro Falcato", "email": "pedro.falcato@gmail.com", "time": "Thu Sep 29 03:28:27 2022 +0100" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Wed Sep 28 19:36:13 2022 -0700" }, "message": "[platform] [riscv-virt] Fix PLIC_PRIORITY macro\n\nOld PLIC_PRIORITY macro had an off-by-one bug, causing you to set the\npriority for the wrong IRQ.\n" }, { "commit": "2550f205b861efd8bfa0cc0a917aa816b4ea3a19", "tree": "97b28ac8346bcea846e170c7ad5de11341056945", "parents": [ "95ac371146939c87b938ac6bc059ac6b4adf3d7c" ], "author": { "name": "Milis Linux", "email": "15840648+milisarge@users.noreply.github.com", "time": "Tue Sep 06 23:07:51 2022 +0300" }, "committer": { "name": "Travis Geiselbrecht", "email": "travisg@gmail.com", "time": "Mon Sep 26 10:08:08 2022 -0700" }, "message": "[documentation] add a getting started guide" } ], "next": "95ac371146939c87b938ac6bc059ac6b4adf3d7c" }