| /* |
| * dts file for Hisilicon Hi6220 SoC |
| * |
| * Copyright (C) 2014, Hisilicon Ltd. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/hi6220-clock.h> |
| #include <dt-bindings/thermal/thermal.h> |
| #include <dt-bindings/pinctrl/hisi.h> |
| |
| / { |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| clocks = <&stub_clock 0>; |
| clock-names = "acpu0"; |
| clock-latency = <0>; |
| operating-points = < |
| /* kHz */ |
| 1200000 1330000 |
| 960000 1180000 |
| 729000 1090000 |
| 432000 1040000 |
| 208000 1040000 |
| >; |
| cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; |
| }; |
| cpu1: cpu@1 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x0 0x1>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; |
| }; |
| cpu2: cpu@2 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x0 0x2>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; |
| }; |
| cpu3: cpu@3 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x0 0x3>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; |
| }; |
| cpu4: cpu@4 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; |
| }; |
| cpu5: cpu@5 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x0 0x101>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; |
| }; |
| cpu6: cpu@6 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x0 0x102>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; |
| }; |
| cpu7: cpu@7 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x0 0x103>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; |
| }; |
| |
| cpu-map { |
| cluster0: cluster0 { |
| #cooling-cells = <2>; /* min followed by max */ |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| core2 { |
| cpu = <&cpu2>; |
| }; |
| core3 { |
| cpu = <&cpu3>; |
| }; |
| }; |
| cluster1: cluster1 { |
| #cooling-cells = <2>; /* min followed by max */ |
| core0 { |
| cpu = <&cpu4>; |
| }; |
| core1 { |
| cpu = <&cpu5>; |
| }; |
| core2 { |
| cpu = <&cpu6>; |
| }; |
| core3 { |
| cpu = <&cpu7>; |
| }; |
| }; |
| }; |
| |
| idle-states { |
| entry-method = "arm,psci"; |
| |
| CPU_SLEEP_0_0: cpu-sleep-0-0 { |
| compatible = "arm,idle-state"; |
| local-timer-stop; |
| arm,psci-suspend-param = <0x0010000>; |
| entry-latency-us = <250>; |
| exit-latency-us = <500>; |
| min-residency-us = <950>; |
| }; |
| |
| CLUSTER_SLEEP_0: cluster-sleep-0 { |
| compatible = "arm,idle-state"; |
| local-timer-stop; |
| arm,psci-suspend-param = <0x1010000>; |
| entry-latency-us = <600>; |
| exit-latency-us = <1100>; |
| min-residency-us = <2700>; |
| wakeup-latency-us = <1500>; |
| }; |
| }; |
| }; |
| |
| gic: interrupt-controller@f6800000 { |
| compatible = "arm,gic-400", "arm,cortex-a15-gic"; |
| reg = <0x0 0xf6801000 0x0 0x1000>, /* GICD */ |
| <0x0 0xf6802000 0x0 0x2000>, /* GICC */ |
| <0x0 0xf6804000 0x0 0x2000>, /* GICH */ |
| <0x0 0xf6806000 0x0 0x2000>; /* GICV */ |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupt-controller; |
| interrupts = <1 9 0xf04>; |
| }; |
| |
| |
| ao_ctrl: ao_ctrl { |
| compatible = "hisilicon,aoctrl", "syscon"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x0 0xf7800000 0x0 0x2000>; |
| ranges = <0 0x0 0xf7800000 0x2000>; |
| |
| clock_ao: clock0@0 { |
| compatible = "hisilicon,hi6220-clock-ao"; |
| reg = <0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| }; |
| |
| sys_ctrl: sys_ctrl { |
| compatible = "hisilicon,sysctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x0 0xf7030000 0x0 0x2000>; |
| ranges = <0 0x0 0xf7030000 0x2000>; |
| |
| clock_sys: clock1@0 { |
| compatible = "hisilicon,hi6220-clock-sys"; |
| reg = <0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| }; |
| |
| media_ctrl: media_ctrl { |
| compatible = "hisilicon,mediactrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x0 0xf4410000 0x0 0x1000>; |
| ranges = <0 0x0 0xf4410000 0x1000>; |
| |
| clock_media: clock2@0 { |
| compatible = "hisilicon,hi6220-clock-media"; |
| reg = <0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| }; |
| |
| pm_ctrl: pm_ctrl { |
| compatible = "hisilicon,pmctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x0 0xf7032000 0x0 0x1000>; |
| ranges = <0 0x0 0xf7032000 0x1000>; |
| |
| clock_power: clock3@0 { |
| compatible = "hisilicon,hi6220-clock-power"; |
| reg = <0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&gic>; |
| interrupts = <1 13 0xff08>, |
| <1 14 0xff08>, |
| <1 11 0xff08>, |
| <1 10 0xff08>; |
| }; |
| |
| reboot { |
| compatible = "syscon-reboot"; |
| regmap = <&ao_ctrl>; |
| offset = <0x10>; |
| mask = <0x48698284>; |
| }; |
| |
| acpu_ctrl: acpu_ctrl@f6504000 { |
| compatible = "hisilicon,acpuctrl"; |
| reg = <0x0 0xf6504000 0x0 0x1000>; |
| }; |
| |
| pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupts = <0 99 4>; |
| }; |
| |
| smb { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| interrupt-parent = <&gic>; |
| ranges; |
| |
| sram: sram@fff80000 { |
| compatible = "hisilicon,hi6220-sramctrl", "syscon"; |
| reg = <0x0 0xfff80000 0x0 0x12000>; |
| }; |
| |
| uart0: uart@f8015000 { /* console */ |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xf8015000 0x0 0x1000>; |
| interrupts = <0 36 4>; |
| clocks = <&clock_ao HI6220_UART0_PCLK>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| uart1: uart@f7111000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xf7111000 0x0 0x1000>; |
| interrupts = <0 37 4>; |
| reset-controller-reg = <0x330 0x334 0x338 5>; |
| clock-freq-high = <1>; |
| clocks = <&clock_sys HI6220_UART1_PCLK>; |
| clock-names = "apb_pclk"; |
| clk-enable-flag = <0>; |
| fifo-deep-size = <64>; |
| status = "disabled"; |
| }; |
| |
| uart2: uart@f7112000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xf7112000 0x0 0x1000>; |
| interrupts = <0 38 4>; |
| reset-controller-reg = <0x330 0x334 0x338 6>; |
| clocks = <&clock_sys HI6220_UART2_PCLK>; |
| clock-names = "apb_pclk"; |
| clk-enable-flag = <0>; |
| fifo-deep-size = <64>; |
| status = "disabled"; |
| }; |
| |
| uart3: uart@f7113000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xf7113000 0x0 0x1000>; |
| interrupts = <0 39 4>; |
| reset-controller-reg = <0x330 0x334 0x338 7>; |
| clocks = <&clock_sys HI6220_UART3_PCLK>; |
| clock-names = "apb_pclk"; |
| clk-enable-flag = <0>; |
| fifo-deep-size = <16>; |
| status = "disabled"; |
| }; |
| |
| uart4: uart@f7114000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xf7114000 0x0 0x1000>; |
| interrupts = <0 40 4>; |
| reset-controller-reg = <0x330 0x334 0x338 8>; |
| clocks = <&clock_sys HI6220_UART4_PCLK>; |
| clock-names = "apb_pclk"; |
| clk-enable-flag = <0>; |
| fifo-deep-size = <16>; |
| status = "disabled"; |
| }; |
| |
| rtc0: rtc@170000 { |
| compatible = "arm,pl031", "arm,primecell"; |
| reg = <0x0 0xf8003000 0x0 0x1000>; |
| interrupts = <0 12 4>; |
| clocks = <&clock_ao HI6220_RTC0_PCLK>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| dma0: dma@f7370000 { |
| compatible = "hisilicon,k3-dma-1.0"; |
| reg = <0x0 0xf7370000 0x0 0x1000>; |
| #dma-cells = <1>; |
| dma-channels = <15>; |
| dma-requests = <32>; |
| interrupts = <0 84 4>; |
| clocks = <&clock_sys HI6220_EDMAC_ACLK>; |
| dma-no-cci; |
| dma-type = "hi6220_dma"; |
| status = "ok"; |
| }; |
| |
| mailbox: mailbox { |
| #mbox-cells = <1>; |
| compatible = "hisilicon,hi6220-mbox"; |
| reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ |
| <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */ |
| interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| dual_timer0: dual_timer@f8008000 { |
| compatible = "arm,sp804", "arm,primecell"; |
| reg = <0x0 0xf8008000 0x0 0x1000>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clock_ao 31>, <&clock_ao 31>; |
| clock-names = "apb_pclk", "apb_pclk"; |
| }; |
| |
| pmx0: pinmux@f7010000 { |
| compatible = "pinctrl-single"; |
| reg = <0x0 0xf7010000 0x0 0x27c>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| #gpio-range-cells = <3>; |
| pinctrl-single,register-width = <32>; |
| pinctrl-single,function-mask = <7>; |
| pinctrl-single,gpio-range = < |
| &range 80 8 MUX_M0 /* gpio 3: [0..7] */ |
| &range 88 8 MUX_M0 /* gpio 4: [0..7] */ |
| &range 96 8 MUX_M0 /* gpio 5: [0..7] */ |
| &range 104 8 MUX_M0 /* gpio 6: [0..7] */ |
| &range 112 8 MUX_M0 /* gpio 7: [0..7] */ |
| &range 120 2 MUX_M0 /* gpio 8: [0..1] */ |
| &range 2 6 MUX_M1 /* gpio 8: [2..7] */ |
| &range 8 8 MUX_M1 /* gpio 9: [0..7] */ |
| &range 0 1 MUX_M1 /* gpio 10: [0] */ |
| &range 16 7 MUX_M1 /* gpio 10: [1..7] */ |
| &range 23 3 MUX_M1 /* gpio 11: [0..2] */ |
| &range 28 5 MUX_M1 /* gpio 11: [3..7] */ |
| &range 33 3 MUX_M1 /* gpio 12: [0..2] */ |
| &range 43 5 MUX_M1 /* gpio 12: [3..7] */ |
| &range 48 8 MUX_M1 /* gpio 13: [0..7] */ |
| &range 56 8 MUX_M1 /* gpio 14: [0..7] */ |
| &range 74 6 MUX_M1 /* gpio 15: [0..5] */ |
| &range 122 1 MUX_M1 /* gpio 15: [6] */ |
| &range 126 1 MUX_M1 /* gpio 15: [7] */ |
| &range 127 8 MUX_M1 /* gpio 16: [0..7] */ |
| &range 135 8 MUX_M1 /* gpio 17: [0..7] */ |
| &range 143 8 MUX_M1 /* gpio 18: [0..7] */ |
| &range 151 8 MUX_M1 /* gpio 19: [0..7] */ |
| >; |
| |
| range: gpio-range { |
| #pinctrl-single,gpio-range-cells = <3>; |
| }; |
| }; |
| |
| pmx1: pinmux@f7010800 { |
| compatible = "pinconf-single"; |
| reg = <0x0 0xf7010800 0x0 0x28c>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| pinctrl-single,register-width = <32>; |
| }; |
| |
| pmx2: pinmux@f8001800 { |
| compatible = "pinconf-single"; |
| reg = <0x0 0xf8001800 0x0 0x78>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| pinctrl-single,register-width = <32>; |
| }; |
| |
| gpio0: gpio@f8011000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf8011000 0x0 0x1000>; |
| interrupts = <0 52 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio1: gpio@f8012000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf8012000 0x0 0x1000>; |
| interrupts = <0 53 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio2: gpio@f8013000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf8013000 0x0 0x1000>; |
| interrupts = <0 54 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio3: gpio@f8014000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf8014000 0x0 0x1000>; |
| interrupts = <0 55 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 80 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio4: gpio@f7020000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf7020000 0x0 0x1000>; |
| interrupts = <0 56 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 88 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio5: gpio@f7021000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf7021000 0x0 0x1000>; |
| interrupts = <0 57 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 96 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio6: gpio@f7022000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf7022000 0x0 0x1000>; |
| interrupts = <0 58 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 104 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio7: gpio@f7023000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf7023000 0x0 0x1000>; |
| interrupts = <0 59 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 112 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio8: gpio@f7024000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf7024000 0x0 0x1000>; |
| interrupts = <0 60 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio9: gpio@f7025000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf7025000 0x0 0x1000>; |
| interrupts = <0 61 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 8 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio10: gpio@f7026000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf7026000 0x0 0x1000>; |
| interrupts = <0 62 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio11: gpio@f7027000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf7027000 0x0 0x1000>; |
| interrupts = <0 63 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio12: gpio@f7028000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf7028000 0x0 0x1000>; |
| interrupts = <0 64 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio13: gpio@f7029000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf7029000 0x0 0x1000>; |
| interrupts = <0 65 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 48 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio14: gpio@f702a000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf702a000 0x0 0x1000>; |
| interrupts = <0 66 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 56 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio15: gpio@f702b000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf702b000 0x0 0x1000>; |
| interrupts = <0 67 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = < |
| &pmx0 0 74 6 |
| &pmx0 6 122 1 |
| &pmx0 7 126 1 |
| >; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio16: gpio@f702c000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf702c000 0x0 0x1000>; |
| interrupts = <0 68 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 127 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio17: gpio@f702d000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf702d000 0x0 0x1000>; |
| interrupts = <0 69 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 135 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio18: gpio@f702e000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf702e000 0x0 0x1000>; |
| interrupts = <0 70 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 143 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| gpio19: gpio@f702f000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x0 0xf702f000 0x0 0x1000>; |
| interrupts = <0 71 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pmx0 0 151 8>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&clock_ao HI6220_CLK_TCXO>; |
| clock-names = "apb_pclk"; |
| status = "ok"; |
| }; |
| |
| i2c2: i2c@f7102000 { |
| compatible = "snps,designware-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0xf7102000 0x0 0x1000>; |
| interrupts = <0 46 4>; |
| |
| clocks = <&clock_sys HI6220_I2C2_CLK>; |
| clock-names = "clk_i2c2"; |
| i2c-sda-hold-time-ns = <300>; |
| delay-reg = <0x0 0x0f8 0x0 4>; |
| reset-controller-reg = <0x330 0x334 0x338 3>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; |
| status = "ok"; |
| |
| adv7533: adv7533@39 { |
| compatible = "adi,adv7533"; |
| reg = <0x39>; |
| interrupt-parent = <&gpio1>; |
| interrupts = <1 2>; |
| pd-gpio = <&gpio0 4 0>; |
| adi,input-depth = <8>; |
| adi,input-colorspace = "rgb"; |
| adi,input-clock = "1x"; |
| adi,clock-delay = <0>; |
| adi,embedded-sync; |
| }; |
| }; |
| |
| spi_0: spi@f7106000 { |
| compatible = "arm,pl022", "arm,primecell"; |
| reg = <0x0 0xf7106000 0x0 0x1000>; |
| interrupts = <0 50 4>; |
| bus-id = <0>; |
| enable-dma = <1>; |
| dmas = <&dma0 12 &dma0 13>; |
| dma-names = "rx", "tx"; |
| |
| clocks = <&clock_sys HI6220_SPI_CLK>; |
| clock-names = "apb_pclk"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; |
| num-cs = <4>; |
| cs-gpios = <&gpio6 2 0>,<&gpio6 3 0>,<&gpio6 4 0>,<&gpio6 5 0>; |
| |
| status = "ok"; |
| }; |
| |
| display-subsystem { |
| compatible = "hisilicon,hi6220-drm"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| dma-coherent; |
| |
| ade: ade@f4100000 { |
| compatible = "hisilicon,hi6220-ade"; |
| reg = <0x0 0xf4100000 0x0 0x7800>, |
| <0x0 0xf4410000 0x0 0x1000>, |
| <0x0 0xf4520000 0x0 0x1000>; |
| reg-names = "ade_base", |
| "media_base", |
| "media_noc_base"; |
| |
| clocks = <&clock_media HI6220_ADE_CORE>, |
| <&clock_media HI6220_CODEC_JPEG>, |
| <&clock_media HI6220_ADE_PIX_SRC>, |
| <&clock_ao HI6220_PLL_SYS>, |
| <&clock_ao HI6220_PLL_SYS_MEDIA>; |
| /*clock name*/ |
| clock-names = "clk_ade_core", |
| "aclk_codec_jpeg_src", |
| "clk_ade_pix", |
| "clk_syspll_src", |
| "clk_medpll_src"; |
| interrupts = <0 114 4>, <0 115 4>; |
| /*ade core clock rate*/ |
| ade_core_clk_rate = <360000000>; |
| /*media_noc clock rate*/ |
| media_noc_clk_rate = <288000000>; |
| }; |
| |
| dsi { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "hisilicon,hi6220-dsi"; |
| reg = <0x0 0xf4107800 0x0 0x100>; |
| clocks = <&clock_media HI6220_DSI_PCLK>; |
| clock-names = "pclk_dsi"; |
| vc = <0>; |
| encoder-slave = <&adv7533>; |
| }; |
| }; |
| |
| }; |
| |
| pmic: pmic@F8000000 { |
| compatible = "hisilicon,hi6552-pmic-driver"; |
| reg = <0x0 0xf8000000 0x0 0x1000>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| pmu_irq_gpio = <&gpio_pmu_irq_n>; |
| status = "ok"; |
| ponkey:ponkey@b1{ |
| compatible = "hisilicon,hi6552-powerkey"; |
| interrupt-parent = <&pmic>; |
| interrupts = <6 0>, <5 0>, <4 0>; |
| interrupt-names = "down", "up", "hold 4s"; |
| }; |
| coul: coul@1 { |
| compatible = "hisilicon,hi6552-coul"; |
| interrupt-parent = <&pmic>; |
| interrupts = <24 0>, <25 0>, <26 0>, <27 0>; |
| interrupt-names = "cl_int_i", "cl_out_i", "cl_in_i", "vbat_int_i"; |
| battery_product_index = <0>; |
| status = "ok"; |
| }; |
| rtc: rtc@1 { |
| compatible = "hisilicon,hi6552-pmu-rtc"; |
| interrupt-parent = <&pmic>; |
| interrupts = <20 0>; |
| interrupt-names = "hi6552_pmu_rtc"; |
| board_id = <1>; |
| }; |
| ldo2: regulator@a21 { |
| compatible = "hisilicon,hi6552-regulator-pmic"; |
| regulator-name = "ldo2"; |
| regulator-min-microvolt = <2500000>; |
| regulator-max-microvolt = <3200000>; |
| hisilicon,valid-modes-mask = <0x02>; |
| hisilicon,valid-ops-mask = <0x01d>; |
| hisilicon,initial-mode = <0x02>; |
| hisilicon,regulator-type = <0x01>; |
| |
| hisilicon,off-on-delay = <120>; |
| hisilicon,ctrl-regs = <0x029 0x02a 0x02b>; |
| hisilicon,ctrl-data = <0x1 0x1>; |
| hisilicon,vset-regs = <0x072>; |
| hisilicon,vset-data = <0 0x3>; |
| hisilicon,regulator-n-vol = <8>; |
| hisilicon,vset-table = <2500000>,<2600000>,<2700000>,<2800000>,<2900000>,<3000000>,<3100000>,<3200000>; |
| hisilicon,num_consumer_supplies = <1>; |
| hisilicon,consumer-supplies = "sensor_analog"; |
| }; |
| ldo7: regulator@a26 { |
| compatible = "hisilicon,hi6552-regulator-pmic"; |
| regulator-name = "ldo7"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| hisilicon,valid-modes-mask = <0x0a>; |
| hisilicon,valid-ops-mask = <0x01d>; |
| hisilicon,initial-mode = <0x02>; |
| hisilicon,regulator-type = <0x01>; |
| |
| hisilicon,off-on-delay = <120>; |
| hisilicon,ctrl-regs = <0x029 0x02a 0x02b>; |
| hisilicon,ctrl-data = <0x6 0x1>; |
| hisilicon,vset-regs = <0x078>; |
| hisilicon,vset-data = <0 0x3>; |
| hisilicon,regulator-n-vol = <8>; |
| hisilicon,vset-table = <1800000>,<1850000>,<2850000>,<2900000>,<3000000>,<3100000>,<3200000>,<3300000>; |
| hisilicon,num_consumer_supplies = <1>; |
| hisilicon,consumer-supplies = "sd_card_io"; |
| }; |
| ldo10: regulator@a29 { |
| compatible = "hisilicon,hi6552-regulator-pmic"; |
| regulator-name = "ldo10"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3000000>; |
| hisilicon,valid-modes-mask = <0x0a>; |
| hisilicon,valid-ops-mask = <0x01d>; |
| hisilicon,initial-mode = <0x02>; |
| hisilicon,regulator-type = <0x01>; |
| |
| hisilicon,off-on-delay = <360>; |
| hisilicon,ctrl-regs = <0x02c 0x02d 0x02e>; |
| hisilicon,ctrl-data = <0x1 0x1>; |
| hisilicon,vset-regs = <0x07b>; |
| hisilicon,vset-data = <0 0x3>; |
| hisilicon,regulator-n-vol = <8>; |
| hisilicon,vset-table = <1800000>,<1850000>,<1900000>,<2750000>,<2800000>,<2850000>,<2900000>,<3000000>; |
| hisilicon,num_consumer_supplies = <1>; |
| hisilicon,consumer-supplies = "sd_card"; |
| }; |
| ldo13: regulator@a32 { |
| compatible = "hisilicon,hi6552-regulator-pmic"; |
| regulator-name = "ldo13"; |
| regulator-min-microvolt = <1600000>; |
| regulator-max-microvolt = <1950000>; |
| hisilicon,valid-modes-mask = <0x0a>; |
| hisilicon,valid-ops-mask = <0x01d>; |
| hisilicon,initial-mode = <0x02>; |
| hisilicon,regulator-type = <0x01>; |
| |
| hisilicon,off-on-delay = <120>; |
| hisilicon,ctrl-regs = <0x02c 0x02d 0x02e>; |
| hisilicon,ctrl-data = <0x4 0x1>; |
| hisilicon,vset-regs = <0x07e>; |
| hisilicon,vset-data = <0 0x3>; |
| hisilicon,regulator-n-vol = <8>; |
| hisilicon,vset-table = <1600000>,<1650000>,<1700000>,<1750000>,<1800000>,<1850000>,<1900000>,<1950000>; |
| hisilicon,num_consumer_supplies = <3>; |
| hisilicon,consumer-supplies = "scamera_core","mcamera_io","scamera_io"; |
| }; |
| ldo14: regulator@a33 { |
| compatible = "hisilicon,hi6552-regulator-pmic"; |
| regulator-name = "ldo14"; |
| regulator-min-microvolt = <2500000>; |
| regulator-max-microvolt = <3200000>; |
| hisilicon,valid-modes-mask = <0x02>; |
| hisilicon,valid-ops-mask = <0x01d>; |
| hisilicon,initial-mode = <0x02>; |
| hisilicon,regulator-type = <0x01>; |
| |
| hisilicon,off-on-delay = <120>; |
| hisilicon,ctrl-regs = <0x02c 0x02d 0x02e>; |
| hisilicon,ctrl-data = <0x5 0x1>; |
| hisilicon,vset-regs = <0x07f>; |
| hisilicon,vset-data = <0 0x3>; |
| hisilicon,regulator-n-vol = <8>; |
| hisilicon,vset-table = <2500000>,<2600000>,<2700000>,<2800000>,<2900000>,<3000000>,<3100000>,<3200000>; |
| hisilicon,num_consumer_supplies = <3>; |
| hisilicon,consumer-supplies = "scamera_avdd","mcamera_avdd","mcamera_vcm"; |
| }; |
| ldo15: regulator@a34 { |
| compatible = "hisilicon,hi6552-regulator-pmic"; |
| regulator-name = "ldo15"; |
| regulator-min-microvolt = <1600000>; |
| regulator-max-microvolt = <1950000>; |
| regulator-boot-on; |
| regulator-always-on; |
| hisilicon,valid-modes-mask = <0x0a>; |
| hisilicon,valid-ops-mask = <0x01d>; |
| hisilicon,initial-mode = <0x02>; |
| hisilicon,regulator-type = <0x01>; |
| |
| hisilicon,off-on-delay = <120>; |
| hisilicon,ctrl-regs = <0x02c 0x02d 0x02e>; |
| hisilicon,ctrl-data = <0x6 0x1>; |
| hisilicon,vset-regs = <0x080>; |
| hisilicon,vset-data = <0 0x3>; |
| hisilicon,regulator-n-vol = <8>; |
| hisilicon,vset-table = <1600000>,<1650000>,<1700000>,<1750000>,<1800000>,<1850000>,<1900000>,<1950000>; |
| hisilicon,num_consumer_supplies = <1>; |
| hisilicon,consumer-supplies = "codec_analog"; |
| }; |
| ldo17: regulator@a36 { |
| compatible = "hisilicon,hi6552-regulator-pmic"; |
| regulator-name = "ldo17"; |
| regulator-min-microvolt = <2500000>; |
| regulator-max-microvolt = <3200000>; |
| hisilicon,valid-modes-mask = <0x02>; |
| hisilicon,valid-ops-mask = <0x01d>; |
| hisilicon,initial-mode = <0x02>; |
| hisilicon,regulator-type = <0x01>; |
| |
| hisilicon,off-on-delay = <120>; |
| hisilicon,ctrl-regs = <0x02f 0x030 0x031>; |
| hisilicon,ctrl-data = <0x0 0x1>; |
| hisilicon,vset-regs = <0x082>; |
| hisilicon,vset-data = <0 0x3>; |
| hisilicon,regulator-n-vol = <8>; |
| hisilicon,vset-table = <2500000>,<2600000>,<2700000>,<2800000>,<2900000>,<3000000>,<3100000>,<3200000>; |
| hisilicon,num_consumer_supplies = <1>; |
| hisilicon,consumer-supplies = "vibrator"; |
| }; |
| ldo19: regulator@a38 { |
| compatible = "hisilicon,hi6552-regulator-pmic"; |
| regulator-name = "ldo19"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3000000>; |
| hisilicon,valid-modes-mask = <0x0a>; |
| hisilicon,valid-ops-mask = <0x01d>; |
| hisilicon,initial-mode = <0x02>; |
| hisilicon,regulator-type = <0x01>; |
| |
| hisilicon,off-on-delay = <360>; |
| hisilicon,ctrl-regs = <0x02f 0x030 0x031>; |
| hisilicon,ctrl-data = <0x2 0x1>; |
| hisilicon,vset-regs = <0x084>; |
| hisilicon,vset-data = <0 0x3>; |
| hisilicon,regulator-n-vol = <8>; |
| hisilicon,vset-table = <1800000>,<1850000>,<1900000>,<2750000>,<2800000>,<2850000>,<2900000>,<3000000>; |
| hisilicon,num_consumer_supplies = <1>; |
| hisilicon,consumer-supplies = "emmc_vddm"; |
| }; |
| ldo21: regulator@a40 { |
| compatible = "hisilicon,hi6552-regulator-pmic"; |
| regulator-name = "ldo21"; |
| regulator-min-microvolt = <1650000>; |
| regulator-max-microvolt = <2000000>; |
| regulator-always-on; |
| hisilicon,valid-modes-mask = <0x02>; |
| hisilicon,valid-ops-mask = <0x01d>; |
| hisilicon,initial-mode = <0x02>; |
| hisilicon,regulator-type = <0x01>; |
| |
| hisilicon,off-on-delay = <120>; |
| hisilicon,ctrl-regs = <0x02f 0x030 0x031>; |
| hisilicon,ctrl-data = <0x4 0x1>; |
| hisilicon,vset-regs = <0x086>; |
| hisilicon,vset-data = <0 0x3>; |
| hisilicon,regulator-n-vol = <8>; |
| hisilicon,vset-table = <1650000>,<1700000>,<1750000>,<1800000>,<1850000>,<1900000>,<1950000>,<2000000>; |
| }; |
| ldo22: regulator@a41 { |
| compatible = "hisilicon,hi6552-regulator-pmic"; |
| regulator-name = "ldo22"; |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1200000>; |
| regulator-boot-on; |
| regulator-always-on; |
| hisilicon,valid-modes-mask = <0x02>; |
| hisilicon,valid-ops-mask = <0x01d>; |
| hisilicon,initial-mode = <0x02>; |
| hisilicon,regulator-type = <0x01>; |
| |
| hisilicon,off-on-delay = <120>; |
| hisilicon,ctrl-regs = <0x02f 0x030 0x031>; |
| hisilicon,ctrl-data = <0x5 0x1>; |
| hisilicon,vset-regs = <0x087>; |
| hisilicon,vset-data = <0 0x3>; |
| hisilicon,regulator-n-vol = <8>; |
| hisilicon,vset-table = <900000>,<1000000>,<1050000>,<1100000>,<1150000>,<1175000>,<1185000>,<1200000>; |
| hisilicon,num_consumer_supplies = <1>; |
| hisilicon,consumer-supplies = "mcamera_core"; |
| }; |
| }; |
| |
| mali:mali@f4080000 { |
| compatible = "arm,mali-450", "arm,mali-utgard"; |
| reg = <0x0 0x3f100000 0x0 0x00708000>; |
| clocks = <&clock_media HI6220_G3D_CLK>, |
| <&clock_media HI6220_G3D_PCLK>; |
| clock-names = "clk_g3d", "pclk_g3d"; |
| G3D_PD_VDD-supply = <&mtcmos1>; |
| mali_def_freq = <500>; |
| pclk_freq = <144>; |
| dfs_steps = <2>; |
| dfs_lockprf = <1>; |
| dfs_limit_max_prf = <1>; |
| dfs_profile_num = <2>; |
| dfs_profiles = <250 3 0>, <500 1 0>; |
| mali_type = <2>; |
| |
| interrupt-parent = <&gic>; |
| interrupts = <1 126 4>, /*gp*/ |
| <1 126 4>, /*gp mmu*/ |
| <1 126 4>, /*pp bc*/ |
| <1 126 4>, /*pmu*/ |
| <1 126 4>, /*pp0*/ |
| <1 126 4>, |
| <1 126 4>, /*pp1*/ |
| <1 126 4>, |
| <1 126 4>, /*pp2*/ |
| <1 126 4>, |
| <1 126 4>, /*pp4*/ |
| <1 126 4>, |
| <1 126 4>, /*pp5*/ |
| <1 126 4>, |
| <1 126 4>, /*pp6*/ |
| <1 126 4>; |
| interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP", "IRQPMU", |
| "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1", |
| "IRQPP2", "IRQPPMMU2","IRQPP4", "IRQPPMMU4", |
| "IRQPP5", "IRQPPMMU5", "IRQPP6", "IRQPPMMU6"; |
| }; |
| |
| dwmmc_0: dwmmc0@f723d000 { |
| compatible = "hisilicon,hi6220-dw-mshc"; |
| num-slots = <0x1>; |
| board-mmc-bus-clk = <0x0>; |
| cap-mmc-highspeed; |
| non-removable; |
| reg = <0x0 0xf723d000 0x0 0x1000>; |
| interrupts = <0x0 0x48 0x4>; |
| clocks = <&clock_sys HI6220_MMC0_CIUCLK>, <&clock_sys HI6220_MMC0_CLK>; |
| clock-names = "ciu", "biu"; |
| vmmc-supply = <&ldo19>; |
| }; |
| |
| dwmmc_1: dwmmc1@f723e000 { |
| compatible = "hisilicon,hi6220-dw-mshc"; |
| num-slots = <0x1>; |
| board-mmc-bus-clk = <0x0>; |
| card-detect-delay = <200>; |
| hisilicon,peripheral-syscon = <&ao_ctrl>; |
| cap-sd-highspeed; |
| sd-uhs-sdr12; |
| sd-uhs-sdr25; |
| sd-uhs-sdr50; |
| reg = <0x0 0xf723e000 0x0 0x1000>; |
| interrupts = <0x0 0x49 0x4>; |
| clocks = <&clock_sys HI6220_MMC1_CIUCLK>, <&clock_sys HI6220_MMC1_CLK>; |
| clock-names = "ciu", "biu"; |
| vqmmc-supply = <&ldo7>; |
| vmmc-supply = <&ldo10>; |
| }; |
| |
| dwmmc_2: dwmmc2@f723f000 { |
| compatible = "hisilicon,hi6220-dw-mshc"; |
| num-slots = <0x1>; |
| board-mmc-bus-clk = <0x0>; |
| reg = <0x0 0xf723f000 0x0 0x1000>; |
| interrupts = <0x0 0x4a 0x4>; |
| #address-cells = <0x1>; |
| #size-cells = <0x0>; |
| clocks = <&clock_sys HI6220_MMC2_CIUCLK>, <&clock_sys HI6220_MMC2_CLK>; |
| clock-names = "ciu", "biu"; |
| bus-width = <0x4>; |
| broken-cd; |
| ti,non-removable; |
| non-removable; |
| /* WL_EN */ |
| vmmc-supply = <&wlan_en_reg>; |
| pinctrl-names = "default", "idle"; |
| pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; |
| pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; |
| |
| wlcore: wlcore@2 { |
| compatible = "ti,wl1835"; |
| reg = <2>; /* sdio func num */ |
| /* WL_IRQ, WL_HOST_WAKE_GPIO1_3 */ |
| interrupt-parent = <&gpio1>; |
| interrupts = <3 IRQ_TYPE_EDGE_RISING>; |
| }; |
| }; |
| wlan_en_reg: fixedregulator@1 { |
| compatible = "regulator-fixed"; |
| regulator-name = "wlan-en-regulator"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| |
| /* WLAN_EN GPIO for this board - GPIO_0_5 */ |
| gpio = <&gpio0 5 0>; |
| |
| /* WLAN card specific delay */ |
| startup-delay-us = <70000>; |
| enable-active-high; |
| }; |
| |
| mtcmos { |
| compatible = "hisilicon,hi6220-mtcmos-driver"; |
| hisilicon,mtcmos-steady-us = <10>; |
| hisilicon,mtcmos-sc-on-base = <0xf7800000>; |
| hisilicon,mtcmos-acpu-on-base = <0xf65a0000>; |
| |
| mtcmos1: regulator@a1{ |
| regulator-name = "G3D_PD_VDD"; |
| regulator-compatible = "mtcmos1"; |
| hisilicon,ctrl-regs = <0x830 0x834 0x83c>; |
| hisilicon,ctrl-data = <1 0x1>; |
| }; |
| mtcmos2: regulator@a2{ |
| regulator-name = "SOC_MED"; |
| regulator-compatible = "mtcmos2"; |
| hisilicon,ctrl-regs = <0x830 0x834 0x83c>; |
| hisilicon,ctrl-data = <2 0x1>; |
| }; |
| }; |
| |
| fixed_5v_hub: regulator@0 { |
| compatible = "regulator-fixed"; |
| regulator-name = "fixed_5v_hub"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| regulator-boot-on; |
| gpio = <&gpio0 7 0>; |
| regulator-always-on; |
| }; |
| |
| peripheral_ctrl: syscon@f7030000 { |
| compatible = "syscon"; |
| reg = <0x0 0xf7030000 0x0 0x1000>; |
| }; |
| |
| usb2_phy: usbphy { |
| compatible = "hisilicon,hi6220-usb-phy"; |
| vhub-supply = <&fixed_5v_hub>; |
| huawei,gpio_vbus_det = <&gpio2 6 0>; |
| huawei,gpio_id_det = <&gpio2 5 0>; |
| hisilicon,peripheral-syscon = <&peripheral_ctrl>; |
| clocks = <&clock_sys HI6220_USBOTG_HCLK>; |
| }; |
| |
| usb: usb@f72c0000 { |
| compatible = "huawei,hisi-usb"; |
| reg = <0x0 0xf72c0000 0x0 0x40000>; |
| phys = <&usb2_phy>; |
| dr_mode = "otg"; |
| g-use-dma; |
| g-rx-fifo-size = <512>; |
| g-np-tx-fifo-size = <128>; |
| g-tx-fifo-size = <128 128 128 128 128 128>; |
| interrupts = <0 77 0x4>; |
| }; |
| |
| stub_clock: stub_clock { |
| compatible = "hisilicon,hi6220-stub-clk"; |
| hisilicon,hi6220-clk-sram = <&sram>; |
| #clock-cells = <1>; |
| mboxes = <&mailbox 1>; |
| }; |
| |
| tsensor: tsensor@0,f7030700 { |
| compatible = "hisilicon,tsensor"; |
| reg = <0x0 0xf7030700 0x0 0x1000>; |
| interrupts = <0 7 0x4>; |
| clocks = <&clock_sys HI6220_TSENSOR_CLK>; |
| clock-names = "thermal_clk"; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| thermal-zones { |
| local: local { |
| polling-delay-passive = <1000>; /* milliseconds */ |
| polling-delay = <5000>; /* milliseconds */ |
| |
| /* sensor ID */ |
| thermal-sensors = <&tsensor 0>; |
| |
| trips { |
| local_alert: local_alert { |
| temperature = <50000>; /* millicelsius */ |
| hysteresis = <2000>; /* millicelsius */ |
| type = "passive"; |
| }; |
| local_crit: local_crit { |
| temperature = <90000>; /* millicelsius */ |
| hysteresis = <2000>; /* millicelsius */ |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| /* There are currently no cooling maps because there are no cooling devices */ |
| }; |
| }; |
| |
| cls1: cls1 { |
| polling-delay-passive = <1000>; /* milliseconds */ |
| polling-delay = <5000>; /* milliseconds */ |
| |
| /* sensor ID */ |
| thermal-sensors = <&tsensor 1>; |
| |
| trips { |
| cluster1_alert: cluster1_alert { |
| temperature = <50000>; /* millicelsius */ |
| hysteresis = <2000>; /* millicelsius */ |
| type = "passive"; |
| }; |
| cluster1_crit: cluster1_crit { |
| temperature = <90000>; /* millicelsius */ |
| hysteresis = <2000>; /* millicelsius */ |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| /* There are currently no cooling maps because there are no cooling devices */ |
| }; |
| }; |
| |
| cls0: cls0 { |
| polling-delay = <1000>; |
| polling-delay-passive = <100>; |
| sustainable-power = <3325>; |
| |
| /* sensor ID */ |
| thermal-sensors = <&tsensor 2>; |
| |
| trips { |
| threshold: trip-point@0 { |
| temperature = <65000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| target: trip-point@1 { |
| temperature = <75000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&target>; |
| contribution = <1024>; |
| cooling-device = <&cluster0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| gpu: gpu { |
| polling-delay-passive = <1000>; /* milliseconds */ |
| polling-delay = <5000>; /* milliseconds */ |
| |
| /* sensor ID */ |
| thermal-sensors = <&tsensor 3>; |
| |
| trips { |
| gpu_alert: gpu_alert { |
| temperature = <50000>; /* millicelsius */ |
| hysteresis = <2000>; /* millicelsius */ |
| type = "passive"; |
| }; |
| gpu_crit: gpu_crit { |
| temperature = <90000>; /* millicelsius */ |
| hysteresis = <2000>; /* millicelsius */ |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| /* There are currently no cooling maps because there are no cooling devices */ |
| }; |
| }; |
| }; |
| }; |
