commit 2169b8455a332aa287a4eda6b15f7eec9c1873da
author YiPing Xu <xuyiping@hisilicon.com> Fri Jun 23 16:07:44 2017 +0800
committer Dmitry Shmidt <dimitrysh@google.com> Wed Jun 28 14:14:08 2017 -0700
tree 7582c7988067a74171f553b494d031ff2389e7c7
parent 81977490e432fab4cca8d222c89f13b1ad396743

dts: hi3660: add pmu dt node for hi3660

Add pmu dt node for hi3660.

Thanks for Ben Gainey suggestion for 'interrupt-affinity' binding.

Change-Id: I4760b79751636279fd5ad341429a4d16bc0afdf2
Signed-off-by: YiPing Xu <xuyiping@hisilicon.com>
Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>

arch/arm64/boot/dts/hisilicon/hi3660.dtsi

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 607a45a..d222252 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -302,6 +302,25 @@
 		clock-frequency = <1920000>;
 	};
 
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>,
+				     <&cpu1>,
+				     <&cpu2>,
+				     <&cpu3>,
+				     <&cpu4>,
+				     <&cpu5>,
+				     <&cpu6>,
+				     <&cpu7>;
+	};
 
 	/* display start */
 	framebuffer@E8600000 {