Update kernel to ab/13436313 Change-Id: Ice7adc204ccfd77e3e4e4c4f74b368271f572321
diff --git a/BUILD.bazel b/BUILD.bazel new file mode 100644 index 0000000..7cb6a23 --- /dev/null +++ b/BUILD.bazel
@@ -0,0 +1,473 @@ +# SPDX-License-Identifier: GPL-2.0-only + +load("//build/bazel_common_rules/dist:dist.bzl", "copy_to_dist_dir") +load( + "//build/kernel/kleaf:kernel.bzl", + "kernel_abi", + "kernel_build", + "kernel_build_config", + "kernel_dtstree", + "kernel_images", + "kernel_module", + "kernel_module_group", + "kernel_modules_install", + "kernel_unstripped_modules_archive", + "merged_kernel_uapi_headers", +) +load("//private/devices/google/common:constants.bzl", "PIXEL_GKI_MODULES_LIST") +load("//private/devices/google/common/kleaf:create_file.bzl", "create_file") +load(":constants.bzl", "GS201_DEVICE_MODULE_OUTS", "GS201_DTBS", "GS201_MODULE_OUTS") + +package( + default_visibility = [ + "//private/devices/google:__subpackages__", + ], +) + +kernel_build_config( + name = "build_config", + srcs = [ + # do not sort + "//common:set_kernel_dir_build_config", + "build.config.gs201", + ], +) + +kernel_dtstree( + name = "dtstree", + srcs = glob(["dts/**"]) + [ + "//private/google-modules/soc/gs:gs.dt-bindings", + ], + makefile = "dts/Makefile", +) + +create_file( + name = "kconfig_ext", + srcs = ["Kconfig.ext.gs201"], + out = "Kconfig.ext", +) + +filegroup( + name = "defconfig_fragments", + srcs = ["gs201_defconfig"], +) + +filegroup( + name = "devices_defconfig_fragments", + srcs = [ + # do not sort + ":defconfig_fragments", + "//private/devices/google/felix:felix_defconfig", + "//private/devices/google/lynx:lynx_defconfig", + "//private/devices/google/pantah:pantah_defconfig", + "//private/devices/google/tangorpro:tangorpro_defconfig", + ], +) + +filegroup( + name = "kernel_sources", + srcs = [ + # keep sorted + "//common:kernel_aarch64_sources", + "//private/google-modules/bms/misc:bms-misc.kconfig", + "//private/google-modules/display/common:common.kconfig", + "//private/google-modules/display/samsung:display.samsung.kconfig", + "//private/google-modules/fingerprint/goodix/fps_touch_handler:fps_touch_handler.kconfig", + "//private/google-modules/power/mitigation:bcl.kconfig", + "//private/google-modules/power/reset:reset.kconfig", + "//private/google-modules/radio/samsung/s5300:cpif.kconfig", + "//private/google-modules/soc/gs:gs_soc.kconfig", + "//private/google-modules/touch/common:touch.common.kconfig", + "//private/google-modules/touch/sec:sec.kconfig", + "//private/google-modules/trusty:trusty.kconfig", + ], +) + +kernel_build( + name = "kernel", + srcs = [":kernel_sources"], + outs = [ + ".config", + ] + GS201_DTBS, + base_kernel = "//common:kernel_aarch64", + build_config = ":build_config", + collect_unstripped_modules = True, + defconfig_fragments = [":devices_defconfig_fragments"], + dtstree = ":dtstree", + kconfig_ext = ":kconfig_ext", + kmi_symbol_list = "//common:android/abi_gki_aarch64_pixel", + make_goals = [ + "modules", + "dtbs", + ], + module_outs = GS201_MODULE_OUTS + GS201_DEVICE_MODULE_OUTS, + strip_modules = True, +) + +kernel_abi( + name = "gs201_abi", + kernel_build = ":kernel", + kernel_modules = [":kernel_ext_device_modules"], + kmi_symbol_list_add_only = True, + module_grouping = False, +) + +kernel_module( + name = "gs201_soc", + srcs = [ + "//private/google-modules/soc/gs:gs_soc_sources", + "//private/google-modules/trusty:headers", + ], + outs = [ + # keep sorted + "drivers/block/zram/zcomp_cpu.ko", + "drivers/block/zram/zcomp_eh.ko", + "drivers/block/zram/zram_gs.ko", + "drivers/bts/bts.ko", + "drivers/clk/gs/clk_exynos_gs.ko", + "drivers/clocksource/exynos_mct.ko", + "drivers/cpufreq/exynos-acme.ko", + "drivers/devfreq-whi/google/exynos_devfreq.ko", + "drivers/dma-buf/heaps/samsung/samsung_dma_heap.ko", + "drivers/dma/pl330.ko", + "drivers/dma/samsung-dma.ko", + "drivers/gpu/exynos/g2d/g2d.ko", + "drivers/i2c/busses/i2c-acpm.ko", + "drivers/i2c/busses/i2c-exynos5.ko", + "drivers/iio/power/odpm-whi.ko", + "drivers/input/fingerprint/goodixfp.ko", + "drivers/input/keyboard/s2mpg12-key.ko", + "drivers/input/keycombo.ko", + "drivers/input/keydebug.ko", + "drivers/input/misc/vl53l1/stmvl53l1.ko", + "drivers/iommu/exynos-pcie-iommu.ko", + "drivers/iommu/iovad-best-fit-algo.ko", + "drivers/iommu/samsung-iommu-group.ko", + "drivers/iommu/samsung-secure-iova.ko", + "drivers/iommu/samsung_iommu.ko", + "drivers/media/platform/exynos/mfc/exynos_mfc.ko", + "drivers/media/platform/exynos/smfc/smfc.ko", + "drivers/mfd/s2mpg12-mfd.ko", + "drivers/mfd/s2mpg13-mfd.ko", + "drivers/mfd/s2mpg1x-gpio.ko", + "drivers/mfd/slg51000-core.ko", + "drivers/mfd/slg51002-core.ko", + "drivers/misc/sbb-mux/sbb-mux.ko", + "drivers/misc/sscoredump/sscoredump.ko", + "drivers/pci/controller/dwc-whi/pcie-exynos-gs.ko", + "drivers/pci/controller/dwc-whi/pcie-exynos-gs201-rc-cal.ko", + "drivers/performance/gs_perf_mon/gs_perf_mon.ko", + "drivers/performance/lat_governors/gs_governor_memlat.ko", + "drivers/performance/lat_governors/gs_governor_utils.ko", + "drivers/phy/samsung/phy-exynos-mipi.ko", + "drivers/phy/samsung/phy-exynos-mipi-dsim.ko", + "drivers/phy/samsung/phy-exynos-usbdrd-super.ko", + "drivers/pinctrl/gs/pinctrl-exynos-gs.ko", + "drivers/pinctrl/pinctrl-slg51000.ko", + "drivers/pinctrl/pinctrl-slg51002.ko", + "drivers/power/reset/debug-reboot.ko", + "drivers/pwm/pwm-exynos.ko", + "drivers/regulator/pmic_class.ko", + "drivers/regulator/s2mpg12-powermeter.ko", + "drivers/regulator/s2mpg12-regulator.ko", + "drivers/regulator/s2mpg13-powermeter.ko", + "drivers/regulator/s2mpg13-regulator.ko", + "drivers/regulator/slg51000-regulator.ko", + "drivers/regulator/slg51002-regulator.ko", + "drivers/rtc/rtc-s2mpg12.ko", + "drivers/soc/google/acpm/acpm_flexpmu_dbg.ko", + "drivers/soc/google/acpm/acpm_mbox_test.ko", + "drivers/soc/google/acpm/gs_acpm.ko", + "drivers/soc/google/acpm/power_stats.ko", + "drivers/soc/google/bcm_dbg.ko", + "drivers/soc/google/cal-if/cmupmucal.ko", + "drivers/soc/google/dbgcore-dump.ko", + "drivers/soc/google/debug/debug-snapshot-debug-kinfo.ko", + "drivers/soc/google/debug/dss.ko", + "drivers/soc/google/debug/ehld.ko", + "drivers/soc/google/debug/etm2dram.ko", + "drivers/soc/google/debug/exynos-adv-tracer.ko", + "drivers/soc/google/debug/exynos-adv-tracer-s2d.ko", + "drivers/soc/google/debug/exynos-coresight.ko", + "drivers/soc/google/debug/exynos-coresight-etm.ko", + "drivers/soc/google/debug/exynos-debug-test.ko", + "drivers/soc/google/debug/exynos-ecc-handler.ko", + "drivers/soc/google/debug/itmon.ko", + "drivers/soc/google/debug/pixel-boot-metrics.ko", + "drivers/soc/google/debug/pixel-debug-test.ko", + "drivers/soc/google/debug/pixel-suspend-diag.ko", + "drivers/soc/google/debug/sjtag-driver.ko", + "drivers/soc/google/ect_parser.ko", + "drivers/soc/google/eh/eh.ko", + "drivers/soc/google/exynos-bcm_dbg-dump.ko", + "drivers/soc/google/exynos-cpuhp.ko", + "drivers/soc/google/exynos-cpupm.ko", + "drivers/soc/google/exynos-dm.ko", + "drivers/soc/google/exynos-pd.ko", + "drivers/soc/google/exynos-pd-dbg.ko", + "drivers/soc/google/exynos-pd_el3.ko", + "drivers/soc/google/exynos-pd_hsi0.ko", + "drivers/soc/google/exynos-pm.ko", + "drivers/soc/google/exynos-pmu-if.ko", + "drivers/soc/google/exynos-seclog.ko", + "drivers/soc/google/exynos_pm_qos.ko", + "drivers/soc/google/gs-chipid.ko", + "drivers/soc/google/gsa/gsa.ko", + "drivers/soc/google/gsa/gsa_gsc.ko", + "drivers/soc/google/hardlockup-debug.ko", + "drivers/soc/google/hardlockup-watchdog.ko", + "drivers/soc/google/kernel-top.ko", + "drivers/soc/google/modemctl/google_modemctl.ko", + "drivers/soc/google/pixel_stat/mm/pixel_stat_mm.ko", + "drivers/soc/google/pixel_stat/pixel_stat_sysfs.ko", + "drivers/soc/google/pkvm-s2mpu/pkvm-s2mpu/pkvm-s2mpu.ko", + "drivers/soc/google/pt/slc_acpm.ko", + "drivers/soc/google/pt/slc_dummy.ko", + "drivers/soc/google/pt/slc_pmon.ko", + "drivers/soc/google/pt/slc_pt.ko", + "drivers/soc/google/smra/smra.ko", + "drivers/soc/google/sysrq-hook.ko", + "drivers/soc/google/vh/kernel/cgroup/vh_cgroup.ko", + "drivers/soc/google/vh/kernel/fs/vh_fs.ko", + "drivers/soc/google/vh/kernel/metrics/pixel_metrics.ko", + "drivers/soc/google/vh/kernel/mm/vh_mm.ko", + "drivers/soc/google/vh/kernel/pixel_em/pixel_em.ko", + "drivers/soc/google/vh/kernel/sched/sched_tp.ko", + "drivers/soc/google/vh/kernel/sched/vh_preemptirq_long.ko", + "drivers/soc/google/vh/kernel/sched/vh_sched.ko", + "drivers/soc/google/vh/kernel/systrace.ko", + "drivers/soc/google/vh/kernel/thermal/vh_thermal.ko", + "drivers/spi/spi-s3c64xx.ko", + "drivers/thermal/google/s2mpg13_spmic_thermal.ko", + "drivers/thermal/samsung/gpu_cooling.ko", + "drivers/thermal/samsung/gs_thermal.ko", + "drivers/tty/serial/exynos_tty.ko", + "drivers/ufs/ufs-exynos-gs.ko", + "drivers/ufs/ufs-pixel-fips140.ko", + "drivers/usb/dwc3/dwc3-exynos-usb.ko", + "drivers/usb/gadget/function/usb_f_dm.ko", + "drivers/usb/gadget/function/usb_f_dm1.ko", + "drivers/usb/gadget/function/usb_f_etr_miu.ko", + "drivers/usb/host/xhci-exynos.ko", + "drivers/usb/typec/tcpm/google/bc_max77759.ko", + "drivers/usb/typec/tcpm/google/google_tcpci_shim.ko", + "drivers/usb/typec/tcpm/google/max77759_contaminant.ko", + "drivers/usb/typec/tcpm/google/max77759_helper.ko", + "drivers/usb/typec/tcpm/google/max77779_contaminant.ko", + "drivers/usb/typec/tcpm/google/max777x9_contaminant.ko", + "drivers/usb/typec/tcpm/google/tcpci_max77759.ko", + "drivers/usb/typec/tcpm/google/usb_psy.ko", + "drivers/usb/typec/tcpm/google/usbc_cooling_dev.ko", + "drivers/video/backlight/rt4539_bl.ko", + "drivers/watchdog/s3c2410_wdt.ko", + ], + kernel_build = "//private/devices/google/common:kernel", + makefile = ["//private/google-modules/soc/gs:Makefile"], + visibility = [ + # keep sorted + "//private/devices/google:__subpackages__", + "//private/google-modules:__subpackages__", + ], + deps = [ + "//private/google-modules/bms/misc:bms-misc", + "//private/google-modules/trusty", + ], +) + +kernel_module_group( + name = "kernel_ext_modules", + srcs = [ + # keep sorted + ":gs201_soc", + "//private/google-modules/amplifiers/audiometrics", + "//private/google-modules/aoc", + "//private/google-modules/aoc/alsa", + "//private/google-modules/aoc/usb:aoc.usb", + "//private/google-modules/bms", + "//private/google-modules/bms/misc:bms-misc", + "//private/google-modules/display/common/gs_drm", + "//private/google-modules/display/common/gs_panel", + "//private/google-modules/display/samsung:display.samsung", + "//private/google-modules/edgetpu/janeiro/drivers/edgetpu:edgetpu.janeiro", + "//private/google-modules/fingerprint/goodix/fps_touch_handler", + "//private/google-modules/gpu/mali_kbase", + "//private/google-modules/gpu/mali_pixel", + "//private/google-modules/gxp/gs201:gxp", + "//private/google-modules/lwis", + "//private/google-modules/misc/sscoredump", + "//private/google-modules/power/mitigation:bcl", + "//private/google-modules/power/reset", + "//private/google-modules/trusty", + "//private/google-modules/video/gchips:video.gchips", + ], +) + +# Extra modules needed for some (but not all) devices, to be loaded after +# common ones. Separate so <device> builds can exclude them. +kernel_module_group( + name = "kernel_ext_device_modules", + srcs = [ + # FIXME: SoC modules need to be loaded first or the device will crash. + # Module dependencies should not rely on the order. This needs be fixed. + ":kernel_ext_modules", + "//private/devices/google/felix:kernel_ext_modules", + "//private/devices/google/lynx:kernel_ext_modules", + "//private/devices/google/pantah:kernel_ext_modules", + "//private/devices/google/tangorpro:kernel_ext_modules", + ], +) + +kernel_modules_install( + name = "kernel_modules_install", + kernel_build = ":kernel", + kernel_modules = [":kernel_ext_device_modules"], +) + +kernel_unstripped_modules_archive( + name = "kernel_unstripped_modules_archive", + kernel_build = ":kernel", + kernel_modules = [":kernel_ext_device_modules"], +) + +merged_kernel_uapi_headers( + name = "merged_kernel_uapi_headers", + kernel_build = ":kernel", + kernel_modules = [":kernel_ext_device_modules"], +) + +filegroup( + name = "vendor_ramdisk_modules_list", + srcs = ["vendor_ramdisk.modules.gs201"], +) + +create_file( + name = "vendor_ramdisk_device_modules_list", + srcs = [ + # do not sort + ":vendor_ramdisk_modules_list", + "vendor_ramdisk.modules.devices", + ], + out = "vendor_ramdisk.modules", +) + +create_file( + name = "system_dlkm_modules_list", + out = "system_dlkm.modules", + # The list is used to filter modules with `grep -w`. + content = ["^kernel/" + m for m in PIXEL_GKI_MODULES_LIST], +) + +create_file( + name = "system_dlkm_props", + srcs = ["system_dlkm.props.gs201"], + out = "system_dlkm.props", +) + +create_file( + name = "vendor_dlkm_modules_list", + out = "vendor_dlkm.modules.gs201", + # The list is used to filter modules with `grep -w`. + content = ["^kernel/" + m for m in GS201_MODULE_OUTS] + ["^extra/.*"], +) + +create_file( + name = "vendor_dlkm_device_modules_list", + srcs = [":vendor_dlkm_modules_list"], + out = "vendor_dlkm.modules", + # The list is used to filter modules with `grep -w`. + content = ["^kernel/" + m for m in GS201_DEVICE_MODULE_OUTS] + ["^extra/.*"], +) + +filegroup( + name = "vendor_dlkm_modules_blocklist", + srcs = ["vendor_dlkm.blocklist.gs201"], +) + +create_file( + name = "vendor_dlkm_device_modules_blocklist", + srcs = [ + # do not sort + ":vendor_dlkm_modules_blocklist", + "vendor_dlkm.blocklist.devices", + ], + out = "vendor_dlkm.blocklist", +) + +create_file( + name = "vendor_dlkm_props", + srcs = ["vendor_dlkm.props.gs201"], + out = "vendor_dlkm.props", +) + +filegroup( + name = "dtbos", + srcs = [ + "//private/devices/google/felix:dtbos", + "//private/devices/google/lynx:dtbos", + "//private/devices/google/pantah:dtbos", + "//private/devices/google/tangorpro:dtbos", + ], +) + +kernel_images( + name = "kernel_images", + base_kernel_images = "//common:kernel_aarch64_images", + boot_image_outs = ["dtb.img"], + build_boot = False, + build_dtbo = True, + build_initramfs = True, + build_system_dlkm = True, + build_vendor_dlkm = True, + build_vendor_kernel_boot = True, + dedup_dlkm_modules = True, + dtbo_srcs = [":dtbos"], + kernel_build = ":kernel", + kernel_modules_install = ":kernel_modules_install", + modules_list = ":vendor_ramdisk_device_modules_list", + ramdisk_compression = "lz4", + system_dlkm_modules_list = ":system_dlkm_modules_list", + system_dlkm_props = ":system_dlkm_props", + vendor_dlkm_archive = True, + vendor_dlkm_etc_files = [":insmod_cfgs"], + vendor_dlkm_modules_blocklist = ":vendor_dlkm_device_modules_blocklist", + vendor_dlkm_modules_list = ":vendor_dlkm_device_modules_list", + vendor_dlkm_props = ":vendor_dlkm_props", + deps = ["//private/devices/google/common:sepolicy"], +) + +filegroup( + name = "insmod_cfgs", + srcs = glob([ + "insmod_cfg/*.cfg", + ]), +) + +copy_to_dist_dir( + name = "dist", + data = [ + # keep sorted + ":dtbos", + ":insmod_cfgs", + ":kernel", + ":kernel_images", + ":kernel_modules_install", + ":kernel_unstripped_modules_archive", + ":merged_kernel_uapi_headers", + "//common:android/abi_gki_aarch64_pixel", + "//common:kernel_aarch64", + "//common:kernel_aarch64_gki_boot_image", + "//common:kernel_aarch64_headers", + "//private/devices/google/common:kernel_gki_modules", + ] + select({ + "//private/devices/google/common:enable_download_fips140": ["@gki_prebuilt_fips140//fips140.ko"], + "//private/devices/google/common:disable_download_fips140": [], + }), + dist_dir = "out/gs201/dist", + flat = True, + log = "info", +) + +alias( + name = "gs201_dist", + actual = ":dist", +)
diff --git a/Kconfig.ext.gs201 b/Kconfig.ext.gs201 new file mode 100644 index 0000000..ce1ec8e --- /dev/null +++ b/Kconfig.ext.gs201
@@ -0,0 +1,89 @@ +# SPDX-License-Identifier: GPL-2.0-only + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/block/zram/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/bts/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/clk/gs/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/clocksource/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/cpufreq/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/devfreq-whi/google/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/dma-buf/heaps/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/dma/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/i2c/busses/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/iio/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/input/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/iommu/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/media/platform/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/mfd/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/misc/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/pci/controller/dwc-whi/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/performance/gs_perf_mon/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/performance/lat_governors/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/phy/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/pinctrl/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/power/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/pwm/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/regulator/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/rtc/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/soc/google/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/spi/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/thermal/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/tty/serial/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/ufs/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/usb/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/video/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/video/backlight/Kconfig" + +source "$(KCONFIG_SOC_GS_PREFIX)drivers/watchdog/Kconfig" + +source "$(KCONFIG_EXT_MODULES_PREFIX)private/google-modules/bms/misc/Kconfig" + +source "$(KCONFIG_EXT_MODULES_PREFIX)private/google-modules/display/common/Kconfig" + +source "$(KCONFIG_EXT_MODULES_PREFIX)private/google-modules/display/samsung/Kconfig" + +source "$(KCONFIG_EXT_MODULES_PREFIX)private/google-modules/display/samsung/panel/Kconfig" + +source "$(KCONFIG_EXT_MODULES_PREFIX)private/google-modules/fingerprint/goodix/fps_touch_handler/Kconfig" + +source "$(KCONFIG_EXT_MODULES_PREFIX)private/google-modules/power/mitigation/Kconfig" + +source "$(KCONFIG_EXT_MODULES_PREFIX)private/google-modules/power/reset/Kconfig" + +source "$(KCONFIG_EXT_MODULES_PREFIX)private/google-modules/touch/common/Kconfig" + +source "$(KCONFIG_EXT_MODULES_PREFIX)private/google-modules/touch/sec/Kconfig" + +source "$(KCONFIG_EXT_MODULES_PREFIX)private/google-modules/trusty/drivers/trusty/Kconfig" + +source "$(KCONFIG_EXT_MODULES_PREFIX)private/google-modules/radio/samsung/s5300/Kconfig"
diff --git a/build.config.gs201 b/build.config.gs201 new file mode 100644 index 0000000..f71fc2f --- /dev/null +++ b/build.config.gs201
@@ -0,0 +1,13 @@ +. ${ROOT_DIR}/${KERNEL_DIR}/build.config.common +. ${ROOT_DIR}/${KERNEL_DIR}/build.config.aarch64 + +KCONFIG_EXT_MODULES_PREFIX=$(realpath ${ROOT_DIR} --relative-to ${ROOT_DIR}/${KERNEL_DIR})/ +KCONFIG_SOC_GS_PREFIX=${KCONFIG_EXT_MODULES_PREFIX}/private/google-modules/soc/gs/ + +DEFCONFIG=gki_defconfig + +BOOT_IMAGE_HEADER_VERSION=4 +TRIM_UNUSED_MODULES=1 + +DTC_INCLUDE=${ROOT_DIR}/private/google-modules/soc/gs/include/dtc +MKDTIMG_FLAGS="--page_size=4096 --id=/:board_id --rev=/:board_rev"
diff --git a/build_gs201.sh b/build_gs201.sh new file mode 100755 index 0000000..0852959 --- /dev/null +++ b/build_gs201.sh
@@ -0,0 +1,7 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0-only + +exec tools/bazel run \ + --config=stamp \ + --config=gs201 \ + //private/devices/google/gs201:dist "$@"
diff --git a/constants.bzl b/constants.bzl new file mode 100644 index 0000000..3724394 --- /dev/null +++ b/constants.bzl
@@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-only + +""" +GS201 constants. +""" + +GS201_DTBS = [ + # keep sorted + "gs201-a0.dtb", + "gs201-b0.dtb", + "gs201-b0_v2-ipop.dtb", +] + +GS201_MODULE_OUTS = [ + # keep sorted + "drivers/gpu/drm/display/drm_display_helper.ko", + "drivers/i2c/i2c-dev.ko", + "drivers/misc/eeprom/at24.ko", + "drivers/perf/arm_dsu_pmu.ko", + "drivers/scsi/sg.ko", + "drivers/spi/spidev.ko", + "drivers/watchdog/softdog.ko", + "net/mac80211/mac80211.ko", + "net/wireless/cfg80211.ko", +] + +GS201_DEVICE_MODULE_OUTS = [ + # keep sorted + "drivers/leds/leds-pwm.ko", + "drivers/regulator/rt4801-regulator.ko", + "drivers/regulator/tps65132-regulator.ko", + "drivers/video/backlight/lp855x_bl.ko", +]
diff --git a/device.bazelrc b/device.bazelrc new file mode 100644 index 0000000..44137eb --- /dev/null +++ b/device.bazelrc
@@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (C) 2024 Google LLC + +build:gs201 --//private/devices/google/common:kernel=//private/devices/google/gs201:kernel +build:gs201 --//private/google-modules/soc/gs:gs_soc_module=//private/devices/google/gs201:gs201_soc
diff --git a/dts/Makefile b/dts/Makefile new file mode 100644 index 0000000..5501a25 --- /dev/null +++ b/dts/Makefile
@@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# Kbuild doesn't recognize that we want overlays, since there aren't any in +# this directory. But we're going to build and apply those from other trees, so +# force __symbols__ generation. +DTC_FLAGS += -@ + +dtb-y += gs201-a0.dtb +dtb-y += gs201-b0.dtb +dtb-y += gs201-b0_v2-ipop.dtb
diff --git a/dts/avf-dpm-eng.dtsi b/dts/avf-dpm-eng.dtsi new file mode 100644 index 0000000..a2aed72 --- /dev/null +++ b/dts/avf-dpm-eng.dtsi
@@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Android Virtualization Framework Debug Policy device tree source + * + * Copyright 2022 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + fragment@avf { + target-path = "/"; + + __overlay__ { + avf { + version = <0>; + variant = "eng"; + guest { + common { + log = <1>; + ramdump = <1>; + }; + + microdroid { + adb = <0>; + adb_root = <0>; + ignore_dentity = <0>; + }; + }; + + pvmfw { + log = <1>; + skip_verified_boot = <0>; + }; + }; + }; + }; +}; /* end of avf */
diff --git a/dts/avf-dpm-user.dtsi b/dts/avf-dpm-user.dtsi new file mode 100644 index 0000000..23c2cbe --- /dev/null +++ b/dts/avf-dpm-user.dtsi
@@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Android Virtualization Framework Debug Policy device tree source + * + * Copyright 2022 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + fragment@avf { + target-path = "/"; + + __overlay__ { + avf { + version = <0>; + variant = "user"; + guest { + common { + log = <0>; + ramdump = <0>; + }; + + microdroid { + adb = <0>; + adb_root = <0>; + ignore_dentity = <0>; + }; + }; + + pvmfw { + log = <0>; + skip_verified_boot = <0>; + }; + }; + }; + }; +}; /* end of avf */
diff --git a/dts/avf-dpm-userdebug.dtsi b/dts/avf-dpm-userdebug.dtsi new file mode 100644 index 0000000..7db74c3 --- /dev/null +++ b/dts/avf-dpm-userdebug.dtsi
@@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Android Virtualization Framework Debug Policy device tree source + * + * Copyright 2022 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + fragment@avf { + target-path = "/"; + + __overlay__ { + avf { + version = <0>; + variant = "userdebug"; + guest { + common { + log = <1>; + ramdump = <1>; + }; + + microdroid { + adb = <0>; + adb_root = <0>; + ignore_dentity = <0>; + }; + }; + + pvmfw { + log = <1>; + skip_verified_boot = <0>; + }; + }; + }; + }; +}; /* end of avf */
diff --git a/dts/gs101-audio.dtsi b/dts/gs101-audio.dtsi new file mode 100644 index 0000000..4fd1b17 --- /dev/null +++ b/dts/gs101-audio.dtsi
@@ -0,0 +1,879 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS101 Common Audio Device Tree Source + * + * Copyright (c) 2020 Google, LLC + * https://www.google.com + * +*/ + +#include <arm64/exynos/exynos-pinctrl.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/sound/google-aoc.h> + +/ { + V_SYS_dummy: cs35l41_dummy_regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "V_SYS_DUMMY"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-boot-on; + regulator-always-on; + }; + + aoc_pcm_ep: aoc_pcm_drv { + compatible = "google-aoc-snd-pcm"; + }; + + aoc_voice_ep: aoc_voice_drv { + compatible = "google-aoc-snd-voice"; + }; + + aoc_compr_ep: aoc_compr_drv { + compatible = "google-aoc-snd-compr"; + }; + + aud_aoc_path: aoc_path { + #sound-dai-cells = <1>; + compatible = "google-aoc-path"; + }; + + aoc_nohost_drv: aoc_nohost { + compatible = "google-aoc-snd-nohost"; + }; + + aoc_voip_ep: aoc_voip_drv { + compatible = "google-aoc-snd-voip"; + }; + + aoc_incall_ep: aoc_incall_drv { + compatible = "google-aoc-snd-incall"; + }; + + aoc_snd_card: sound-aoc { + compatible = "google-aoc-snd-card"; + aoc-card-name = "google,aoc-snd-card"; + + dai_link { + dai_fe_ep1_rx: fe_ep1_rx { + dai-name = "audio_playback0"; + stream-name = "EP1 playback"; + id = <IDX_EP1_RX>; + dynamic; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_EP1_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_pcm_ep>; + }; + }; + }; + + dai_fe_ep2_rx: fe_ep2_rx { + dai-name = "audio_playback1"; + stream-name = "EP2 playback"; + id = <IDX_EP2_RX>; + dynamic; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_EP2_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_pcm_ep>; + }; + }; + }; + + dai_fe_ep3_rx: fe_ep3_rx { + dai-name = "audio_playback2"; + stream-name = "EP3 playback"; + id = <IDX_EP3_RX>; + dynamic; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_EP3_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_pcm_ep>; + }; + }; + }; + + dai_fe_ep4_rx: fe_ep4_rx { + dai-name = "audio_playback3"; + stream-name = "EP4 playback"; + id = <IDX_EP4_RX>; + dynamic; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_EP4_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_pcm_ep>; + }; + }; + }; + + dai_fe_ep5_rx: fe_ep5_rx { + dai-name = "audio_playback4"; + stream-name = "EP5 playback"; + id = <IDX_EP5_RX>; + dynamic; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_EP5_RX>; + }; + platform { + vorx { + of_drv = <&aoc_voice_ep>; + }; + }; + }; + + dai_fe_ep6_rx: fe_ep6_rx { + dai-name = "audio_playback5"; + stream-name = "EP6 playback"; + id = <IDX_EP6_RX>; + dynamic; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_EP6_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_pcm_ep>; + }; + }; + }; + + dai_fe_ep7_rx: fe_ep7_rx { + dai-name = "audio_playback6"; + stream-name = "EP7 playback"; + id = <IDX_EP7_RX>; + dynamic; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_EP7_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_compr_ep>; + }; + }; + }; + + dai_fe_ep8_rx: fe_ep8_rx { + dai-name = "audio_haptics"; + stream-name = "EP8 playback"; + id = <IDX_EP8_RX>; + dynamic; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_EP8_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_pcm_ep>; + }; + }; + }; + + dai_fe_ep1_tx: fe_ep1_tx { + dai-name = "audio_capture0"; + stream-name = "EP1 capture"; + id = <IDX_EP1_TX>; + dynamic; + capture; + cpu { + sound-dai = <&aud_aoc_path IDX_EP1_TX>; + }; + platform { + tx1 { + of_drv = <&aoc_pcm_ep>; + }; + }; + }; + + dai_fe_ep2_tx: fe_ep2_tx { + dai-name = "audio_capture1"; + stream-name = "EP2 capture"; + id = <IDX_EP2_TX>; + dynamic; + capture; + cpu { + sound-dai = <&aud_aoc_path IDX_EP2_TX>; + }; + platform { + tx1 { + of_drv = <&aoc_pcm_ep>; + }; + }; + }; + + dai_fe_ep3_tx: fe_ep3_tx { + dai-name = "audio_capture2"; + stream-name = "EP3 capture"; + id = <IDX_EP3_TX>; + dynamic; + capture; + cpu { + sound-dai = <&aud_aoc_path IDX_EP3_TX>; + }; + platform { + tx1 { + of_drv = <&aoc_pcm_ep>; + }; + }; + }; + + dai_fe_ep4_tx: fe_ep4_tx { + dai-name = "audio_capture3"; + stream-name = "EP4 capture"; + id = <IDX_EP4_TX>; + dynamic; + capture; + cpu { + sound-dai = <&aud_aoc_path IDX_EP4_TX>; + }; + platform { + votx { + of_drv = <&aoc_voice_ep>; + }; + }; + }; + + dai_fe_ep5_tx: fe_ep5_tx { + dai-name = "ultrasonic_capture"; + stream-name = "EP5 capture"; + id = <IDX_EP5_TX>; + dynamic; + capture; + cpu { + sound-dai = <&aud_aoc_path IDX_EP5_TX>; + }; + platform { + tx1 { + of_drv = <&aoc_pcm_ep>; + }; + }; + }; + + dai_fe_ep6_tx: fe_ep6_tx { + dai-name = "audio_capture5"; + stream-name = "EP6 capture"; + id = <IDX_EP6_TX>; + dynamic; + capture; + cpu { + sound-dai = <&aud_aoc_path IDX_EP6_TX>; + }; + platform { + tx1 { + of_drv = <&aoc_pcm_ep>; + }; + }; + }; + + dai_fe_nohost1_rx: fe_nohost1_rx { + dai-name = "nohost1 playback"; + stream-name = "nohost1 playback"; + id = <IDX_NOHOST1_RX>; + dynamic; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_NOHOST1_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_nohost_drv>; + }; + }; + }; + + dai_fe_nohost1_tx: fe_nohost1_tx { + dai-name = "nohost1 capture"; + stream-name = "nohost1 capture"; + id = <IDX_NOHOST1_TX>; + dynamic; + capture; + cpu { + sound-dai = <&aud_aoc_path IDX_NOHOST1_TX>; + }; + platform { + tx1 { + of_drv = <&aoc_nohost_drv>; + }; + }; + }; + + dai_fe_voip_rx: fe_voip_rx { + dai-name = "audio_voip_rx"; + stream-name = "audio_voip_rx"; + id = <IDX_VOIP_RX>; + dynamic; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_VOIP_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_voip_ep>; + }; + }; + }; + + dai_fe_voip_tx: fe_voip_tx { + dai-name = "audio_voip_tx"; + stream-name = "audio_voip_tx"; + id = <IDX_VOIP_TX>; + dynamic; + capture; + cpu { + sound-dai = <&aud_aoc_path IDX_VOIP_TX>; + }; + platform { + tx1 { + of_drv = <&aoc_voip_ep>; + }; + }; + }; + + dai_fe_incall_pb0_rx: fe_incall_pb0_rx { + dai-name = "audio_incall_pb_0"; + stream-name = "audio_incall_pb_0"; + id = <IDX_INCALL_PB0_RX>; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_INCALL_PB0_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_incall_ep>; + }; + }; + }; + + dai_fe_incall_pb1_rx: fe_incall_pb1_rx { + dai-name = "audio_incall_pb_1"; + stream-name = "audio_incall_pb_1"; + id = <IDX_INCALL_PB1_RX>; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_INCALL_PB1_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_incall_ep>; + }; + }; + }; + + dai_fe_incall_cap0_tx: fe_incall_cap0_tx { + dai-name = "audio_incall_cap_0"; + stream-name = "audio_incall_cap_0"; + id = <IDX_INCALL_CAP0_TX>; + capture; + cpu { + sound-dai = <&aud_aoc_path IDX_INCALL_CAP0_TX>; + }; + platform { + tx1 { + of_drv = <&aoc_incall_ep>; + }; + }; + }; + + dai_fe_incall_cap1_tx: fe_incall_cap1_tx { + dai-name = "audio_incall_cap_1"; + stream-name = "audio_incall_cap_1"; + id = <IDX_INCALL_CAP1_TX>; + capture; + cpu { + sound-dai = <&aud_aoc_path IDX_INCALL_CAP1_TX>; + }; + platform { + tx1 { + of_drv = <&aoc_incall_ep>; + }; + }; + }; + + dai_fe_incall_cap2_tx: fe_incall_cap2_tx { + dai-name = "audio_incall_cap_2"; + stream-name = "audio_incall_cap_2"; + id = <IDX_INCALL_CAP2_TX>; + capture; + cpu { + sound-dai = <&aud_aoc_path IDX_INCALL_CAP2_TX>; + }; + platform { + tx1 { + of_drv = <&aoc_incall_ep>; + }; + }; + }; + + dai_fe_raw_rx: fe_raw_rx { + dai-name = "audio_raw"; + stream-name = "audio_raw"; + id = <IDX_RAW_RX>; + dynamic; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_RAW_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_pcm_ep>; + }; + }; + }; + + dai_fe_haptic_nohost_rx: fe_haptic_nohost_rx { + dai-name = "haptic nohost playback"; + stream-name = "haptic nohost playback"; + id = <IDX_HAPTIC_NoHOST_RX>; + dynamic; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_HAPTIC_NoHOST_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_nohost_drv>; + + }; + }; + }; + + dai_fe_hifi_rx: fe_hifi_rx { + dai-name = "audio_hifiout"; + stream-name = "audio_hifiout"; + id = <IDX_HIFI_RX>; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_HIFI_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_incall_ep>; + }; + }; + }; + + dai_fe_hifi_tx: fe_hifi_tx { + dai-name = "audio_hifiin"; + stream-name = "audio_hifiin"; + id = <IDX_HIFI_TX>; + capture; + cpu { + sound-dai = <&aud_aoc_path IDX_HIFI_TX>; + }; + platform { + tx1 { + of_drv = <&aoc_incall_ep>; + }; + }; + }; + + dai_fe_android_aec_tx: fe_android_aec_tx { + dai-name = "audio_android_aec"; + stream-name = "audio_android_aec"; + id = <IDX_ANDROID_AEC_TX>; + capture; + cpu { + sound-dai = <&aud_aoc_path IDX_ANDROID_AEC_TX>; + }; + platform { + tx1 { + of_drv = <&aoc_incall_ep>; + }; + }; + }; + + dai_fe_us_rx: fe_us_rx { + dai-name = "audio_ultrasonic"; + stream-name = "audio_ultrasonic"; + id = <IDX_US_RX>; + dynamic; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_US_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_pcm_ep>; + }; + }; + }; + + dai_fe_incall_pb2_rx: fe_incall_pb2_rx { + dai-name = "audio_incall_pb_2"; + stream-name = "audio_incall_pb_2"; + id = <IDX_INCALL_PB2_RX>; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_INCALL_PB2_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_incall_ep>; + }; + }; + }; + + dai_fe_ims_rx: fe_ims_rx { + dai-name = "audio_immersive"; + stream-name = "audio_immersive"; + id = <IDX_IMSV_RX>; + dynamic; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_IMSV_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_pcm_ep>; + }; + }; + }; + + dai_fe_cap_inj_rx: fe_capture_inject_rx { + dai-name = "audio_capture_inject"; + stream-name = "audio_capture_inject"; + id = <IDX_CAP_INJ_RX>; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_CAP_INJ_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_incall_ep>; + }; + }; + }; + + dai_fe_hotword_tap_tx: fe_hotword_tap_tx { + dai-name = "audio_hotword_tap"; + stream-name = "audio_hotword_tap"; + id = <IDX_HOTWORD_TAP_TX>; + capture; + cpu { + sound-dai = <&aud_aoc_path IDX_HOTWORD_TAP_TX>; + }; + platform { + tx1 { + of_drv = <&aoc_incall_ep>; + }; + }; + }; + + dai_be_i2s0_rx: be_i2s0_rx { + dai-name = "I2S_0_RX Playback"; + stream-name = "I2S_0_RX Playback"; + id = <I2S_0_RX>; + playback; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path I2S_0_RX>; + }; + daifmt { + dai-format = "i2s"; + }; + }; + + dai_be_i2s0_tx: be_i2s0_tx { + dai-name = "I2S_0_TX Capture"; + stream-name = "I2S_0_TX Capture"; + id = <I2S_0_TX>; + capture; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path I2S_0_TX>; + }; + daifmt { + dai-format = "i2s"; + }; + }; + + dai_be_i2s1_rx: be_i2s1_rx { + dai-name = "I2S_1_RX Playback"; + stream-name = "I2S_1_RX Playback"; + id = <I2S_1_RX>; + playback; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path I2S_1_RX>; + }; + daifmt { + dai-format = "i2s"; + }; + }; + + dai_be_i2s1_tx: be_i2s1_tx { + dai-name = "I2S_1_TX Capture"; + stream-name = "I2S_1_TX Capture"; + id = <I2S_1_TX>; + capture; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path I2S_1_TX>; + }; + daifmt { + dai-format = "i2s"; + }; + }; + + dai_be_i2s2_rx: be_i2s2_rx { + dai-name = "I2S_2_RX Playback"; + stream-name = "I2S_2_RX Playback"; + id = <I2S_2_RX>; + playback; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path I2S_2_RX>; + }; + daifmt { + dai-format = "i2s"; + bitclock-inversion; + }; + }; + + dai_be_i2s2_tx: be_i2s2_tx{ + dai-name = "I2S_2_TX Capture"; + stream-name = "I2S_2_TX Capture"; + id = <I2S_2_TX>; + capture; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path I2S_2_TX>; + }; + daifmt { + dai-format = "i2s"; + }; + }; + + dai_be_tdm0_rx: be_tdm0_rx { + dai-name = "TDM_0_RX Playback"; + stream-name = "TDM_0_RX Playback"; + id = <TDM_0_RX>; + playback; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path TDM_0_RX>; + }; + daifmt { + dai-format = "dsp_a"; + }; + }; + + dai_be_tdm0_tx: be_tdm0_tx { + dai-name = "TDM_0_TX Capture"; + stream-name = "TDM_0_TX Capture"; + id = <TDM_0_TX>; + capture; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path TDM_0_TX>; + }; + daifmt { + dai-format = "dsp_a"; + }; + }; + + dai_be_tdm1_rx: be_tdm1_rx { + dai-name = "TDM_1_RX Playback"; + stream-name = "TDM_1_RX Playback"; + id = <TDM_1_RX>; + playback; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path TDM_1_RX>; + }; + daifmt { + dai-format = "i2s"; + }; + }; + + dai_be_tdm1_tx: be_tdm1_tx { + dai-name = "TDM_1_TX Capture"; + stream-name = "TDM_1_TX Capture"; + id = <TDM_1_TX>; + capture; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path TDM_1_TX>; + }; + daifmt { + dai-format = "i2s"; + }; + }; + + dai_be_internal_mic_tx: be_internal_mic_tx { + dai-name = "INTERNAL_MIC_TX Capture"; + stream-name = "INTERNAL_MIC_TX Capture"; + id = <INTERNAL_MIC_TX>; + capture; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path INTERNAL_MIC_TX>; + }; + }; + + dai_be_internal_mic_us_tx: be_internal_mic_us_tx { + dai-name = "INTERNAL_MIC_US_TX Capture"; + stream-name = "INTERNAL_MIC_US_TX Capture"; + id = <INTERNAL_MIC_US_TX>; + capture; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path INTERNAL_MIC_US_TX>; + }; + }; + + dai_be_bt_rx: be_bt_rx { + dai-name = "BT_RX Playback"; + stream-name = "BT_RX Playback"; + id = <BT_RX>; + playback; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path BT_RX>; + }; + }; + + dai_be_bt_tx: be_bt_tx { + dai-name = "BT_TX Capture"; + stream-name = "BT_TX Capture"; + id = <BT_TX>; + capture; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path BT_TX>; + }; + }; + + dai_be_usb_rx: be_usb_rx { + dai-name = "USB_RX Playback"; + stream-name = "USB_RX Playback"; + id = <USB_RX>; + playback; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path USB_RX>; + }; + }; + + dai_be_usb_tx: be_usb_tx { + dai-name = "USB_TX Capture"; + stream-name = "USB_TX Capture"; + id = <USB_TX>; + capture; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path USB_TX>; + }; + }; + + dai_be_incall_rx: be_incall_rx { + dai-name = "INCALL_RX Playback"; + stream-name = "INCALL_RX Playback"; + id = <INCALL_RX>; + playback; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path INCALL_RX>; + }; + }; + + dai_be_incall_tx: be_incall_tx { + dai-name = "INCALL_TX Capture"; + stream-name = "INCALL_TX Capture"; + id = <INCALL_TX>; + capture; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path INCALL_TX>; + }; + }; + + dai_be_haptic_rx: be_haptic_rx { + dai-name = "HAPTIC_RX Playback"; + stream-name = "HAPTIC_RX Playback"; + id = <HAPTIC_RX>; + playback; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path HAPTIC_RX>; + }; + daifmt { + dai-format = "dsp_a"; + }; + }; + + dai_be_eraser_tx: be_eraser_tx { + dai-name = "ERASER_TX Capture"; + stream-name = "ERASER_TX Capture"; + id = <ERASER_TX>; + capture; + no-pcm; + useops; + usefixup; + cpu { + sound-dai = <&aud_aoc_path ERASER_TX>; + }; + }; + + }; + }; + + max98357a_hac: max98357a { + compatible = "maxim,max98357a"; + #sound-dai-cells = <0>; + + status = "disabled"; + }; +};
diff --git a/dts/gs101-cp-s5200-thermal-zone.dtsi b/dts/gs101-cp-s5200-thermal-zone.dtsi new file mode 100644 index 0000000..a23a173 --- /dev/null +++ b/dts/gs101-cp-s5200-thermal-zone.dtsi
@@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * CP thermal zones + * + * Copyright 2020 Google, LLC. + */ + +#include <dt-bindings/thermal/thermal.h> + +&cp_tm1 { + num_sensors = <9>; +}; + +&thermal_zones { + cp_on_chip_0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&cp_tm1 0>; + trips { + trip_config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + cp_on_chip_1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&cp_tm1 1>; + trips { + trip_config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + cp_on_chip_2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&cp_tm1 2>; + trips { + trip_config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + cp_on_chip_3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&cp_tm1 3>; + trips { + trip_config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + cp_on_chip_4 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&cp_tm1 4>; + trips { + trip_config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + cp_on_chip_5 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&cp_tm1 5>; + trips { + trip_config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + cp_on_chip_6 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&cp_tm1 6>; + trips { + trip_config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + rf2_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&cp_tm1 7>; + trips { + trip_config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + rf1_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&cp_tm1 8>; + trips { + trip_config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +};
diff --git a/dts/gs101-cp-tm.dtsi b/dts/gs101-cp-tm.dtsi new file mode 100644 index 0000000..46b3cae --- /dev/null +++ b/dts/gs101-cp-tm.dtsi
@@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * CP temperature manager. + * + * Copyright 2020 Google, LLC. + */ + +#include <dt-bindings/thermal/thermal.h> + +/ { + cp_tm1: cp-tm1 { + compatible = "google,gs101-cp-thermal"; + #thermal-sensor-cells = <1>; + }; +}; \ No newline at end of file
diff --git a/dts/gs101-display-timing.dtsi b/dts/gs101-display-timing.dtsi new file mode 100644 index 0000000..cd68441 --- /dev/null +++ b/dts/gs101-display-timing.dtsi
@@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SAMSUNG EXYNOS SoC device tree source + * + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + */ + +/ { + dsim_modes: dsim_modes { + /* parameters used to calcuate dsim_mode at runtime */ + pll-input = /bits/ 64 <24576000>; /* 24.576 MHz */ + pll-optimum = /bits/ 64 <13000000>; /* 13 MHz */ + pll-out-range = /bits/ 64 <52000000 6600000000>; /* 55 to 6600 MHz*/ + pll-vco-range = /bits/ 64 <3300000000 6600000000>; /* 3300 to 6600 MHz */ + p-range = <1 63>; /* inclusive */ + m-range = <64 1023>; /* inclusive */ + s-range = <0 6>; /* inclusive */ + k-bits = <16>; /* K is a two's complement 16-bit intger */ + + dsim-modes { + 1440x3040 { + mode-name = "1440x3040"; + /* + * p m s k + * mfr mrr sel_pf icp + * afc_enb extafc feed_en fsel + * fout_mask rsel + */ + pmsk = < + 0x2 0xB3 0x2 0x0955 + 0xd 0x3 0x0 0x0 + 0x0 0x0 0x0 0x0 + 0x0 0x0 + >; + hs-clk = <1100>; + esc-clk = <20>; + }; + 1440x2960 { + mode-name = "1440x2960"; + pmsk = < + /* 0x2 0xe4 0x2 0xdd55 */ + 0x2 0xF3 0x2 0x8355 /* p m s k */ + >; + hs-clk = <1490>; + esc-clk = <20>; + }; + 1080x2340 { + mode-name = "1080x2340"; + pmsk = < + 0x2 0xD4 0x3 0x96AB /* p m s k */ + >; + hs-clk = <650>; + esc-clk = <20>; + }; + 1440x3120 { + mode-name = "1440x3120"; + pmsk = < + 0x2 0xDB 0x2 0x1355 /* p m s k */ + >; + hs-clk = <1346>; + esc-clk = <20>; + }; + 1080x2400 { + mode-name = "1080x2400"; + pmsk = < + 0x2 0xB6 0x2 0x4AAB /* p m s k */ + >; + hs-clk = <1120>; + esc-clk = <20>; + }; + 1200x1920 { + mode-name = "1200x1920"; + pmsk = < + 0x2 0x9E 0x2 0xB700 /* p m s k */ + >; + hs-clk = <969>; + esc-clk = <20>; + }; + 1840x2208 { + mode-name = "1840x2208"; + pmsk = < + 0x2 0xD0 0x2 0x5555 /* p m s k */ + >; + hs-clk = <1280>; + esc-clk = <20>; + }; + 1080x2092 { + mode-name = "1080x2092"; + pmsk = < + 0x2 0xEE 0x3 0xA155 /* p m s k */ + >; + hs-clk = <730>; + esc-clk = <20>; + }; + }; + }; + + dphy_diags: dphy_diags { + reg_400m { + diag-name = "reg_400m"; + desc = "Reference voltage-400mV for HS Function control pin"; + help = "0: 380mV, 1: 390mV, 2: 400mV, 3: 410mV, 4: 420mV, 5: 430mV, +6: 440mV, 7: 450mV"; + reg-base = "dphy-extra"; + reg-offset = /bits/ 16 <0x8>; + bit-range = /bits/ 8 <6 4>; /* bit [6:4] */ + }; + edge_con { + diag-name = "edge_con"; + desc = "Cap Peaking Control Registers for clock and 4 data lanes"; + help = "0: Cap-Peaking Off, 1: Low-strength cap-peaking, +3: Mid-strength cap-peaking, 7: High-strength cap-peaking"; + reg-base = "dphy"; + /* M0_DPHY_M#C_ANA_CON0 + * M0_COMBO_M#D0_ANA_CON0 + * M0_COMBO_M#D1_ANA_CON0 + * M0_COMBO_M#D2_ANA_CON0 + * M0_COMBO_M#D3_ANA_CON0 + */ + reg-offset = /bits/ 16 <0x208 0x308 0x408 0x508 0x608>; + bit-range = /bits/ 8 <14 12>; + }; + edge_con_dir { + diag-name = "edge_con_dir"; + desc = "Cap Peaking Direction Control Registers for clock and data lanes"; + help = "0: Forward CapPeaking (@slop high), +1: Backward Cap Peaking (@slop low)"; + reg-base = "dphy"; + reg-offset = /bits/ 16 <0x208 0x308 0x408 0x508 0x608>; + bit-range = /bits/ 8 <9 9>; + }; + edge_con_en { + diag-name = "edge_con_en"; + desc = "Cap Peaking Enable Registers for clock and data lanes"; + help = "0: disable, 1: enable"; + reg-base = "dphy"; + reg-offset = /bits/ 16 <0x208 0x308 0x408 0x508 0x608>; + bit-range = /bits/ 8 <8 8>; + }; + res_up { + diag-name = "res_up"; + desc = "High-Speed Driver Up Resistor Control Registers for clock and +data lanes"; + help = "0: 43, 1: 46, 2: 49, 3: 52, 4: 56, 5: 60, 7: 73, 8: 30, 9: 31.2, +10: 32.5, 11: 34, 12: 35.5, 13: 37, 14: 39, 15: 31"; + reg-base = "dphy"; + reg-offset = /bits/ 16 <0x208 0x308 0x408 0x508 0x608>; + bit-range = /bits/ 8 <7 4>; + }; + res_down { + diag-name = "res_down"; + desc = "High-Speed Driver Down Resistor Control Registers for clock and +data lanes"; + help = "0: 43, 1: 46, 2: 49, 3: 52, 4: 56, 5: 60, 7: 73, 8: 30, 9: 31.2, +10: 32.5, 11: 34, 12: 35.5, 13: 37, 14: 39, 15: 31"; + reg-base = "dphy"; + reg-offset = /bits/ 16 <0x208 0x308 0x408 0x508 0x608>; + bit-range = /bits/ 8 <3 0>; + }; + emp { + diag-name = "emp"; + desc = "De-Emphasis Control Registers for clock and data lanes"; + help = "0: de-emphasis off, 1: -1.6 dB, 2: -3.5 dB, 3 -6 dB"; + reg-base = "dphy"; + /* M0_DPHY_M#C_ANA_CON1 + * M0_COMBO_M#D0_ANA_CON1 + * M0_COMBO_M#D1_ANA_CON1 + * M0_COMBO_M#D2_ANA_CON1 + * M0_COMBO_M#D3_ANA_CON1 + */ + reg-offset = /bits/ 16 <0x20c 0x30c 0x40c 0x50c 0x60c>; + bit-range = /bits/ 8 <1 0>; + }; + hs_prepare { + diag-name = "hs_prepare"; + desc = "THS-PREPARE (D-PHY) Timing Counter Registers for data lanes"; + help = "This count value is used in High-Speed Transmit operation."; + reg-base = "dphy"; + /* M0_COMBO_M#D0_TIME_CON1 + * M0_COMBO_M#D1_TIME_CON1 + * M0_COMBO_M#D2_TIME_CON1 + * M0_COMBO_M#D3_TIME_CON1 + */ + reg-offset = /bits/ 16 <0x334 0x434 0x534 0x634>; + bit-range = /bits/ 8 <7 0>; + }; + clk_prepare { + diag-name = "clk_prepare"; + desc = "TCLK-PREPARE Timing Counter Register"; + help = "This count value is used in High-Speed Transmit operations"; + reg-base = "dphy"; + /* M0_DPHY_M#C_TIME_CON1 */ + reg-offset = /bits/ 16 <0x234>; + bit-range = /bits/ 8 <7 0>; + }; + }; + +};
diff --git a/dts/gs101-dma-heap.dtsi b/dts/gs101-dma-heap.dtsi new file mode 100644 index 0000000..c3faf6a --- /dev/null +++ b/dts/gs101-dma-heap.dtsi
@@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * GS101 SoC DMA-HEAP + * + * Copyright 2021 Google LLC + */ + +/ { + system_dma_heap { + compatible = "samsung,dma-heap-system"; + dma-heap,name = "system"; + }; + + video_system_dma_heap { + compatible = "samsung,dma-heap-system"; + dma-heap,name = "video_system"; + dma-heap,video_aligned; + }; + + faceauth_model_heap: faceauth_model_heap { + compatible = "samsung,dma-heap-carveout"; + memory-region = <&famodel>; + dma-heap,name = "famodel"; + dma-heap,dynamic-secure; + dma-heap,protection_id = <19>; + dma-heap,alignment = <0x10000>; + status = "disabled"; + }; +}; + +&trusty { + video_stream_dma_heap { + compatible = "samsung,dma-heap-chunk"; + memory-region = <&vstream>; + dma-heap,name = "vstream"; + dma-heap,video_aligned; + dma-heap,secure; + dma-heap,protection_id = <3>; + dma-heap,alignment = <0x10000>; + }; + + video_frame_dma_heap { + compatible = "samsung,dma-heap-chunk"; + memory-region = <&vframe>; + dma-heap,name = "vframe"; + dma-heap,secure; + dma-heap,protection_id = <5>; + dma-heap,alignment = <0x10000>; + }; + + video_scaler_dma_heap { + compatible = "samsung,dma-heap-chunk"; + memory-region = <&vscaler>; + dma-heap,name = "vscaler"; + dma-heap,secure; + dma-heap,protection_id = <6>; + dma-heap,alignment = <0x10000>; + }; + + tui_dma_heap { + compatible = "samsung,dma-heap-carveout"; + memory-region = <&tui>; + dma-heap,name = "tui"; + dma-heap,secure; + dma-heap,protection_id = <20>; + dma-heap,alignment = <0x10000>; + }; + + faceauth_tpu_dma_heap: faceauth_tpu_dma_heap { + compatible = "samsung,dma-heap-chunk"; + memory-region = <&faceauth_tpu>; + dma-heap,name = "faceauth_tpu"; + dma-heap,secure; + dma-heap,protection_id = <15>; + dma-heap,alignment = <0x10000>; + status = "disabled"; + }; + + faceauth_image_heap: faceauth_image_heap { + compatible = "samsung,dma-heap-cma"; + memory-region = <&faimg>; + dma-heap,name = "faimg"; + dma-heap,secure; + dma-heap,protection_id = <16>; + dma-heap,alignment = <0x10000>; + status = "disabled"; + }; + + faceauth_rawimage_heap: faceauth_rawimage_heap { + compatible = "samsung,dma-heap-cma"; + memory-region = <&farawimg>; + dma-heap,name = "farawimg"; + dma-heap,secure; + dma-heap,protection_id = <17>; + dma-heap,alignment = <0x10000>; + status = "disabled"; + }; + + faceauth_preview_heap: faceauth_preview_heap { + compatible = "samsung,dma-heap-cma"; + memory-region = <&faprev>; + dma-heap,name = "faprev"; + dma-heap,secure; + dma-heap,protection_id = <18>; + dma-heap,alignment = <0x10000>; + status = "disabled"; + }; + + mfc_fw_dma_heap { + compatible = "samsung,dma-heap-carveout"; + memory-region = <&mfc_fw>; + dma-heap,name = "mfc_fw"; + dma-heap,secure; + dma-heap,protection_id = <2>; + dma-heap,alignment = <0x10000>; + }; +}; + +&reserved_memory { + #address-cells = <2>; + #size-cells = <1>; + + vstream: vstream { + compatible = "shared-dma-pool"; + reusable; + size = <0x4800000>; + alignment = <0x0 0x00010000>; + alloc-ranges = <0x9 0x80000000 0x80000000>, + <0x9 0x00000000 0x80000000>, + <0x8 0x80000000 0x80000000>, + <0x0 0x80000000 0x80000000>; + }; + + vframe: vframe { + compatible = "shared-dma-pool"; + size = <0x20000000>; + alignment = <0x0 0x00010000>; + alloc-ranges = <0x9 0x80000000 0x80000000>, + <0x9 0x00000000 0x80000000>, + <0x8 0x80000000 0x80000000>, + <0x0 0x80000000 0x80000000>; + reusable; + }; + + vscaler: vscaler { + compatible = "shared-dma-pool"; + size = <0x3400000>; + alignment = <0x0 0x00010000>; + alloc-ranges = <0x9 0x80000000 0x80000000>, + <0x9 0x00000000 0x80000000>, + <0x8 0x80000000 0x80000000>, + <0x0 0x80000000 0x80000000>; + reusable; + }; + + tui: tui { + size = <0x3000000>; + alloc-ranges = <0x0 0x80000000 0x80000000>; + alignment = <0x0 0x00010000>; + }; + + xhci_dma: xhci_dma@97000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x97000000 0x400000>; + no-map; + }; + + faceauth_tpu: faceauth_tpu { + compatible = "shared-dma-pool"; + reusable; + size = <0x2000000>; + alignment = <0x0 0x00010000>; + alloc-ranges = <0x9 0x80000000 0x80000000>, + <0x9 0x00000000 0x80000000>, + <0x8 0x80000000 0x80000000>, + <0x0 0x80000000 0x80000000>; + status = "disabled"; + }; + + famodel: famodel { + size = <0x4B00000>; + alignment = <0x0 0x00010000>; + alloc-ranges = <0x9 0x80000000 0x80000000>, + <0x9 0x00000000 0x80000000>, + <0x8 0x80000000 0x80000000>, + <0x0 0x80000000 0x80000000>; + status = "disabled"; + }; + + faimg: faimg { + compatible = "shared-dma-pool"; + reusable; + size = <0x3C00000>; + alignment = <0x0 0x00010000>; + alloc-ranges = <0x9 0x80000000 0x80000000>, + <0x9 0x00000000 0x80000000>, + <0x8 0x80000000 0x80000000>, + <0x0 0x80000000 0x80000000>; + status = "disabled"; + }; + + farawimg: farawimg { + compatible = "shared-dma-pool"; + reusable; + size = <0x10000000>; + alignment = <0x0 0x00010000>; + alloc-ranges = <0x9 0x80000000 0x80000000>, + <0x9 0x00000000 0x80000000>, + <0x8 0x80000000 0x80000000>, + <0x0 0x80000000 0x80000000>; + status = "disabled"; + }; + + faprev: faprev { + compatible = "shared-dma-pool"; + reusable; + size = <0x3000000>; + alignment = <0x0 0x00010000>; + alloc-ranges = <0x9 0x80000000 0x80000000>, + <0x9 0x00000000 0x80000000>, + <0x8 0x80000000 0x80000000>, + <0x0 0x80000000 0x80000000>; + status = "disabled"; + }; + + mfc_fw: mfc_fw { + size = <0x210000>; + alloc-ranges = <0x0 0x80000000 0x80000000>; + alignment = <0x0 0x00010000>; + }; +};
diff --git a/dts/gs101-faceauth-dma-heap.dtsi b/dts/gs101-faceauth-dma-heap.dtsi new file mode 100644 index 0000000..434c391 --- /dev/null +++ b/dts/gs101-faceauth-dma-heap.dtsi
@@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * GS101 SoC Faceauth-HEAP + * + * Copyright 2021 Google LLC + */ + +&faceauth_tpu_dma_heap { + status = "okay"; +}; + +&faceauth_rawimage_heap { + status = "okay"; +}; + +&faceauth_preview_heap { + status = "okay"; +}; + +&faceauth_model_heap { + status = "okay"; +}; + +&faceauth_tpu { + status = "okay"; +}; + +&famodel { + status = "okay"; +}; + +&farawimg { + status = "okay"; +}; + +&faprev { + status = "okay"; +};
diff --git a/dts/gs101-fake-battery-data.dtsi b/dts/gs101-fake-battery-data.dtsi new file mode 100644 index 0000000..810425a --- /dev/null +++ b/dts/gs101-fake-battery-data.dtsi
@@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Battery device tree entries + * + * Copyright 2020 Google LLC + * + */ + +maxim,config { + /* for fake battery: 0xAA */ + maxim,default-fake-batt { + maxim,batt-id-kohm = <170>; + maxim,model-version = <2>; + maxim,force-reset-model-data; + maxim,fg-model = /bits/ 16 < + 0x9760 0xa510 0xb100 0xb600 0xb7a0 0xb900 0xba70 0xbc70 + 0xbde0 0xbfc0 0xc250 0xc510 0xc990 0xcea0 0xd040 0xd750 + 0x0060 0x0120 0x0200 0x0710 0x0e80 0x0df0 0x1430 0x1bd0 + 0x1520 0x0d70 0x0950 0x08e0 0x0800 0x0780 0x06b0 0x01e0 + 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 + 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 + >; + maxim,fg-params = /bits/ 16 < + /* 0x0036 */ 0xf060 /* IAvgEmpty */ + /* 0x002a */ 0x2038 /* RelaxCFG */ + /* 0x0028 */ 0x260E /* LearnCFG */ + /* 0x001D */ 0x4217 /* Config */ + /* 0x00BB */ 0x0090 /* Config2 */ + /* 0x0013 */ 0x5F00 /* FullSOCthr */ + /* 0x0035 */ 0x08D6 /* FullCAPRep */ + /* 0x0018 */ 0x08D6 /* DesignCap */ + /* 0x0046 */ 0x0c80 /* dPacc */ + /* 0x0045 */ 0x008D /* dQacc */ + /* 0x0023 */ 0x08D6 /* FullCAPNom */ + /* 0x003A */ 0xA561 /* V_empty */ + /* 0x0012 */ 0x1100 /* QResidual00 */ + /* 0x0022 */ 0x0800 /* QResidual10 */ + /* 0x0032 */ 0x0301 /* QResidual20 */ + /* 0x0042 */ 0x0302 /* QResidual30 */ + /* 0x0038 */ 0x0700 /* RCOMP0 */ + /* 0x0039 */ 0x223E /* TempCo */ + /* 0x001E */ 0x02d3 /* ICHGTerm */ + /* 0x002C */ 0xED51 /* TGain */ + /* 0x002D */ 0x1EBA /* TOff */ + /* 0x00B9 */ 0x0014 /* Curve */ + /* 0x002B */ 0x3870 /* MiscCFG */ + /* 0x0004 */ 0x0000 /* AtRate */ + /* 0x0049 */ 0x2241 /* convgcfg */ + /* 0x0029 */ 0xc623 /* FilterCFG */ + /* 0x003c */ 0x2D00 /* TaskPeriod */ + >; + }; +};
diff --git a/dts/gs101-pinctrl.h b/dts/gs101-pinctrl.h new file mode 100644 index 0000000..7a0c840 --- /dev/null +++ b/dts/gs101-pinctrl.h
@@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Pinctrl binding constants for GS101 + * + * Copyright (c) 2020-2021 Google, LLC. + */ + +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__ +#define __DT_BINDINGS_PINCTRL_GS101_H__ + +/* GS101 drive strengths */ +#define GS101_PIN_DRV_2_5_MA 0 +#define GS101_PIN_DRV_5_MA 1 +#define GS101_PIN_DRV_7_5_MA 2 +#define GS101_PIN_DRV_10_MA 3 + +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */
diff --git a/dts/gs101-trusty.dtsi b/dts/gs101-trusty.dtsi new file mode 100644 index 0000000..2d4b8d2 --- /dev/null +++ b/dts/gs101-trusty.dtsi
@@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google Slider Board device tree source + * + * Copyright 2019-2020 Google LLC + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + trusty: trusty { + compatible = "android,trusty-smc-v1"; + + irq { + compatible = "android,trusty-irq-v1"; + ipi-range = <8 15 8>; + }; + + log { + compatible = "android,trusty-log-v1"; + }; + + virtio { + compatible = "android,trusty-virtio-v1"; + }; + }; +};
diff --git a/dts/gs201-a0.dts b/dts/gs201-a0.dts new file mode 100644 index 0000000..a5cdf99 --- /dev/null +++ b/dts/gs201-a0.dts
@@ -0,0 +1,585 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Google LLC. + * + */ + +/dts-v1/; +/ { + /* soc revision info */ + soc_id = <0x09855000 0x00000000>; +}; + +#include "gs201.dtsi" + +&mfc { + ip_ver = <0x15060000>; + /* FW base security ctrl */ + security_ctrl = <1>; +}; +&mfc_core0 { + ip_ver = <0x15060000>; +}; + +&bts_smc0 { + reg = <0x0 0x2084F258 0x4>; +}; +&bts_smc1 { + reg = <0x0 0x2094F258 0x4>; +}; +&bts_smc2 { + reg = <0x0 0x20A4F258 0x4>; +}; +&bts_smc3 { + reg = <0x0 0x20B4F258 0x4>; +}; + +/ { + tmuctrl_0: BIG@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_TOP_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "BIG"; + id = <0>; + ect_nouse; + pause_enable; + resume_threshold = <110>; + pause_threshold = <115>; + pause_cpus = "6-7"; + hardlimit_enable; + hardlimit_clr_threshold = <103>; + hardlimit_threshold = <105>; + hardlimit_cooling_state = <THERMAL_NO_LIMIT>; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <50>; + i_max = <5>; + integral_cutoff = <0>; + sustainable_power = <2000>; + + tmu_work_affinity = "0-7"; + hotplug_work_affinity = "0-3"; + has-dfs-support; + }; + + tmuctrl_1: MID@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_TOP_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "MID"; + id = <1>; + ect_nouse; + pause_enable; + resume_threshold = <110>; + pause_threshold = <115>; + pause_cpus = "4-5"; + hardlimit_enable; + hardlimit_clr_threshold = <103>; + hardlimit_threshold = <105>; + hardlimit_cooling_state = <THERMAL_NO_LIMIT>; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <1000>; + + tmu_work_affinity = "0-7"; + hotplug_work_affinity = "0-3"; + }; + + tmuctrl_2: LITTLE@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_TOP_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "LITTLE"; + id = <2>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <200>; + + tmu_work_affinity = "0-7"; + }; + + tmuctrl_3: G3D@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_SUB_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "G3D"; + id = <3>; + ect_nouse; + hardlimit_enable; + hardlimit_clr_threshold = <103>; + hardlimit_threshold = <105>; + hardlimit_cooling_state = <THERMAL_NO_LIMIT>; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <200>; + + tmu_work_affinity = "0-7"; + }; + + tmuctrl_4: ISP@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_TOP_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "ISP"; + id = <4>; + ect_nouse; + #thermal-sensor-cells = <0>; + + tmu_work_affinity = "0-7"; + }; + + tmuctrl_5: TPU@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_SUB_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "TPU"; + id = <5>; + ect_nouse; + hardlimit_enable; + hardlimit_clr_threshold = <103>; + hardlimit_threshold = <105>; + hardlimit_cooling_state = <THERMAL_NO_LIMIT>; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <200>; + + tmu_work_affinity = "0-7"; + }; + + tmuctrl_6: AUR@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_SUB_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "AUR"; + id = <6>; + ect_nouse; + hardlimit_enable; + hardlimit_clr_threshold = <103>; + hardlimit_threshold = <105>; + hardlimit_cooling_state = <THERMAL_NO_LIMIT>; + #thermal-sensor-cells = <0>; + tmu_work_affinity = "0-7"; + }; + + thermal_zones: thermal-zones { + big_thermal: BIG { + zone_name = "BIG_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_0>; + + trips { + big_cold: big-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + big_switch_on: big-switch-on { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_control_temp: big-control-temp { + temperature = <95000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + big_alert1: big-alert1 { + temperature = <98000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + big_alert2: big-alert2 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_alert3: big-alert3 { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_dfs: big-dfs { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + big_hot: big-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&big_control_temp>; + cooling-device = <&cpufreq_domain2 0 0>; + }; + }; + }; + mid_thermal: MID { + zone_name = "MID_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_1>; + + trips { + mid_cold: mid-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + mid_switch_on: mid-switch-on { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_control_temp: mid-control-temp { + temperature = <95000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + mid_alert1: mid-alert1 { + temperature = <98000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + mid_alert2: mid-alert2 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_alert3: mid-alert3 { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_dfs: mid-dfs { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + mid_hot: mid-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&mid_control_temp>; + cooling-device = <&cpufreq_domain1 0 0>; + }; + }; + }; + little_thermal: LITTLE { + zone_name = "LITTLE_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_2>; + + trips { + little_cold: little-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_switch_on: little-switch-on { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_control_temp: little-control-temp { + temperature = <95000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + little_alert1: little-alert1 { + temperature = <98000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + little_alert2: little-alert2 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_alert5: little-alert5 { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_alert6: little-alert6 { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_hot: little-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&little_control_temp>; + cooling-device = <&cpufreq_domain0 0 0>; + }; + }; + }; + gpu_thermal: G3D { + zone_name = "G3D_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_3>; + + trips { + gpu_cold: gpu-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + gpu_switch_on: gpu-switch-on { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_control_temp: gpu-control-temp { + temperature = <95000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + gpu_alert0: gpu-alert0 { + temperature = <98000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_alert1: gpu-alert1 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_alert2: gpu-alert2 { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_dfs: gpu-dfs { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + gpu_hot: gpu-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&gpu_control_temp>; + cooling-device = <&mali + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + isp_thermal: ISP { + zone_name = "ISP_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_4>; + + trips { + isp_alert0: isp-alert0 { + temperature = <20000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_alert1: isp-alert1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + isp_alert2: isp-alert2 { + temperature = <95000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_alert3: isp-alert3 { + temperature = <98000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + isp_alert4: isp-alert4 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + isp_alert5: isp-alert5 { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + isp_alert6: isp-alert6 { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_hot: isp-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + }; + tpu_thermal: TPU { + zone_name = "TPU_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_5>; + + trips { + tpu_cold: tpu-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + tpu_switch_on: tpu-switch-on { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_control_temp: tpu-control-temp { + temperature = <95000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + tpu_alert0: tpu-alert0 { + temperature = <98000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_alert1: tpu-alert1 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_alert2: tpu-alert2 { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_dfs: tpu-dfs { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + tpu_hot: tpu-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&tpu_control_temp>; + cooling-device = <&tpu_cooling 0 0>; + }; + }; + }; + aur_thermal: AUR { + zone_name = "AUR_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_6>; + + trips { + aur_alert0: aur-alert0 { + temperature = <20000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + aur_switch_on: aur-switch-on { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + aur_control_temp: aur-control-temp { + temperature = <95000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + aur_alert3: aur-alert3 { + temperature = <98000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + aur_alert4: aur-alert4 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + aur_hardlimit: aur-hardlimit { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + aur_dfs: aur-dfs { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + aur_hot: aur-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&aur_control_temp>; + cooling-device = <&gxp_cooling 0 0>; + }; + }; + }; + }; +};
diff --git a/dts/gs201-aoc.dtsi b/dts/gs201-aoc.dtsi new file mode 100644 index 0000000..dce2dcf --- /dev/null +++ b/dts/gs201-aoc.dtsi
@@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AoC device tree source + * + * Copyright 2019 Google,LLC. + */ + +/ { + mbox_aoc: mbox@176a0000 { + compatible = "google,mailbox-whitechapel"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0x0 0x18300000 0x1000>; + interrupts = <GIC_SPI IRQ_MAILBOX_AOCA322AP_ALIVE + IRQ_TYPE_LEVEL_HIGH>; + mbox-name = "aoc2ap"; + #mbox-cells = <1>; + + wc-mbox-non-wake-channels = <0x7000>; + }; + + mbox_aoc_f1: mbox@18320000 { + compatible = "google,mailbox-whitechapel"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0x0 0x18320000 0x1000>; + interrupts = <GIC_SPI IRQ_MAILBOX_AOCF12AP_ALIVE + IRQ_TYPE_LEVEL_HIGH>; + mbox-name = "aoc_f1_ap"; + #mbox-cells = <1>; + + wc-mbox-non-wake-channels = <0xF000>; + }; + + mbox_aoc_p6: mbox@18340000 { + compatible = "google,mailbox-whitechapel"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0x0 0x18340000 0x1000>; + interrupts = <GIC_SPI IRQ_MAILBOX_AOCP62AP_ALIVE + IRQ_TYPE_LEVEL_HIGH>; + mbox-name = "aoc_p6_ap"; + #mbox-cells = <1>; + + wc-mbox-non-wake-channels = <0xF000>; + }; + + pinctrl@10840000 { + aoc_vsync_pins: aoc-vsync-pins { + /* go/p22-gpio */ + samsung,pins = "gpp3-1", "gpp5-1", "gpp7-1", "gpp9-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + }; + }; + + aoc: aoc@19000000 { + compatible = "google,aoc"; + + reg = <0x0 0x19000000 0x01000000>, + <0x0 0x181D0000 0x00001000>, + <0x0 0x1A0B0000 0x00001000>, + <0x0 0x1A060000 0x00005000>; + + reg-names = "blk_aoc", "aoc_req", "aoc_s2mpu", "ssmt_aoc"; + + interrupts = <GIC_SPI IRQ_AOC_Watchdog_CPU_AOC + IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "watchdog"; + + pinctrl-names = "default"; + pinctrl-0 = <&aoc_vsync_pins>; + + gsa-enabled = "true"; + + iommus = <&sysmmu_asoc>; + memory-region = <&aoc_reserve>; + samsung,iommu-group = <&iommu_group_aoc>; + + mbox-channels = <48>; + mbox-names = "aoc2ap", "aoc_f1_ap"; + mboxes = <&mbox_aoc 0 + &mbox_aoc 1 + &mbox_aoc 2 + &mbox_aoc 3 + &mbox_aoc 4 + &mbox_aoc 5 + &mbox_aoc 6 + &mbox_aoc 7 + &mbox_aoc 8 + &mbox_aoc 9 + &mbox_aoc 10 + &mbox_aoc 11 + &mbox_aoc 12 + &mbox_aoc 13 + &mbox_aoc 14 + &mbox_aoc 15 + &mbox_aoc_f1 0 + &mbox_aoc_f1 1 + &mbox_aoc_f1 2 + &mbox_aoc_f1 3 + &mbox_aoc_f1 4 + &mbox_aoc_f1 5 + &mbox_aoc_f1 6 + &mbox_aoc_f1 7 + &mbox_aoc_f1 8 + &mbox_aoc_f1 9 + &mbox_aoc_f1 10 + &mbox_aoc_f1 11 + &mbox_aoc_f1 12 + &mbox_aoc_f1 13 + &mbox_aoc_f1 14 + &mbox_aoc_f1 15 + &mbox_aoc_p6 0 + &mbox_aoc_p6 1 + &mbox_aoc_p6 2 + &mbox_aoc_p6 3 + &mbox_aoc_p6 4 + &mbox_aoc_p6 5 + &mbox_aoc_p6 6 + &mbox_aoc_p6 7 + &mbox_aoc_p6 8 + &mbox_aoc_p6 9 + &mbox_aoc_p6 10 + &mbox_aoc_p6 11 + &mbox_aoc_p6 12 + &mbox_aoc_p6 13 + &mbox_aoc_p6 14 + &mbox_aoc_p6 15 + >; + + acpm-ipc-channel = <13>; + + force-vnom = <0>; + + gsa-device = <&gsa>; + + pcu-base = <0xA00000>; + gpio-base = <0xD70000>; + pcu-db-set-offset = <0xD004>; + pcu-db-clr-offset = <0xD008>; + cp-aperture-start-offset = <0x7FDF80>; + cp-aperture-end-offset = <0x7FFFFF>; + clock-divider = <1>; + + channel-max-pending-msgs = <128>; + block-channel-threshold = <64>; + + notify-on-state-transition = "true"; + hotword-supported = "true"; + chre-supported = "true"; + }; + aoc_gpiochip: aoc_gpiochip { + compatible = "google,aoc_uwb_rst"; + gpio-controller; + #gpio-cells = <2>; + ngpio = <1>; + }; + +};
diff --git a/dts/gs201-b0.dts b/dts/gs201-b0.dts new file mode 100644 index 0000000..6c09a60 --- /dev/null +++ b/dts/gs201-b0.dts
@@ -0,0 +1,685 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS201 SoC silicon revision B0 + * + * Copyright 2020-2022 Google LLC. + * + */ + +/dts-v1/; +/ { + /* soc revision info */ + /* The bootloader combines the value 0x09855000 of the product id + * register with the value 0x1 of the major revision register before it + * compares the combined value with the first word of the soc_id + * property. + */ + soc_id = <0x09855001 0x00000000>; +}; + +#include "gs201.dtsi" +#include "gs201-sysmmu_sync.dtsi" + +&mfc { + ip_ver = <0x15060000>; + /* FW base security ctrl */ + security_ctrl = <1>; +}; +&mfc_core0 { + ip_ver = <0x15060000>; +}; + +&bts_smc0 { + reg = <0x0 0x2084F258 0x4>; +}; +&bts_smc1 { + reg = <0x0 0x2094F258 0x4>; +}; +&bts_smc2 { + reg = <0x0 0x20A4F258 0x4>; +}; +&bts_smc3 { + reg = <0x0 0x20B4F258 0x4>; +}; + +&s2mpu_aur_idma { + sysmmu_syncs = <&sysmmu_sync_aur_idma>; +}; +&s2mpu_aur_inst_data { + sysmmu_syncs = <&sysmmu_sync_aur_inst_data>; +}; +&s2mpu_bo { + sysmmu_syncs = <&sysmmu_sync_bo>; +}; +&s2mpu_cpucl0 { + sysmmu_syncs = <&sysmmu_sync_cpucl0>; +}; +&s2mpu_csis0 { + sysmmu_syncs = <&sysmmu_sync_csis0>; +}; +&s2mpu_csis1 { + sysmmu_syncs = <&sysmmu_sync_csis1>; +}; +&s2mpu_dns { + sysmmu_syncs = <&sysmmu_sync_dns>; +}; +&s2mpu_dpu0 { + sysmmu_syncs = <&sysmmu_sync_dpu0>; +}; +&s2mpu_dpu1 { + sysmmu_syncs = <&sysmmu_sync_dpu1>; +}; +&s2mpu_dpu2 { + sysmmu_syncs = <&sysmmu_sync_dpu2>; +}; +&s2mpu_eh { + sysmmu_syncs = <&sysmmu_sync_eh>; +}; +&s2mpu_g2d0 { + sysmmu_syncs = <&sysmmu_sync_g2d0>; +}; +&s2mpu_g2d1 { + sysmmu_syncs = <&sysmmu_sync_g2d1>; +}; +&s2mpu_g2d2 { + sysmmu_syncs = <&sysmmu_sync_g2d2>; +}; +&s2mpu_g3aa { + sysmmu_syncs = <&sysmmu_sync_g3aa>; +}; +&s2mpu_g3d { + sysmmu_syncs = <&sysmmu_sync_g3d0 &sysmmu_sync_g3d1 + &sysmmu_sync_g3d2 &sysmmu_sync_g3d3>; +}; +&s2mpu_gdc0 { + sysmmu_syncs = <&sysmmu_sync_gdc0>; +}; +&s2mpu_gdc1 { + sysmmu_syncs = <&sysmmu_sync_gdc1>; +}; +&s2mpu_gdc2 { + sysmmu_syncs = <&sysmmu_sync_gdc2>; +}; +&s2mpu_gsa { + sysmmu_syncs = <&sysmmu_sync_gsa>; +}; +&s2mpu_hsi0 { + sysmmu_syncs = <&sysmmu_sync_hsi0>; +}; +&s2mpu_hsi1 { + sysmmu_syncs = <&sysmmu_sync_hsi1>; +}; +&s2mpu_hsi2 { + sysmmu_syncs = <&sysmmu_sync_hsi2>; +}; +&s2mpu_ipp { + sysmmu_syncs = <&sysmmu_sync_ipp>; +}; +&s2mpu_mcsc0 { + sysmmu_syncs = <&sysmmu_sync_mcsc0>; +}; +&s2mpu_mcsc1 { + sysmmu_syncs = <&sysmmu_sync_mcsc1>; +}; +&s2mpu_mcsc2 { + sysmmu_syncs = <&sysmmu_sync_mcsc2>; +}; +&s2mpu_mfc0 { + sysmmu_syncs = <&sysmmu_sync_mfc0>; +}; +&s2mpu_mfc1 { + sysmmu_syncs = <&sysmmu_sync_mfc1>; +}; +&s2mpu_misc { + sysmmu_syncs = <&sysmmu_sync_misc>; +}; +&s2mpu_tnr0 { + sysmmu_syncs = <&sysmmu_sync_tnr0>; +}; +&s2mpu_tnr1 { + sysmmu_syncs = <&sysmmu_sync_tnr1>; +}; +&s2mpu_tnr2 { + sysmmu_syncs = <&sysmmu_sync_tnr2>; +}; +&s2mpu_tnr3 { + sysmmu_syncs = <&sysmmu_sync_tnr3>; +}; +&s2mpu_tnr4 { + sysmmu_syncs = <&sysmmu_sync_tnr4>; +}; + +/ { + tmuctrl_0: BIG@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_TOP_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "BIG"; + id = <0>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <50>; + i_max = <2>; + integral_cutoff = <10>; + sustainable_power = <2000>; + control_temp_step = <100>; + + tmu_work_affinity = "0-7"; + hotplug_work_affinity = "0-3"; + has-dfs-support; + dfs_throttled_cpus = "4-7"; + }; + + tmuctrl_1: MID@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_TOP_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "MID"; + id = <1>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <1000>; + control_temp_step = <100>; + + tmu_work_affinity = "0-7"; + hotplug_work_affinity = "0-3"; + has-dfs-support; + dfs_throttled_cpus = "4-7"; + }; + + tmuctrl_2: LITTLE@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_TOP_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "LITTLE"; + id = <2>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <40>; + k_pu = <40>; + k_i = <0>; + i_max = <0>; + sustainable_power = <350>; + control_temp_step = <100>; + + tmu_work_affinity = "0-7"; + }; + + tmuctrl_3: G3D@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_SUB_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "G3D"; + id = <3>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <200>; + control_temp_step = <100>; + + tmu_work_affinity = "0-7"; + has-dfs-support; + }; + + tmuctrl_4: ISP@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_TOP_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "ISP"; + id = <4>; + ect_nouse; + #thermal-sensor-cells = <0>; + + tmu_work_affinity = "0-7"; + }; + + tmuctrl_5: TPU@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_SUB_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "TPU"; + id = <5>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <200>; + control_temp_step = <100>; + + tmu_work_affinity = "0-7"; + has-dfs-support; + }; + + tmuctrl_6: AUR@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_SUB_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "AUR"; + id = <6>; + ect_nouse; + hardlimit_enable; + hardlimit_clr_threshold = <103>; + hardlimit_threshold = <105>; + hardlimit_cooling_state = <THERMAL_NO_LIMIT>; + #thermal-sensor-cells = <0>; + tmu_work_affinity = "0-7"; + }; + + thermal_zones: thermal-zones { + big_thermal: BIG { + zone_name = "BIG_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_0>; + + trips { + big_cold: big-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + big_switch_on: big-switch-on { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_control_temp: big-control-temp { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + big_pre_switch_on: big-pre-switch-on { + temperature = <55000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_alert2: big-alert2 { + temperature = <104000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_alert3: big-alert3 { + temperature = <106000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_dfs: big-dfs { + temperature = <110000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + big_hot: big-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&big_control_temp>; + cooling-device = <&cpufreq_domain2 0 0>; + }; + }; + }; + mid_thermal: MID { + zone_name = "MID_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_1>; + + trips { + mid_cold: mid-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + mid_switch_on: mid-switch-on { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_control_temp: mid-control-temp { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + mid_pre_switch_on: mid-pre-switch-on { + temperature = <55000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_alert2: mid-alert2 { + temperature = <104000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_alert3: mid-alert3 { + temperature = <106000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_dfs: mid-dfs { + temperature = <110000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + mid_hot: mid-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&mid_control_temp>; + cooling-device = <&cpufreq_domain1 0 0>; + }; + }; + }; + little_thermal: LITTLE { + zone_name = "LITTLE_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_2>; + + trips { + little_cold: little-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_switch_on: little-switch-on { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_control_temp: little-control-temp { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + little_pre_switch_on: little-pre-switch-on { + temperature = <55000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_alert2: little-alert2 { + temperature = <104000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_alert5: little-alert5 { + temperature = <106000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_alert6: little-alert6 { + temperature = <110000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_hot: little-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&little_control_temp>; + cooling-device = <&cpufreq_domain0 0 0>; + }; + }; + }; + gpu_thermal: G3D { + zone_name = "G3D_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_3>; + + trips { + gpu_cold: gpu-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + gpu_switch_on: gpu-switch-on { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_control_temp: gpu-control-temp { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + gpu_alert0: gpu-alert0 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_alert1: gpu-alert1 { + temperature = <104000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_alert2: gpu-alert2 { + temperature = <106000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_dfs: gpu-dfs { + temperature = <110000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + gpu_hot: gpu-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&gpu_control_temp>; + cooling-device = <&mali + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + isp_thermal: ISP { + zone_name = "ISP_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_4>; + + trips { + isp_alert0: isp-alert0 { + temperature = <20000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_alert1: isp-alert1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + isp_alert2: isp-alert2 { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_alert3: isp-alert3 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + isp_alert4: isp-alert4 { + temperature = <104000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + isp_alert5: isp-alert5 { + temperature = <106000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + isp_alert6: isp-alert6 { + temperature = <110000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_hot: isp-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + }; + tpu_thermal: TPU { + zone_name = "TPU_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_5>; + + trips { + tpu_cold: tpu-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + tpu_switch_on: tpu-switch-on { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_control_temp: tpu-control-temp { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + tpu_alert0: tpu-alert0 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_alert1: tpu-alert1 { + temperature = <104000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_alert2: tpu-alert2 { + temperature = <106000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_dfs: tpu-dfs { + temperature = <110000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + tpu_hot: tpu-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&tpu_control_temp>; + cooling-device = <&tpu_cooling 0 0>; + }; + }; + }; + aur_thermal: AUR { + zone_name = "AUR_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_6>; + + trips { + aur_alert0: aur-alert0 { + temperature = <20000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + aur_switch_on: aur-switch-on { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + aur_control_temp: aur-control-temp { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + aur_alert3: aur-alert3 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + aur_alert4: aur-alert4 { + temperature = <104000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + aur_hardlimit: aur-hardlimit { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + aur_dfs: aur-dfs { + temperature = <110000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + aur_hot: aur-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&aur_control_temp>; + cooling-device = <&gxp_cooling 0 6>; + }; + }; + }; + }; +};
diff --git a/dts/gs201-b0_v2-ipop.dts b/dts/gs201-b0_v2-ipop.dts new file mode 100644 index 0000000..9cfa37a --- /dev/null +++ b/dts/gs201-b0_v2-ipop.dts
@@ -0,0 +1,789 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS201 SoC silicon revision B0 + * + * Copyright 2020-2022 Google LLC. + * + */ + +/dts-v1/; +/ { + /* List of SoCs that this device tree is compatible with */ + soc_compatible { + B0_IPOP { + description = "B0,IPOP"; + product_id = <0x09855>; + major = <0x1>; + minor = <0x0>; + pkg_mode = <0x1>; + }; + }; +}; + +#include "gs201.dtsi" + +&mfc { + ip_ver = <0x15060000>; + /* FW base security ctrl */ + security_ctrl = <1>; +}; +&mfc_core0 { + ip_ver = <0x15060000>; +}; + +&bts_smc0 { + reg = <0x0 0x2084F258 0x4>; +}; +&bts_smc1 { + reg = <0x0 0x2094F258 0x4>; +}; +&bts_smc2 { + reg = <0x0 0x20A4F258 0x4>; +}; +&bts_smc3 { + reg = <0x0 0x20B4F258 0x4>; +}; + +/ { + tmuctrl_0: BIG@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_TOP_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "BIG"; + id = <0>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <50>; + i_max = <2>; + integral_cutoff = <10>; + sustainable_power = <2000>; + control_temp_step = <25>; + + tmu_work_affinity = "0-7"; + hotplug_work_affinity = "0-3"; + has-dfs-support; + dfs_throttled_cpus = "4-7"; + }; + + tmuctrl_1: MID@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_TOP_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "MID"; + id = <1>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <1000>; + control_temp_step = <25>; + + tmu_work_affinity = "0-7"; + hotplug_work_affinity = "0-3"; + has-dfs-support; + dfs_throttled_cpus = "4-7"; + }; + + tmuctrl_2: LITTLE@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_TOP_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "LITTLE"; + id = <2>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <40>; + k_pu = <40>; + k_i = <0>; + i_max = <0>; + sustainable_power = <350>; + control_temp_step = <25>; + + tmu_work_affinity = "0-7"; + }; + + tmuctrl_3: G3D@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_SUB_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "G3D"; + id = <3>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <200>; + control_temp_step = <25>; + + tmu_work_affinity = "0-7"; + has-dfs-support; + }; + + tmuctrl_4: ISP@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_TOP_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "ISP"; + id = <4>; + ect_nouse; + #thermal-sensor-cells = <0>; + + tmu_work_affinity = "0-7"; + }; + + tmuctrl_5: TPU@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_SUB_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "TPU"; + id = <5>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <200>; + control_temp_step = <25>; + + tmu_work_affinity = "0-7"; + has-dfs-support; + }; + + tmuctrl_6: AUR@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = <GIC_SPI IRQ_TMU_TMU_SUB_MISC IRQ_TYPE_LEVEL_HIGH>; + tmu_name = "AUR"; + id = <6>; + ect_nouse; + #thermal-sensor-cells = <0>; + tmu_work_affinity = "0-7"; + }; + + thermal_zones: thermal-zones { + big_thermal: BIG { + zone_name = "BIG_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_0>; + + trips { + big_cold: big-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + big_switch_on: big-switch-on { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_control_temp: big-control-temp { + temperature = <90000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + big_pre_switch_on: big-pre-switch-on { + temperature = <55000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_alert2: big-alert2 { + temperature = <94000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_alert3: big-alert3 { + temperature = <96000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_dfs: big-dfs { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + big_hot: big-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&big_control_temp>; + cooling-device = <&cpufreq_domain2 0 0>; + }; + }; + }; + mid_thermal: MID { + zone_name = "MID_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_1>; + + trips { + mid_cold: mid-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + mid_switch_on: mid-switch-on { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_control_temp: mid-control-temp { + temperature = <90000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + mid_pre_switch_on: mid-pre-switch-on { + temperature = <55000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_alert2: mid-alert2 { + temperature = <94000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_alert3: mid-alert3 { + temperature = <96000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_dfs: mid-dfs { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + mid_hot: mid-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&mid_control_temp>; + cooling-device = <&cpufreq_domain1 0 0>; + }; + }; + }; + little_thermal: LITTLE { + zone_name = "LITTLE_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_2>; + + trips { + little_cold: little-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_switch_on: little-switch-on { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_control_temp: little-control-temp { + temperature = <90000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + little_pre_switch_on: little-pre-switch-on { + temperature = <55000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_alert2: little-alert2 { + temperature = <94000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_alert5: little-alert5 { + temperature = <96000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_alert6: little-alert6 { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_hot: little-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&little_control_temp>; + cooling-device = <&cpufreq_domain0 0 0>; + }; + }; + }; + gpu_thermal: G3D { + zone_name = "G3D_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_3>; + + trips { + gpu_cold: gpu-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + gpu_switch_on: gpu-switch-on { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_control_temp: gpu-control-temp { + temperature = <90000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + gpu_alert0: gpu-alert0 { + temperature = <92000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_alert1: gpu-alert1 { + temperature = <94000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_alert2: gpu-alert2 { + temperature = <96000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_dfs: gpu-dfs { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + gpu_hot: gpu-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&gpu_control_temp>; + cooling-device = <&mali + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + isp_thermal: ISP { + zone_name = "ISP_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_4>; + + trips { + isp_alert0: isp-alert0 { + temperature = <20000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_alert1: isp-alert1 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + isp_alert2: isp-alert2 { + temperature = <90000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + isp_alert3: isp-alert3 { + temperature = <92000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + isp_alert4: isp-alert4 { + temperature = <94000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + isp_alert5: isp-alert5 { + temperature = <96000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + isp_alert6: isp-alert6 { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + isp_hot: isp-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + }; + tpu_thermal: TPU { + zone_name = "TPU_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_5>; + + trips { + tpu_cold: tpu-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + tpu_switch_on: tpu-switch-on { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_control_temp: tpu-control-temp { + temperature = <90000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + tpu_alert0: tpu-alert0 { + temperature = <92000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + tpu_alert1: tpu-alert1 { + temperature = <94000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_alert2: tpu-alert2 { + temperature = <96000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_dfs: tpu-dfs { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + tpu_hot: tpu-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&tpu_control_temp>; + cooling-device = <&tpu_cooling 0 0>; + }; + }; + }; + aur_thermal: AUR { + zone_name = "AUR_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_6>; + + trips { + aur_alert0: aur-alert0 { + temperature = <20000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + aur_alert1: aur-alert1 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + aur_alert2: aur-alert2 { + temperature = <90000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + aur_alert3: aur-alert3 { + temperature = <92000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + aur_alert4: aur-alert4 { + temperature = <94000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + aur_alert5: aur-alert5 { + temperature = <96000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + aur_alert6: aur-alert6 { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + aur_hot: aur-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&aur_alert2>; + cooling-device = <&gxp_cooling 0 6>; + }; + }; + }; + }; +}; + +&pixel_em_table { + profiles = + "default + cpu0 { + 300000 26 11000 + 574000 50 21000 + 738000 64 28000 + 930000 81 38000 + 1098000 96 54000 + 1197000 104 61000 + 1328000 116 70000 + 1401000 122 79000 + 1598000 140 103000 + 1704000 149 118000 + 1803000 158 131000 + } + cpu4 { + 400000 129 56000 + 553000 179 85000 + 696000 226 114000 + 799000 259 138000 + 910000 295 166000 + 1024000 332 203000 + 1197000 388 260000 + 1328000 431 308000 + 1491000 484 384000 + 1663000 540 510000 + 1836000 596 615000 + 1999000 649 757000 + 2130000 692 908000 + 2253000 732 1086000 + 2348000 763 1262000 + } + cpu6 { + 500000 179 115000 + 851000 305 194000 + 984000 353 237000 + 1106000 397 283000 + 1277000 458 371000 + 1426000 512 464000 + 1582000 568 556000 + 1745000 626 682000 + 1826000 656 755000 + 2048000 735 960000 + 2188000 786 1116000 + 2252000 809 1219000 + 2401000 862 1495000 + 2507000 900 1721000 + 2630000 944 2034000 + 2704000 971 2247000 + 2802000 1006 2598000 + 2850000 1024 2774000 + } + ", + "cam1 + cpu0 { + 300000 45 6000 + 574000 73 9000 + 738000 88 18000 + 930000 102 36000 + 1098000 109 45000 + 1197000 118 56000 + 1328000 127 77000 + 1401000 134 80000 + 1598000 141 116000 + 1704000 157 138000 + 1803000 166 168000 + } + cpu4 { + 400000 135 41000 + 553000 171 53000 + 696000 191 61000 + 799000 201 86000 + 910000 221 99000 + 1024000 239 117000 + 1197000 268 145000 + 1328000 299 163000 + 1491000 366 209000 + 1663000 405 249000 + 1836000 445 294000 + 1999000 497 351000 + 2130000 538 387000 + 2253000 578 489000 + 2348000 608 556000 + } + cpu6 { + 500000 204 98000 + 851000 325 148000 + 984000 346 165000 + 1106000 365 200000 + 1277000 385 245000 + 1426000 399 286000 + 1582000 423 322000 + 1745000 456 370000 + 1826000 488 399000 + 2048000 511 479000 + 2188000 566 551000 + 2252000 612 582000 + 2401000 686 689000 + 2507000 766 778000 + 2630000 858 899000 + 2704000 914 1005000 + 2802000 987 1146000 + 2850000 1024 1238000 + } + ", + "cam2 + cpu0 { + 300000 38 12000 + 574000 47 18000 + 738000 61 22000 + 930000 77 40000 + 1098000 92 77000 + 1197000 101 93000 + 1328000 114 112000 + 1401000 121 132000 + 1598000 141 171000 + 1704000 153 205000 + 1803000 166 239000 + } + cpu4 { + 400000 165 89000 + 553000 178 121000 + 696000 201 154000 + 799000 217 178000 + 910000 238 210000 + 1024000 285 240000 + 1197000 327 289000 + 1328000 357 334000 + 1491000 380 393000 + 1663000 419 466000 + 1836000 460 532000 + 1999000 521 633000 + 2130000 568 727000 + 2253000 615 841000 + 2348000 662 963000 + } + cpu6 { + 500000 193 208000 + 851000 267 314000 + 984000 295 360000 + 1106000 320 403000 + 1277000 357 482000 + 1426000 390 549000 + 1582000 419 606000 + 1745000 471 691000 + 1826000 497 739000 + 2048000 568 877000 + 2188000 620 1007000 + 2252000 650 1070000 + 2401000 720 1266000 + 2507000 781 1414000 + 2630000 842 1638000 + 2704000 902 1809000 + 2802000 963 2099000 + 2850000 1024 2262000 + } + ", + "ui + cpu0 { + 300000 60 24000 + 574000 114 52000 + 738000 147 72000 + 930000 185 101000 + 1098000 218 132000 + 1197000 238 155000 + 1328000 264 186000 + 1401000 278 204000 + 1598000 317 269000 + 1704000 338 309000 + 1803000 358 358000 + } + cpu4 { + 400000 146 85000 + 553000 202 131000 + 696000 254 184000 + 799000 292 227000 + 910000 333 278000 + 1024000 374 336000 + 1197000 437 440000 + 1328000 485 537000 + 1491000 545 658000 + 1663000 608 821000 + 1836000 671 1021000 + 1999000 730 1247000 + 2130000 778 1479000 + 2253000 823 1712000 + 2348000 858 1925000 + } + cpu6 { + 500000 180 165000 + 851000 306 340000 + 984000 354 422000 + 1106000 397 518000 + 1277000 459 650000 + 1426000 512 786000 + 1582000 568 944000 + 1745000 627 1157000 + 1826000 656 1265000 + 2048000 736 1608000 + 2188000 786 1863000 + 2252000 809 2019000 + 2401000 863 2345000 + 2507000 901 2634000 + 2630000 945 3029000 + 2704000 972 3326000 + 2802000 1007 3797000 + 2850000 1024 4064000 + } + "; +}; +
diff --git a/dts/gs201-bigo.dtsi b/dts/gs201-bigo.dtsi new file mode 100644 index 0000000..428bc6e --- /dev/null +++ b/dts/gs201-bigo.dtsi
@@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Bigocean device tree source + * + * Copyright 2021 Google LLC. + * + */ + +#include <dt-bindings/clock/gs201.h> +/ { + bigocean: bigocean@1CB00000 { + compatible = "google,bigocean"; + status = "ok"; + reg = <0x0 0x1CB00000 0x550 + 0x0 0x1CA94000 0xa00>; + reg-names = "regs", "ssmt_pid"; + interrupts = <GIC_SPI IRQ_BO_XINT_BO IRQ_TYPE_LEVEL_HIGH>; + vpu-opp-table = <&vpu_opp_table>; + vpu-bw-table = <&vpu_bw_table>; + iommus = <&sysmmu_bo>; + samsung,iommu-group = <&iommu_group_bo>; + pt_id = "bigocean"; + power-domains = <&pd_bo>; + samsung,tzmp; + }; + + vpu_opp_table: vpu_opp_table { + opp-95000000 { + freq-khz = <95000>; + /* 1920x1088@30fps */ + load-pps = <61200>; + }; + opp-222000000 { + freq-khz = <222000>; + /* 1920x1088@60fps */ + load-pps = <122400>; + }; + opp-400000000 { + freq-khz = <400000>; + /* 4096x2160@30fps */ + load-pps = <259200>; + }; + opp-620000000 { + freq-khz = <620000>; + /* 4096x2160@60fps */ + load-pps = <518400>; + }; + }; + + vpu_bw_table: vpu_bw_table { + bw-1080p-30 { + rd-bw = <190000>; + wr-bw = <85000>; + pk-bw = <210000>; + load-pps = <61200>; + }; + bw-1080p-60 { + rd-bw = <340000>; + wr-bw = <165000>; + pk-bw = <410000>; + load-pps = <122400>; + }; + bw-2160p-30 { + rd-bw = <700000>; + wr-bw = <340000>; + pk-bw = <820000>; + load-pps = <259200>; + }; + bw-2160p-60 { + rd-bw = <6000000>; + wr-bw = <2000000>; + pk-bw = <8000000>; + load-pps = <518400>; + }; + }; +};
diff --git a/dts/gs201-bts.dtsi b/dts/gs201-bts.dtsi new file mode 100644 index 0000000..f0b9c28 --- /dev/null +++ b/dts/gs201-bts.dtsi
@@ -0,0 +1,1813 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SAMSUNG EXYNOS SoC BTS device tree source + * + * Copyright (c) 2018 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SAMSUNG EXYNOS SoC BTS device nodes are listed in this file. + * EXYNOS based board files should include this file. + * + */ + +#include <dt-bindings/soc/google/gs-bts.h> + +/ { + exynos-bts { + compatible = "samsung,exynos-bts"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + /* BUS1 to INT mapping table */ + bus1_int_map = < + /* + * bus1 int + * clk clk + *------------- + */ + 620000 533000 + 533000 465000 + 400000 332000 + 310000 267000 + 267000 200000 + 200000 155000 + 134000 100000 + >; + + list-scen = "default", + "mfc_uhd", + "mfc_uhd_10bit", + "mfc_8k_dec30", + "g3d_performance", + "tpu_performance", + "dp_default", + "camera_default", + "mfc_uhd_enc60"; + + rt-names = "DECON0", + "DECON1", + "DECON2", + "csi", + "ipp", + "g3aa"; + + /* TREX_D_NOCL0 */ + + bts_corem0{ + #address-cells = <2>; + #size-cells = <1>; + ranges; + reg = <0x0 0x1E4B4000 0x400>; + status = "okay"; + bts-type = <TREX_BTS>; + }; + bts_corem1{ + reg = <0x0 0x1E4C4000 0x400>; + status = "okay"; + bts-type = <TREX_BTS>; + }; + bts_corem2{ + reg = <0x0 0x1E4D4000 0x400>; + status = "okay"; + bts-type = <TREX_BTS>; + }; + bts_corem3{ + reg = <0x0 0x1E4E4000 0x400>; + status = "okay"; + bts-type = <TREX_BTS>; + }; + + /* SMC */ + bts_smc0: bts_smc0 { + /* reg is set in gs101-a0.dts and gs101-b0.dts */ + status = "okay"; + bts-type = <SMC_BTS>; + }; + bts_smc1: bts_smc1 { + /* reg is set in gs101-a0.dts and gs101-b0.dts */ + status = "okay"; + bts-type = <SMC_BTS>; + }; + bts_smc2: bts_smc2 { + /* reg is set in gs101-a0.dts and gs101-b0.dts */ + status = "okay"; + bts-type = <SMC_BTS>; + }; + bts_smc3: bts_smc3 { + /* reg is set in gs101-a0.dts and gs101-b0.dts */ + status = "okay"; + bts-type = <SMC_BTS>; + }; + + /* TREX_VC_NUM */ + bts_vc_num_0 { + reg = <0x0 0x1EA81000 0x4>; + status = "okay"; + bts-type = <INTERNAL_BTS>; + vc-string = "gsa, cssys, aoc, alive"; + }; + bts_vc_num_1 { + reg = <0x0 0x1EA81004 0x4>; + status = "okay"; + bts-type = <INTERNAL_BTS>; + vc-string = "na, na, hsi1, hs10"; + }; + bts_vc_num_2 { + reg = <0x0 0x1F601000 0x4>; + status = "okay"; + bts-type = <INTERNAL_BTS>; + vc-string = "dns, csis1, csis0, bo"; + }; + bts_vc_num_3 { + reg = <0x0 0x1F601004 0x4>; + status = "okay"; + bts-type = <INTERNAL_BTS>; + vc-string = "g2d0, dpu2, dpu1, dpu0"; + }; + bts_vc_num_4 { + reg = <0x0 0x1F601008 0x4>; + status = "okay"; + bts-type = <INTERNAL_BTS>; + vc-string = "gdc0, g3aa, g2d2, g2d1"; + }; + bts_vc_num_5 { + reg = <0x0 0x1F60100C 0x4>; + status = "okay"; + bts-type = <INTERNAL_BTS>; + vc-string = "ipp, hsi2, gdc2, gdc1"; + }; + bts_vc_num_6 { + reg = <0x0 0x1F601010 0x4>; + status = "okay"; + bts-type = <INTERNAL_BTS>; + vc-string = "mfc0, mcsc2, mcsc1, mcsc0"; + }; + bts_vc_num_7 { + reg = <0x0 0x1F601014 0x4>; + status = "okay"; + bts-type = <INTERNAL_BTS>; + vc-string = "tnr1, tnr0, misc, mfc1"; + }; + bts_vc_num_8 { + reg = <0x0 0x1F601018 0x4>; + status = "okay"; + bts-type = <INTERNAL_BTS>; + vc-string = "na, tnr4, tnr3, tnr2"; + }; + bts_vc_num_9 { + reg = <0x0 0x20511000 0x4>; + status = "okay"; + bts-type = <INTERNAL_BTS>; + vc-string = "gpu1, gpu0, aur1, aur0"; + }; + bts_vc_num_10 { + reg = <0x0 0x20511004 0x4>; + status = "okay"; + bts-type = <INTERNAL_BTS>; + vc-string = "tpu, gpummu, gpu3, gpu2"; + }; + bts_vc_num_11 { + reg = <0x0 0x1E501000 0x4>; + status = "okay"; + bts-type = <INTERNAL_BTS>; + vc-string = "cpu3, cpu2, cpu1, cpu0"; + }; + bts_vc_num_12 { + reg = <0x0 0x20512000 0x4>; + status = "okay"; + bts-type = <INTERNAL_BTS>; + vc-string = "pbcg_trex_d_nocl1a"; + }; + + /* TREX_D_NOCL2A */ + bts_nocl2a_0 { + reg = <0x0 0x1F5B2000 0x100>; + status = "okay"; + bts-type = <BUSC_BTS>; + }; + bts_nocl2a_1 { + reg = <0x0 0x1F5C2000 0x100>; + status = "okay"; + bts-type = <BUSC_BTS>; + }; + bts_nocl2a_2 { + reg = <0x0 0x1F5D2000 0x100>; + status = "okay"; + bts-type = <BUSC_BTS>; + }; + bts_nocl2a_3 { + reg = <0x0 0x1F5E2000 0x100>; + status = "okay"; + bts-type = <BUSC_BTS>; + }; + /* TREX_D_NOCL1A */ + bts_nocl1a_0 { + reg = <0x0 0x204C2000 0x100>; + status = "okay"; + bts-type = <BUSC_BTS>; + }; + bts_nocl1a_1 { + reg = <0x0 0x204D2000 0x100>; + status = "okay"; + bts-type = <BUSC_BTS>; + }; + bts_nocl1a_2 { + reg = <0x0 0x204E2000 0x100>; + status = "okay"; + bts-type = <BUSC_BTS>; + }; + bts_nocl1a_3 { + reg = <0x0 0x204F2000 0x100>; + status = "okay"; + bts-type = <BUSC_BTS>; + }; + /* TREX_D_NOCL1B */ + bts_nocl1b { + reg = <0x0 0x1EA62000 0x100>; + status = "okay"; + bts-type = <BUSC_BTS>; + }; + + /* TREX_D_NOCL2A */ + bts_bo { + reg = <0x0 0x1F400000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x10>; + wmo = <0x10>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_csis0 { + reg = <0x0 0x1F410000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0xC>; + awqos = <0xC>; + rmo = <0xFFFF>; + wmo = <0x40>; + qurgent_on = <0>; + qurgent_th_r = <0x10>; + qurgent_th_w = <0x10>; + blocking_on = <0>; + ex_qurgent_on = <1>; + }; + }; + bts_csis1 { + reg = <0x0 0x1F420000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0xC>; + awqos = <0xC>; + rmo = <0xFFFF>; + wmo = <0x40>; + qurgent_on = <0>; + qurgent_th_r = <0x10>; + qurgent_th_w = <0x10>; + blocking_on = <0>; + ex_qurgent_on = <1>; + }; + }; + bts_dns { + reg = <0x0 0x1F430000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0xF>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_dpu0 { + reg = <0x0 0x1F440000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0xC>; + qurgent_th_w = <0x6>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + }; + bts_dpu1 { + reg = <0x0 0x1F450000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + qurgent_th_w = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0xC>; + qurgent_th_w = <0x6>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + }; + bts_dpu2 { + reg = <0x0 0x1F460000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + wmo = <0x20>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + wmo = <0x20>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + wmo = <0x20>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + wmo = <0x20>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + wmo = <0x20>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + wmo = <0x20>; + qurgent_on = <1>; + qurgent_th_r = <0xC>; + qurgent_th_w = <0x6>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + }; + bts_gdc0 { + reg = <0x0 0x1F470000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0xA>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_gdc1 { + reg = <0x0 0x1F480000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0xA>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_gdc2 { + reg = <0x0 0x1F490000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0xA>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_g2d0 { + reg = <0x0 0x1F4A0000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_g2d1 { + reg = <0x0 0x1F4B0000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_g2d2 { + reg = <0x0 0x1F4C0000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_g3aa { + reg = <0x0 0x1F4D0000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0xC>; + awqos = <0xC>; + rmo = <0x8>; + wmo = <0x8>; + qurgent_on = <1>; + qurgent_th_r = <0x10>; + qurgent_th_w = <0x10>; + blocking_on = <0>; + }; + }; + bts_hsi2 { + reg = <0x0 0x1F4E0000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <0>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_ipp { + reg = <0x0 0x1F4F0000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0xC>; + awqos = <0xC>; + rmo = <0xFFFF>; + wmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x10>; + qurgent_th_w = <0x10>; + blocking_on = <0>; + }; + }; + bts_mcsc0 { + reg = <0x0 0x1F500000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_mcsc1 { + reg = <0x0 0x1F510000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_mcsc2 { + reg = <0x0 0x1F520000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_mfc0 { + reg = <0x0 0x1F530000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x10>; + wmo = <0x10>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x40>; + wmo = <0x40>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x10>; + wmo = <0x10>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x12>; + wmo = <0x12>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_mfc1 { + reg = <0x0 0x1F540000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x10>; + wmo = <0x10>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x40>; + wmo = <0x40>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x10>; + wmo = <0x10>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x12>; + wmo = <0x12>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_misc { + reg = <0x0 0x1F550000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0xF>; + wmo = <0xF>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_tnr0 { + reg = <0x0 0x1F560000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x6>; + wmo = <0x6>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x32>; + wmo = <0x9>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_tnr1 { + reg = <0x0 0x1F570000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x6>; + wmo = <0x6>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x32>; + wmo = <0x9>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_tnr2 { + reg = <0x0 0x1F580000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x6>; + wmo = <0x6>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x10>; + wmo = <0x1>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_tnr3 { + reg = <0x0 0x1F590000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x6>; + wmo = <0x6>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x10>; + wmo = <0x1>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_tnr4 { + reg = <0x0 0x1F5A0000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x6>; + wmo = <0x6>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x7>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + /* TREX_D_NOCL1A */ + bts_aur0 { + reg = <0x0 0x20400000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_aur1 { + reg = <0x0 0x20410000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_gpu0 { + reg = <0x0 0x20430000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_gpu1 { + reg = <0x0 0x20440000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_gpu2 { + reg = <0x0 0x20450000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_gpu3 { + reg = <0x0 0x20460000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_tpu { + reg = <0x0 0x20470000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x40>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + tpu_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x40>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + /* TREX_D_NOCL1B */ + bts_alive { + reg = <0x0 0x1EA00000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <0>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_aoc { + reg = <0x0 0x1EA10000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + qurgent_th_r = <0xF>; + qurgent_th_w = <0xF>; + blocking_on = <0>; + }; + }; + bts_cssys { + reg = <0x0 0x1EA20000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <0>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_gsa { + reg = <0x0 0x1EA30000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <0>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_hsi0 { + reg = <0x0 0x1EA40000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <0>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_hsi1 { + reg = <0x0 0x1EA50000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <0>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + /* TREX_D_CORE */ + bts_cpu0 { + reg = <0x0 0x1E400000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_cpu1 { + reg = <0x0 0x1E410000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_cpu2 { + reg = <0x0 0x1E420000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_cpu3 { + reg = <0x0 0x1E430000 0x100>; + status = "okay"; + bts-type = <IP_BTS>; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + }; +};
diff --git a/dts/gs201-cloudripper-battery.dtsi b/dts/gs201-cloudripper-battery.dtsi new file mode 100644 index 0000000..d4bd7d4 --- /dev/null +++ b/dts/gs201-cloudripper-battery.dtsi
@@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Battery device tree entries specific to raviole + * + * Copyright 2020 Google,LLC + * + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + fragment@battery { + target-path = "/"; + __overlay__ { + + google_battery: google,battery { + status = "okay"; + compatible = "google,battery"; + google,fg-psy-name = "maxfg"; + + /* charge table */ + google,chg-temp-limits = <0 100 200 420 460 480 550>; + google,chg-cv-limits = <4200000 4300000 4450000>; + google,chg-cc-limits = < + 30 10 0 + 50 30 30 + 100 70 50 + 80 50 50 + 50 50 0 + 30 0 0 + >; + + google,aact-cv-limits = <4200000 4300000 4450000>; + google,aact-temp-limits = <0 100 200 420 460 480 550>; + google,chg-aact-ecc = <0 300 1000>; + google,aact-cc-limits = < + 30 10 0 + 50 30 30 + 100 70 50 + 80 50 50 + 50 50 0 + 30 0 0 + 30 10 0 + 50 30 30 + 95 70 50 + 80 50 50 + 50 50 0 + 30 0 0 + 30 10 0 + 50 30 30 + 90 70 50 + 80 50 50 + 50 50 0 + 30 0 0 + >; + + google,ttf-temp-idx= <2>; + google,ttf-adapter = <1800>; + google,ttf-soc-table = <49 59 72 78 93 95 98 100>; + google,ttf-elap-table = <45 52 56 67 78 91 104 120>; + google,ttf-tier-table = <0 71 78>; + + /* IRDrop Compensation */ + google,fv-uv-resolution = <10000>; + /* NOTE: high value for DC charging */ + google,fv-uv-margin-dpct = <1025>; + /* tier switch */ + google,cv-range-accuracy = <20000>; + google,cv-otv-margin = <12000>; + google,cv-debounce-cnt = <3>; + google,cv-tier-ov-cnt = <10>; + google,cv-tier-switch-cnt = <3>; + + google,eeprom-pairing; + + /* rest charging */ + google,chg-rest-rate = <15>; + google,chg-rest-soc = <80>; + /* TRICKLE-DEFEND threshold */ + google,bd-trickle-recharge-soc = <80>; + /* Disable TRICKLE-DEFEND, b/259428308 */ + /* google,bd-trickle-enable; */ + /* Battery virtual sensor */ + google,batt-vs-tz-name = "batt_vs"; + + /* record over temperature time */ + google,temp-record-thr = <300 350 400>; + google,soc-record-thr = <90 90 95>; + + #thermal-sensor-cells = <0>; + #cooling-cells = <2>; + google,dc-irdrop; + google,fv-dc-ratio = <35>; + + google,bhi-status-marginal = <79>; + google,bhi-status-need-rep = <79>; + google,bhi-cycle-grace = <200>; + + google,first-usage-date = <0>; + }; + + google_bms { + nvmem = <&pack_bee>; + nvmem-names = "6-00500"; + /* pack eeprom is available only with P20+ batteries */ + google,bee-name = "6-00500"; + }; + + }; + }; +}; + +&pinctrl_0 { +/* [MAX77759: FG_INTB] > FG_INT_L > [XEINT_23 : SC59845XWE] */ + if_pmic_fg_irq: if-pmic-fg-irq { + samsung,pins = "gpa9-3"; /* XEINT_23 */ + samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; +}; + +&pinctrl_0 { +/* [MAX77729FEWN : INTB] > IF_PMIC_IRQ_L > [XEINT_24 : SC59845XWE] */ + if_pmic_irq: if-pmic-irq { + samsung,pins = "gpa9-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + +}; + +&hsi2c13_bus { + samsung,pins = "gpp25-0", "gpp25-1"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; +}; + +&hsi2c_15 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c15_bus>; + + pack_bee: m24c08@50 { + status = "okay"; + compatible = "at,24c08"; + + reg = <0x50>; + }; +}; + +&hsi2c_13 { + + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + clock-frequency = <400000>; + + /* also as max77759 pmic */ + max77729_pmic:max77729pmic@66 { + status = "okay"; + compatible = "maxim,max77729pmic"; + reg = <0x66>; + + pinctrl-names = "default"; + pinctrl-0 = <&if_pmic_irq>; + max777x9,irq-gpio = <&gpa9 4 GPIO_ACTIVE_LOW>; + + max77759,max_m5 = <&max77759_fg>; + + max777x9_gpio: max777x9_gpio { + gpio-controller; + #gpio-cells = <2>; + ngpios = <6>; + + interrupt-parent = <&gpa9>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <5 IRQ_TYPE_NONE>, + <6 IRQ_TYPE_NONE>; + }; + }; + + max77759_fg:max77759fg@36 { + status = "okay"; + compatible = "maxim,max77759"; + reg = <0x36>; + + /* FG_INT_L -> XEINT_23 */ + pinctrl-names = "default"; + pinctrl-0 = <&if_pmic_fg_irq>; + maxim,irq-gpio = <&gpa9 3 GPIO_ACTIVE_LOW>; + + maxim,gauge-type = <2>; + maxim,force-batt-id = <170>; + maxim,rsense-default = <500>; + maxim,batt-id-range-pct = <0>; + + maxim,psy-type-unknown; + maxim,fg-data { + #include "gs101-fake-battery-data.dtsi" + }; + }; + + max77759_chg:max77759chrg@69 { + status = "okay"; + compatible = "maxim,max77759chrg"; + reg = <0x69>; + + interrupt-parent = <&gpa9>; + max77759,irq-gpio = <&gpa9 4 GPIO_ACTIVE_LOW>; + + max77759,max_m5 = <&max77759_fg>; + max77759,pmic = <&max77729_pmic>; + + max77759,chg-term-voltage = <4400>; + + #thermal-sensor-cells = <1>; + + max77759,wcin-inlim-headroom = <40000>; + + max77759_gpio: max77759_gpio { + gpio-controller; + #gpio-cells = <2>; + ngpios = <1>; + }; + }; + +}; + +
diff --git a/dts/gs201-cloudripper-bcl.dtsi b/dts/gs201-cloudripper-bcl.dtsi new file mode 100644 index 0000000..709f6a2 --- /dev/null +++ b/dts/gs201-cloudripper-bcl.dtsi
@@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS201 Cloudripper-specific bcl device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + */ + +#include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/soc/google/gs201-bcl.h> + +/ { + fragment@battery { + target-path = "/"; + __overlay__ { + google_mitigation: google,mitigation { + compatible = "google,google-bcl"; + #thermal-sensor-cells = <1>; + google,charger = <&max77759_chg>; + google,pmic = <&max77759_chg>; + google,power-supply = <&max77759_fg>; + google,main-power = <&s2mpg12mfd>; + google,sub-power = <&s2mpg13mfd>; + ppm_settings = <0>; + mpmm_settings = <0x1a>; + tpu_con_heavy = <0xfff041c3>; + tpu_con_light = <0xfff041c1>; + tpu_clkdivstep = <0x1>; + gpu_con_heavy = <0xfff04385>; + gpu_con_light = <0xfff041c1>; + gpu_clkdivstep = <0x1>; + cpu2_clkdivstep = <0x1>; + cpu1_clkdivstep = <0x1>; + cpu0_clkdivstep = <0x1>; + batoilo_lower = <3800>; + batoilo_upper = <6800>; + batoilo_trig_lvl = <5000>; + batoilo_usb_trig_lvl = <4800>; + batoilo_otg_trig_lvl = <4800>; + batoilo_det = <0x1>; /* 30us */ + uvlo1_det = <0x0>; /* 0us */ + uvlo2_det = <0x0>; /* 0us */ + odpm_ratio = <3>; + gpios = <&gpa5 5 0>, /* VDROOP1 */ + <&gpa5 6 0>; /* VDROOP2 */ + cpu0_cluster = <0>; + cpu1_cluster = <4>; + cpu2_cluster = <6>; + usb_otg_conf; + + irq_config { + irq,uvlo1; + irq,uvlo2; + irq,batoilo; + irq,smpl_warn; + /* Disabled IRQ + * irq,ocp_cpu1; + * irq,ocp_cpu2; + * irq,ocp_tpu; + * irq,ocp_gpu; + * irq,soft_ocp_cpu1; + * irq,soft_ocp_cpu2; + * irq,soft_ocp_tpu; + * irq,soft_ocp_gpu; + */ + }; + main_limit { + pmic = "main_limit"; + ch1 { setting = <209>; }; + ch2 { setting = <157>; }; + ch3 { setting = <182>; }; + ch4 { setting = <202>; }; + ch5 { setting = <143>; }; + ch6 { setting = <89>; }; + ch7 { setting = <238>; }; + ch8 { setting = <74>; }; + ch9 { setting = <177>; }; + ch10 { setting = <171>; }; + ch11 { setting = <60>; }; + ch12 { setting = <60>; }; + }; + sub_limit { + pmic = "sub_limit"; + ch1 { setting = <85>; }; + ch2 { setting = <144>; }; + ch3 { setting = <107>; }; + ch4 { setting = <25>; }; + ch5 { setting = <40>; }; + ch6 { setting = <34>; }; + ch7 { setting = <199>; }; + ch8 { setting = <113>; }; + ch9 { setting = <85>; }; + ch10 { setting = <114>; }; + ch11 { setting = <137>; }; + ch12 { setting = <106>; }; + }; + freq_qos { + batoilo { + cpucl0 = <930000>; + cpucl1 = <1197000>; + cpucl2 = <1426000>; + gpu = <701000>; + tpu = <627000>; + }; + vdroop1 { + cpucl0 = <1803000>; + cpucl1 = <1999000>; + cpucl2 = <2252000>; + gpu = <848000>; + tpu = <627000>; + }; + vdroop2 { + cpucl0 = <1803000>; + cpucl1 = <1999000>; + cpucl2 = <2252000>; + gpu = <572000>; + tpu = <401000>; + }; + smpl_gm { + cpucl0 = <1803000>; + cpucl1 = <1999000>; + cpucl2 = <2252000>; + gpu = <572000>; + tpu = <401000>; + }; + }; + }; + }; + }; +}; + +/* Thermal Zones */ +&thermal_zones { + batoilo { + zone_name = "BATOILO"; + polling-delay-passive = <1000>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 12>; + trips { + batoilo: batoilo{ + temperature = <5000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + + vdroop1 { + zone_name = "VDROOP1"; + polling-delay-passive = <1000>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 10>; + trips { + vdroop1: vdroop1{ + temperature = <1000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + + vdroop2 { + zone_name = "VDROOP2"; + polling-delay-passive = <1000>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 11>; + trips { + vdroop2: vdroop2{ + temperature = <1200>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + + battery_cycle { + zone_name = "BATTERY_CYCLE"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_battery>; + + /* TODO(b/251537418): fix this trips entry since it's required */ + trips { + fake_trip:dud0 { + temperature = <9999>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + + pmic_120c { + zone_name = "PMIC_120C"; + polling-delay-passive = <1000>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 13>; + trips { + pmic_120c: pmic-120c { + temperature = <1200>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + + pmic_140c { + zone_name = "PMIC_140C"; + polling-delay-passive = <1000>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 14>; + trips { + pmic_140c: pmic-140c { + temperature = <1400>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + + pmic_overheat { + zone_name = "PMIC_OVERHEAT"; + polling-delay-passive = <1000>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 15>; + trips { + pmic_overheat: pmic-overheat{ + temperature = <2000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + + soc { + zone_name = "BATT_SOC_MOD"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 9>; + + trips { + soc_trip:soc-trip { + temperature = <80>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + smpl_gm { + zone_name = "SMPL_GM"; + polling-delay-passive = <1000>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 0>; + + trips { + smpl:smpl_0 { + temperature = <1100>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + ocp_cpu1 { + zone_name = "OCP_CPU1"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 1>; + + trips { + ocp_cpu1:ocp-cpu1 { + temperature = <8000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + ocp_cpu2 { + zone_name = "OCP_CPU2"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 2>; + + trips { + ocp_cpu2:ocp-cpu2 { + temperature = <12000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + soft_ocp_cpu1 { + zone_name = "SOFT_OCP_CPU1"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 3>; + + trips { + soft_ocp_cpu1:soft-ocp-cpu1 { + temperature = <8000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + soft_ocp_cpu2 { + zone_name = "SOFT_OCP_CPU2"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 4>; + + trips { + soft_ocp_cpu2:soft-ocp-cpu2 { + temperature = <12000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + ocp_tpu { + zone_name = "OCP_TPU"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 5>; + + trips { + ocp_tpu:ocp-tpu{ + temperature = <12000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + soft_ocp_tpu { + zone_name = "SOFT_OCP_TPU"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 6>; + + trips { + soft_ocp_tpu:soft-ocp-tpu { + temperature = <8500>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + ocp_gpu { + zone_name = "OCP_GPU"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 7>; + + trips { + ocp_gpu:ocp-gpu{ + temperature = <12000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + soft_ocp_gpu { + zone_name = "SOFT_OCP_GPU"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 8>; + + trips { + soft_ocp_gpu:soft-ocp-gpu { + temperature = <9000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; +};
diff --git a/dts/gs201-cloudripper-bluetooth.dtsi b/dts/gs201-cloudripper-bluetooth.dtsi new file mode 100644 index 0000000..38b35c6 --- /dev/null +++ b/dts/gs201-cloudripper-bluetooth.dtsi
@@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Bluetooth device tree for raven. + * + * Copyright 2021 Google LLC + * + */ + +#include <dt-bindings/gpio/gpio.h> +#include <arm64/exynos/exynos-pinctrl.h> +#include "gs101-pinctrl.h" + +&pinctrl_4 { + bt_timesync: bt-timesync { + samsung,pins = "gpp11-1"; + samsung,pin-function= <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_DOWN>; + }; +}; + +&btbcm { + pinctrl-0 = <&bt_reg_on &bt_dev_wake &bt_host_wake &bt_timesync>; + timesync-gpios = <&gpp11 1 GPIO_ACTIVE_HIGH>; +};
diff --git a/dts/gs201-cloudripper-cp-s5300-sit.dtsi b/dts/gs201-cloudripper-cp-s5300-sit.dtsi new file mode 100644 index 0000000..8f0ed84 --- /dev/null +++ b/dts/gs201-cloudripper-cp-s5300-sit.dtsi
@@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Samsung CP interface device tree source + * + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include "gs201-cp-s5300-sit.dtsi" +#include "gs101-cp-s5200-thermal-zone.dtsi" + +/ { + fragment@modemif { + target-path = "/"; + __overlay__ { + #address-cells = <2>; + #size-cells = <1>; + + /* Modem interface information */ + cpif { + pinctrl-names = "default"; + pinctrl-0 = <&s5100_ap2cp_cp_pwr_on>, + <&s5100_ap2cp_cp_nreset_n>, + <&s5100_cp2ap_cp_ps_hold>, + <&s5100_ap2cp_wakeup>, + <&s5100_cp2ap_wakeup>, + <&s5100_ap2cp_dump_noti>, + <&s5100_ap2cp_pda_active>, + <&s5100_cp2ap_phone_active>, + <&s5100_ap2cp_cp_wrst_n>, + <&s5100_cp2ap_cp_wrst_n>, + <&s5100_ap2cp_pm_wrst_n>; + + /* Definition of GPIOs */ + gpio_ap2cp_wake_up = <&gph0 2 0x1>; + gpio_ap2cp_dump_noti = <&gph0 3 0x1>; + gpio_ap2cp_cp_pwr_on = <&gph1 2 0x1>; + gpio_ap2cp_pda_active = <&gph1 1 0x1>; + gpio_ap2cp_nreset_n = <&gph1 3 0x1>; + gpio_ap2cp_cp_wrst_n = <&gph1 6 0x1>; + gpio_cp2ap_cp_wrst_n = <&gpa0 2 0x1>; + gpio_ap2cp_pm_wrst_n = <&gpa0 3 0x1>; + + gpio_cp2ap_phone_active = <&gpa8 4 0x1>; + gpio_cp2ap_cp_ps_hold = <&gpa8 2 0x1>; + gpio_cp2ap_wake_up = <&gpa8 3 0x1>; + + /* + * The pad assignment of CP2AP_ACTIVE is not in PAD_ALIVE + * to be registered wake-up source. (Bug 152900487) + * CP2AP_ACTIVE is assigned to XEINT_17 for factor designs. + */ + mif,cp2ap_active_not_alive = <0>; + }; + }; + }; +}; + +&pinctrl_0 { + s5100_cp2ap_cp_wrst_n: s5100_cp2ap_cp_wrst_n { + samsung,pins = "gpa0-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; + + s5100_ap2cp_pm_wrst_n: s5100_ap2cp_pm_wrst_n { + samsung,pins = "gpa0-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + }; +}; + +&pinctrl_1 { + s5100_cp2ap_wakeup: s5100_cp2ap_wakeup { + samsung,pins = "gpa8-3"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; + + s5100_cp2ap_phone_active: s5100_cp2ap_phone_active { + samsung,pins = "gpa8-4"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; + + s5100_cp2ap_cp_ps_hold: s5100_cp2ap_cp_ps_hold { + samsung,pins = "gpa8-2"; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; +}; + +&pinctrl_6 { + s5100_ap2cp_cp_nreset_n: s5100_ap2cp_cp_nreset_n { + samsung,pins = "gph1-3"; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + + s5100_ap2cp_cp_pwr_on: s5100_ap2cp_cp_pwr_on { + samsung,pins = "gph1-2"; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + + s5100_ap2cp_pda_active: s5100_ap2cp_pda_active { + samsung,pins = "gph1-1"; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + + s5100_ap2cp_wakeup: s5100_ap2cp_wakeup { + samsung,pins = "gph0-2"; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + + s5100_ap2cp_dump_noti: s5100_ap2cp_dump_noti { + samsung,pins = "gph0-3"; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + + s5100_ap2cp_cp_wrst_n: s5100_ap2cp_cp_wrst_n { + samsung,pins = "gph1-6"; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; +};
diff --git a/dts/gs201-cloudripper-ese.dtsi b/dts/gs201-cloudripper-ese.dtsi new file mode 100644 index 0000000..a07a714 --- /dev/null +++ b/dts/gs201-cloudripper-ese.dtsi
@@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS101 Board device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + * +*/ + +#include <arm64/exynos/exynos-pinctrl.h> +#include "gs101-pinctrl.h" +#include <dt-bindings/gpio/gpio.h> + +&pinctrl_6 { + ese1_spi_rst: ese1-spi-rst { + samsung,pins ="gph1-4"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; + ese2_spi_rst: ese2-spi-rst { + samsung,pins ="gph0-4"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; +}; + +&spi10_bus { + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; +}; + +&spi10_cs { + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; +}; + +&spi17_bus { + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; +}; + +&pinctrl_0 { + spi17_bus_off: spi17-bus-off { + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-val = <0>; + }; + spi17_cs_on: spi17-cs-on { + samsung,pins = "gpa4-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-val = <1>; + }; + spi17_cs_off: spi17-cs-off { + samsung,pins = "gpa4-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-val = <0>; + }; +}; + +&spi_17 { + /* XAPM_USI0 */ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + cs-gpios = <&gpa4 3 GPIO_ACTIVE_HIGH>; + + ese2: ese@0 { + compatible = "st,st33spi"; + reg = <0>; + spi-max-frequency = <8000000>; + esereset-gpio = <&gph0 4 GPIO_ACTIVE_HIGH>; + power_mode = "ST33"; + pinctrl-names = "default","on","off"; + pinctrl-0 = <&spi17_bus_off &spi17_cs_off &ese2_spi_rst>; + pinctrl-1 = <&spi17_bus &spi17_cs_on &ese2_spi_rst>; + pinctrl-2 = <&spi17_bus_off &spi17_cs_off &ese2_spi_rst>; + + controller-data { + cs-gpio = <&gpa4 3 GPIO_ACTIVE_HIGH>; + cs-clock-delay = <10>; + cs-init-state = <0>; + samsung,spi-chip-select-mode = <0>; + }; + }; +}; + +&spi_10 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi10_bus &spi10_cs &ese1_spi_rst>; + cs-gpios = <&gpp21 3 GPIO_ACTIVE_HIGH>; + + ese1: ese@0 { + compatible = "st,st54spi"; + reg = <0>; + spi-max-frequency = <8000000>; + esereset-gpio = <&gph1 4 GPIO_ACTIVE_HIGH>; + power_mode = "ST54J"; + + controller-data { + cs-gpio = <&gpp21 3 GPIO_ACTIVE_HIGH>; + cs-clock-delay = <10>; + samsung,spi-chip-select-mode = <0>; + }; + }; +}; +
diff --git a/dts/gs201-cloudripper-gsa-gsc.dtsi b/dts/gs201-cloudripper-gsa-gsc.dtsi new file mode 100644 index 0000000..6cf3daf --- /dev/null +++ b/dts/gs201-cloudripper-gsa-gsc.dtsi
@@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/* Setup GSA_GSC proxy driver to talk to GSC over GSA */ +&gsa { + gsa_gsc@0 { + compatible = "google,gs101-gsa-gsc-v1"; + + interrupt-parent = <&gpa0>; + interrupts = <5 0 0>; + gsc,ctdl_ap_irq = <&gpa0 0 0>; // XPCIE0_WAKEN0 + }; +};
diff --git a/dts/gs201-cloudripper-nfc.dtsi b/dts/gs201-cloudripper-nfc.dtsi new file mode 100644 index 0000000..07b4778 --- /dev/null +++ b/dts/gs201-cloudripper-nfc.dtsi
@@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS101 Board device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + * +*/ +#include <dt-bindings/clock/gs201.h> +#include <arm64/exynos/exynos-pinctrl.h> +#include "gs101-pinctrl.h" + +&pinctrl_6 { + nfc_rst: nfc-rst { + samsung,pins = "gph1-5"; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; + nfc_pidle: nfc-pidle { + samsung,pins = "gph0-5"; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>; + }; +}; + +&hsi2c_8 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + status = "okay"; + st21nfc@8 { + compatible = "st,st21nfc"; + reg = <0x08>; + + pinctrl-names = "default"; + pinctrl-0 = <&nfc_rst &nfc_pidle>; + interrupt-parent = <&gpa9>; + interrupts = <0 0 0>; + reset-gpios = <&gph1 5 0>; + irq-gpios = <&gpa9 1 0>; + clkreq-gpios = <&gpp25 3 0>; + pidle-gpios = <&gph0 5 0>; + st,pidle_active_low; + clock-names = "nfc_ref_clk"; + clocks = <&clock CLKOUT1>; + pmu_clk_pad = <0x3e84>; + status = "ok"; + }; +};
diff --git a/dts/gs201-cloudripper-sbbm.dtsi b/dts/gs201-cloudripper-sbbm.dtsi new file mode 100644 index 0000000..38a7121 --- /dev/null +++ b/dts/gs201-cloudripper-sbbm.dtsi
@@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SideBand Bit Multiplexer device tree source + * + * Copyright 2021 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <arm64/exynos/exynos-pinctrl.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + fragment@sbbmux { + target-path = "/"; + __overlay__ { + sbb_mux: sbb-mux { + compatible = "google,sbb-mux"; + gpios = <&gpp18 0 0>, <&gpp18 1 0>, <&gpp0 2 0>, <&gpp1 0 0>; + gpio_names = "C1_T0__KIBBLE1_TRIG0", + "C1_T1__KIBBLE1_TRIG1", + "C1_T2__KIBBLE1_TRIG2", + "C1_T3__KIBBLE1_TRIG3"; + default_signals = "gp_region_0", "gp_region_1", + "gp_region_2", "gp_region_3"; + }; + }; + }; +};
diff --git a/dts/gs201-cloudripper-wlan.dtsi b/dts/gs201-cloudripper-wlan.dtsi new file mode 100644 index 0000000..80b08b0 --- /dev/null +++ b/dts/gs201-cloudripper-wlan.dtsi
@@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 wlan device tree source + * + * Copyright 2021 Google,LLC + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <arm64/exynos/exynos-pinctrl.h> +#include "gs101-pinctrl.h" + +&pinctrl_1 { + wlan_host_wake: wlan_host_wake { + samsung,pins = "gpa6-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_DOWN>; + }; +}; + +&pinctrl_7 { + cfg_wlanen: cfg_wlanen { + samsung,pins = "gph2-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; + + wlan_dev_wake: wlan_dev_wake { + samsung,pins = "gph2-5"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_DOWN>; + }; +}; + +&pcie_1 { + pinctrl-0 = <&pcie1_clkreq &pcie1_perst &cfg_wlanen &wlan_host_wake &wlan_dev_wake>; + use-cache-coherency = "true"; + dma-coherent; + + wlan { + compatible = "android,bcmdhd_wlan"; + wl_reg_on = <&gph2 4 0x1>; /* wlan reg_on pin */ + wl_host_wake = <&gpa6 1 0x1>; /* wlan oob pin */ + wl_dev_wake = <&gph2 5 0x1>; /* wlan dev pin */ + ch-num = <1>; + status = "okay"; + }; +};
diff --git a/dts/gs201-common-audio.dtsi b/dts/gs201-common-audio.dtsi new file mode 100644 index 0000000..20554d2 --- /dev/null +++ b/dts/gs201-common-audio.dtsi
@@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 common audio device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + * +*/ + +#include "gs201-cs40l26a-config.dtsi"
diff --git a/dts/gs201-common-bluetooth.dtsi b/dts/gs201-common-bluetooth.dtsi new file mode 100644 index 0000000..24cabb9 --- /dev/null +++ b/dts/gs201-common-bluetooth.dtsi
@@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Common Bluetooth device tree for gs101 boards. + * + * Copyright 2021 Google LLC + * + */ + +#include <dt-bindings/gpio/gpio.h> +#include <arm64/exynos/exynos-pinctrl.h> +#include "gs101-pinctrl.h" + +&pinctrl_4 { + bt_reg_on: bt-reg-on { + samsung,pins ="gpp16-2"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; + bt_dev_wake: bt-dev-wake { + samsung,pins ="gpp16-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_DOWN>; + }; +}; + +&pinctrl_1 { + bt_host_wake: bt-host-wake { + samsung,pins ="gpa6-6"; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_DOWN>; + }; +}; + +&serial_18 { + status = "okay"; +}; + +&odm { + btbcm: btbcm { + compatible = "goog,nitrous"; + pinctrl-0 = <&bt_reg_on &bt_dev_wake &bt_host_wake>; + pinctrl-names = "default"; + shutdown-gpios = <&gpp16 2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpa6 6 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpp16 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +};
diff --git a/dts/gs201-common-gps.dtsi b/dts/gs201-common-gps.dtsi new file mode 100644 index 0000000..34279d7 --- /dev/null +++ b/dts/gs201-common-gps.dtsi
@@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 GPS device tree source + * + * Copyright 2021 Google,LLC + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <arm64/exynos/exynos-pinctrl.h> + +&spi_5 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_bus &spi5_cs_func>; + + dma-mode; + dmas = <&pdma0 10 &pdma0 11>; + swap-mode = <1> ; + + bcm4775@0 { + compatible = "ssp-spi,bcm4775"; + reg = <0>; + spi-max-frequency = <26000000>; + spi-cpol; + spi-cpha; + + pinctrl-names = "default"; + pinctrl-0 = + <&gps_host_req &gps_mcu_req &gps_mcu_resp &gps_nstandby>; + + mcu-req-gpios = <&gpp4 3 GPIO_ACTIVE_HIGH>; + nstandby-gpios= <&gph2 3 GPIO_ACTIVE_LOW>; + host-req-gpios = <&gpa6 4 GPIO_ACTIVE_HIGH>; + mcu-resp-gpios = <&gph2 2 GPIO_ACTIVE_HIGH>; + + controller-data { + samsung,spi-feedback-delay = <1>; + samsung,spi-chip-select-mode = <0>; + }; + }; +}; + +&pinctrl_1 { + gps_host_req: gps-host-req { + samsung,pins = "gpa6-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; +}; + +&pinctrl_4 { + gps_mcu_req: gps-mcu-req { + samsung,pins = "gpp4-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; +}; + +&pinctrl_7 { + gps_mcu_resp: gps-mcu-resp { + samsung,pins = "gph2-2"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_DOWN>; + }; + gps_nstandby: gps-nstandby { + samsung,pins ="gph2-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; +}; + +/ { + fragment@bbd_pps { + target-path = "/"; + __overlay__ { + bbd_pps { + compatible = "bbd-pps-gpio"; + status = "okay"; + gpios = <&gpp15 1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + assert-falling-edge = <0>; + }; + }; + }; +}; \ No newline at end of file
diff --git a/dts/gs201-common-touch.dtsi b/dts/gs201-common-touch.dtsi new file mode 100644 index 0000000..22c240f --- /dev/null +++ b/dts/gs201-common-touch.dtsi
@@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google Cloudripper device tree source + * + * Copyright 2021 Google Inc. + * + */ + +/* Touch is connected to spi_0, pins: + * CLK=GPP20[0], MOSI=GPP20[1], MISO=GPP20[2], CS=GPP20[3] + * TS_RESET_L = C26 = XAPC_USI11_RTSN_DI = GPP23[2] = <&gpp23 2 0> + * TS_INT_L = AT22 = XEINT_8 = GPA7[0] = <&gpa7 0 0> + * + * DVDD = PP1800_L25M_TSP_DVDD = ??? = VLDO25M = "PP1800_L25M_TSP"? + * AVDD = PP3300_L26M_TS_AVDD = ??? = VLDO26M = "PP3300_L26M_TSP"? + * + * AP2AOC: XHSI1_GPIO2 - GPH1[0] -> XAOC_GPIO13 - gpio_in[87] + * AOC2AP: XAOC_GPIO8 - gpio_in[74] -> XEINT_19 - GPA8[7] + */ + +#include <arm64/exynos/exynos-pinctrl.h> +#include "gs101-pinctrl.h" + +/ { + fragment@touch_bus_negotiator { + target-path = "/"; + __overlay__ { + tbn: tbn { + compatible = "touch_bus_negotiator"; + + /* Low: AP, High: AOC */ + /* Note: The following GPIO flags are not used by the driver. */ + tbn,ap2aoc_gpio = <&gph1 0 GPIO_ACTIVE_LOW>; + tbn,aoc2ap_gpio = <&gpa8 7 GPIO_ACTIVE_LOW>; + }; + }; + }; +}; + +&pinctrl_1 { + ts_irq: ts-irq { + samsung,pins = "gpa7-0"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + + aoc2ap_irq: aoc2ap-irq { + samsung,pins = "gpa8-7"; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; +}; + +&pinctrl_5 { + ts_reset: ts-reset { + samsung,pins = "gpp23-2"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; + + ts_spi_bus_active: ts_spi_bus_active { + samsung,pins = "gpp20-0", "gpp20-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + + ts_spi_miso_active: ts_spi_miso_active { + samsung,pins = "gpp20-2"; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + + ts_spi_cs_active: ts_spi_cs_active { + samsung,pins = "gpp20-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + + ts_spi_bus_sleep: ts_spi_bus_sleep { + samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; + + ts_spi_cs_sleep: ts_spi_cs_sleep { + samsung,pins = "gpp20-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>; + }; +}; + +&pinctrl_6 { + ap2aoc: ap2aoc-spi-sel { + samsung,pins = "gph1-0"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; +}; + +&spi_0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <>; + + spitouch: touchscreen@0 { + status = "disabled"; + reg = <0>; + + pinctrl-names = "ts_active", "ts_suspend"; + pinctrl-0 = <&ts_irq &ts_reset &ap2aoc &aoc2ap_irq + &ts_spi_bus_active &ts_spi_miso_active &ts_spi_cs_active>; + pinctrl-1 = <&ts_spi_bus_sleep &ts_spi_cs_sleep>; + + vdd-supply = <&m_ldo25_reg>; /* VIO 1.8V */ + avdd-supply = <&m_ldo26_reg>; /* AVDD 3.3V */ + }; +};
diff --git a/dts/gs201-common-typec.dtsi b/dts/gs201-common-typec.dtsi new file mode 100644 index 0000000..2d568b2 --- /dev/null +++ b/dts/gs201-common-typec.dtsi
@@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021, Google LLC + * + * Cloudripper Type-C device tree + */ +#include <dt-bindings/usb/pd.h> +#include <dt-bindings/gpio/gpio.h> +#include <arm64/exynos/exynos-pinctrl.h> +#include "gs101-pinctrl.h" + +&hsi2c_13{ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + max77759tcpc: max77759tcpc@25 { + status = "okay"; + compatible = "max77759tcpc"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_pd_irq>; + interrupt-parent = <&gpa9>; + usbpd,usbpd_int = <&gpa9 7 GPIO_ACTIVE_LOW>; + usb-psy-name = "usb"; + /* Enable when BMS is up */ + chg-psy-name = "gcpm"; + /* Default OVP IC is SLG59H1313C. Config others in overlay if needed. */ + ovp-present; + in-switch-gpio = <&max777x9_gpio 5 GPIO_ACTIVE_LOW>; + quick-ramp-vbus-ovp; + conn = <&conn>; + orientation-switch; + bcl-usb-voting; + + conn: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + self-powered; + op-sink-microwatt = <2600000>; + new-source-frs-typec-current = <FRS_5V_1P5A>; + usb-role-switch; + slow-charger-loop; + /* + * b/174044466: Extboost can only do ~1A. + * However, max77759 operating in reverse boost + * mode (0xA) can do till 1.5A. + * Since extboost is the primary path, set this + * to 900mA. + */ + source-pdos = <PDO_FIXED(5000, 900, + PDO_FIXED_SUSPEND | + PDO_FIXED_USB_COMM | + PDO_FIXED_DATA_SWAP | + PDO_FIXED_DUAL_ROLE)>; + sink-pdos = <PDO_FIXED(5000, 3000, + PDO_FIXED_DATA_SWAP | + PDO_FIXED_USB_COMM | + PDO_FIXED_HIGHER_CAP | + PDO_FIXED_DUAL_ROLE) + PDO_FIXED(9000, 2200, 0) + PDO_PPS_APDO(5000, 11000, 3000)>; + sink-vdos = <VDO_IDH(/* usbh */ 1, /* usbd */ 1, IDH_PTYPE_PERIPH, + /* is_modal */ 0, IDH_PTYPE_DFP_HOST, /* conn */ 2, + 0x18D1) + VDO_CERT(0x0) + VDO_PRODUCT(0x4EE1, 0x0) + VDO_UFP(UFP_VDO_VER1_2, DEV_USB2_CAPABLE | DEV_USB3_CAPABLE, + UFP_RECEPTACLE, /* rsvd */ 0, AMA_VCONN_NOT_REQ, + /* rsvd */ 0, UFP_ALTMODE_NOT_SUPP, UFP_USB32_GEN1) + /* padding */ 0 + VDO_DFP(DFP_VDO_VER1_1, HOST_USB2_CAPABLE | HOST_USB3_CAPABLE, + DFP_RECEPTACLE, /* pnum */ 0)>; + sink-vdos-v1 = <VDO_IDH(/* usbh */ 1, /* usbd */ 1, IDH_PTYPE_PERIPH, + /* is_modal */ 0, /* rsvd */ 0, /* rsvd */ 0, + 0x18D1) + VDO_CERT(0x0) + VDO_PRODUCT(0x4EE1, 0x0)>; + + port { + #address-cells = <1>; + #size-cells = <0>; + mux_notification_src: endpoint@0 { + reg = <0>; + remote-endpoint = <&mux_notification_snk>; + }; + + }; + }; + + port { + #address-cells = <1>; + #size-cells = <0>; + + mux_notification_snk: endpoint@0 { + reg = <0>; + remote-endpoint = <&mux_notification_src>; + }; + }; + + /* EXT_BST_EN exposed as GPIO */ + max77759_tcpc_gpio: max77759_tcpc_gpio { + gpio-controller; + #gpio-cells = <2>; + ngpios = <1>; + }; + }; +}; + +&hsi2c13_bus { + samsung,pins = "gpp25-0", "gpp25-1"; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; +}; + +&pinctrl_0 { + usb_pd_irq: usb-pd-irq { + samsung,pins = "gpa9-7"; + samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; +}; + +/ { + fragment@typec { + target-path = "/"; + __overlay__ { + google,usbc_port_cooling_dev { + extcon = <&max77759tcpc>; + compatible = "google,usbc_port_cooling_dev"; + google,usb-cd-polling-interval-ms = <5000>; + google,usb-cd-connected-interval-ms = <700>; + google,usb-cd-unplug-interval-sec = <2>; + #cooling-cells = <2>; + }; + }; + }; +};
diff --git a/dts/gs201-common.dtsi b/dts/gs201-common.dtsi new file mode 100644 index 0000000..5fcfce5 --- /dev/null +++ b/dts/gs201-common.dtsi
@@ -0,0 +1,384 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Common device tree for all gs201 boards. + * + * Copyright 2021 Google LLC + * + */ +#include <dt-bindings/gpio/gpio.h> +#include "gs201-common-audio.dtsi" +#include "gs201-common-bluetooth.dtsi" +#include "gs201-common-gps.dtsi" +#include "gs201-common-touch.dtsi" +#include "gs201-common-typec.dtsi" +#include "gs201-ldaf.dtsi" +#include "gs201-pmic.dtsi" + +#include <dt-bindings/pci/pci.h> + +&serial_0 { + status = "okay"; +}; + +&pinctrl_1 { + key_volup: key-volup { + samsung,pins = "gpa8-5"; /* VOL_UP_L */ + samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; +}; + +&pinctrl_0 { + key_power: key-power { + samsung,pins = "gpa10-0"; /* PMIC_PWRON_OD_L */ + samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + key_voldown: key-voldown { + samsung,pins = "gpa10-1"; /* VOL_DN_L */ + samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + +}; + +&gpio_keys { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&key_voldown &key_volup &key_power>; + button@1 { + label = "gpio-keys: KEY_VOLUMEDOWN"; + linux,code = <114>; + gpios = <&gpa10 1 0xf>; + wakeup-source; + }; + button@2 { + label = "gpio-keys: KEY_VOLUMEUP"; + linux,code = <115>; + gpios = <&gpa8 5 0xf>; + wakeup-source; + }; +}; + +&udc { + adj-sof-accuracy = <1>; + samsung,no-extra-delay; + usb_host_device_timeout = <0x7ff>; /* Max value */ + extcon = <&max77759tcpc>; + + u1u2_exitfail_quirk; + /* ux_exit_in_px should be defined in MK, LT */ + ux_exit_in_px_quirk; + /* elastic_buf_mode_quirk should be defined in MK */ + elastic_buf_mode_quirk; + xhci_l2_support = <1>; + + usbdrd_dwc3: dwc3 { + dr_mode = "peripheral"; + maximum-speed = "super-speed-plus"; + usb-psy-name = "usb"; + snps,quirk-frame-length-adjustment = <0x20>; + + snps,has-lpm-erratum; + snps,lpm-nyet-threshold = <0>; + + snps,usb2-gadget-lpm-disable; + + /* + * dis-u2-freeclk-exists-quirk, dis_u2_susphy_quirk are alternative. + * One of them should be selected + */ + snps,dis-u2-freeclk-exists-quirk; + /*snps,dis_u2_susphy_quirk;*/ + + /* http://b/171478776 : disabling U1/U2 speed up NCM tethering by >2x */ + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + xhci_l2_support = <1>; + }; +}; + +&usbdrd_phy0 { + usb_hs_tune:hs_tune { + status = "disabled"; + hs_tune_cnt = <6>; + /* value = <device host> */ + hs_tune1 { + tune_name = "tx_pre_emp"; + tune_value = <0x1 0x1>; + }; + + hs_tune2 { + tune_name = "tx_vref"; + tune_value = <0x8 0x8>; + }; + + hs_tune3 { + tune_name = "rx_sqrx"; + tune_value = <0x5 0x5>; + }; + + hs_tune4 { + tune_name = "utmi_clk"; + tune_value = <0x1 0x1>; + }; + + hs_tune5 { + tune_name = "compdis"; + tune_value = <0x7 0x7>; + }; + + hs_tune6 { + tune_name = "tx_res"; + tune_value = <0x3 0x3>; + }; + }; + + usb_ss_tune:ss_tune { + status = "disabled"; + ss_tune_cnt = <36>; + /* value = <device host> */ + /* 0xffffffff means using default value */ + ss_tune1 { + tune_name = "ssrx_sqhs_th_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune2 { + tune_name = "ssrx_sqhs_th_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune3 { + tune_name = "ssrx_lfps_th"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune4 { + tune_name = "ssrx_adap_coef_sel"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune5 { + tune_name = "ssrx_mf_eq_psel_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune6 { + tune_name = "ssrx_mf_eq_psel_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune7 { + tune_name = "ssrx_mf_eq_zsel_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune8 { + tune_name = "ssrx_mf_eq_zsel_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune9 { + tune_name = "ssrx_hf_eq_rsel_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune10 { + tune_name = "ssrx_hf_eq_rsel_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune11 { + tune_name = "ssrx_hf_eq_csel_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune12 { + tune_name = "ssrx_hf_eq_csel_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune13 { + tune_name = "ssrx_dfe_1tap_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune14 { + tune_name = "ssrx_dfe_1tap_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune15 { + tune_name = "ssrx_dfe_2tap_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune16 { + tune_name = "ssrx_dfe_2tap_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune17 { + tune_name = "ssrx_dfe_3tap_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune18 { + tune_name = "ssrx_dfe_3tap_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune19 { + tune_name = "ssrx_dfe_4tap_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune20 { + tune_name = "ssrx_dfe_4tap_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune21 { + tune_name = "ssrx_dfe_5tap_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune22 { + tune_name = "ssrx_dfe_5tap_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune23 { + tune_name = "ssrx_term_cal"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune24 { + tune_name = "sstx_amp_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune25 { + tune_name = "sstx_deemp_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune26 { + tune_name = "sstx_pre_shoot_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune27 { + tune_name = "sstx_amp_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune28 { + tune_name = "sstx_deemp_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune29 { + tune_name = "sstx_pre_shoot_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune30 { + tune_name = "sstx_idrv_up"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune31 { + tune_name = "sstx_lfps_idrv_up"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune32 { + tune_name = "sstx_up_term"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune33 { + tune_name = "sstx_dn_term"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune34 { + tune_name = "rext_ovrd"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune35 { + tune_name = "ssrx_cdr_fbb_fine_ctrl_sp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune36 { + tune_name = "ssrx_cdr_fbb_fine_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + }; +}; + +&usbdrd_phy0 { + status = "okay"; + + hs_tune_param = <&usb_hs_tune>; + ss_tune_param = <&usb_ss_tune>; + extcon = <&max77759tcpc>; +}; + +&sub_pd_hsi0 { + vdd_hsi-supply = <&m_ldo7_reg>; + /* PP0850_L8M_USB: AVDD_PLL_USB, AVDD085_USB20, AVDD085_USBDP */ + /* PP1800_L9M_USB: AVDD18_USB20, AVDD18_USBDP */ + /* PP3000_L10M_USB: AVDD33_USB20 */ + vdd085-supply = <&m_ldo8_reg>; + vdd18-supply = <&m_ldo9_reg>; + vdd30-supply = <&m_ldo10_reg>; +}; + +&pcie_0 { /* pcie ch0 used for the connection with CP */ + status = "okay"; + use-cache-coherency = "true"; + use-msi = "true"; + use-sicd = "true"; + use-ia = "true"; + use-l1ss = "true"; + phy-power-off = "false"; + use-pcieon-sleep = "true"; + use-sysmmu = "true"; + use-secure-atu = "true"; + ep-device-type = <EP_SAMSUNG_MODEM>; + vreg1-supply = <&m_ldo16_reg>; /* PP0850_L16M_PCIE0: AVDD085_PCIE_GEN4_0 */ + vreg2-supply = <&m_ldo18_reg>; /* PP1800_L18M_PCIE0: AVDD18_PCIE_GEN4_0 */ +}; + +&sysmmu_hsi1 { + use-map-once = "true"; + status = "okay"; +}; + +&pcie_1 { /* pcie ch1 used for the connection with WiFi */ + status = "okay"; + num-lanes = <1>; + use-sicd = "true"; + use-ia = "true"; + use-l1ss = "true"; + use-sysmmu = "true"; + max-link-speed = <LINK_SPEED_GEN2>; + ep-device-type = <EP_BCM_WIFI>; + pcie,wlan-gpio = <&gph2 4 0x1 /* WLAN_EN */ >; /* WLAN_REG_ON */ + vreg1-supply = <&s_ldo3_reg>; /* PP0850_L3S_PCIE1: AVDD085_PCIE_GEN4_1 */ + vreg2-supply = <&s_ldo18_reg>; /* PP1800_L18S_PCIE1: AVDD18_PCIE_GEN4_1 */ +}; + +&aoc { + sensor_1v8-supply = <&s_ldo7_reg>; + sensor_3v3-supply = <&s_ldo5_reg>; + sensor_power_list = "sensor_1v8", "sensor_3v3"; +};
diff --git a/dts/gs201-cp-s5300-sit.dtsi b/dts/gs201-cp-s5300-sit.dtsi new file mode 100644 index 0000000..cf19db5 --- /dev/null +++ b/dts/gs201-cp-s5300-sit.dtsi
@@ -0,0 +1,535 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Samsung CP interface device tree source + * + * Copyright (c) 2019-2020 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include <dt-bindings/soc/google/exynos-cpif.h> +#include <dt-bindings/pci/pci.h> + +/ { + fragment@modemif { + target-path = "/"; + __overlay__ { + #address-cells = <2>; + #size-cells = <1>; + + /* Modem interface information */ + cpif { + compatible = "samsung,exynos-cp"; + status = "okay"; + + pci_ch_num = <0>; + pci_db_addr = <0x14E60000>; + cpboot_spi_bus_num = <9>; + + /* */ + mif,name = "s5300"; + mif,cp_num = <0>; + mif,modem_type = <SEC_S5100>; + mif,protocol = <PROTOCOL_SIT>; + mif,ipc_version = <SIPC_VER_50>; + mif,link_type = <LINKDEV_PCIE>; + mif,link_name = "PCIE"; + mif,link_attrs = <( + LINK_ATTR_XMIT_BTDLR_PCIE | + LINK_ATTR_XMIT_BTDLR | + LINK_ATTR_DUMP_ALIGNED | + LINK_ATTR_BOOT_ALIGNED | + LINK_ATTR_MEM_DUMP | + LINK_ATTR_MEM_BOOT | + LINK_ATTR_DPRAM_MAGIC)>; + mif,interrupt_types = <INTERRUPT_GPIO>; + mif,capability_check = <1>; + + /* Mailbox interrupt number from AP to CP */ + mif,int_ap2cp_msg = <0>; + mif,int_ap2cp_wakeup = <1>; + mif,int_ap2cp_status = <2>; + mif,int_ap2cp_active = <3>; + mif,int_ap2cp_lcd_status = <4>; + mif,int_ap2cp_pcie_link_ack = <14>; + mif,int_ap2cp_uart_noti = <15>; + + /* Mailbox interrupt number from CP to AP */ + mif,irq_cp2ap_msg = <0>; + mif,irq_cp2ap_status = <2>; + mif,irq_cp2ap_active = <3>; + mif,irq_cp2ap_wakelock = <8>; + mif,irq_cp2ap_ratmode = <9>; + + /* Legacy Buffers (FMT, RAW) */ + legacy_fmt_head_tail_offset = <0x8>; + legacy_fmt_buffer_offset = <0x1000>; + legacy_fmt_txq_size = <0x1000>; + legacy_fmt_rxq_size = <0x1000>; + legacy_raw_head_tail_offset = <0x18>; + legacy_raw_buffer_offset = <0x3000>; + legacy_raw_txq_size = <0x1FD000>; + legacy_raw_rxq_size = <0x200000>; + legacy_raw_rx_buffer_cached = <0>; + + offset_srinfo_offset = <0x64>; + offset_capability_offset = <0x70>; + + srinfo_offset = <0x400000>; + srinfo_size = <0x300000>; + capability_offset = <0xA0>; + + /* capability value */ + ap_capability_0 = <0x0>; + ap_capability_1 = <0x0>; + + /* + * Control messages containing two elements + * <MAILBOX_SR [shared register number]> + * <DRAM_V1 [offset from ipc base]> + * <DRAM_V2 [offset from cmsg offset]> + */ + ap2cp_msg = <DRAM_V1 2048>; + cp2ap_msg = <DRAM_V1 2052>; + ap2cp_united_status = <DRAM_V1 2056>; + cp2ap_united_status = <DRAM_V1 2060>; + ap2cp_kerneltime = <DRAM_V1 2084>; + ap2cp_handover_block_info = <DRAM_V1 2092>; + + /* Status bit info + * for mbx_ap2cp_united_status + */ + sbi_lcd_status_mask = <0x1>; + sbi_lcd_status_pos = <27>; + sbi_crash_type_mask = <0xf>; + sbi_crash_type_pos = <23>; + sbi_uart_noti_mask = <0x1>; + sbi_uart_noti_pos = <16>; + sbi_ds_det_mask = <0x3>; + sbi_ds_det_pos = <14>; + sbi_pda_active_mask = <0x1>; + sbi_pda_active_pos = <5>; + sbi_ap_status_mask = <0xf>; + sbi_ap_status_pos = <1>; + + /* Status bit info + * for mbx_cp2ap_united_status + */ + sbi_cp_rat_mode_mask = <0x3f>; + sbi_cp_rat_mode_pos = <26>; + sbi_cp2ap_wakelock_mask = <0x1>; + sbi_cp2ap_wakelock_pos = <6>; + sbi_lte_active_mask = <0x1>; + sbi_lte_active_pos = <5>; + sbi_cp_status_mask = <0xf>; + sbi_cp_status_pos = <1>; + + /* Status bit info for mbx_ap2cp_kerneltime */ + sbi_ap2cp_kerneltime_sec_mask = <0xfff>; + sbi_ap2cp_kerneltime_sec_pos = <20>; + sbi_ap2cp_kerneltime_usec_mask = <0xfffff>; + sbi_ap2cp_kerneltime_usec_pos = <0>; + + /* Packet processor */ + pktproc_use_36bit_addr = <0>; + pktproc_cp_base = <0x0 0x20000000>; + + pktproc_dl_support = <1>; + pktproc_dl_version = <2>; + + pktproc_dl_info_rgn_offset = <0x00000000>; + pktproc_dl_info_rgn_size = <0x00001000>; + pktproc_dl_desc_rgn_offset = <0x00001000>; + pktproc_dl_desc_rgn_size = <0x000FF000>; + pktproc_dl_buff_rgn_offset = <0x00100000>; + pktproc_dl_buff_rgn_size = <0x01B00000>; + /* Size of data region is defined + * by reserved mem size + */ + + pktproc_dl_info_rgn_cached = <1>; + pktproc_dl_desc_rgn_cached = <1>; + pktproc_dl_buff_rgn_cached = <1>; + + /* 0:ringbuf mode, 1:sktbuf mode */ + pktproc_dl_desc_mode = <1>; + pktproc_dl_num_queue = <4>; + pktproc_dl_use_exclusive_irq = <1>; + /* H/W IO cache coherency */ + pktproc_dl_use_hw_iocc = <1>; + pktproc_dl_max_packet_size = <1584>; + pktproc_dl_use_dedicated_baaw = <0>; + + /* Packet processor for UL */ + pktproc_ul_support = <1>; + pktproc_ul_info_rgn_offset = <0x01C00000>; + pktproc_ul_info_rgn_size = <0x00001000>; + pktproc_ul_desc_rgn_offset = <0x01C01000>; + pktproc_ul_desc_rgn_size = <0x0008F000>; + pktproc_ul_buff_rgn_offset = <0x01C90000>; + pktproc_ul_buff_rgn_size = <0x00370000>; + pktproc_ul_padding_required = <1>; /* for s5123 EVT1 only */ + pktproc_ul_num_queue = <2>; + pktproc_ul_max_packet_size = <2048>; + pktproc_ul_hiprio_ack_only = <1>; + pktproc_ul_info_rgn_cached = <1>; + pktproc_ul_desc_rgn_cached = <1>; + pktproc_ul_buff_rgn_cached = <1>; + pktproc_ul_use_hw_iocc = <1>; /* H/W IO cache coherency */ + + /* TPMON: CP throughput monitor */ + cpif_tpmon { + trigger_msec_min = <500>; + trigger_msec_max = <1500>; + + monitor_interval_msec = <1000>; + monitor_hold_msec = <3000>; + monitor_stop_mbps = <15>; + + boost_hold_msec = <6000>; + + tpmon_rps { + boost_name = "RPS"; + target = <TPMON_TARGET_RPS>; + extra_idx = <0>; + level = <0x03 0x30 0xC0>; + + boost0 { + enable = <1>; + measure = <TPMON_MEASURE_TP>; + proto = <TPMON_PROTO_ALL>; + boost_threshold = <150 1600>; + unboost_threshold_mbps = <60 600>; + }; + }; + + tpmon_gro_flush_time { + boost_name = "GRO"; + target = <TPMON_TARGET_GRO>; + extra_idx = <0>; + level = <250000 2000000>; + + boost0 { + enable = <1>; + measure = <TPMON_MEASURE_TP>; + proto = <TPMON_PROTO_ALL>; + boost_threshold = <100>; + unboost_threshold_mbps = <50>; + }; + }; + + tpmon_mif { + boost_name = "MIF"; + target = <TPMON_TARGET_MIF>; + extra_idx = <0>; + level = <0 1014000>; + + boost0 { + enable = <0>; + measure = <TPMON_MEASURE_TP>; + proto = <TPMON_PROTO_TCP>; + boost_threshold = <1100>; + unboost_threshold_mbps = <400>; + }; + }; + + tpmon_cpu_cl0 { + boost_name = "CL0"; + target = <TPMON_TARGET_CPU_CL0>; + extra_idx = <0>; + level = <0 1066000 1274000>; + + boost0 { + enable = <0>; + measure = <TPMON_MEASURE_TP>; + proto = <TPMON_PROTO_TCP>; + boost_threshold = <100 300>; + unboost_threshold_mbps = <40 120>; + }; + }; + + tpmon_cpu_cl1 { + boost_name = "CL1"; + target = <TPMON_TARGET_CPU_CL1>; + extra_idx = <4>; + level = <0 799000>; + + boost0 { + enable = <1>; + measure = <TPMON_MEASURE_TP>; + proto = <TPMON_PROTO_ALL>; + boost_threshold = <2000>; + unboost_threshold_mbps = <800>; + }; + }; + + tpmon_pcie_low_power { + boost_name = "PCIE_LP"; + target = <TPMON_TARGET_PCIE_LOW_POWER>; + extra_idx = <0>; + level = <1 0>; + + boost0 { + enable = <1>; + measure = <TPMON_MEASURE_TP>; + proto = <TPMON_PROTO_ALL>; + boost_threshold = <3000>; + unboost_threshold_mbps = <1200>; + }; + }; + + tpmon_irq_affinity_0 { + boost_name = "IRQ_0"; + target = <TPMON_TARGET_IRQ_PCIE>; + extra_idx = <3>; + level = <0x0C 0x30>; + + boost0 { + enable = <1>; + measure = <TPMON_MEASURE_TP>; + proto = <TPMON_PROTO_ALL>; + boost_threshold = <500>; + unboost_threshold_mbps = <200>; + }; + }; + + tpmon_irq_dit { + boost_name = "IRQ_DIT"; + target = <TPMON_TARGET_IRQ_DIT>; + extra_idx = <0>; + level = <0x04 0x20>; + + boost0 { + enable = <0>; + measure = <TPMON_MEASURE_TP>; + proto = <TPMON_PROTO_ALL>; + boost_threshold = <250>; + unboost_threshold_mbps = <100>; + }; + + boost1 { + enable = <0>; + measure = <TPMON_MEASURE_PKTPROC_DL_Q>; + proto = <TPMON_PROTO_ALL>; + boost_threshold = <6000>; + unboost_threshold_mbps = <2000>; + }; + + boost2 { + enable = <0>; + measure = <TPMON_MEASURE_DIT_SRC_Q>; + proto = <TPMON_PROTO_ALL>; + boost_threshold = <7000>; + unboost_threshold_mbps = <2000>; + }; + }; + }; + + /* IO devices */ + iodevs { + io_device_0 { + iod,name = "umts_ipc"; + iod,ch = <EXYNOS_CH_ID_FMT_0>; + iod,format = <IPC_FMT>; + iod,io_type = <IODEV_IPC>; + iod,link_type = <LINKDEV_PCIE>; + iod,attrs = <(IO_ATTR_MULTI_CH)>; + iod,ch_count = <2>; + }; + io_device_1 { + iod,name = "umts_rfs0"; + iod,ch = <EXYNOS_CH_ID_RFS_0>; + iod,format = <IPC_RAW>; + iod,io_type = <IODEV_IPC>; + iod,link_type = <LINKDEV_PCIE>; + iod,attrs = <(0x0)>; + }; + io_device_2 { + iod,name = "umts_router"; + iod,ch = <EXYNOS_CH_ID_BT_DUN>; + iod,format = <IPC_RAW>; + iod,io_type = <IODEV_IPC>; + iod,link_type = <LINKDEV_PCIE>; + iod,attrs = <(0x0)>; + }; + io_device_3 { + iod,name = "umts_dm0"; + iod,ch = <EXYNOS_CH_ID_CPLOG>; + iod,format = <IPC_RAW>; + iod,io_type = <IODEV_IPC>; + iod,link_type = <LINKDEV_PCIE>; + iod,attrs = <(IO_ATTR_STATE_RESET_NOTI)>; + }; + io_device_4 { + iod,name = "umts_loopback"; + iod,ch = <EXYNOS_CH_ID_LOOPBACK>; + iod,format = <IPC_RAW>; + iod,io_type = <IODEV_IPC>; + iod,link_type = <LINKDEV_PCIE>; + iod,attrs = <(0x0)>; + }; + io_device_5 { + iod,name = "rmnet"; + iod,ch = <EXYNOS_CH_EX_ID_PDP_0>; + iod,format = <IPC_RAW>; + iod,io_type = <IODEV_NET>; + iod,link_type = <LINKDEV_PCIE>; + iod,attrs = <(IO_ATTR_MULTI_CH)>; + iod,ch_count = <30>; + }; + io_device_6 { + iod,name = "umts_dummy"; + iod,ch = <EXYNOS_CH_EX_ID_PDP_30>; + iod,format = <IPC_RAW>; + iod,io_type = <IODEV_NET>; + iod,link_type = <LINKDEV_PCIE>; + iod,attrs = <(0x0)>; + }; + io_device_7 { + iod,name = "multipdp"; + iod,ch = <EXYNOS_CH_ID_MULTIPDP>; + iod,format = <IPC_MULTI_RAW>; + iod,io_type = <IODEV_DUMMY>; + iod,link_type = <LINKDEV_PCIE>; + iod,attrs = <(0x0)>; + }; + io_device_8 { + iod,name = "umts_boot0"; + iod,ch = <EXYNOS_CH_ID_BOOT>; + iod,format = <IPC_BOOT>; + iod,io_type = <IODEV_BOOTDUMP>; + iod,link_type = <LINKDEV_PCIE>; + iod,attrs = <(IO_ATTR_NO_CHECK_MAXQ)>; + }; + io_device_9 { + iod,name = "umts_rcs0"; + iod,ch = <EXYNOS_CH_ID_RCS_0>; + iod,format = <IPC_FMT>; + iod,io_type = <IODEV_IPC>; + iod,link_type = <LINKDEV_PCIE>; + iod,attrs = <(0x0)>; + }; + io_device_10 { + iod,name = "umts_rcs1"; + iod,ch = <EXYNOS_CH_ID_RCS_1>; + iod,format = <IPC_RAW>; + iod,io_type = <IODEV_IPC>; + iod,link_type = <LINKDEV_PCIE>; + iod,attrs = <(0x0)>; + }; + io_device_11 { + iod,name = "umts_wfc0"; + iod,ch = <EXYNOS_CH_ID_WFS_0>; + iod,format = <IPC_FMT>; + iod,io_type = <IODEV_IPC>; + iod,link_type = <LINKDEV_PCIE>; + iod,attrs = <(0x0)>; + }; + io_device_12 { + iod,name = "umts_wfc1"; + iod,ch = <EXYNOS_CH_ID_WFS_1>; + iod,format = <IPC_RAW>; + iod,io_type = <IODEV_IPC>; + iod,link_type = <LINKDEV_PCIE>; + iod,attrs = <(0x0)>; + }; + io_device_13 { + iod,name = "oem_ipc"; + iod,ch = <129>; + iod,format = <IPC_FMT>; + iod,io_type = <IODEV_IPC>; + iod,link_type = <LINKDEV_PCIE>; + iod,attrs = <(IO_ATTR_MULTI_CH)>; + iod,ch_count = <8>; + }; + io_device_14 { + iod,name = "oem_test"; + iod,ch = <137>; + iod,format = <IPC_RAW>; + iod,io_type = <IODEV_IPC>; + iod,link_type = <LINKDEV_PCIE>; + iod,attrs = <(0x0)>; + }; + }; + }; + + /* Shared memory information*/ + cp_shmem { + compatible = "samsung,exynos-cp-shmem"; + + memory-region = + <&cp_rmem>, + <&cp_msi_rmem>, + <&cp_rmem_1>, + <&cp_aoc_rmem>; + + cp_num = <0>; + use_mem_map_on_cp = <0>; + + regions { + ipc { + region,name = "IPC"; + region,index = <SHMEM_IPC>; + region,rmem = <0>; + region,offset = <0x00000000>; + region,size = <0x00800000>; + region,cached = <1>; + }; + msi { + region,name = "MSI"; + region,index = <SHMEM_MSI>; + region,rmem = <1>; + region,offset = <0x00000000>; + region,size = <0x00001000>; + region,cached = <0>; + }; + pktproc { + region,name = "PKTPROC"; + region,index = <SHMEM_PKTPROC>; + region,rmem = <2>; + region,offset = <0x00000000>; + region,size = <0x01C00000>; + /* Cached info is defined by pktproc itself */ + }; + pktproc_ul { + region,name = "PKTPROC_UL"; + region,index = <SHMEM_PKTPROC_UL>; + region,rmem = <2>; + region,offset = <0x01C00000>; + region,size = <0x00400000>; + /* Cached info is defined by pktproc_ul itself */ + }; + vss_aoc { + region,name = "VSS_AOC"; + region,index = <SHMEM_VSS>; + region,rmem = <3>; + region,offset = <0x00000000>; + region,size = <0x00003000>; + region,cached = <0>; + }; + }; + }; + }; + }; +}; + +&spi9_cs_func { + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; +}; + +&spi_9 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi9_bus &spi9_cs_func>; + cpboot_spi@0 { + compatible = "samsung,exynos-cp-spi"; + reg = <0x0>; + spi-max-frequency = <2150000>; + controller-data { + samsung,spi-feedback-delay = <0>; + samsung,spi-chip-select-mode = <1>; + }; + }; +};
diff --git a/dts/gs201-cpu.dtsi b/dts/gs201-cpu.dtsi new file mode 100644 index 0000000..1a5c680 --- /dev/null +++ b/dts/gs201-cpu.dtsi
@@ -0,0 +1,579 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS201 SoC CPU device tree source + * + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * GS201 SoC CPU device nodes are listed in this file. + * GS201 based board files should include this file. + * + */ + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + #define CPU_CL0 "0-3" + #define CPU_CL1 "4-5" + #define CPU_CL2 "6-7" + #define CPU_ALL "0-7" + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + core4 { + cpu = <&cpu4>; + }; + core5 { + cpu = <&cpu5>; + }; + core6 { + cpu = <&cpu6>; + }; + core7 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0000>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + capacity-dmips-mhz = <250>; + dynamic-power-coefficient = <89>; + }; + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0100>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + capacity-dmips-mhz = <250>; + dynamic-power-coefficient = <89>; + }; + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0200>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + capacity-dmips-mhz = <250>; + dynamic-power-coefficient = <89>; + }; + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0300>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + capacity-dmips-mhz = <250>; + dynamic-power-coefficient = <89>; + }; + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0400>; + enable-method = "psci"; + cpu-idle-states = <&HERCULES_CPU_SLEEP>; + capacity-dmips-mhz = <927>; + dynamic-power-coefficient = <513>; + }; + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0500>; + enable-method = "psci"; + cpu-idle-states = <&HERCULES_CPU_SLEEP>; + capacity-dmips-mhz = <927>; + dynamic-power-coefficient = <513>; + }; + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0600>; + enable-method = "psci"; + cpu-idle-states = <&HERA_CPU_SLEEP>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <757>; + }; + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0700>; + enable-method = "psci"; + cpu-idle-states = <&HERA_CPU_SLEEP>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <757>; + }; + + idle-states { + entry-method = "arm,psci"; + + ANANKE_CPU_SLEEP: ananke-cpu-sleep { + idle-state-name = "c2"; + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <70>; + exit-latency-us = <160>; + min-residency-us = <2000>; + status = "okay"; + }; + + HERCULES_CPU_SLEEP: hercules-cpu-sleep { + idle-state-name = "c2"; + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <150>; + exit-latency-us = <190>; + min-residency-us = <2500>; + status = "okay"; + }; + + HERA_CPU_SLEEP: hera-cpu-sleep { + idle-state-name = "c2"; + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <235>; + exit-latency-us = <220>; + min-residency-us = <3500>; + status = "okay"; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + exynos-cpuphp { + compatible = "samsung,exynos-cpuhp"; + status = "okay"; + }; + + cpupm { + #define POWERMODE_TYPE_CLUSTER 0 + #define POWERMODE_TYPE_SYSTEM 1 + + compatible = "samsung,exynos-cpupm"; + status = "okay"; + + cpd_cl0 { + device_type = "cpupm"; + target-residency = <10000>; + type = <POWERMODE_TYPE_CLUSTER>; + cal-id = <0>; + siblings = CPU_CL0; + }; + + cpd_cl1 { + device_type = "cpupm"; + target-residency = <10000>; + type = <POWERMODE_TYPE_CLUSTER>; + cal-id = <1>; + siblings = CPU_CL1; + entry-allowed = CPU_CL1; + }; + + cpd_cl2 { + device_type = "cpupm"; + target-residency = <10000>; + type = <POWERMODE_TYPE_CLUSTER>; + cal-id = <2>; + siblings = CPU_CL2; + entry-allowed = CPU_CL2; + }; + + sicd { + device_type = "cpupm"; + target-residency = <10000>; + type = <POWERMODE_TYPE_SYSTEM>; + siblings = CPU_ALL; + entry-allowed = CPU_ALL; + }; + + wakeup-mask { + wakeup-masks { + wakeup-mask { + mask-reg-offset = <0x3944>; + stat-reg-offset = <0x3950>; + mask = <0x0ff00000>; + }; + wakeup-mask2 { + mask-reg-offset = <0x3964>; + stat-reg-offset = <0x3970>; + mask = <0x00>; + }; + }; + + eint-wakeup-masks { + eint-wakeup-mask { + mask-reg-offset = <0x3a80>; + }; + eint-wakeup-mask2 { + mask-reg-offset = <0x3a84>; + }; + eint-wakeup-mask3 { + mask-reg-offset = <0x3a88>; + }; + }; + }; + + idle-ip { + extern-idle-ip = + "dbg_core"; + }; + }; + + exynos-acme { + compatible = "samsung,exynos-acme"; + status = "okay"; + + cpufreq_domain0: domain@0 { + sibling-cpus = CPU_CL0; + cal-id = <ACPM_DVFS_CPUCL0>; + dm-type = <DM_CPU_CL0>; + + min-freq = <300000>; + max-freq = <1803000>; + resume-freq = <1197000>; + + #cooling-cells = <2>; /* min followed by max */ + ect-coeff-index = <2>; + tz-cooling-name = "LITTLE"; + max-dfs-count= <0>; + skip-boot-pmqos; + use-em-coeff; + + dm-constraints { + list = <&lit_mif_perf>; + }; + }; + + cpufreq_domain1: domain@1 { + sibling-cpus = CPU_CL1; + cal-id = <ACPM_DVFS_CPUCL1>; + dm-type = <DM_CPU_CL1>; + + min-freq = <400000>; + max-freq = <2348000>; + resume-freq = <1491000>; + + #cooling-cells = <2>; /* min followed by max */ + ect-coeff-index = <1>; + tz-cooling-name = "MID"; + max-dfs-count = <2>; + skip-boot-pmqos; + use-em-coeff; + + dm-constraints { + list = <&med_ank_perf>; + }; + }; + + cpufreq_domain2: domain@2 { + sibling-cpus = CPU_CL2; + cal-id = <ACPM_DVFS_CPUCL2>; + dm-type = <DM_CPU_CL2>; + + min-freq = <500000>; + max-freq = <2850000>; + resume-freq = <1826000>; + + #cooling-cells = <2>; /* min followed by max */ + ect-coeff-index = <0>; + tz-cooling-name = "BIG"; + max-dfs-count = <2>; + skip-boot-pmqos; + use-em-coeff; + + dm-constraints { + list = <&big_ank_perf>; + }; + }; + }; + + dm-tables { + lit_mif_perf: dm-table@0 { + }; + med_ank_perf: dm-table@3 { + const-type = <CONSTRAINT_MIN>; + dm-constraint = <DM_CPU_CL0>; + driver-cal-id = <ACPM_DVFS_CPUCL1>; + constraint-cal-id = <ACPM_DVFS_CPUCL0>; + + /* CL1 CL0 */ + table = < 2348000 1328000 + 2253000 1197000 + 2130000 1098000 + 1999000 1098000 + 1836000 1098000 + 1663000 1098000 + 1491000 930000 + 1328000 930000 + 1197000 738000 + 1024000 738000 + 910000 574000 + 799000 574000 + 696000 574000 + 553000 574000 + 400000 300000 >; + }; + big_ank_perf: dm-table@6 { + const-type = <CONSTRAINT_MIN>; + dm-constraint = <DM_CPU_CL0>; + driver-cal-id = <ACPM_DVFS_CPUCL2>; + constraint-cal-id = <ACPM_DVFS_CPUCL0>; + + /* CL2 CL0 */ + table = < 2850000 1401000 + 2802000 1401000 + 2704000 1401000 + 2630000 1401000 + 2507000 1401000 + 2401000 1401000 + 2252000 1328000 + 2188000 1328000 + 2048000 1197000 + 1826000 1098000 + 1745000 1098000 + 1582000 930000 + 1426000 930000 + 1277000 738000 + 1106000 738000 + 984000 738000 + 851000 574000 + 500000 300000 >; + }; + }; + + pixel_em_table: pixel-em { + compatible = "google,pixel-em"; + profiles = + "cam1 + cpu0 { + 300000 38 6000 + 574000 47 11000 + 738000 71 14000 + 930000 92 29000 + 1098000 93 60000 + 1197000 103 73000 + 1328000 104 89000 + 1401000 134 106000 + 1598000 141 138000 + 1704000 157 167000 + 1803000 166 195000 + } + cpu4 { + 400000 165 73000 + 553000 178 99000 + 696000 191 126000 + 799000 207 146000 + 910000 223 172000 + 1024000 240 197000 + 1197000 287 237000 + 1328000 334 274000 + 1491000 381 322000 + 1663000 427 382000 + 1836000 474 436000 + 1999000 521 519000 + 2130000 568 596000 + 2253000 615 689000 + 2348000 662 789000 + } + cpu6 { + 500000 193 160000 + 851000 274 245000 + 984000 289 282000 + 1106000 305 317000 + 1277000 307 381000 + 1426000 340 435000 + 1582000 379 481000 + 1745000 453 549000 + 1826000 477 588000 + 2048000 538 699000 + 2188000 599 804000 + 2252000 659 855000 + 2401000 720 1013000 + 2507000 781 1132000 + 2630000 842 1313000 + 2704000 902 1451000 + 2802000 963 1685000 + 2850000 1024 1816000 + } + ", + "cam2 + cpu0 { + 300000 38 6000 + 574000 47 11000 + 738000 61 14000 + 930000 77 29000 + 1098000 92 60000 + 1197000 101 73000 + 1328000 114 89000 + 1401000 121 106000 + 1598000 141 138000 + 1704000 153 167000 + 1803000 166 195000 + } + cpu4 { + 400000 165 73000 + 553000 178 99000 + 696000 201 126000 + 799000 217 146000 + 910000 238 172000 + 1024000 285 197000 + 1197000 327 237000 + 1328000 357 274000 + 1491000 380 322000 + 1663000 419 382000 + 1836000 460 436000 + 1999000 521 519000 + 2130000 568 596000 + 2253000 615 689000 + 2348000 662 789000 + } + cpu6 { + 500000 193 160000 + 851000 267 245000 + 984000 295 282000 + 1106000 320 317000 + 1277000 357 381000 + 1426000 390 435000 + 1582000 419 481000 + 1745000 471 549000 + 1826000 497 588000 + 2048000 568 699000 + 2188000 620 804000 + 2252000 650 855000 + 2401000 720 1013000 + 2507000 781 1132000 + 2630000 842 1313000 + 2704000 902 1451000 + 2802000 963 1685000 + 2850000 1024 1816000 + } + ", + "ui + cpu0 { + 300000 60 16000 + 574000 114 39000 + 738000 147 56000 + 930000 185 80000 + 1098000 218 106000 + 1197000 238 125000 + 1328000 264 151000 + 1401000 278 166000 + 1598000 317 220000 + 1704000 338 253000 + 1803000 358 294000 + } + cpu4 { + 400000 146 70000 + 553000 202 107000 + 696000 254 151000 + 799000 292 186000 + 910000 333 228000 + 1024000 374 275000 + 1197000 437 361000 + 1328000 485 440000 + 1491000 545 539000 + 1663000 608 673000 + 1836000 671 837000 + 1999000 730 1022000 + 2130000 778 1212000 + 2253000 823 1403000 + 2348000 858 1578000 + } + cpu6 { + 500000 180 125000 + 851000 306 266000 + 984000 354 332000 + 1106000 397 410000 + 1277000 459 516000 + 1426000 512 626000 + 1582000 568 753000 + 1745000 627 925000 + 1826000 656 1012000 + 2048000 736 1289000 + 2188000 786 1494000 + 2252000 809 1620000 + 2401000 863 1883000 + 2507000 901 2116000 + 2630000 945 2435000 + 2704000 972 2674000 + 2802000 1007 3054000 + 2850000 1024 3269000 + } + "; + idle_energy = + " + cpu0 { + 300000 2000 + 574000 2000 + 738000 2000 + 930000 2000 + 1098000 2000 + 1197000 3000 + 1328000 3000 + 1401000 3000 + 1598000 4000 + 1704000 4000 + 1803000 5000 + } + cpu4 { + 400000 4000 + 553000 5000 + 696000 5000 + 799000 5000 + 910000 6000 + 1024000 6000 + 1197000 6000 + 1328000 7000 + 1491000 8000 + 1663000 9000 + 1836000 11000 + 1999000 13000 + 2130000 15000 + 2253000 19000 + 2348000 24000 + } + cpu6 { + 500000 15000 + 851000 17000 + 984000 18000 + 1106000 18000 + 1277000 21000 + 1426000 23000 + 1582000 24000 + 1745000 27000 + 1826000 29000 + 2048000 33000 + 2188000 37000 + 2252000 41000 + 2401000 48000 + 2507000 54000 + 2630000 62000 + 2704000 70000 + 2802000 83000 + 2850000 96000 + } + "; + }; +};
diff --git a/dts/gs201-cs40l26a-config.dtsi b/dts/gs201-cs40l26a-config.dtsi new file mode 100644 index 0000000..b378551 --- /dev/null +++ b/dts/gs201-cs40l26a-config.dtsi
@@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 cs40l26 device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + * +*/ + +#include <dt-bindings/gpio/gpio.h> +#include <arm64/exynos/exynos-pinctrl.h> + +&dai_be_haptic_rx { + dai_be_haptic_rx_codec: codec { + sound-dai = <&cs40l26_codec 0>; + }; +}; + +&aoc_snd_card { + clks { + sys { + sys@cs40l26_codec { + comp = <&cs40l26_codec>; + src = "BCLK"; + /* clk id */ + id = <0>; + /* clk source */ + srcid = <0>; + /* in clk multiple */ + in_mul = <1>; + /* out clk multiple */ + out_mul = <1>; + }; + }; + }; +}; + +/* GPIO_FAR_ALIVE */ +&pinctrl_1 { + hapt_amp_irq: hapt-amp-irq { + samsung,pins = "gpa8-1"; /* XEINT_13 */ + samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; +}; + +/* GPIO_PERIC1 */ +&pinctrl_5 { + hapt_amp_rst: hapt-amp-rst { + samsung,pins = "gpp24-3"; /* XAPC_USI15_CTSn_CSn */ + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; + + hapt_amp_trig: hapt-amp-trig { + samsung,pins = "gpp24-2"; /* XAPC_USI15_RTSn_DI */ + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; +}; + +&hsi2c_8 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c8_bus>; + + clock-frequency = <400000>; + + cs40l26a_haptics: cs40l26a@43 { + compatible = "cirrus,cs40l26a"; + reg = <0x43>; + input-device-name = "cs40l26_input"; /* input device name */ + + pinctrl-names = "default"; + pinctrl-0 = <&hapt_amp_irq &hapt_amp_rst &hapt_amp_trig>; + + interrupt-parent = <&gpa8>; + interrupts = <1 0 0>; + + reset-gpios = <&gpp24 3 GPIO_ACTIVE_LOW>; + + cirrus,bst-dcm-en = <0>; + cirrus,pwle-zero-cross-en; + cirrus,vpbr-enable; + cirrus,vpbr-thld-uv = <3000000>; /* 3.0V */ + cirrus,bst-expl-mode-disable; + cirrus,bst-ipk-microamp = <2500000>; /* 2.5A */ + cirrus,bst-ctl-microvolt = <11000000>; /* 11V */ + cirrus,f0-default = <0x244000>; /* 145 Hz */ + cirrus,redc-default = <0x68000>; /* 13 Ohm */ + cirrus,pm-active-timeout-ms = <5>; + + status = "okay"; + + cs40l26_codec: cs40l26_codec@snd { + #sound-dai-cells = <1>; + compatible = "cs40l26-codec"; + status = "okay"; + }; + }; +};
diff --git a/dts/gs201-debug.dtsi b/dts/gs201-debug.dtsi new file mode 100644 index 0000000..88184cc --- /dev/null +++ b/dts/gs201-debug.dtsi
@@ -0,0 +1,817 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * debug device tree source code for gs201 SoC + * + * Copyright (C) 2020 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include <dt-bindings/interrupt-controller/gs201.h> +#include "gs201-dpm.dtsi" +#include "gs201-ppmu.dtsi" +/ { + dss: dss { + compatible = "google,debug-snapshot"; + freq_names = "LIT", "MID", "BIG", "INT", "MIF", "ISP", + "DISP", "INTCAM", "TPU", "TNR", "MFC", + "BO"; + memory-region = <&header>, <&log_kevents>, <&log_bcm>, <&log_s2d>, + <&log_arrdumpreset>, <&log_arrdumppanic>, + <&log_slcdump>, <&log_preslcdump>, + <&log_itmon>; + panic-action = <GO_DEFAULT_ID>; + }; + + hardlockup-debugger { + compatible = "google,hardlockup-debug"; + use_multistage_wdt_irq = <830>; /* IRQ_WDT_CLUSTER1_MISC + 32 */ + }; + + hardlockup-watchdog { + compatible = "google,hardlockup-watchdog"; + sampling_time = <4>; + opportunity_count = <3>; + panic = <1>; + }; + + dss-built { + compatible = "google,debug-snapshot-built"; + memory-region = <&header>; + }; + + dss-qdump { + compatible = "google,debug-snapshot-qdump"; + }; + + dss-sfrdump { + compatible = "google,debug-snapshot-sfrdump"; + /* + * -----------<< Example >>------------------- + * dump-info { + * #address-cells = <1>; + * #size-cells = <1>; + * + * gic-setenable { + * reg = <0x11f01100 0x100>; + * }; + * gic-setpend { + * reg = <0x11f01200 0x100>; + * }; + * gic-setactive { + * reg = <0x11f01300 0x100>; + * }; + *}; + */ + }; + + dss-debug-kinfo { + compatible = "google,debug-snapshot-debug-kinfo"; + memory-region = <&debug_kinfo_reserved>; + }; + + exynos-debug-test { + compatible = "google,exynos-debug-test"; + ps_hold_control_offset = <0x3e9c>; + nr_cpu = <0x8>; + nr_little_cpu = <0x4>; + nr_mid_cpu = <0x2>; + nr_big_cpu = <0x2>; + little_cpu_start = <0x0>; + mid_cpu_start = <0x4>; + big_cpu_start = <0x6>; + }; + + keydebug { + compatible = "keydebug"; + key_down_delay = <6000>; + keys_down = <116 115>; + dbg_fn_delay = <2000>; + }; + + debug-kinfo { + compatible = "google,debug-kinfo"; + memory-region = <&debug_kinfo_reserved>; + }; + + boot-metrics { + compatible = "google,boot-metrics"; + + reg = <0x0 0x02038000 0x00001000>; + reg-names = "ns_sram_base"; + offset = <0x880>; + }; + + pixel-suspend-diag { + compatible = "google,pixel-suspend-diag"; + memory-region = <&suspend_diag_log_reserved>; + }; + + gs201-itmon { + compatible = "google,gs201-itmon"; + interrupts = + <GIC_SPI IRQ_TREX_D_NOCL1B_debugInterrupt_NOCL1B + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_TREX_D_NOCL2A_debugInterrupt_NOCL2A + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_TREX_D_NOCL1A_debugInterrupt_NOCL1A + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_TREX_D_NOCL0_debugInterrupt_NOCL0 + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_TREX_P_NOCL0_debugInterrupt_NOCL0 + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_TREX_P_NOCL1B_debugInterrupt_NOCL1B + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_TREX_P_NOCL2A_debugInterrupt_NOCL2A + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_TREX_P_NOCL1A_debugInterrupt_NOCL1A + IRQ_TYPE_LEVEL_HIGH>; + panic_count = <0>; + err_fatal = <GO_S2D_ID>; + err_drex_tmout = <GO_S2D_ID>; + err_ip = <GO_DEFAULT_ID>; + err_cpu = <GO_S2D_ID>; + err_unhandled = <GO_PANIC_ID>; + }; + + coresight@2b000000 { + compatible = "google,exynos-coresight"; + dbg_base = <0x2b810000>, <0x2b910000>, <0x2ba10000>, <0x2bb10000>, + <0x2bc10000>, <0x2bd10000>, <0x2be10000>, <0x2bf10000>; + cti_base = <0x2b820000>, <0x2b920000>, <0x2ba20000>, <0x2bb20000>, + <0x2bc20000>, <0x2bd20000>, <0x2be20000>, <0x2bf20000>; + pmu_base = <0x2b830000>, <0x2b930000>, <0x2ba30000>, <0x2bb30000>, + <0x2bc30000>, <0x2bd30000>, <0x2be30000>, <0x2bf30000>; + sgi_base = <0x10450000>, <0x10470000>, <0x10490000>, <0x104b0000>, + <0x104d0000>, <0x104f0000>, <0x10510000>, <0x10530000>; + gpr_base = <0x2b001000>; + dbgack-mask = <0xff00000>; + halt = <1>; + retention = <1>; + }; + + ecc-handler { + compatible = "google,exynos-ecc-handler"; + interrupts = <GIC_SPI IRQ_CPUCL0_ERRIRQ_0_CPUCL0 IRQ_TYPE_LEVEL_HIGH>, /* DSU */ + <GIC_SPI IRQ_CPUCL0_ERRIRQ_1_CPUCL0 IRQ_TYPE_LEVEL_HIGH>, /* CORE0 */ + <GIC_SPI IRQ_CPUCL0_ERRIRQ_2_CPUCL0 IRQ_TYPE_LEVEL_HIGH>, /* CORE1 */ + <GIC_SPI IRQ_CPUCL0_ERRIRQ_3_CPUCL0 IRQ_TYPE_LEVEL_HIGH>, /* CORE2 */ + <GIC_SPI IRQ_CPUCL0_ERRIRQ_4_CPUCL0 IRQ_TYPE_LEVEL_HIGH>, /* CORE3 */ + <GIC_SPI IRQ_CPUCL0_ERRIRQ_5_CPUCL0 IRQ_TYPE_LEVEL_HIGH>, /* CORE4 */ + <GIC_SPI IRQ_CPUCL0_ERRIRQ_6_CPUCL0 IRQ_TYPE_LEVEL_HIGH>, /* CORE5 */ + <GIC_SPI IRQ_CPUCL0_ERRIRQ_7_CPUCL0 IRQ_TYPE_LEVEL_HIGH>, /* CORE6 */ + <GIC_SPI IRQ_CPUCL0_ERRIRQ_8_CPUCL0 IRQ_TYPE_LEVEL_HIGH>; /* CORE7 */ + + interrupt-names ="DSU, L3 DATA or TAG or Snoop filter RAM", + "CORE0, L1,L2 DATA or TAG RAM", + "CORE1, L1,L2 DATA or TAG RAM", + "CORE2, L1,L2 DATA or TAG RAM", + "CORE3, L1,L2 DATA or TAG RAM", + "CORE4, L1,L2 DATA or TAG RAM", + "CORE5, L1,L2 DATA or TAG RAM", + "CORE6, L1,L2 DATA or TAG RAM", + "CORE7, L1,L2 DATA or TAG RAM"; + }; + + exynos-etm { + compatible = "google,exynos-etm"; + cs_base = <0x2b000000>; + boot-start = <0>; + funnel-num = <3>; + etf-num = <2>; + trex-num = <4>; + /* funnel-port = <(funnel num) (port num)>; */ + etm0 { + device_type = "etm"; + offset = <0x840000>; + funnel-port = <0 0>; + }; + etm1 { + device_type = "etm"; + offset = <0x940000>; + funnel-port = <0 1>; + }; + etm2 { + device_type = "etm"; + offset = <0xa40000>; + funnel-port = <1 0>; + }; + etm3 { + device_type = "etm"; + offset = <0xb40000>; + funnel-port = <1 1>; + }; + etm4 { + device_type = "etm"; + offset = <0xc40000>; + funnel-port = <1 2>; + }; + etm5 { + device_type = "etm"; + offset = <0xd40000>; + funnel-port = <1 3>; + }; + etm6 { + device_type = "etm"; + offset = <0xe40000>; + funnel-port = <0 2>; + }; + etm7 { + device_type = "etm"; + offset = <0xf40000>; + funnel-port = <0 3>; + }; + etf0@4000 { + device_type = "etf"; + offset = <0x4000>; + funnel-port = <2 0>; + }; + etf1@5000 { + device_type = "etf"; + offset = <0x5000>; + funnel-port = <2 1>; + }; + funnel0@7000 { + device_type = "funnel"; + offset = <0x7000>; + }; + funnel1@8000 { + device_type = "funnel"; + offset = <0x8000>; + }; + funnel2@9000 { + device_type = "funnel"; + offset = <0x9000>; + }; + etr@A000 { + device_type = "etr"; + sfr_base = <0x2b00c000 0x100>; + qch-offset = <0x2c>; + offset = <0xA000>; + buf-size = <0x100000>; + }; + bdu@10000 { + device_type = "bdu"; + offset = <0x10000>; + funnel-port = <1 5>; + }; + bdu_etf@11000 { + device_type = "bdu_etf"; + offset = <0x11000>; + }; + trex0 { + device_type = "trex"; + mux_ctrl = <0x66>; + dbg_trace_addr = <0x1ea83010>; + dbg_trace_val = <5>; + }; + trex1 { + device_type = "trex"; + mux_ctrl = <0x77>; + dbg_trace_addr = <0x1f603010>; + dbg_trace_val = <26>; + }; + trex2 { + device_type = "trex"; + mux_ctrl = <0x88>; + dbg_trace_addr = <0x204e3010>; + dbg_trace_val = <8>; + }; + trex3 { + device_type = "trex"; + mux_ctrl = <0x55>; + dbg_trace_addr = <0x1e503010>; + dbg_trace_val = <8>; + }; + }; + + etm0: etm@2b840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0 0x2b840000 0x1000>; + cpu = <&cpu0>; + + coresight-name = "coresight-etm0"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&funnel0_in_port0>; + }; + }; + }; + }; + + etm1: etm@2b940000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0 0x2b940000 0x1000>; + cpu = <&cpu1>; + + coresight-name = "coresight-etm1"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&funnel0_in_port1>; + }; + }; + }; + }; + + etm2: etm@2ba40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0 0x2ba40000 0x1000>; + cpu = <&cpu2>; + + coresight-name = "coresight-etm2"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm2_out_port: endpoint { + remote-endpoint = <&funnel1_in_port0>; + }; + }; + }; + }; + + etm3: etm@2bb40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0 0x2bb40000 0x1000>; + cpu = <&cpu3>; + + coresight-name = "coresight-etm3"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm3_out_port: endpoint { + remote-endpoint = <&funnel1_in_port1>; + }; + }; + }; + }; + + etm4: etm@2bc40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0 0x2bc40000 0x1000>; + cpu = <&cpu4>; + + coresight-name = "coresight-etm4"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm4_out_port: endpoint { + remote-endpoint = <&funnel1_in_port2>; + }; + }; + }; + }; + + etm5: etm@2bd40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0 0x2bd40000 0x1000>; + cpu = <&cpu5>; + + coresight-name = "coresight-etm5"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm5_out_port: endpoint { + remote-endpoint = <&funnel1_in_port3>; + }; + }; + }; + }; + + etm6: etm@2be40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0 0x2be40000 0x1000>; + cpu = <&cpu6>; + + coresight-name = "coresight-etm6"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm6_out_port: endpoint { + remote-endpoint = <&funnel0_in_port2>; + }; + }; + }; + }; + + etm7: etm@2bf40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0 0x2bf40000 0x1000>; + cpu = <&cpu7>; + + coresight-name = "coresight-etm7"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm7_out_port: endpoint { + remote-endpoint = <&funnel0_in_port3>; + }; + }; + }; + }; + + funnel0: funnel@2b007000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0 0x2b007000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel0"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel0_out_port: endpoint { + remote-endpoint = <&etf0_in_port>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel0_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel0_in_port1: endpoint { + remote-endpoint = <&etm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + funnel0_in_port2: endpoint { + remote-endpoint = <&etm6_out_port>; + }; + }; + + port@3 { + reg = <3>; + funnel0_in_port3: endpoint { + remote-endpoint = <&etm7_out_port>; + }; + }; + }; + }; + + funnel1: funnel@2b008000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0 0x2b008000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel1"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel1_out_port: endpoint { + remote-endpoint = <&etf1_in_port>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel1_in_port0: endpoint { + remote-endpoint = <&etm2_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel1_in_port1: endpoint { + remote-endpoint = <&etm3_out_port>; + }; + }; + + port@2 { + reg = <2>; + funnel1_in_port2: endpoint { + remote-endpoint = <&etm4_out_port>; + }; + }; + + port@3 { + reg = <3>; + funnel1_in_port3: endpoint { + remote-endpoint = <&etm5_out_port>; + }; + }; + }; + }; + + funnel2: funnel@2b009000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0 0x2b009000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel2"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel2_out_port: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel2_in_port0: endpoint { + remote-endpoint = <&etf0_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel2_in_port1: endpoint { + remote-endpoint = <&etf1_out_port>; + }; + }; + }; + }; + + etf0: etf@2b004000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + arm,primecell-periphid = <0x001bb961>; + reg = <0 0x2b004000 0x1000>; + + coresight-name = "coresight-etf0"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + etf0_in_port: endpoint { + remote-endpoint = <&funnel0_out_port>; + }; + }; + }; + + out-ports { + port { + etf0_out_port: endpoint { + remote-endpoint = <&funnel2_in_port0>; + }; + }; + }; + }; + + etf1: etf@2b005000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + arm,primecell-periphid = <0x001bb961>; + reg = <0 0x2b005000 0x1000>; + + coresight-name = "coresight-etf1"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + etf1_in_port: endpoint { + remote-endpoint = <&funnel1_out_port>; + }; + }; + }; + + out-ports { + port { + etf1_out_port: endpoint { + remote-endpoint = <&funnel2_in_port1>; + }; + }; + }; + }; + + etr: etr@2b00a000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + arm,primecell-periphid = <0x001bb961>; + reg = <0 0x2b00a000 0x1000>; + + coresight-name = "coresight-etr"; + arm,scatter-gather; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&funnel2_out_port>; + }; + }; + }; + }; + + etr-miu@110B0000 { + compatible = "google,gs101-etr-miu"; + reg = <0x0 0x110B0000 0x100>; + tmc_buf_addr = <0x00000010 0x00000000>; + tmc_buf_size = <0x10000000>; + }; + + exynos-adv_tracer { + compatible = "google,exynos-adv-tracer"; + reg = <0x0 0x18360000 0x1000>; + reg-names = "mailbox"; + interrupts = <GIC_SPI IRQ_MAILBOX_DBGCORE2AP_ALIVE IRQ_TYPE_LEVEL_HIGH>; + pmu-dbgcore-config = <0x3080>; + pmu-dbgcore-status = <0x3084>; + intr-bitoffset = <0>; + status = "ok"; + }; + + exynos_adv_tracer_s2d { + compatible = "google,exynos-adv-tracer-s2d"; + plugin-len = <3>; + plugin-name = "S2D"; + pmu-burnin-ctrl = <0x3cd0>; + sel-scanmode-bit = <25>; + dbgsel-sw-bit = <4>; + blk-list = "AOC", "AOCCORE", "AUR", "AURCORE", "BO", "BOCORE", + "CMU", "CPUCL0", "CLUSTER0", "CSIS", + "DISP", "DNS", "DPU", "EH", "G2D", "G3AA", + "G3D", "GPU", "GDC", "GSA", "HSI0", "HSI1", + "HSI2", "IPP", "ITP", "MCSC", "MFC", "MIF0", "MIF1", + "MIF2", "MIF3", "NOCL0", "NOCL1A", "NOCL1B", "NOCL2A", + "PDP", "PERIC0", "PERIC1", "TNR", + "TPU", "TPUCORE", "SLC0", "SLC1", "SLC2", "SLC3"; + status = "ok"; + }; + + exynos-ehld { + compatible = "google,exynos-ehld"; + #address-cells = <1>; + #size-cells = <1>; + cs_base = <0x2b000000>; + sgi_base = <0x10450000>, <0x10470000>, <0x10490000>, <0x104b0000>, + <0x104d0000>, <0x104f0000>, <0x10510000>, <0x10530000>; + status = "ok"; + + dbgc { + /* IPC */ + plugin-len = <4>; + plugin-name = "ELD"; + support = <1>; + interval = <1000>; + warn-count = <4>; + use-tick-timer = <0>; + }; + + cpu0 { + dbg-offset = <0x810000>; + }; + cpu1 { + dbg-offset = <0x910000>; + }; + cpu2 { + dbg-offset = <0xa10000>; + }; + cpu3 { + dbg-offset = <0xb10000>; + }; + cpu4 { + dbg-offset = <0xc10000>; + }; + cpu5 { + dbg-offset = <0xd10000>; + }; + cpu6 { + dbg-offset = <0xe10000>; + }; + cpu7 { + dbg-offset = <0xf10000>; + }; + }; + + sjtag_ap { + compatible = "google,sjtag"; + ms-per-tick = <5590>; + ipc-timeout-ms = <450>; + pubkey = /bits/ 8 <0xc1 0x13 0xb3 0x1d 0x85 0x6a 0xac 0xc2 0x35 0xf1 0xd7 0x9e + 0x08 0x91 0xc6 0xab 0x16 0xf8 0xfd 0x2f 0x14 0xaa 0x91 0x1d + 0x85 0xc0 0xf6 0x08 0xb1 0xa3 0xfe 0xb8 0x2f 0xa2 0x11 0x1a + 0x6b 0x2b 0xcb 0x21 0x29 0x8b 0xda 0xba 0x30 0x2d 0xb0 0x52 + 0x8f 0x19 0x8f 0x77 0x2b 0x0c 0x69 0x29 0x04 0x14 0x7b 0x3c + 0x5c 0x96 0x74 0x90 0x7e 0x01 0x00 0x00 0x37 0x6a 0x20 0x58 + 0xd3 0xc0 0xb9 0xd0 0x36 0xd1 0x7b 0x1a 0x98 0xc7 0x4b 0xb3 + 0xf8 0xb4 0x13 0xcc 0xf0 0x82 0x17 0x44 0x1e 0x5e 0x64 0xa3 + 0x2e 0x62 0x8b 0x6e 0x14 0xa1 0x45 0x14 0x75 0xc3 0x86 0xff + 0x4d 0x05 0x8b 0x6a 0x42 0x94 0xd7 0x04 0xc2 0x1c 0xe8 0x34 + 0xda 0xed 0x1e 0xbb 0x9a 0x0f 0xcc 0xad 0x3f 0xbe 0xf9 0x4c + 0x52 0x01 0x00 0x00>; + dbg-domain = <0x8028eff9>; + access-lvl = <0xc0000cc0 0xfcffffc3>; + dbg-itvl = <0>; + gsa-device = <&gsa>; + }; + + sjtag_gsa { + compatible = "google,sjtag"; + ms-per-tick = <5590>; + ipc-timeout-ms = <450>; + pubkey = /bits/ 8 <0xe2 0x15 0xce 0xbb 0xc4 0xcb 0x55 0x24 0xf9 0xb3 0x54 0xd8 + 0x3f 0x71 0xf7 0xd5 0x16 0x2b 0xa3 0x38 0x74 0x31 0x4b 0x9b + 0x4d 0xa3 0x5f 0xe8 0x5b 0xf0 0x34 0xa1 0x00 0x96 0x71 0x31 + 0x25 0x34 0x97 0xcd 0x83 0xb8 0x59 0x5e 0xa3 0xdb 0xb5 0xe8 + 0x9e 0x7f 0xb0 0x9d 0x10 0x16 0x7e 0x02 0x27 0x90 0x47 0x74 + 0x71 0xc1 0x37 0xcb 0x81 0x00 0x00 0x00 0x68 0xb9 0xd3 0x84 + 0x72 0x4f 0xa3 0xdf 0x5e 0x7a 0x51 0x83 0x75 0x79 0x02 0x5b + 0x77 0xd5 0x43 0x05 0x00 0x40 0xa6 0x64 0x92 0x33 0xcf 0x32 + 0x43 0x8c 0x5b 0x46 0x92 0xc0 0x96 0x41 0x7a 0x4a 0x01 0xed + 0xd1 0x2d 0x58 0xe2 0x3e 0xb3 0x4b 0xfa 0x0c 0x8c 0x69 0x11 + 0x46 0x25 0x3d 0xa4 0xb7 0x20 0x9b 0x82 0x87 0xb0 0x9e 0x95 + 0xc6 0x01 0x00 0x00>; + dbg-domain = <0x0000006f>; + access-lvl = <0x00000000 0x00003cff>; + dbg-itvl = <0>; + gsa-device = <&gsa>; + }; +};
diff --git a/dts/gs201-dit.dtsi b/dts/gs201-dit.dtsi new file mode 100644 index 0000000..5ae2cce --- /dev/null +++ b/dts/gs201-dit.dtsi
@@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Samsung CP interface device tree source + * + * Copyright (c) 2019-2020 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include <dt-bindings/soc/google/exynos-dit.h> + +/ { + dit { + compatible = "samsung,exynos-dit"; + status = "okay"; + + interrupt-parent = <&gic>; + interrupts = <GIC_SPI IRQ_DIT_RxDst00_MISC IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DIT_RxDst1_MISC IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DIT_RxDst2_MISC IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DIT_TxDst0_MISC IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "DIT-RxDst00", "DIT-RxDst1", "DIT-RxDst2", "DIT-Tx"; + + reg = <0x0 0x10190000 0x00010000>, <0x0 0x10030000 0x00002000>; + reg-names = "dit", "sysreg"; + + /* DIT_SHARABILITY_CON or DIT_BUS_CON */ + dit_sharability_offset = <0x00001108>; + dit_sharability_value = <0x00110011>; + + dit_hw_capabilities = <(DIT_CAP_MASK_NONE)>; + + dit_use_tx = <0>; + dit_use_rx = <0>; + dit_use_clat = <0>; + dit_use_recycling = <0>; + + dit_hal_support = <1>; + dit_hal_enqueue_rx = <0>; + + dit_rx_extra_desc_ring_len = <2048>; + dit_irq_affinity = <2>; + }; +};
diff --git a/dts/gs201-dpm-eng.dts b/dts/gs201-dpm-eng.dts new file mode 100644 index 0000000..0d2acf7 --- /dev/null +++ b/dts/gs201-dpm-eng.dts
@@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; +/plugin/; + +#include "gs201-dpm-eng.dtsi" +#include "avf-dpm-eng.dtsi"
diff --git a/dts/gs201-dpm-eng.dtsi b/dts/gs201-dpm-eng.dtsi new file mode 100644 index 0000000..d585cc3 --- /dev/null +++ b/dts/gs201-dpm-eng.dtsi
@@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <dt-bindings/soc/google/debug-snapshot-def.h> + +&dpm { + version = <101>; + variant = "eng"; + + security { + cp_mem_not_clear = <0>; + dbg_mem_enable = <1>; + seh_enable = <0>; + pm_test_enable = <0>; + seclog_enable = <0>; + harxlog_enable = <0>; + sdm_enable = <0>; + ERXPFG_enable = <1>; + }; + + abl { + ramdump_mode = <DPM_ENABLE>; + ramdump2usb = <DPM_ENABLE>; + }; + + feature { + /* dump-mode support */ + dump-mode { + enabled = <1>; + file-support = <0>; + }; + + event { + method = DSS_LOG_TASK, + DSS_LOG_WORK, + DSS_LOG_CPUIDLE, + DSS_LOG_SUSPEND, + DSS_LOG_IRQ, + DSS_LOG_HRTIMER, + DSS_LOG_CLK, + DSS_LOG_PMU, + DSS_LOG_FREQ, + DSS_LOG_DM, + DSS_LOG_REGULATOR, + DSS_LOG_THERMAL, + DSS_LOG_ACPM, + DSS_LOG_PRINTK; + }; + + /* debug-kinfo support */ + debug-kinfo { + enabled = <1>; + }; + }; + + policy { + exception { + pre_log = <1>; + + el1_da = <GO_DEFAULT_ID>; + el1_ia = <GO_DEFAULT_ID>; + el1_undef = <GO_DEFAULT_ID>; + el1_sp_pc = <GO_DEFAULT_ID>; + el1_inv = <GO_DEFAULT_ID>; + el1_serror = <GO_DEFAULT_ID>; + }; + }; +}; /* end of dpm */
diff --git a/dts/gs201-dpm-user.dts b/dts/gs201-dpm-user.dts new file mode 100644 index 0000000..b9ed38e --- /dev/null +++ b/dts/gs201-dpm-user.dts
@@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; +/plugin/; + +#include "gs201-dpm-user.dtsi" +#include "avf-dpm-user.dtsi"
diff --git a/dts/gs201-dpm-user.dtsi b/dts/gs201-dpm-user.dtsi new file mode 100644 index 0000000..40da348 --- /dev/null +++ b/dts/gs201-dpm-user.dtsi
@@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <dt-bindings/soc/google/debug-snapshot-def.h> + +&dpm { + version = <101>; + variant = "user"; + + security { + cp_mem_not_clear = <0>; + dbg_mem_enable = <0>; + seh_enable = <0>; + pm_test_enable = <0>; + seclog_enable = <0>; + harxlog_enable = <0>; + sdm_enable = <0>; + ERXPFG_enable = <0>; + }; + + abl { + ramdump_mode = <0>; + ramdump2usb = <0>; + }; + + feature { + /* dump-mode support */ + dump-mode { + enabled = <1>; + file-support = <0>; + }; + + event { + method = DSS_LOG_TASK, + DSS_LOG_WORK, + DSS_LOG_CPUIDLE, + DSS_LOG_SUSPEND, + DSS_LOG_IRQ, + DSS_LOG_HRTIMER, + DSS_LOG_CLK, + DSS_LOG_PMU, + DSS_LOG_FREQ, + DSS_LOG_DM, + DSS_LOG_REGULATOR, + DSS_LOG_THERMAL, + DSS_LOG_ACPM, + DSS_LOG_PRINTK; + }; + + /* debug-kinfo support */ + debug-kinfo { + enabled = <1>; + }; + }; + + policy { + exception { + pre_log = <1>; + + el1_da = <GO_DEFAULT_ID>; + el1_ia = <GO_DEFAULT_ID>; + el1_undef = <GO_DEFAULT_ID>; + el1_sp_pc = <GO_DEFAULT_ID>; + el1_inv = <GO_DEFAULT_ID>; + el1_serror = <GO_DEFAULT_ID>; + }; + }; +}; /* end of dpm */ + +&log_arrdumppanic { + status = "disabled"; +}; + +&log_preslcdump { + status = "disabled"; +}; + +&log_slcdump { + status = "disabled"; +};
diff --git a/dts/gs201-dpm-userdebug.dts b/dts/gs201-dpm-userdebug.dts new file mode 100644 index 0000000..ea7082b --- /dev/null +++ b/dts/gs201-dpm-userdebug.dts
@@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; +/plugin/; + +#include "gs201-dpm-userdebug.dtsi" +#include "avf-dpm-userdebug.dtsi"
diff --git a/dts/gs201-dpm-userdebug.dtsi b/dts/gs201-dpm-userdebug.dtsi new file mode 100644 index 0000000..f9c1201 --- /dev/null +++ b/dts/gs201-dpm-userdebug.dtsi
@@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <dt-bindings/soc/google/debug-snapshot-def.h> + +&dpm { + version = <101>; + variant = "userdebug"; + + security { + cp_mem_not_clear = <0>; + dbg_mem_enable = <1>; + seh_enable = <0>; + pm_test_enable = <0>; + seclog_enable = <0>; + harxlog_enable = <0>; + sdm_enable = <0>; + ERXPFG_enable = <1>; + }; + + abl { + ramdump_mode = <DPM_ENABLE>; + ramdump2usb = <PRIVILEGED_ENABLE>; + }; + + feature { + /* dump-mode support */ + dump-mode { + enabled = <1>; + file-support = <0>; + }; + + event { + method = DSS_LOG_TASK, + DSS_LOG_WORK, + DSS_LOG_CPUIDLE, + DSS_LOG_SUSPEND, + DSS_LOG_IRQ, + DSS_LOG_HRTIMER, + DSS_LOG_CLK, + DSS_LOG_PMU, + DSS_LOG_FREQ, + DSS_LOG_DM, + DSS_LOG_REGULATOR, + DSS_LOG_THERMAL, + DSS_LOG_ACPM, + DSS_LOG_PRINTK; + }; + + /* debug-kinfo support */ + debug-kinfo { + enabled = <1>; + }; + }; + + policy { + exception { + pre_log = <1>; + + el1_da = <GO_DEFAULT_ID>; + el1_ia = <GO_DEFAULT_ID>; + el1_undef = <GO_DEFAULT_ID>; + el1_sp_pc = <GO_DEFAULT_ID>; + el1_inv = <GO_DEFAULT_ID>; + el1_serror = <GO_DEFAULT_ID>; + }; + }; +}; /* end of dpm */ + +&log_arrdumppanic { + status = "disabled"; +}; + +&log_preslcdump { + status = "disabled"; +}; + +&log_slcdump { + status = "disabled"; +};
diff --git a/dts/gs201-dpm.dtsi b/dts/gs201-dpm.dtsi new file mode 100644 index 0000000..8b58ae2 --- /dev/null +++ b/dts/gs201-dpm.dtsi
@@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 Debug Policy Manager device tree source + * + * Copyright 2021 Google LLC + */ + +/ { + #address-cells = <2>; + #size-cells = <1>; + dpm: dpm { + }; /* end of dpm */ +}; /* end of root */ + +/* default settings built into kernel dt */ +#include "gs201-dpm-user.dtsi"
diff --git a/dts/gs201-drm-dpu.dtsi b/dts/gs201-drm-dpu.dtsi new file mode 100644 index 0000000..387df72 --- /dev/null +++ b/dts/gs201-drm-dpu.dtsi
@@ -0,0 +1,536 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SAMSUNG GS201 SoC device tree source + * + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/gs201.h> +#include <dt-bindings/display/exynos-display.h> +#include "gs201-pinctrl.dtsi" +#include "gs201-sysmmu.dtsi" +#include "gs101-display-timing.dtsi" + +/ { + drmdpp0: drmdpp@1C0B0000 { /* L0 */ + compatible = "samsung,exynos-dpp"; + reg = <0x0 0x1C0B0000 0x1000>, /* DPU_DMA */ + <0x0 0x1C0D0000 0x1000>, /* DPP */ + <0x0 0x1C0E0000 0x1000>; /* HDR */ + reg-names = "dma", "dpp", "hdr"; + + /* DPU_DMA IRQ, DPP IRQ */ + interrupts = <GIC_SPI IRQ_DPU_DMA_L0_DPU IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DPU_DPP_L0_DPU IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma", "dpp"; + + /* Each bit indicates DPP attribute */ + /* 0:AFBC 1:BLOCK 2:FLIP 3:ROT 4:CSC 5:SCALE 6:HDR 11:HDR10P */ + /* 16:IDMA 17:ODMA 18:DPP */ + attr = <0x50047>; + port = <0>; /* AXI port number */ + + /* 1: scale X, 2: 1/2x scale down, 4: 1/4x scale down */ + scale_down = <1>; + /* 1: scale X, 2: 2x scale up, 4: 4x scale up */ + scale_up = <1>; + + dpp,id = <0>; + }; + + drmdpp1: drmdpp@1C0B1000 { /* L1 */ + compatible = "samsung,exynos-dpp"; + reg = <0x0 0x1C0B1000 0x1000>, + <0x0 0x1C0D1000 0x1000>, + <0x0 0x1C0E1000 0x1000>; + reg-names = "dma", "dpp", "hdr"; + + interrupts = <GIC_SPI IRQ_DPU_DMA_L1_DPU IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DPU_DPP_L1_DPU IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma", "dpp"; + + attr = <0x50C7F>; + port = <0>; + scale_down = <4>; + scale_up = <8>; + + dpp,id = <1>; + dpp,video; + }; + + drmdpp2: drmdpp@1C0B2000 { /* L2 */ + compatible = "samsung,exynos-dpp"; + reg = <0x0 0x1C0B2000 0x1000>, + <0x0 0x1C0D2000 0x1000>, + <0x0 0x1C0E2000 0x1000>; + reg-names = "dma", "dpp", "hdr"; + + interrupts = <GIC_SPI IRQ_DPU_DMA_L2_DPU IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DPU_DPP_L2_DPU IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma", "dpp"; + + attr = <0x50047>; + port = <1>; + scale_down = <1>; + scale_up = <1>; + + dpp,id = <2>; + }; + + drmdpp3: drmdpp@1C0B3000 { /* L3 */ + compatible = "samsung,exynos-dpp"; + reg = <0x0 0x1C0B3000 0x1000>, + <0x0 0x1C0D3000 0x1000>, + <0x0 0x1C0E3000 0x1000>; + reg-names = "dma", "dpp", "hdr"; + + interrupts = <GIC_SPI IRQ_DPU_DMA_L3_DPU IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DPU_DPP_L3_DPU IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma", "dpp"; + + attr = <0x50C7F>; + port = <1>; + scale_down = <4>; + scale_up = <8>; + + dpp,id = <3>; + dpp,video; + }; + + drmdpp4: drmdpp@1C0B4000 { /* L4 */ + compatible = "samsung,exynos-dpp"; + reg = <0x0 0x1C0B4000 0x1000>, + <0x0 0x1C0D4000 0x1000>, + <0x0 0x1C0E4000 0x1000>; + reg-names = "dma", "dpp", "hdr"; + + interrupts = <GIC_SPI IRQ_DPU_DMA_L4_DPU IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DPU_DPP_L4_DPU IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma", "dpp"; + + attr = <0x50047>; + port = <2>; + scale_down = <1>; + scale_up = <1>; + + dpp,id = <4>; + }; + + drmdpp5: drmdpp@1C0B5000 { /* L5 */ + compatible = "samsung,exynos-dpp"; + reg = <0x0 0x1C0B5000 0x1000>, + <0x0 0x1C0D5000 0x1000>, + <0x0 0x1C0E5000 0x1000>; + reg-names = "dma", "dpp", "hdr"; + + interrupts = <GIC_SPI IRQ_DPU_DMA_L5_DPU IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DPU_DPP_L5_DPU IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma", "dpp"; + + attr = <0x50C7F>; + port = <2>; + scale_down = <4>; + scale_up = <8>; + + dpp,id = <5>; + dpp,video; + }; + + drmdpp8: drmdpp@1C0B8000 { + compatible = "samsung,exynos-dpp"; + reg = <0x0 0x1C0B8000 0x1000>; + reg-names = "dma"; + + interrupts = <GIC_SPI IRQ_DPU_DMA_RCD0_DPU IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma"; + + /* 20:RCD */ + attr = <0x100000>; + port = <0>; + dpp,id = <6>; + }; + + drmdpp9: drmdpp@1C0B9000 { + compatible = "samsung,exynos-dpp"; + reg = <0x0 0x1C0B9000 0x1000>; + reg-names = "dma"; + + interrupts = <GIC_SPI IRQ_DPU_DMA_RCD1_DPU IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma"; + + /* 20:RCD */ + attr = <0x100000>; + port = <1>; + dpp,id = <7>; + }; + + drmdpp12: drmdpp@1C0BC000 { /* L12 : WB */ + compatible = "samsung,exynos-writeback"; + reg = <0x0 0x1C0BC000 0x1000>, <0x0 0x1C0DC000 0x1000>; + reg-names = "dma", "dpp"; + + interrupts = <GIC_SPI IRQ_DPU_DMA_WB_DPU IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma"; + + /* 4:CSC 10:SBWC 17:ODMA 18:DPP */ + attr = <0x60410>; + port = <2>; + scale_down = <1>; + scale_up = <1>; + + dpp,id = <8>; + }; + + disp_ss: disp_ss@1C221000 { + compatible = "samsung,exynos9-disp_ss"; + reg = <0x0 0x1C221000 0x10>; + reg-names = "sys"; + }; + + mipi_phy_dsim0_m4m4: dphy_m4s4_dsim0@1C2E0000 { + compatible = "samsung,mipi-phy-m4m4"; + isolation = <0x3eb8>; + owner = <0>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + drmdsim0: drmdsim@1C2C0000 { + compatible = "samsung,exynos-dsim"; + reg = <0x0 0x1C2C0000 0x300>, /* DSI */ + <0x0 0x1C2E0100 0x700>, /* M4M4S0 PHY */ + <0x0 0x1C2E0000 0x100>; /* M4M4S0 PHY BIAS */ + reg-names = "dsi", "dphy", "dphy-extra"; + + dsim,id = <0>; + + interrupts = <GIC_SPI IRQ_DISP_DSIM0_DISP IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dsim"; + + phys = <&mipi_phy_dsim0_m4m4 0>; + phy-names = "dsim_dphy"; + + dsim_mode = <&dsim_modes>; + dphy_diag = <&dphy_diags>; + + te_from = <0>; + /* EINT for TE */ + te-gpio = <&gpp0 3 0xf>; + + /* pinctrl */ + pinctrl-names = "hw_te_on", "hw_te_off"; + pinctrl-0 = <&disp_te_pri_on>; + pinctrl-1 = <&disp_te_pri_off>; + + #address-cells = <1>; + #size-cells = <0>; + }; + + drmdsim1: drmdsim@1C2D0000 { + status = "disabled"; + + compatible = "samsung,exynos-dsim"; + reg = <0x0 0x1C2D0000 0x300>, /* DSI */ + <0x0 0x1C2E0900 0x700>, /* M4M4S0 PHY */ + <0x0 0x1C2E0000 0x100>; /* M4M4S0 PHY BIAS */ + reg-names = "dsi", "dphy", "dphy-extra"; + + dsim,id = <1>; + + interrupts = <GIC_SPI IRQ_DISP_DSIM1_DISP IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dsim"; + + phys = <&mipi_phy_dsim0_m4m4 0>; + phy-names = "dsim_dphy"; + + dsim_mode = <&dsim_modes>; + dphy_diag = <&dphy_diags>; + + te_from = <1>; + /* EINT for TE */ + te-gpio = <&gpp0 4 0xf>; + + pinctrl-names = "hw_te_on", "hw_te_off"; + pinctrl-0 = <&disp_te_sec_on>; + pinctrl-1 = <&disp_te_sec_off>; + + #address-cells = <1>; + #size-cells = <0>; + }; + + drmdecon0: drmdecon@1C240000 { + compatible = "samsung,exynos-decon"; + reg = <0x0 0x1C240000 0x6000>, /* DECON0_MAIN */ + <0x0 0x1C250000 0x6000>, /* DECON_WIN */ + <0x0 0x1C260000 0x10000>, /* DECON_SUB */ + <0x0 0x1C270000 0x6000>, /* DECON0_WINCON */ + <0x0 0x1C2A0000 0xF000>, /* DQE0 */ + <0x0 0x1C0BE000 0x1000>; /* CGC_DMA */ + + reg-names = "main", "win", "sub", "wincon", "dqe", "cgc-dma"; + + decon,id = <0>; + cgc-dma,id = <9>; + + interrupts = <GIC_SPI IRQ_DISP_DECON0_FRAME_START_DISP + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DISP_DECON0_FRAME_DONE_DISP + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DISP_DECON0_EXTRA_DISP + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DISP_DECON0_DQE_DIMMING_START_DISP + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DISP_DECON0_DQE_DIMMING_END_DISP + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DPU_DMA_CGC0_DPU + IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "frame_start", "frame_done", "extra", + "dimming_start", "dimming_end", "cgc-dma"; + iommus = <&sysmmu_dpu0>, <&sysmmu_dpu1>, <&sysmmu_dpu2>; + samsung,iommu-group = <&iommu_group_dpu>; + samsung,tzmp; + power-domains = <&pd_dpu>; + + max_win = <6>; + + /* BTS */ + ppc = <2>; /* pixel per clock */ + ppc_rotator = <4>; /* rotator ppc : 4(9830), 8(9840) */ + ppc_scaler = <2>; /* scaler ppc : 2(9830), 4(9840) */ + delay_comp = <4>; /* line delay for afbc or sbwc : DMA */ + delay_scaler = <3>; /* line delay for scaler : DPP */ + + /* bus info */ + bus_width = <16>; /* 16-Byte : 128-bit bus */ + bus_util = <65>; /* 65% */ + rot_util = <60>; /* UTIL gets worse at rotation */ + + /* dpu dvfs */ + dfs_lv_cnt = <7>; + dfs_lv = <664000 533000 465000 400000 310000 267000 134000>; + + /* Urgent */ + rd_en = <1>; + rd_hi_thres = <0x800>; + rd_lo_thres = <0x400>; + rd_wait_cycle = <0x10>; + wr_en = <0>; + wr_hi_thres = <0x0>; + wr_lo_thres = <0x0>; + + /* DTA */ + dta_en = <1>; + dta_hi_thres = <0x3200>; + dta_lo_thres = <0x600>; + + dpps = <&drmdpp0 &drmdpp1 &drmdpp2 &drmdpp3 &drmdpp4 &drmdpp5>; + + /* + * connector type that can be connected to the DECON. please + * refer to enum exynos_drm_output_type in exynos_drm_drv.h + * + * DSI0(0x1), DSI1(0x2), VIDI(0x8) + */ + connector = <0x1 0x2 0x8>; + + hibernation; + rcd = <&drmdpp8>; + + itmon,port = "DPU", "DISP"; + itmon,dest = "DPU", "DISP"; + }; + + drmdecon1: drmdecon@1C241000 { + status = "disabled"; + compatible = "samsung,exynos-decon"; + reg = <0x0 0x1C241000 0x6000>, /* DECON1_MAIN */ + <0x0 0x1C250000 0x6000>, /* DECON_WIN */ + <0x0 0x1C260000 0x10000>, /* DECON_SUB */ + <0x0 0x1C280000 0x6000>, /* DECON1_WINCON */ + <0x0 0x1C2B0000 0xF000>, /* DQE1 */ + <0x0 0x1C0BF000 0x1000>; /* CGC_DMA */ + reg-names = "main", "win", "sub", "wincon", "dqe", "cgc-dma"; + + decon,id = <1>; + cgc-dma,id = <10>; + + interrupts = <GIC_SPI IRQ_DISP_DECON1_FRAME_START_DISP + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DISP_DECON1_FRAME_DONE_DISP + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DISP_DECON1_EXTRA_DISP + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DISP_DECON1_DQE_DIMMING_START_DISP + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DISP_DECON1_DQE_DIMMING_END_DISP + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DPU_DMA_CGC1_DPU + IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "frame_start", "frame_done", "extra", + "dimming_start", "dimming_end", "cgc-dma"; + iommus = <&sysmmu_dpu0>, <&sysmmu_dpu1>, <&sysmmu_dpu2>; + samsung,iommu-group = <&iommu_group_dpu>; + samsung,tzmp; + power-domains = <&pd_dpu>; + + max_win = <6>; + + /* BTS */ + ppc = <2>; /* pixel per clock */ + ppc_rotator = <4>; /* rotator ppc : 4(9830), 8(9840) */ + ppc_scaler = <2>; /* scaler ppc : 2(9830), 4(9840) */ + delay_comp = <4>; /* line delay for afbc or sbwc : DMA */ + delay_scaler = <3>; /* line delay for scaler : DPP */ + + /* bus info */ + bus_width = <16>; /* 16-Byte : 128-bit bus */ + bus_util = <65>; /* 65% */ + rot_util = <60>; /* UTIL gets worse at rotation */ + + /* dpu dvfs */ + dfs_lv_cnt = <7>; + dfs_lv = <664000 533000 465000 400000 310000 267000 134000>; + + /* Urgent */ + rd_en = <1>; + rd_hi_thres = <0x800>; + rd_lo_thres = <0x400>; + rd_wait_cycle = <0x11>; + wr_en = <0>; + wr_hi_thres = <0x0>; + wr_lo_thres = <0x0>; + + /* DTA */ + dta_en = <1>; + dta_hi_thres = <0x3200>; + dta_lo_thres = <0x600>; + + dpps = <&drmdpp0 &drmdpp1 &drmdpp2 &drmdpp3 &drmdpp4 &drmdpp5>; + + /* + * connector type that can be connected to the DECON. please + * refer to enum exynos_drm_output_type in exynos_drm_drv.h + * + * DSI0(0x1), DSI1(0x2), VIDI(0x8) + */ + connector = <0x1 0x2 0x8>; + + hibernation; + rcd = <&drmdpp9>; + + itmon,port = "DPU", "DISP"; + itmon,dest = "DPU", "DISP"; + }; + + drmdecon2: drmdecon@1C242000 { + compatible = "samsung,exynos-decon"; + reg = <0x0 0x1C242000 0x4000>, /* DECON2_MAIN */ + <0x0 0x1C250000 0x6000>, /* DECON_WIN */ + <0x0 0x1C260000 0x10000>, /* DECON_SUB */ + <0x0 0x1C290000 0x6000>; /* DECON2_WINCON */ + reg-names = "main", "win", "sub", "wincon"; + + decon,id = <2>; + + interrupts = <GIC_SPI IRQ_DISP_DECON2_FRAME_START_DISP + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DISP_DECON2_FRAME_DONE_DISP + IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_DISP_DECON2_EXTRA_DISP + IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "frame_start", "frame_done", "extra"; + iommus = <&sysmmu_dpu0>, <&sysmmu_dpu1>, <&sysmmu_dpu2>; + samsung,iommu-group = <&iommu_group_dpu>; + samsung,tzmp; + power-domains = <&pd_dpu>; + + max_win = <6>; + + /* BTS */ + ppc = <2>; /* pixel per clock */ + ppc_rotator = <4>; /* rotator ppc : 4(9830), 8(9840) */ + ppc_scaler = <2>; /* scaler ppc : 2(9830), 4(9840) */ + delay_comp = <4>; /* line delay for afbc or sbwc : DMA */ + delay_scaler = <3>; /* line delay for scaler : DPP */ + + /* bus info */ + bus_width = <16>; /* 16-Byte : 128-bit bus */ + bus_util = <65>; /* 65% */ + rot_util = <60>; /* UTIL gets worse at rotation */ + + /* dpu dvfs */ + dfs_lv_cnt = <7>; + dfs_lv = <664000 533000 465000 400000 310000 267000 134000>; + + dpps = <&drmdpp0 &drmdpp1 &drmdpp2 &drmdpp3 &drmdpp4 &drmdpp5>; + + /* + * connector type that can be connected to the DECON. please + * refer to enum exynos_drm_output_type in exynos_drm_drv.h + * + * DSI0(0x1), DSI1(0x2), VIDI(0x8) + */ + connector = <0x8>; + + itmon,port = "DPU", "DISP"; + itmon,dest = "DPU", "DISP"; + }; + + disp_vddi: disp-vddi { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "disp_vddi"; + regulator-boot-on; + enable-active-high; + }; + + disp_vddr_en: disp-vddr_en { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "disp_vddr_en"; + regulator-boot-on; + enable-active-high; + }; + + disp_vddr_0: disp-vddr_0 { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "disp_vddr_0"; + regulator-boot-on; + enable-active-high; + }; + + disp_vddr_1: disp-vddr_1 { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "disp_vddr_1"; + regulator-boot-on; + enable-active-high; + }; + + disp_vddd: disp-vddd { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "disp_vddd"; + regulator-boot-on; + enable-active-high; + }; + + disp_vci: disp-vci { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "disp_vci"; + regulator-boot-on; + enable-active-high; + }; + + disp_bl_en: disp-bl_en { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "disp_bl_en"; + regulator-boot-on; + enable-active-high; + }; +};
diff --git a/dts/gs201-emulator.dts b/dts/gs201-emulator.dts new file mode 100644 index 0000000..217c148 --- /dev/null +++ b/dts/gs201-emulator.dts
@@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * +*/ + +/dts-v1/; +/plugin/; + +/ { + fragment@zebu { + target-path="/"; + __overlay__ { + model = "GS201 EVT0 EMULATOR ML3_DEV06 board based on GS201"; + compatible = "samsung,GS201", "samsung,GS201 EMULATOR"; + + firmware { + android: android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system: system { + compatible = "android,system"; + dev = "/dev/block/platform/14620000.dwmmc2/by-name/system"; + type = "ext4"; + mnt_flags = "ro"; + fsmgr_flags = "wait"; + status = "okay"; + }; + vendor: vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/14620000.dwmmc2/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro"; + fsmgr_flags = "wait"; + status = "okay"; + }; + }; + }; + }; + + virtio_block@14630000 { + compatible = "virtio,mmio"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x14630000 0x10000>; + interrupts = <0 222 4>; + }; + }; + }; +}; + +/ { + fragment@serial0 { + target-path = "/"; + __overlay__ { + uart@10A00000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + }; + }; + }; +}; + +&serial_0 { + samsung,fifo-size = <256>; + clocks = <&ext_26m>, <&ext_26m>; + status = "okay"; +}; + +&mct { + clocks = <&ext_26m>, <&ext_26m>; +}; + +&memory_0 { + reg = <0x0 0x80000000 0x40000000>; +}; + +&chosen { + bootargs = "earlycon=exynos4210,mmio32,0x10A00000 console=ttySAC0,115200n8 root=/dev/ram0 rw ramdisk_size=65536 initrd=0x84000000,64M clk_ignore_unused mem=1024M maxcpus=1 firmware_class.path=/vendor/firmware androidboot.first_stage_console=1 androidboot.force_normal_boot=1"; +}; + +&pinctrl_6 { + status = "disabled"; +}; + +&pinctrl_7 { + status = "disabled"; +}; + +&amba { + status = "disabled"; +};
diff --git a/dts/gs201-gpu.dtsi b/dts/gs201-gpu.dtsi new file mode 100644 index 0000000..040dd67 --- /dev/null +++ b/dts/gs201-gpu.dtsi
@@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS201 Mali GPU device tree source + * + * Copyright 2021 Google LLC + * + */ + +/ { + mali_mgm: physical-memory-group-manager { + compatible = "arm,physical-memory-group-manager"; + + /* Memory groups */ + groups = + "gpu_g0", + "gpu_g1"; + + /* Base partition index for each group */ + group_base_pt = <0 10>; + + /* Number of partitions for each group */ + group_pt_num = <10 1>; + + /* SLC partitions */ + pt_id = + "gpu_g0_p0", + "gpu_g0_p1", + "gpu_g0_p2", + "gpu_g0_p3", + "gpu_g0_p4", + "gpu_g0_p5", + "gpu_g0_p6", + "gpu_g0_p7", + "gpu_g0_p8", + "gpu_g0_p9", + "gpu_g1_p0"; + + /* SLC partition sizes KB */ + pt_size = <256 512 768 1024 1536 2048 3072 4096 6144 8192 8192>; + }; + + mali_pcm: priority-control-manager { + compatible = "arm,priority-control-manager"; + }; + + mali_pma: protected-memory-allocator { + compatible = "arm,protected-memory-allocator"; + }; + + mali: mali@28000000 { + compatible = "arm,malit6xx"; + reg = <0x0 0x28000000 0x480000>; + interrupts = + <GIC_SPI IRQ_G3D_IRQJOB_G3D IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_G3D_IRQMMU_G3D IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_G3D_IRQGPU_G3D IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "JOB", "MMU", "GPU"; + + /* Power */ + power-domains = <&pd_g3d>, <&pd_embedded_g3d>; + power-domain-names = "top", "cores"; + g3d_genpd_name = "pd-embedded_g3d"; + gpu_pmu_status_reg_offset = <0x2004>; + gpu_pmu_status_local_pwr_mask = <0x1>; /*0x1 << 0*/ + power_policy = "adaptive"; + firmware_idle_hysteresis_time_ms = <60>; + + /* Memory */ + physical-memory-group-manager = <&mali_mgm>; + + /* Priority control */ + /*priority-control-manager = <&mali_pcm>;*/ + + /* Protected memory allocator */ + protected-memory-allocator = <&mali_pma>; + + /* Clocks */ + gpu0_cmu_cal_id = <ACPM_DVFS_G3DL2>; + gpu1_cmu_cal_id = <ACPM_DVFS_G3D>; + + /* DVFS */ + gpu_dvfs_governor = "quickstep"; + gpu_dvfs_clockdown_hysteresis = <50>; + + /* DVFS v1 operating points */ + gpu_dvfs_table_size_v1 = <11 10>; /*<row col>*/ + gpu_dvfs_table_v1 = < + /* + *gpu0 gpu1 down up hys int mif little middle big + * clk clk util util ticks min min min min max + *-------------------------------------------------------------------------- + */ + 996000 848000 85 100 1 533000 3172000 0 0 0 + 996000 762000 81 97 1 0 845000 0 0 0 + 885000 701000 76 94 1 0 845000 0 0 0 + 750000 572000 85 96 2 0 0 0 0 0 + 750000 510000 83 97 3 0 0 0 0 0 + 603000 471000 78 95 3 0 0 0 0 0 + 603000 400000 80 96 3 0 0 0 0 0 + 470000 351000 76 95 3 0 0 0 0 0 + 470000 302000 72 94 3 0 0 0 0 0 + 302000 251000 67 94 2 0 0 0 0 0 + 302000 202000 0 92 1 0 0 0 0 0 + >; + + /* DVFS v2 operating points */ + gpu_dvfs_table_size_v2 = <13 10>; /*<row col>*/ + gpu_dvfs_table_v2 = < + /* + *gpu0 gpu1 down up hys int mif little middle big + * clk clk util util ticks min min min min max + *-------------------------------------------------------------------------- + */ + 996000 848000 85 100 1 533000 3172000 0 0 0 + 996000 762000 81 97 1 0 845000 0 0 0 + 885000 701000 76 94 1 0 845000 0 0 0 + 885000 633000 80 95 2 0 0 0 0 0 + 750000 572000 85 96 2 0 0 0 0 0 + 750000 510000 83 97 3 0 0 0 0 0 + 603000 471000 78 95 3 0 0 0 0 0 + 603000 434000 79 95 3 0 0 0 0 0 + 603000 400000 80 96 3 0 0 0 0 0 + 470000 351000 76 95 3 0 0 0 0 0 + 470000 302000 72 94 3 0 0 0 0 0 + 302000 251000 67 94 2 0 0 0 0 0 + 302000 202000 0 92 1 0 0 0 0 0 + >; + + /* DVFS step up value */ + gpu_dvfs_step_up_val = <3>; + + /* DVFS Level locks */ + gpu_dvfs_max_freq = <900000>; + gpu_dvfs_min_freq = <0>; + + /* QOS */ + gpu_dvfs_qos_bts_scenario = "g3d_performance"; + gpu_dvfs_qos_bts_threshold = <400000>; + + /* Thermal */ + #cooling-cells = <2>; + gpu_power_coeff = <625>; + ect-coeff-index = <3>; + }; +};
diff --git a/dts/gs201-gsa.dtsi b/dts/gs201-gsa.dtsi new file mode 100644 index 0000000..ada087c --- /dev/null +++ b/dts/gs201-gsa.dtsi
@@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only +/ { + gsa: gsa-ns { + compatible = "google,gs101-gsa-v1"; + #address-cells = <2>; + #size-cells = <1>; + + /* NS mailbox */ + reg = <0 0x17c90000 0x1000>; + interrupts = <GIC_SPI IRQ_MAILBOX_GSA2NONTZ_GSA + IRQ_TYPE_LEVEL_HIGH>; + + s2mpu = <&s2mpu_gsa>; + }; +};
diff --git a/dts/gs201-gxp.dtsi b/dts/gs201-gxp.dtsi new file mode 100644 index 0000000..e3d3207 --- /dev/null +++ b/dts/gs201-gxp.dtsi
@@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GXP device tree source + * + * Copyright 2021 Google,LLC + */ + +#include <dt-bindings/interrupt-controller/gs201.h> + +/ { + /* GXP */ + gxp: gxp@25C00000 { + compatible = "google,gxp"; + #dma-address-cells = <1>; + #dma-size-cells = <1>; + dma-window = <0x00001000 0xFFFFF000>; + gcip-dma-window = <0x30000000 0xC0000000>; /* GCIP IOMMU attribute. */ + gcip-reserved-map = <0x80000000 0x1000>; + pasid-num-bits = <3>; + reg = <0x0 0x25C00000 0x01400000 + /* Mailboxes */ + 0x0 0x18380000 0x00001000 + 0x0 0x183A0000 0x00001000 + 0x0 0x183C0000 0x00001000 + 0x0 0x183E0000 0x00001000 + /* CMU AUR */ + 0x0 0x25A00000 0x00001000 + /* SSMTs */ + 0x0 0x25AD0000 0x00010000 + 0x0 0x25AE0000 0x00010000>; + reg-names = "aur", + "mailbox0", "mailbox1", "mailbox2", "mailbox3", + "cmu", "ssmt_idma", "ssmt_inst_data"; + interrupts = <GIC_SPI IRQ_MAILBOX_AUR02AP_ALIVE IRQ_TYPE_LEVEL_HIGH + GIC_SPI IRQ_MAILBOX_AUR12AP_ALIVE IRQ_TYPE_LEVEL_HIGH + GIC_SPI IRQ_MAILBOX_AUR22AP_ALIVE IRQ_TYPE_LEVEL_HIGH + GIC_SPI IRQ_MAILBOX_AUR32AP_ALIVE IRQ_TYPE_LEVEL_HIGH + GIC_SPI IRQ_AUR_WDOG_CPU_IRQ_AUR IRQ_TYPE_EDGE_RISING>; + tpu-device = <&edgetpu>; + gsa-device = <&gsa>; + gxp-tpu-mbx-offset = <0x0 0xC0000>; + iommus = <&sysmmu_aur_idma>, <&sysmmu_aur_inst_data>; + samsung,iommu-group = <&iommu_group_aur>; + gxp-fw-region = <&gxp_fw_reserved>; + gxp-scratchpad-region = <&gxp_scratchpad_reserved>; + gxp-memory-per-core = <0 512>; + gcip-dvfs-table-size = <7 2>; /*<row col>*/ + gcip-dvfs-table = < + /* + * when updating gcip-dvfs-table, update gcip-dvfs-table-size as well + * freq power(mW) + * ------------------- + */ + 1065000 78 + 861000 58 + 713000 40 + 560000 27 + 355000 20 + 256000 16 + 178000 13 + >; + }; + gxp_cooling: gxp-cooling { + #cooling-cells = <2>; + }; +};
diff --git a/dts/gs201-hybrid.dts b/dts/gs201-hybrid.dts new file mode 100644 index 0000000..b9132e0 --- /dev/null +++ b/dts/gs201-hybrid.dts
@@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * +*/ + +/dts-v1/; +/plugin/; + +/ { + fragment@zebu { + target-path="/"; + __overlay__ { + model = "GS201 EVT0 HYBRID EMULATOR ML3_DEV06 board based on GS201"; + compatible = "samsung,GS201", "samsung,GS201 EMULATOR"; + + firmware { + android: android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system: system { + compatible = "android,system"; + dev = "/dev/block/platform/14620000.dwmmc2/by-name/system"; + type = "ext4"; + mnt_flags = "ro"; + fsmgr_flags = "wait"; + status = "okay"; + }; + vendor: vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/14620000.dwmmc2/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro"; + fsmgr_flags = "wait"; + status = "okay"; + }; + }; + }; + }; + + virtio_block@14630000 { + compatible = "virtio,mmio"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x14630000 0x10000>; + interrupts = <0 222 4>; + }; + }; + }; +}; + +/ { + fragment@serial0 { + target-path = "/"; + __overlay__ { + uart@10A00000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + }; + }; + }; +}; + +&serial_0 { + samsung,fifo-size = <256>; + clocks = <&ext_26m>, <&ext_26m>; + status = "okay"; +}; + +&mct { + clocks = <&ext_1m>, <&ext_1m>; +}; + +&memory_0 { + reg = <0x0 0x80000000 0x40000000>; +}; + +&chosen { + bootargs = "earlycon=exynos4210,mmio32,0x10A00000 console=ttySAC0,115200n8 root=/dev/ram0 rw ramdisk_size=65536 initrd=0x84000000,64M clk_ignore_unused mem=1024M maxcpus=1 firmware_class.path=/vendor/firmware androidboot.first_stage_console=1 androidboot.force_normal_boot=1 clocksource=arch_sys_counter"; +}; + +&pinctrl_6 { + status = "disabled"; +}; + +&pinctrl_7 { + status = "disabled"; +}; + +&amba { + status = "disabled"; +}; + +&dwmmc_2 { + status = "okay"; +}; + +/* [TEMP] Temporarily disable SysMMU power-domains as this feature has not yet + * been implemented on the hybrid emulator. + * + * Also disable the TPU SysMMU instance because it is not available on the + * hybrid emulator. + */ + +&sysmmu_bo { + power-domains; +}; + +&sysmmu_csis0 { + power-domains; +}; + +&sysmmu_csis1 { + power-domains; +}; + +&sysmmu_dns { + power-domains; +}; + +&sysmmu_dpu0 { + power-domains; +}; + +&sysmmu_dpu1 { + power-domains; +}; + +&sysmmu_dpu2 { + power-domains; +}; + +&sysmmu_g2d0 { + power-domains; +}; + +&sysmmu_g2d1 { + power-domains; +}; + +&sysmmu_g2d2 { + power-domains; +}; + +&sysmmu_g3aa { + power-domains; +}; + +&sysmmu_gdc0 { + power-domains; +}; + +&sysmmu_gdc1 { + power-domains; +}; + +&sysmmu_gdc2 { + power-domains; +}; + +&sysmmu_ipp { + power-domains; +}; + +&sysmmu_mcsc0 { + power-domains; +}; + +&sysmmu_mcsc1 { + power-domains; +}; + +&sysmmu_mcsc2 { + power-domains; +}; + +&sysmmu_mfc0 { + power-domains; +}; + +&sysmmu_mfc1 { + power-domains; +}; + +&sysmmu_tnr0 { + power-domains; +}; + +&sysmmu_tnr1 { + power-domains; +}; + +&sysmmu_tnr2 { + power-domains; +}; + +&sysmmu_tnr3 { + power-domains; +}; + +&sysmmu_tnr4 { + power-domains; +}; + +&sysmmu_tpu { + status = "disabled"; + power-domains; +}; + +&sysmmu_aur_idma { + power-domains; +}; + +&sysmmu_aur_inst_data { + power-domains; +};
diff --git a/dts/gs201-isp-event-info.dtsi b/dts/gs201-isp-event-info.dtsi new file mode 100644 index 0000000..ec86237 --- /dev/null +++ b/dts/gs201-isp-event-info.dtsi
@@ -0,0 +1,4467 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 ISP device tree for interrupt events + * + * Copyright 2021 Google LLC. + */ + +#include <dt-bindings/lwis/platform/gs201/csi.h> +#include <dt-bindings/lwis/platform/gs201/g3aa.h> +#include <dt-bindings/lwis/platform/gs201/gdc.h> +#include <dt-bindings/lwis/platform/gs201/gtnr_align.h> +#include <dt-bindings/lwis/platform/gs201/gtnr_merge.h> +#include <dt-bindings/lwis/platform/gs201/ipp.h> +#include <dt-bindings/lwis/platform/gs201/itp.h> +#include <dt-bindings/lwis/platform/gs201/mcsc.h> +#include <dt-bindings/lwis/platform/gs201/pdp.h> +#include <dt-bindings/lwis/platform/gs201/scsc.h> + +/ { + /* + * CSI Interrupt Event Definitions + */ + + csi_ctx0_csis_int0: csi-event-info@0 { + irq-reg-space = "csis-link0"; + irq-src-reg = <0x0 0x14>; + irq-reset-reg = <0x0 0x14>; + irq-mask-reg = <0x0 0x10>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_ID>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_CRC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_ECC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_WRONG_CONFIG>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_OVER>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_CRC_PH>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_RX_INVALID_CODE_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_RX_INVALID_CODE_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_RX_INVALID_CODE_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_RX_INVALID_CODE_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_SOT_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_SOT_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_SOT_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_SOT_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_SOT_SYNC_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_SOT_SYNC_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_SOT_SYNC_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_SOT_SYNC_HS_LANE3>; + int-reg-bits = + <CSI_CSIS_INT0_CTX0_ERR_ID>, + <CSI_CSIS_INT0_CTX0_ERR_CRC>, + <CSI_CSIS_INT0_CTX0_ERR_ECC>, + <CSI_CSIS_INT0_CTX0_ERR_WRONG_CONFIG>, + <CSI_CSIS_INT0_CTX0_ERR_OVER>, + <CSI_CSIS_INT0_CTX0_ERR_CRC_PH>, + <CSI_CSIS_INT0_CTX0_MAL_CRC>, + <CSI_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE0>, + <CSI_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE1>, + <CSI_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE2>, + <CSI_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE3>, + <CSI_CSIS_INT0_CTX0_ERR_SOT_HS_LANE0>, + <CSI_CSIS_INT0_CTX0_ERR_SOT_HS_LANE1>, + <CSI_CSIS_INT0_CTX0_ERR_SOT_HS_LANE2>, + <CSI_CSIS_INT0_CTX0_ERR_SOT_HS_LANE3>, + <CSI_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE0>, + <CSI_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE1>, + <CSI_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE2>, + <CSI_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE3>; + }; + + csi_ctx1_csis_int0: csi-event-info@1 { + irq-reg-space = "csis-link1"; + irq-src-reg = <0x0 0x14>; + irq-reset-reg = <0x0 0x14>; + irq-mask-reg = <0x0 0x10>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_ID>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_CRC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_ECC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_WRONG_CONFIG>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_OVER>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_CRC_PH>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_RX_INVALID_CODE_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_RX_INVALID_CODE_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_RX_INVALID_CODE_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_RX_INVALID_CODE_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_SOT_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_SOT_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_SOT_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_SOT_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_SOT_SYNC_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_SOT_SYNC_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_SOT_SYNC_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_SOT_SYNC_HS_LANE3>; + int-reg-bits = + <CSI_CSIS_INT0_CTX1_ERR_ID>, + <CSI_CSIS_INT0_CTX1_ERR_CRC>, + <CSI_CSIS_INT0_CTX1_ERR_ECC>, + <CSI_CSIS_INT0_CTX1_ERR_WRONG_CONFIG>, + <CSI_CSIS_INT0_CTX1_ERR_OVER>, + <CSI_CSIS_INT0_CTX1_ERR_CRC_PH>, + <CSI_CSIS_INT0_CTX1_MAL_CRC>, + <CSI_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE0>, + <CSI_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE1>, + <CSI_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE2>, + <CSI_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE3>, + <CSI_CSIS_INT0_CTX1_ERR_SOT_HS_LANE0>, + <CSI_CSIS_INT0_CTX1_ERR_SOT_HS_LANE1>, + <CSI_CSIS_INT0_CTX1_ERR_SOT_HS_LANE2>, + <CSI_CSIS_INT0_CTX1_ERR_SOT_HS_LANE3>, + <CSI_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE0>, + <CSI_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE1>, + <CSI_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE2>, + <CSI_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE3>; + }; + + csi_ctx2_csis_int0: csi-event-info@2 { + irq-reg-space = "csis-link2"; + irq-src-reg = <0x0 0x14>; + irq-reset-reg = <0x0 0x14>; + irq-mask-reg = <0x0 0x10>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_ID>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_CRC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_ECC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_WRONG_CONFIG>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_OVER>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_CRC_PH>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_RX_INVALID_CODE_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_RX_INVALID_CODE_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_RX_INVALID_CODE_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_RX_INVALID_CODE_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_SOT_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_SOT_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_SOT_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_SOT_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_SOT_SYNC_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_SOT_SYNC_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_SOT_SYNC_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_SOT_SYNC_HS_LANE3>; + int-reg-bits = + <CSI_CSIS_INT0_CTX2_ERR_ID>, + <CSI_CSIS_INT0_CTX2_ERR_CRC>, + <CSI_CSIS_INT0_CTX2_ERR_ECC>, + <CSI_CSIS_INT0_CTX2_ERR_WRONG_CONFIG>, + <CSI_CSIS_INT0_CTX2_ERR_OVER>, + <CSI_CSIS_INT0_CTX2_ERR_CRC_PH>, + <CSI_CSIS_INT0_CTX2_MAL_CRC>, + <CSI_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE0>, + <CSI_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE1>, + <CSI_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE2>, + <CSI_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE3>, + <CSI_CSIS_INT0_CTX2_ERR_SOT_HS_LANE0>, + <CSI_CSIS_INT0_CTX2_ERR_SOT_HS_LANE1>, + <CSI_CSIS_INT0_CTX2_ERR_SOT_HS_LANE2>, + <CSI_CSIS_INT0_CTX2_ERR_SOT_HS_LANE3>, + <CSI_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE0>, + <CSI_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE1>, + <CSI_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE2>, + <CSI_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE3>; + }; + + csi_ctx3_csis_int0: csi-event-info@3 { + irq-reg-space = "csis-link3"; + irq-src-reg = <0x0 0x14>; + irq-reset-reg = <0x0 0x14>; + irq-mask-reg = <0x0 0x10>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_ID>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_CRC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_ECC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_WRONG_CONFIG>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_OVER>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_CRC_PH>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_RX_INVALID_CODE_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_RX_INVALID_CODE_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_RX_INVALID_CODE_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_RX_INVALID_CODE_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_SOT_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_SOT_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_SOT_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_SOT_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_SOT_SYNC_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_SOT_SYNC_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_SOT_SYNC_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_SOT_SYNC_HS_LANE3>; + int-reg-bits = + <CSI_CSIS_INT0_CTX3_ERR_ID>, + <CSI_CSIS_INT0_CTX3_ERR_CRC>, + <CSI_CSIS_INT0_CTX3_ERR_ECC>, + <CSI_CSIS_INT0_CTX3_ERR_WRONG_CONFIG>, + <CSI_CSIS_INT0_CTX3_ERR_OVER>, + <CSI_CSIS_INT0_CTX3_ERR_CRC_PH>, + <CSI_CSIS_INT0_CTX3_MAL_CRC>, + <CSI_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE0>, + <CSI_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE1>, + <CSI_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE2>, + <CSI_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE3>, + <CSI_CSIS_INT0_CTX3_ERR_SOT_HS_LANE0>, + <CSI_CSIS_INT0_CTX3_ERR_SOT_HS_LANE1>, + <CSI_CSIS_INT0_CTX3_ERR_SOT_HS_LANE2>, + <CSI_CSIS_INT0_CTX3_ERR_SOT_HS_LANE3>, + <CSI_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE0>, + <CSI_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE1>, + <CSI_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE2>, + <CSI_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE3>; + }; + + csi_ctx4_csis_int0: csi-event-info@4 { + irq-reg-space = "csis-link4"; + irq-src-reg = <0x0 0x14>; + irq-reset-reg = <0x0 0x14>; + irq-mask-reg = <0x0 0x10>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_ID>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_CRC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_ECC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_WRONG_CONFIG>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_OVER>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_CRC_PH>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_RX_INVALID_CODE_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_RX_INVALID_CODE_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_RX_INVALID_CODE_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_RX_INVALID_CODE_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_SOT_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_SOT_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_SOT_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_SOT_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_SOT_SYNC_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_SOT_SYNC_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_SOT_SYNC_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_SOT_SYNC_HS_LANE3>; + int-reg-bits = + <CSI_CSIS_INT0_CTX4_ERR_ID>, + <CSI_CSIS_INT0_CTX4_ERR_CRC>, + <CSI_CSIS_INT0_CTX4_ERR_ECC>, + <CSI_CSIS_INT0_CTX4_ERR_WRONG_CONFIG>, + <CSI_CSIS_INT0_CTX4_ERR_OVER>, + <CSI_CSIS_INT0_CTX4_ERR_CRC_PH>, + <CSI_CSIS_INT0_CTX4_MAL_CRC>, + <CSI_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE0>, + <CSI_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE1>, + <CSI_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE2>, + <CSI_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE3>, + <CSI_CSIS_INT0_CTX4_ERR_SOT_HS_LANE0>, + <CSI_CSIS_INT0_CTX4_ERR_SOT_HS_LANE1>, + <CSI_CSIS_INT0_CTX4_ERR_SOT_HS_LANE2>, + <CSI_CSIS_INT0_CTX4_ERR_SOT_HS_LANE3>, + <CSI_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE0>, + <CSI_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE1>, + <CSI_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE2>, + <CSI_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE3>; + }; + + csi_ctx5_csis_int0: csi-event-info@5 { + irq-reg-space = "csis-link5"; + irq-src-reg = <0x0 0x14>; + irq-reset-reg = <0x0 0x14>; + irq-mask-reg = <0x0 0x10>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_ID>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_CRC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_ECC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_WRONG_CONFIG>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_OVER>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_CRC_PH>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_RX_INVALID_CODE_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_RX_INVALID_CODE_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_RX_INVALID_CODE_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_RX_INVALID_CODE_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_SOT_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_SOT_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_SOT_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_SOT_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_SOT_SYNC_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_SOT_SYNC_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_SOT_SYNC_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_SOT_SYNC_HS_LANE3>; + int-reg-bits = + <CSI_CSIS_INT0_CTX5_ERR_ID>, + <CSI_CSIS_INT0_CTX5_ERR_CRC>, + <CSI_CSIS_INT0_CTX5_ERR_ECC>, + <CSI_CSIS_INT0_CTX5_ERR_WRONG_CONFIG>, + <CSI_CSIS_INT0_CTX5_ERR_OVER>, + <CSI_CSIS_INT0_CTX5_ERR_CRC_PH>, + <CSI_CSIS_INT0_CTX5_MAL_CRC>, + <CSI_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE0>, + <CSI_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE1>, + <CSI_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE2>, + <CSI_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE3>, + <CSI_CSIS_INT0_CTX5_ERR_SOT_HS_LANE0>, + <CSI_CSIS_INT0_CTX5_ERR_SOT_HS_LANE1>, + <CSI_CSIS_INT0_CTX5_ERR_SOT_HS_LANE2>, + <CSI_CSIS_INT0_CTX5_ERR_SOT_HS_LANE3>, + <CSI_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE0>, + <CSI_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE1>, + <CSI_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE2>, + <CSI_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE3>; + }; + + csi_ctx6_csis_int0: csi-event-info@6 { + irq-reg-space = "csis-link6"; + irq-src-reg = <0x0 0x14>; + irq-reset-reg = <0x0 0x14>; + irq-mask-reg = <0x0 0x10>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_ID>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_CRC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_ECC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_WRONG_CONFIG>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_OVER>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_CRC_PH>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_RX_INVALID_CODE_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_RX_INVALID_CODE_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_RX_INVALID_CODE_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_RX_INVALID_CODE_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_SOT_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_SOT_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_SOT_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_SOT_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_SOT_SYNC_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_SOT_SYNC_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_SOT_SYNC_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_SOT_SYNC_HS_LANE3>; + int-reg-bits = + <CSI_CSIS_INT0_CTX6_ERR_ID>, + <CSI_CSIS_INT0_CTX6_ERR_CRC>, + <CSI_CSIS_INT0_CTX6_ERR_ECC>, + <CSI_CSIS_INT0_CTX6_ERR_WRONG_CONFIG>, + <CSI_CSIS_INT0_CTX6_ERR_OVER>, + <CSI_CSIS_INT0_CTX6_ERR_CRC_PH>, + <CSI_CSIS_INT0_CTX6_MAL_CRC>, + <CSI_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE0>, + <CSI_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE1>, + <CSI_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE2>, + <CSI_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE3>, + <CSI_CSIS_INT0_CTX6_ERR_SOT_HS_LANE0>, + <CSI_CSIS_INT0_CTX6_ERR_SOT_HS_LANE1>, + <CSI_CSIS_INT0_CTX6_ERR_SOT_HS_LANE2>, + <CSI_CSIS_INT0_CTX6_ERR_SOT_HS_LANE3>, + <CSI_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE0>, + <CSI_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE1>, + <CSI_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE2>, + <CSI_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE3>; + }; + + csi_ctx7_csis_int0: csi-event-info@7 { + irq-reg-space = "csis-link7"; + irq-src-reg = <0x0 0x14>; + irq-reset-reg = <0x0 0x14>; + irq-mask-reg = <0x0 0x10>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_ID>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_CRC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_ECC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_WRONG_CONFIG>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_OVER>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_CRC_PH>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_RX_INVALID_CODE_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_RX_INVALID_CODE_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_RX_INVALID_CODE_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_RX_INVALID_CODE_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_SOT_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_SOT_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_SOT_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_SOT_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_SOT_SYNC_HS_LANE0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_SOT_SYNC_HS_LANE1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_SOT_SYNC_HS_LANE2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_SOT_SYNC_HS_LANE3>; + int-reg-bits = + <CSI_CSIS_INT0_CTX7_ERR_ID>, + <CSI_CSIS_INT0_CTX7_ERR_CRC>, + <CSI_CSIS_INT0_CTX7_ERR_ECC>, + <CSI_CSIS_INT0_CTX7_ERR_WRONG_CONFIG>, + <CSI_CSIS_INT0_CTX7_ERR_OVER>, + <CSI_CSIS_INT0_CTX7_ERR_CRC_PH>, + <CSI_CSIS_INT0_CTX7_MAL_CRC>, + <CSI_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE0>, + <CSI_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE1>, + <CSI_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE2>, + <CSI_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE3>, + <CSI_CSIS_INT0_CTX7_ERR_SOT_HS_LANE0>, + <CSI_CSIS_INT0_CTX7_ERR_SOT_HS_LANE1>, + <CSI_CSIS_INT0_CTX7_ERR_SOT_HS_LANE2>, + <CSI_CSIS_INT0_CTX7_ERR_SOT_HS_LANE3>, + <CSI_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE0>, + <CSI_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE1>, + <CSI_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE2>, + <CSI_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE3>; + }; + + csi_ctx0_csis_int1: csi-event-info@8 { + irq-reg-space = "csis-link0"; + irq-src-reg = <0x0 0x1c>; + irq-reset-reg = <0x0 0x1c>; + irq-mask-reg = <0x0 0x18>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_LINE_END>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_LOST_FE>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_LOST_FS>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_HRESOL_MISMATCH>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_VRESOL_MISMATCH>; + int-reg-bits = + <CSI_CSIS_INT1_CTX0_LINE_END>, + <CSI_CSIS_INT1_CTX0_FRAME_END>, + <CSI_CSIS_INT1_CTX0_FRAME_START>, + <CSI_CSIS_INT1_CTX0_ERR_LOST_FE>, + <CSI_CSIS_INT1_CTX0_ERR_LOST_FS>, + <CSI_CSIS_INT1_CTX0_HRESOL_MISMATCH>, + <CSI_CSIS_INT1_CTX0_VRESOL_MISMATCH>; + }; + + csi_ctx1_csis_int1: csi-event-info@9 { + irq-reg-space = "csis-link1"; + irq-src-reg = <0x0 0x1c>; + irq-reset-reg = <0x0 0x1c>; + irq-mask-reg = <0x0 0x18>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_LINE_END>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_LOST_FE>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_LOST_FS>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_HRESOL_MISMATCH>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_VRESOL_MISMATCH>; + int-reg-bits = + <CSI_CSIS_INT1_CTX1_LINE_END>, + <CSI_CSIS_INT1_CTX1_FRAME_END>, + <CSI_CSIS_INT1_CTX1_FRAME_START>, + <CSI_CSIS_INT1_CTX1_ERR_LOST_FE>, + <CSI_CSIS_INT1_CTX1_ERR_LOST_FS>, + <CSI_CSIS_INT1_CTX1_HRESOL_MISMATCH>, + <CSI_CSIS_INT1_CTX1_VRESOL_MISMATCH>; + }; + + csi_ctx2_csis_int1: csi-event-info@10 { + irq-reg-space = "csis-link2"; + irq-src-reg = <0x0 0x1c>; + irq-reset-reg = <0x0 0x1c>; + irq-mask-reg = <0x0 0x18>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_LINE_END>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_LOST_FE>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_LOST_FS>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_HRESOL_MISMATCH>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_VRESOL_MISMATCH>; + int-reg-bits = + <CSI_CSIS_INT1_CTX2_LINE_END>, + <CSI_CSIS_INT1_CTX2_FRAME_END>, + <CSI_CSIS_INT1_CTX2_FRAME_START>, + <CSI_CSIS_INT1_CTX2_ERR_LOST_FE>, + <CSI_CSIS_INT1_CTX2_ERR_LOST_FS>, + <CSI_CSIS_INT1_CTX2_HRESOL_MISMATCH>, + <CSI_CSIS_INT1_CTX2_VRESOL_MISMATCH>; + }; + + csi_ctx3_csis_int1: csi-event-info@11 { + irq-reg-space = "csis-link3"; + irq-src-reg = <0x0 0x1c>; + irq-reset-reg = <0x0 0x1c>; + irq-mask-reg = <0x0 0x18>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_LINE_END>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_LOST_FE>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_LOST_FS>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_HRESOL_MISMATCH>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_VRESOL_MISMATCH>; + int-reg-bits = + <CSI_CSIS_INT1_CTX3_LINE_END>, + <CSI_CSIS_INT1_CTX3_FRAME_END>, + <CSI_CSIS_INT1_CTX3_FRAME_START>, + <CSI_CSIS_INT1_CTX3_ERR_LOST_FE>, + <CSI_CSIS_INT1_CTX3_ERR_LOST_FS>, + <CSI_CSIS_INT1_CTX3_HRESOL_MISMATCH>, + <CSI_CSIS_INT1_CTX3_VRESOL_MISMATCH>; + }; + + csi_ctx4_csis_int1: csi-event-info@12 { + irq-reg-space = "csis-link4"; + irq-src-reg = <0x0 0x1c>; + irq-reset-reg = <0x0 0x1c>; + irq-mask-reg = <0x0 0x18>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_LINE_END>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_LOST_FE>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_LOST_FS>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_HRESOL_MISMATCH>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_VRESOL_MISMATCH>; + int-reg-bits = + <CSI_CSIS_INT1_CTX4_LINE_END>, + <CSI_CSIS_INT1_CTX4_FRAME_END>, + <CSI_CSIS_INT1_CTX4_FRAME_START>, + <CSI_CSIS_INT1_CTX4_ERR_LOST_FE>, + <CSI_CSIS_INT1_CTX4_ERR_LOST_FS>, + <CSI_CSIS_INT1_CTX4_HRESOL_MISMATCH>, + <CSI_CSIS_INT1_CTX4_VRESOL_MISMATCH>; + }; + + csi_ctx5_csis_int1: csi-event-info@13 { + irq-reg-space = "csis-link5"; + irq-src-reg = <0x0 0x1c>; + irq-reset-reg = <0x0 0x1c>; + irq-mask-reg = <0x0 0x18>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_LINE_END>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_LOST_FE>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_LOST_FS>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_HRESOL_MISMATCH>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_VRESOL_MISMATCH>; + int-reg-bits = + <CSI_CSIS_INT1_CTX5_LINE_END>, + <CSI_CSIS_INT1_CTX5_FRAME_END>, + <CSI_CSIS_INT1_CTX5_FRAME_START>, + <CSI_CSIS_INT1_CTX5_ERR_LOST_FE>, + <CSI_CSIS_INT1_CTX5_ERR_LOST_FS>, + <CSI_CSIS_INT1_CTX5_HRESOL_MISMATCH>, + <CSI_CSIS_INT1_CTX5_VRESOL_MISMATCH>; + }; + + csi_ctx6_csis_int1: csi-event-info@14 { + irq-reg-space = "csis-link6"; + irq-src-reg = <0x0 0x1c>; + irq-reset-reg = <0x0 0x1c>; + irq-mask-reg = <0x0 0x18>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_LINE_END>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_LOST_FE>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_LOST_FS>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_HRESOL_MISMATCH>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_VRESOL_MISMATCH>; + int-reg-bits = + <CSI_CSIS_INT1_CTX6_LINE_END>, + <CSI_CSIS_INT1_CTX6_FRAME_END>, + <CSI_CSIS_INT1_CTX6_FRAME_START>, + <CSI_CSIS_INT1_CTX6_ERR_LOST_FE>, + <CSI_CSIS_INT1_CTX6_ERR_LOST_FS>, + <CSI_CSIS_INT1_CTX6_HRESOL_MISMATCH>, + <CSI_CSIS_INT1_CTX6_VRESOL_MISMATCH>; + }; + + csi_ctx7_csis_int1: csi-event-info@15 { + irq-reg-space = "csis-link7"; + irq-src-reg = <0x0 0x1c>; + irq-reset-reg = <0x0 0x1c>; + irq-mask-reg = <0x0 0x18>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_LINE_END>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_LOST_FE>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_LOST_FS>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_HRESOL_MISMATCH>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_VRESOL_MISMATCH>; + int-reg-bits = + <CSI_CSIS_INT1_CTX7_LINE_END>, + <CSI_CSIS_INT1_CTX7_FRAME_END>, + <CSI_CSIS_INT1_CTX7_FRAME_START>, + <CSI_CSIS_INT1_CTX7_ERR_LOST_FE>, + <CSI_CSIS_INT1_CTX7_ERR_LOST_FS>, + <CSI_CSIS_INT1_CTX7_HRESOL_MISMATCH>, + <CSI_CSIS_INT1_CTX7_VRESOL_MISMATCH>; + }; + + csi_ctx0_fs_int: csi-event-info@16 { + irq-reg-space = "csis-link0"; + irq-src-reg = <0x0 0x24>; + irq-reset-reg = <0x0 0x24>; + irq-mask-reg = <0x0 0x20>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH4>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH5>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH6>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH7>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH8>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH9>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH10>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH11>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH12>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH13>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH14>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH15>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH16>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH17>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH18>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH19>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH20>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH21>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH22>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH23>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH24>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH25>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH26>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH27>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH28>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH29>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH30>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH31>; + int-reg-bits = + <CSI_FS_INT_CTX0_FRAME_START_CH0>, + <CSI_FS_INT_CTX0_FRAME_START_CH1>, + <CSI_FS_INT_CTX0_FRAME_START_CH2>, + <CSI_FS_INT_CTX0_FRAME_START_CH3>, + <CSI_FS_INT_CTX0_FRAME_START_CH4>, + <CSI_FS_INT_CTX0_FRAME_START_CH5>, + <CSI_FS_INT_CTX0_FRAME_START_CH6>, + <CSI_FS_INT_CTX0_FRAME_START_CH7>, + <CSI_FS_INT_CTX0_FRAME_START_CH8>, + <CSI_FS_INT_CTX0_FRAME_START_CH9>, + <CSI_FS_INT_CTX0_FRAME_START_CH10>, + <CSI_FS_INT_CTX0_FRAME_START_CH11>, + <CSI_FS_INT_CTX0_FRAME_START_CH12>, + <CSI_FS_INT_CTX0_FRAME_START_CH13>, + <CSI_FS_INT_CTX0_FRAME_START_CH14>, + <CSI_FS_INT_CTX0_FRAME_START_CH15>, + <CSI_FS_INT_CTX0_FRAME_START_CH16>, + <CSI_FS_INT_CTX0_FRAME_START_CH17>, + <CSI_FS_INT_CTX0_FRAME_START_CH18>, + <CSI_FS_INT_CTX0_FRAME_START_CH19>, + <CSI_FS_INT_CTX0_FRAME_START_CH20>, + <CSI_FS_INT_CTX0_FRAME_START_CH21>, + <CSI_FS_INT_CTX0_FRAME_START_CH22>, + <CSI_FS_INT_CTX0_FRAME_START_CH23>, + <CSI_FS_INT_CTX0_FRAME_START_CH24>, + <CSI_FS_INT_CTX0_FRAME_START_CH25>, + <CSI_FS_INT_CTX0_FRAME_START_CH26>, + <CSI_FS_INT_CTX0_FRAME_START_CH27>, + <CSI_FS_INT_CTX0_FRAME_START_CH28>, + <CSI_FS_INT_CTX0_FRAME_START_CH29>, + <CSI_FS_INT_CTX0_FRAME_START_CH30>, + <CSI_FS_INT_CTX0_FRAME_START_CH31>; + }; + + csi_ctx1_fs_int: csi-event-info@17 { + irq-reg-space = "csis-link1"; + irq-src-reg = <0x0 0x24>; + irq-reset-reg = <0x0 0x24>; + irq-mask-reg = <0x0 0x20>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH4>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH5>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH6>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH7>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH8>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH9>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH10>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH11>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH12>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH13>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH14>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH15>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH16>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH17>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH18>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH19>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH20>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH21>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH22>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH23>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH24>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH25>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH26>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH27>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH28>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH29>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH30>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH31>; + int-reg-bits = + <CSI_FS_INT_CTX1_FRAME_START_CH0>, + <CSI_FS_INT_CTX1_FRAME_START_CH1>, + <CSI_FS_INT_CTX1_FRAME_START_CH2>, + <CSI_FS_INT_CTX1_FRAME_START_CH3>, + <CSI_FS_INT_CTX1_FRAME_START_CH4>, + <CSI_FS_INT_CTX1_FRAME_START_CH5>, + <CSI_FS_INT_CTX1_FRAME_START_CH6>, + <CSI_FS_INT_CTX1_FRAME_START_CH7>, + <CSI_FS_INT_CTX1_FRAME_START_CH8>, + <CSI_FS_INT_CTX1_FRAME_START_CH9>, + <CSI_FS_INT_CTX1_FRAME_START_CH10>, + <CSI_FS_INT_CTX1_FRAME_START_CH11>, + <CSI_FS_INT_CTX1_FRAME_START_CH12>, + <CSI_FS_INT_CTX1_FRAME_START_CH13>, + <CSI_FS_INT_CTX1_FRAME_START_CH14>, + <CSI_FS_INT_CTX1_FRAME_START_CH15>, + <CSI_FS_INT_CTX1_FRAME_START_CH16>, + <CSI_FS_INT_CTX1_FRAME_START_CH17>, + <CSI_FS_INT_CTX1_FRAME_START_CH18>, + <CSI_FS_INT_CTX1_FRAME_START_CH19>, + <CSI_FS_INT_CTX1_FRAME_START_CH20>, + <CSI_FS_INT_CTX1_FRAME_START_CH21>, + <CSI_FS_INT_CTX1_FRAME_START_CH22>, + <CSI_FS_INT_CTX1_FRAME_START_CH23>, + <CSI_FS_INT_CTX1_FRAME_START_CH24>, + <CSI_FS_INT_CTX1_FRAME_START_CH25>, + <CSI_FS_INT_CTX1_FRAME_START_CH26>, + <CSI_FS_INT_CTX1_FRAME_START_CH27>, + <CSI_FS_INT_CTX1_FRAME_START_CH28>, + <CSI_FS_INT_CTX1_FRAME_START_CH29>, + <CSI_FS_INT_CTX1_FRAME_START_CH30>, + <CSI_FS_INT_CTX1_FRAME_START_CH31>; + }; + + csi_ctx2_fs_int: csi-event-info@18 { + irq-reg-space = "csis-link2"; + irq-src-reg = <0x0 0x24>; + irq-reset-reg = <0x0 0x24>; + irq-mask-reg = <0x0 0x20>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH4>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH5>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH6>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH7>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH8>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH9>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH10>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH11>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH12>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH13>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH14>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH15>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH16>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH17>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH18>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH19>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH20>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH21>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH22>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH23>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH24>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH25>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH26>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH27>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH28>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH29>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH30>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH31>; + int-reg-bits = + <CSI_FS_INT_CTX2_FRAME_START_CH0>, + <CSI_FS_INT_CTX2_FRAME_START_CH1>, + <CSI_FS_INT_CTX2_FRAME_START_CH2>, + <CSI_FS_INT_CTX2_FRAME_START_CH3>, + <CSI_FS_INT_CTX2_FRAME_START_CH4>, + <CSI_FS_INT_CTX2_FRAME_START_CH5>, + <CSI_FS_INT_CTX2_FRAME_START_CH6>, + <CSI_FS_INT_CTX2_FRAME_START_CH7>, + <CSI_FS_INT_CTX2_FRAME_START_CH8>, + <CSI_FS_INT_CTX2_FRAME_START_CH9>, + <CSI_FS_INT_CTX2_FRAME_START_CH10>, + <CSI_FS_INT_CTX2_FRAME_START_CH11>, + <CSI_FS_INT_CTX2_FRAME_START_CH12>, + <CSI_FS_INT_CTX2_FRAME_START_CH13>, + <CSI_FS_INT_CTX2_FRAME_START_CH14>, + <CSI_FS_INT_CTX2_FRAME_START_CH15>, + <CSI_FS_INT_CTX2_FRAME_START_CH16>, + <CSI_FS_INT_CTX2_FRAME_START_CH17>, + <CSI_FS_INT_CTX2_FRAME_START_CH18>, + <CSI_FS_INT_CTX2_FRAME_START_CH19>, + <CSI_FS_INT_CTX2_FRAME_START_CH20>, + <CSI_FS_INT_CTX2_FRAME_START_CH21>, + <CSI_FS_INT_CTX2_FRAME_START_CH22>, + <CSI_FS_INT_CTX2_FRAME_START_CH23>, + <CSI_FS_INT_CTX2_FRAME_START_CH24>, + <CSI_FS_INT_CTX2_FRAME_START_CH25>, + <CSI_FS_INT_CTX2_FRAME_START_CH26>, + <CSI_FS_INT_CTX2_FRAME_START_CH27>, + <CSI_FS_INT_CTX2_FRAME_START_CH28>, + <CSI_FS_INT_CTX2_FRAME_START_CH29>, + <CSI_FS_INT_CTX2_FRAME_START_CH30>, + <CSI_FS_INT_CTX2_FRAME_START_CH31>; + }; + + csi_ctx3_fs_int: csi-event-info@19 { + irq-reg-space = "csis-link3"; + irq-src-reg = <0x0 0x24>; + irq-reset-reg = <0x0 0x24>; + irq-mask-reg = <0x0 0x20>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH4>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH5>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH6>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH7>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH8>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH9>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH10>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH11>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH12>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH13>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH14>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH15>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH16>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH17>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH18>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH19>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH20>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH21>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH22>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH23>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH24>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH25>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH26>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH27>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH28>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH29>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH30>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH31>; + int-reg-bits = + <CSI_FS_INT_CTX3_FRAME_START_CH0>, + <CSI_FS_INT_CTX3_FRAME_START_CH1>, + <CSI_FS_INT_CTX3_FRAME_START_CH2>, + <CSI_FS_INT_CTX3_FRAME_START_CH3>, + <CSI_FS_INT_CTX3_FRAME_START_CH4>, + <CSI_FS_INT_CTX3_FRAME_START_CH5>, + <CSI_FS_INT_CTX3_FRAME_START_CH6>, + <CSI_FS_INT_CTX3_FRAME_START_CH7>, + <CSI_FS_INT_CTX3_FRAME_START_CH8>, + <CSI_FS_INT_CTX3_FRAME_START_CH9>, + <CSI_FS_INT_CTX3_FRAME_START_CH10>, + <CSI_FS_INT_CTX3_FRAME_START_CH11>, + <CSI_FS_INT_CTX3_FRAME_START_CH12>, + <CSI_FS_INT_CTX3_FRAME_START_CH13>, + <CSI_FS_INT_CTX3_FRAME_START_CH14>, + <CSI_FS_INT_CTX3_FRAME_START_CH15>, + <CSI_FS_INT_CTX3_FRAME_START_CH16>, + <CSI_FS_INT_CTX3_FRAME_START_CH17>, + <CSI_FS_INT_CTX3_FRAME_START_CH18>, + <CSI_FS_INT_CTX3_FRAME_START_CH19>, + <CSI_FS_INT_CTX3_FRAME_START_CH20>, + <CSI_FS_INT_CTX3_FRAME_START_CH21>, + <CSI_FS_INT_CTX3_FRAME_START_CH22>, + <CSI_FS_INT_CTX3_FRAME_START_CH23>, + <CSI_FS_INT_CTX3_FRAME_START_CH24>, + <CSI_FS_INT_CTX3_FRAME_START_CH25>, + <CSI_FS_INT_CTX3_FRAME_START_CH26>, + <CSI_FS_INT_CTX3_FRAME_START_CH27>, + <CSI_FS_INT_CTX3_FRAME_START_CH28>, + <CSI_FS_INT_CTX3_FRAME_START_CH29>, + <CSI_FS_INT_CTX3_FRAME_START_CH30>, + <CSI_FS_INT_CTX3_FRAME_START_CH31>; + }; + + csi_ctx4_fs_int: csi-event-info@20 { + irq-reg-space = "csis-link4"; + irq-src-reg = <0x0 0x24>; + irq-reset-reg = <0x0 0x24>; + irq-mask-reg = <0x0 0x20>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH4>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH5>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH6>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH7>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH8>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH9>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH10>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH11>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH12>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH13>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH14>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH15>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH16>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH17>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH18>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH19>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH20>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH21>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH22>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH23>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH24>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH25>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH26>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH27>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH28>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH29>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH30>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH31>; + int-reg-bits = + <CSI_FS_INT_CTX4_FRAME_START_CH0>, + <CSI_FS_INT_CTX4_FRAME_START_CH1>, + <CSI_FS_INT_CTX4_FRAME_START_CH2>, + <CSI_FS_INT_CTX4_FRAME_START_CH3>, + <CSI_FS_INT_CTX4_FRAME_START_CH4>, + <CSI_FS_INT_CTX4_FRAME_START_CH5>, + <CSI_FS_INT_CTX4_FRAME_START_CH6>, + <CSI_FS_INT_CTX4_FRAME_START_CH7>, + <CSI_FS_INT_CTX4_FRAME_START_CH8>, + <CSI_FS_INT_CTX4_FRAME_START_CH9>, + <CSI_FS_INT_CTX4_FRAME_START_CH10>, + <CSI_FS_INT_CTX4_FRAME_START_CH11>, + <CSI_FS_INT_CTX4_FRAME_START_CH12>, + <CSI_FS_INT_CTX4_FRAME_START_CH13>, + <CSI_FS_INT_CTX4_FRAME_START_CH14>, + <CSI_FS_INT_CTX4_FRAME_START_CH15>, + <CSI_FS_INT_CTX4_FRAME_START_CH16>, + <CSI_FS_INT_CTX4_FRAME_START_CH17>, + <CSI_FS_INT_CTX4_FRAME_START_CH18>, + <CSI_FS_INT_CTX4_FRAME_START_CH19>, + <CSI_FS_INT_CTX4_FRAME_START_CH20>, + <CSI_FS_INT_CTX4_FRAME_START_CH21>, + <CSI_FS_INT_CTX4_FRAME_START_CH22>, + <CSI_FS_INT_CTX4_FRAME_START_CH23>, + <CSI_FS_INT_CTX4_FRAME_START_CH24>, + <CSI_FS_INT_CTX4_FRAME_START_CH25>, + <CSI_FS_INT_CTX4_FRAME_START_CH26>, + <CSI_FS_INT_CTX4_FRAME_START_CH27>, + <CSI_FS_INT_CTX4_FRAME_START_CH28>, + <CSI_FS_INT_CTX4_FRAME_START_CH29>, + <CSI_FS_INT_CTX4_FRAME_START_CH30>, + <CSI_FS_INT_CTX4_FRAME_START_CH31>; + }; + + csi_ctx5_fs_int: csi-event-info@21 { + irq-reg-space = "csis-link5"; + irq-src-reg = <0x0 0x24>; + irq-reset-reg = <0x0 0x24>; + irq-mask-reg = <0x0 0x20>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH4>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH5>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH6>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH7>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH8>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH9>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH10>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH11>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH12>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH13>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH14>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH15>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH16>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH17>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH18>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH19>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH20>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH21>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH22>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH23>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH24>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH25>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH26>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH27>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH28>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH29>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH30>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH31>; + int-reg-bits = + <CSI_FS_INT_CTX5_FRAME_START_CH0>, + <CSI_FS_INT_CTX5_FRAME_START_CH1>, + <CSI_FS_INT_CTX5_FRAME_START_CH2>, + <CSI_FS_INT_CTX5_FRAME_START_CH3>, + <CSI_FS_INT_CTX5_FRAME_START_CH4>, + <CSI_FS_INT_CTX5_FRAME_START_CH5>, + <CSI_FS_INT_CTX5_FRAME_START_CH6>, + <CSI_FS_INT_CTX5_FRAME_START_CH7>, + <CSI_FS_INT_CTX5_FRAME_START_CH8>, + <CSI_FS_INT_CTX5_FRAME_START_CH9>, + <CSI_FS_INT_CTX5_FRAME_START_CH10>, + <CSI_FS_INT_CTX5_FRAME_START_CH11>, + <CSI_FS_INT_CTX5_FRAME_START_CH12>, + <CSI_FS_INT_CTX5_FRAME_START_CH13>, + <CSI_FS_INT_CTX5_FRAME_START_CH14>, + <CSI_FS_INT_CTX5_FRAME_START_CH15>, + <CSI_FS_INT_CTX5_FRAME_START_CH16>, + <CSI_FS_INT_CTX5_FRAME_START_CH17>, + <CSI_FS_INT_CTX5_FRAME_START_CH18>, + <CSI_FS_INT_CTX5_FRAME_START_CH19>, + <CSI_FS_INT_CTX5_FRAME_START_CH20>, + <CSI_FS_INT_CTX5_FRAME_START_CH21>, + <CSI_FS_INT_CTX5_FRAME_START_CH22>, + <CSI_FS_INT_CTX5_FRAME_START_CH23>, + <CSI_FS_INT_CTX5_FRAME_START_CH24>, + <CSI_FS_INT_CTX5_FRAME_START_CH25>, + <CSI_FS_INT_CTX5_FRAME_START_CH26>, + <CSI_FS_INT_CTX5_FRAME_START_CH27>, + <CSI_FS_INT_CTX5_FRAME_START_CH28>, + <CSI_FS_INT_CTX5_FRAME_START_CH29>, + <CSI_FS_INT_CTX5_FRAME_START_CH30>, + <CSI_FS_INT_CTX5_FRAME_START_CH31>; + }; + + csi_ctx6_fs_int: csi-event-info@22 { + irq-reg-space = "csis-link6"; + irq-src-reg = <0x0 0x24>; + irq-reset-reg = <0x0 0x24>; + irq-mask-reg = <0x0 0x20>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH4>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH5>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH6>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH7>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH8>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH9>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH10>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH11>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH12>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH13>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH14>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH15>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH16>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH17>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH18>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH19>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH20>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH21>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH22>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH23>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH24>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH25>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH26>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH27>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH28>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH29>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH30>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH31>; + int-reg-bits = + <CSI_FS_INT_CTX6_FRAME_START_CH0>, + <CSI_FS_INT_CTX6_FRAME_START_CH1>, + <CSI_FS_INT_CTX6_FRAME_START_CH2>, + <CSI_FS_INT_CTX6_FRAME_START_CH3>, + <CSI_FS_INT_CTX6_FRAME_START_CH4>, + <CSI_FS_INT_CTX6_FRAME_START_CH5>, + <CSI_FS_INT_CTX6_FRAME_START_CH6>, + <CSI_FS_INT_CTX6_FRAME_START_CH7>, + <CSI_FS_INT_CTX6_FRAME_START_CH8>, + <CSI_FS_INT_CTX6_FRAME_START_CH9>, + <CSI_FS_INT_CTX6_FRAME_START_CH10>, + <CSI_FS_INT_CTX6_FRAME_START_CH11>, + <CSI_FS_INT_CTX6_FRAME_START_CH12>, + <CSI_FS_INT_CTX6_FRAME_START_CH13>, + <CSI_FS_INT_CTX6_FRAME_START_CH14>, + <CSI_FS_INT_CTX6_FRAME_START_CH15>, + <CSI_FS_INT_CTX6_FRAME_START_CH16>, + <CSI_FS_INT_CTX6_FRAME_START_CH17>, + <CSI_FS_INT_CTX6_FRAME_START_CH18>, + <CSI_FS_INT_CTX6_FRAME_START_CH19>, + <CSI_FS_INT_CTX6_FRAME_START_CH20>, + <CSI_FS_INT_CTX6_FRAME_START_CH21>, + <CSI_FS_INT_CTX6_FRAME_START_CH22>, + <CSI_FS_INT_CTX6_FRAME_START_CH23>, + <CSI_FS_INT_CTX6_FRAME_START_CH24>, + <CSI_FS_INT_CTX6_FRAME_START_CH25>, + <CSI_FS_INT_CTX6_FRAME_START_CH26>, + <CSI_FS_INT_CTX6_FRAME_START_CH27>, + <CSI_FS_INT_CTX6_FRAME_START_CH28>, + <CSI_FS_INT_CTX6_FRAME_START_CH29>, + <CSI_FS_INT_CTX6_FRAME_START_CH30>, + <CSI_FS_INT_CTX6_FRAME_START_CH31>; + }; + + csi_ctx7_fs_int: csi-event-info@23 { + irq-reg-space = "csis-link7"; + irq-src-reg = <0x0 0x24>; + irq-reset-reg = <0x0 0x24>; + irq-mask-reg = <0x0 0x20>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH4>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH5>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH6>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH7>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH8>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH9>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH10>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH11>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH12>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH13>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH14>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH15>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH16>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH17>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH18>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH19>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH20>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH21>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH22>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH23>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH24>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH25>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH26>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH27>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH28>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH29>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH30>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH31>; + int-reg-bits = + <CSI_FS_INT_CTX7_FRAME_START_CH0>, + <CSI_FS_INT_CTX7_FRAME_START_CH1>, + <CSI_FS_INT_CTX7_FRAME_START_CH2>, + <CSI_FS_INT_CTX7_FRAME_START_CH3>, + <CSI_FS_INT_CTX7_FRAME_START_CH4>, + <CSI_FS_INT_CTX7_FRAME_START_CH5>, + <CSI_FS_INT_CTX7_FRAME_START_CH6>, + <CSI_FS_INT_CTX7_FRAME_START_CH7>, + <CSI_FS_INT_CTX7_FRAME_START_CH8>, + <CSI_FS_INT_CTX7_FRAME_START_CH9>, + <CSI_FS_INT_CTX7_FRAME_START_CH10>, + <CSI_FS_INT_CTX7_FRAME_START_CH11>, + <CSI_FS_INT_CTX7_FRAME_START_CH12>, + <CSI_FS_INT_CTX7_FRAME_START_CH13>, + <CSI_FS_INT_CTX7_FRAME_START_CH14>, + <CSI_FS_INT_CTX7_FRAME_START_CH15>, + <CSI_FS_INT_CTX7_FRAME_START_CH16>, + <CSI_FS_INT_CTX7_FRAME_START_CH17>, + <CSI_FS_INT_CTX7_FRAME_START_CH18>, + <CSI_FS_INT_CTX7_FRAME_START_CH19>, + <CSI_FS_INT_CTX7_FRAME_START_CH20>, + <CSI_FS_INT_CTX7_FRAME_START_CH21>, + <CSI_FS_INT_CTX7_FRAME_START_CH22>, + <CSI_FS_INT_CTX7_FRAME_START_CH23>, + <CSI_FS_INT_CTX7_FRAME_START_CH24>, + <CSI_FS_INT_CTX7_FRAME_START_CH25>, + <CSI_FS_INT_CTX7_FRAME_START_CH26>, + <CSI_FS_INT_CTX7_FRAME_START_CH27>, + <CSI_FS_INT_CTX7_FRAME_START_CH28>, + <CSI_FS_INT_CTX7_FRAME_START_CH29>, + <CSI_FS_INT_CTX7_FRAME_START_CH30>, + <CSI_FS_INT_CTX7_FRAME_START_CH31>; + }; + + csi_ctx0_fe_int: csi-event-info@24 { + irq-reg-space = "csis-link0"; + irq-src-reg = <0x0 0x2c>; + irq-reset-reg = <0x0 0x2c>; + irq-mask-reg = <0x0 0x28>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH4>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH5>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH6>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH7>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH8>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH9>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH10>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH11>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH12>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH13>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH14>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH15>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH16>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH17>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH18>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH19>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH20>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH21>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH22>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH23>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH24>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH25>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH26>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH27>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH28>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH29>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH30>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH31>; + int-reg-bits = + <CSI_FE_INT_CTX0_FRAME_END_CH0>, + <CSI_FE_INT_CTX0_FRAME_END_CH1>, + <CSI_FE_INT_CTX0_FRAME_END_CH2>, + <CSI_FE_INT_CTX0_FRAME_END_CH3>, + <CSI_FE_INT_CTX0_FRAME_END_CH4>, + <CSI_FE_INT_CTX0_FRAME_END_CH5>, + <CSI_FE_INT_CTX0_FRAME_END_CH6>, + <CSI_FE_INT_CTX0_FRAME_END_CH7>, + <CSI_FE_INT_CTX0_FRAME_END_CH8>, + <CSI_FE_INT_CTX0_FRAME_END_CH9>, + <CSI_FE_INT_CTX0_FRAME_END_CH10>, + <CSI_FE_INT_CTX0_FRAME_END_CH11>, + <CSI_FE_INT_CTX0_FRAME_END_CH12>, + <CSI_FE_INT_CTX0_FRAME_END_CH13>, + <CSI_FE_INT_CTX0_FRAME_END_CH14>, + <CSI_FE_INT_CTX0_FRAME_END_CH15>, + <CSI_FE_INT_CTX0_FRAME_END_CH16>, + <CSI_FE_INT_CTX0_FRAME_END_CH17>, + <CSI_FE_INT_CTX0_FRAME_END_CH18>, + <CSI_FE_INT_CTX0_FRAME_END_CH19>, + <CSI_FE_INT_CTX0_FRAME_END_CH20>, + <CSI_FE_INT_CTX0_FRAME_END_CH21>, + <CSI_FE_INT_CTX0_FRAME_END_CH22>, + <CSI_FE_INT_CTX0_FRAME_END_CH23>, + <CSI_FE_INT_CTX0_FRAME_END_CH24>, + <CSI_FE_INT_CTX0_FRAME_END_CH25>, + <CSI_FE_INT_CTX0_FRAME_END_CH26>, + <CSI_FE_INT_CTX0_FRAME_END_CH27>, + <CSI_FE_INT_CTX0_FRAME_END_CH28>, + <CSI_FE_INT_CTX0_FRAME_END_CH29>, + <CSI_FE_INT_CTX0_FRAME_END_CH30>, + <CSI_FE_INT_CTX0_FRAME_END_CH31>; + }; + + csi_ctx1_fe_int: csi-event-info@25 { + irq-reg-space = "csis-link1"; + irq-src-reg = <0x0 0x2c>; + irq-reset-reg = <0x0 0x2c>; + irq-mask-reg = <0x0 0x28>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH4>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH5>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH6>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH7>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH8>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH9>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH10>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH11>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH12>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH13>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH14>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH15>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH16>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH17>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH18>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH19>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH20>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH21>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH22>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH23>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH24>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH25>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH26>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH27>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH28>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH29>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH30>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH31>; + int-reg-bits = + <CSI_FE_INT_CTX1_FRAME_END_CH0>, + <CSI_FE_INT_CTX1_FRAME_END_CH1>, + <CSI_FE_INT_CTX1_FRAME_END_CH2>, + <CSI_FE_INT_CTX1_FRAME_END_CH3>, + <CSI_FE_INT_CTX1_FRAME_END_CH4>, + <CSI_FE_INT_CTX1_FRAME_END_CH5>, + <CSI_FE_INT_CTX1_FRAME_END_CH6>, + <CSI_FE_INT_CTX1_FRAME_END_CH7>, + <CSI_FE_INT_CTX1_FRAME_END_CH8>, + <CSI_FE_INT_CTX1_FRAME_END_CH9>, + <CSI_FE_INT_CTX1_FRAME_END_CH10>, + <CSI_FE_INT_CTX1_FRAME_END_CH11>, + <CSI_FE_INT_CTX1_FRAME_END_CH12>, + <CSI_FE_INT_CTX1_FRAME_END_CH13>, + <CSI_FE_INT_CTX1_FRAME_END_CH14>, + <CSI_FE_INT_CTX1_FRAME_END_CH15>, + <CSI_FE_INT_CTX1_FRAME_END_CH16>, + <CSI_FE_INT_CTX1_FRAME_END_CH17>, + <CSI_FE_INT_CTX1_FRAME_END_CH18>, + <CSI_FE_INT_CTX1_FRAME_END_CH19>, + <CSI_FE_INT_CTX1_FRAME_END_CH20>, + <CSI_FE_INT_CTX1_FRAME_END_CH21>, + <CSI_FE_INT_CTX1_FRAME_END_CH22>, + <CSI_FE_INT_CTX1_FRAME_END_CH23>, + <CSI_FE_INT_CTX1_FRAME_END_CH24>, + <CSI_FE_INT_CTX1_FRAME_END_CH25>, + <CSI_FE_INT_CTX1_FRAME_END_CH26>, + <CSI_FE_INT_CTX1_FRAME_END_CH27>, + <CSI_FE_INT_CTX1_FRAME_END_CH28>, + <CSI_FE_INT_CTX1_FRAME_END_CH29>, + <CSI_FE_INT_CTX1_FRAME_END_CH30>, + <CSI_FE_INT_CTX1_FRAME_END_CH31>; + }; + + csi_ctx2_fe_int: csi-event-info@26 { + irq-reg-space = "csis-link2"; + irq-src-reg = <0x0 0x2c>; + irq-reset-reg = <0x0 0x2c>; + irq-mask-reg = <0x0 0x28>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH4>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH5>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH6>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH7>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH8>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH9>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH10>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH11>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH12>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH13>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH14>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH15>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH16>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH17>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH18>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH19>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH20>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH21>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH22>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH23>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH24>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH25>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH26>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH27>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH28>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH29>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH30>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH31>; + int-reg-bits = + <CSI_FE_INT_CTX2_FRAME_END_CH0>, + <CSI_FE_INT_CTX2_FRAME_END_CH1>, + <CSI_FE_INT_CTX2_FRAME_END_CH2>, + <CSI_FE_INT_CTX2_FRAME_END_CH3>, + <CSI_FE_INT_CTX2_FRAME_END_CH4>, + <CSI_FE_INT_CTX2_FRAME_END_CH5>, + <CSI_FE_INT_CTX2_FRAME_END_CH6>, + <CSI_FE_INT_CTX2_FRAME_END_CH7>, + <CSI_FE_INT_CTX2_FRAME_END_CH8>, + <CSI_FE_INT_CTX2_FRAME_END_CH9>, + <CSI_FE_INT_CTX2_FRAME_END_CH10>, + <CSI_FE_INT_CTX2_FRAME_END_CH11>, + <CSI_FE_INT_CTX2_FRAME_END_CH12>, + <CSI_FE_INT_CTX2_FRAME_END_CH13>, + <CSI_FE_INT_CTX2_FRAME_END_CH14>, + <CSI_FE_INT_CTX2_FRAME_END_CH15>, + <CSI_FE_INT_CTX2_FRAME_END_CH16>, + <CSI_FE_INT_CTX2_FRAME_END_CH17>, + <CSI_FE_INT_CTX2_FRAME_END_CH18>, + <CSI_FE_INT_CTX2_FRAME_END_CH19>, + <CSI_FE_INT_CTX2_FRAME_END_CH20>, + <CSI_FE_INT_CTX2_FRAME_END_CH21>, + <CSI_FE_INT_CTX2_FRAME_END_CH22>, + <CSI_FE_INT_CTX2_FRAME_END_CH23>, + <CSI_FE_INT_CTX2_FRAME_END_CH24>, + <CSI_FE_INT_CTX2_FRAME_END_CH25>, + <CSI_FE_INT_CTX2_FRAME_END_CH26>, + <CSI_FE_INT_CTX2_FRAME_END_CH27>, + <CSI_FE_INT_CTX2_FRAME_END_CH28>, + <CSI_FE_INT_CTX2_FRAME_END_CH29>, + <CSI_FE_INT_CTX2_FRAME_END_CH30>, + <CSI_FE_INT_CTX2_FRAME_END_CH31>; + }; + + csi_ctx3_fe_int: csi-event-info@27 { + irq-reg-space = "csis-link3"; + irq-src-reg = <0x0 0x2c>; + irq-reset-reg = <0x0 0x2c>; + irq-mask-reg = <0x0 0x28>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH4>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH5>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH6>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH7>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH8>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH9>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH10>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH11>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH12>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH13>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH14>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH15>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH16>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH17>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH18>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH19>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH20>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH21>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH22>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH23>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH24>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH25>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH26>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH27>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH28>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH29>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH30>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH31>; + int-reg-bits = + <CSI_FE_INT_CTX3_FRAME_END_CH0>, + <CSI_FE_INT_CTX3_FRAME_END_CH1>, + <CSI_FE_INT_CTX3_FRAME_END_CH2>, + <CSI_FE_INT_CTX3_FRAME_END_CH3>, + <CSI_FE_INT_CTX3_FRAME_END_CH4>, + <CSI_FE_INT_CTX3_FRAME_END_CH5>, + <CSI_FE_INT_CTX3_FRAME_END_CH6>, + <CSI_FE_INT_CTX3_FRAME_END_CH7>, + <CSI_FE_INT_CTX3_FRAME_END_CH8>, + <CSI_FE_INT_CTX3_FRAME_END_CH9>, + <CSI_FE_INT_CTX3_FRAME_END_CH10>, + <CSI_FE_INT_CTX3_FRAME_END_CH11>, + <CSI_FE_INT_CTX3_FRAME_END_CH12>, + <CSI_FE_INT_CTX3_FRAME_END_CH13>, + <CSI_FE_INT_CTX3_FRAME_END_CH14>, + <CSI_FE_INT_CTX3_FRAME_END_CH15>, + <CSI_FE_INT_CTX3_FRAME_END_CH16>, + <CSI_FE_INT_CTX3_FRAME_END_CH17>, + <CSI_FE_INT_CTX3_FRAME_END_CH18>, + <CSI_FE_INT_CTX3_FRAME_END_CH19>, + <CSI_FE_INT_CTX3_FRAME_END_CH20>, + <CSI_FE_INT_CTX3_FRAME_END_CH21>, + <CSI_FE_INT_CTX3_FRAME_END_CH22>, + <CSI_FE_INT_CTX3_FRAME_END_CH23>, + <CSI_FE_INT_CTX3_FRAME_END_CH24>, + <CSI_FE_INT_CTX3_FRAME_END_CH25>, + <CSI_FE_INT_CTX3_FRAME_END_CH26>, + <CSI_FE_INT_CTX3_FRAME_END_CH27>, + <CSI_FE_INT_CTX3_FRAME_END_CH28>, + <CSI_FE_INT_CTX3_FRAME_END_CH29>, + <CSI_FE_INT_CTX3_FRAME_END_CH30>, + <CSI_FE_INT_CTX3_FRAME_END_CH31>; + }; + + csi_ctx4_fe_int: csi-event-info@28 { + irq-reg-space = "csis-link4"; + irq-src-reg = <0x0 0x2c>; + irq-reset-reg = <0x0 0x2c>; + irq-mask-reg = <0x0 0x28>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH4>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH5>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH6>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH7>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH8>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH9>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH10>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH11>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH12>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH13>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH14>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH15>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH16>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH17>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH18>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH19>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH20>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH21>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH22>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH23>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH24>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH25>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH26>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH27>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH28>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH29>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH30>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH31>; + int-reg-bits = + <CSI_FE_INT_CTX4_FRAME_END_CH0>, + <CSI_FE_INT_CTX4_FRAME_END_CH1>, + <CSI_FE_INT_CTX4_FRAME_END_CH2>, + <CSI_FE_INT_CTX4_FRAME_END_CH3>, + <CSI_FE_INT_CTX4_FRAME_END_CH4>, + <CSI_FE_INT_CTX4_FRAME_END_CH5>, + <CSI_FE_INT_CTX4_FRAME_END_CH6>, + <CSI_FE_INT_CTX4_FRAME_END_CH7>, + <CSI_FE_INT_CTX4_FRAME_END_CH8>, + <CSI_FE_INT_CTX4_FRAME_END_CH9>, + <CSI_FE_INT_CTX4_FRAME_END_CH10>, + <CSI_FE_INT_CTX4_FRAME_END_CH11>, + <CSI_FE_INT_CTX4_FRAME_END_CH12>, + <CSI_FE_INT_CTX4_FRAME_END_CH13>, + <CSI_FE_INT_CTX4_FRAME_END_CH14>, + <CSI_FE_INT_CTX4_FRAME_END_CH15>, + <CSI_FE_INT_CTX4_FRAME_END_CH16>, + <CSI_FE_INT_CTX4_FRAME_END_CH17>, + <CSI_FE_INT_CTX4_FRAME_END_CH18>, + <CSI_FE_INT_CTX4_FRAME_END_CH19>, + <CSI_FE_INT_CTX4_FRAME_END_CH20>, + <CSI_FE_INT_CTX4_FRAME_END_CH21>, + <CSI_FE_INT_CTX4_FRAME_END_CH22>, + <CSI_FE_INT_CTX4_FRAME_END_CH23>, + <CSI_FE_INT_CTX4_FRAME_END_CH24>, + <CSI_FE_INT_CTX4_FRAME_END_CH25>, + <CSI_FE_INT_CTX4_FRAME_END_CH26>, + <CSI_FE_INT_CTX4_FRAME_END_CH27>, + <CSI_FE_INT_CTX4_FRAME_END_CH28>, + <CSI_FE_INT_CTX4_FRAME_END_CH29>, + <CSI_FE_INT_CTX4_FRAME_END_CH30>, + <CSI_FE_INT_CTX4_FRAME_END_CH31>; + }; + + csi_ctx5_fe_int: csi-event-info@29 { + irq-reg-space = "csis-link5"; + irq-src-reg = <0x0 0x2c>; + irq-reset-reg = <0x0 0x2c>; + irq-mask-reg = <0x0 0x28>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH4>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH5>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH6>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH7>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH8>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH9>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH10>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH11>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH12>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH13>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH14>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH15>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH16>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH17>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH18>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH19>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH20>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH21>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH22>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH23>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH24>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH25>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH26>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH27>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH28>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH29>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH30>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH31>; + int-reg-bits = + <CSI_FE_INT_CTX5_FRAME_END_CH0>, + <CSI_FE_INT_CTX5_FRAME_END_CH1>, + <CSI_FE_INT_CTX5_FRAME_END_CH2>, + <CSI_FE_INT_CTX5_FRAME_END_CH3>, + <CSI_FE_INT_CTX5_FRAME_END_CH4>, + <CSI_FE_INT_CTX5_FRAME_END_CH5>, + <CSI_FE_INT_CTX5_FRAME_END_CH6>, + <CSI_FE_INT_CTX5_FRAME_END_CH7>, + <CSI_FE_INT_CTX5_FRAME_END_CH8>, + <CSI_FE_INT_CTX5_FRAME_END_CH9>, + <CSI_FE_INT_CTX5_FRAME_END_CH10>, + <CSI_FE_INT_CTX5_FRAME_END_CH11>, + <CSI_FE_INT_CTX5_FRAME_END_CH12>, + <CSI_FE_INT_CTX5_FRAME_END_CH13>, + <CSI_FE_INT_CTX5_FRAME_END_CH14>, + <CSI_FE_INT_CTX5_FRAME_END_CH15>, + <CSI_FE_INT_CTX5_FRAME_END_CH16>, + <CSI_FE_INT_CTX5_FRAME_END_CH17>, + <CSI_FE_INT_CTX5_FRAME_END_CH18>, + <CSI_FE_INT_CTX5_FRAME_END_CH19>, + <CSI_FE_INT_CTX5_FRAME_END_CH20>, + <CSI_FE_INT_CTX5_FRAME_END_CH21>, + <CSI_FE_INT_CTX5_FRAME_END_CH22>, + <CSI_FE_INT_CTX5_FRAME_END_CH23>, + <CSI_FE_INT_CTX5_FRAME_END_CH24>, + <CSI_FE_INT_CTX5_FRAME_END_CH25>, + <CSI_FE_INT_CTX5_FRAME_END_CH26>, + <CSI_FE_INT_CTX5_FRAME_END_CH27>, + <CSI_FE_INT_CTX5_FRAME_END_CH28>, + <CSI_FE_INT_CTX5_FRAME_END_CH29>, + <CSI_FE_INT_CTX5_FRAME_END_CH30>, + <CSI_FE_INT_CTX5_FRAME_END_CH31>; + }; + + csi_ctx6_fe_int: csi-event-info@30 { + irq-reg-space = "csis-link6"; + irq-src-reg = <0x0 0x2c>; + irq-reset-reg = <0x0 0x2c>; + irq-mask-reg = <0x0 0x28>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH4>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH5>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH6>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH7>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH8>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH9>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH10>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH11>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH12>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH13>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH14>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH15>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH16>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH17>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH18>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH19>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH20>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH21>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH22>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH23>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH24>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH25>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH26>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH27>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH28>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH29>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH30>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH31>; + int-reg-bits = + <CSI_FE_INT_CTX6_FRAME_END_CH0>, + <CSI_FE_INT_CTX6_FRAME_END_CH1>, + <CSI_FE_INT_CTX6_FRAME_END_CH2>, + <CSI_FE_INT_CTX6_FRAME_END_CH3>, + <CSI_FE_INT_CTX6_FRAME_END_CH4>, + <CSI_FE_INT_CTX6_FRAME_END_CH5>, + <CSI_FE_INT_CTX6_FRAME_END_CH6>, + <CSI_FE_INT_CTX6_FRAME_END_CH7>, + <CSI_FE_INT_CTX6_FRAME_END_CH8>, + <CSI_FE_INT_CTX6_FRAME_END_CH9>, + <CSI_FE_INT_CTX6_FRAME_END_CH10>, + <CSI_FE_INT_CTX6_FRAME_END_CH11>, + <CSI_FE_INT_CTX6_FRAME_END_CH12>, + <CSI_FE_INT_CTX6_FRAME_END_CH13>, + <CSI_FE_INT_CTX6_FRAME_END_CH14>, + <CSI_FE_INT_CTX6_FRAME_END_CH15>, + <CSI_FE_INT_CTX6_FRAME_END_CH16>, + <CSI_FE_INT_CTX6_FRAME_END_CH17>, + <CSI_FE_INT_CTX6_FRAME_END_CH18>, + <CSI_FE_INT_CTX6_FRAME_END_CH19>, + <CSI_FE_INT_CTX6_FRAME_END_CH20>, + <CSI_FE_INT_CTX6_FRAME_END_CH21>, + <CSI_FE_INT_CTX6_FRAME_END_CH22>, + <CSI_FE_INT_CTX6_FRAME_END_CH23>, + <CSI_FE_INT_CTX6_FRAME_END_CH24>, + <CSI_FE_INT_CTX6_FRAME_END_CH25>, + <CSI_FE_INT_CTX6_FRAME_END_CH26>, + <CSI_FE_INT_CTX6_FRAME_END_CH27>, + <CSI_FE_INT_CTX6_FRAME_END_CH28>, + <CSI_FE_INT_CTX6_FRAME_END_CH29>, + <CSI_FE_INT_CTX6_FRAME_END_CH30>, + <CSI_FE_INT_CTX6_FRAME_END_CH31>; + }; + + csi_ctx7_fe_int: csi-event-info@31 { + irq-reg-space = "csis-link7"; + irq-src-reg = <0x0 0x2c>; + irq-reset-reg = <0x0 0x2c>; + irq-mask-reg = <0x0 0x28>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH4>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH5>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH6>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH7>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH8>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH9>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH10>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH11>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH12>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH13>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH14>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH15>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH16>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH17>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH18>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH19>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH20>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH21>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH22>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH23>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH24>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH25>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH26>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH27>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH28>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH29>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH30>, + <LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH31>; + int-reg-bits = + <CSI_FE_INT_CTX7_FRAME_END_CH0>, + <CSI_FE_INT_CTX7_FRAME_END_CH1>, + <CSI_FE_INT_CTX7_FRAME_END_CH2>, + <CSI_FE_INT_CTX7_FRAME_END_CH3>, + <CSI_FE_INT_CTX7_FRAME_END_CH4>, + <CSI_FE_INT_CTX7_FRAME_END_CH5>, + <CSI_FE_INT_CTX7_FRAME_END_CH6>, + <CSI_FE_INT_CTX7_FRAME_END_CH7>, + <CSI_FE_INT_CTX7_FRAME_END_CH8>, + <CSI_FE_INT_CTX7_FRAME_END_CH9>, + <CSI_FE_INT_CTX7_FRAME_END_CH10>, + <CSI_FE_INT_CTX7_FRAME_END_CH11>, + <CSI_FE_INT_CTX7_FRAME_END_CH12>, + <CSI_FE_INT_CTX7_FRAME_END_CH13>, + <CSI_FE_INT_CTX7_FRAME_END_CH14>, + <CSI_FE_INT_CTX7_FRAME_END_CH15>, + <CSI_FE_INT_CTX7_FRAME_END_CH16>, + <CSI_FE_INT_CTX7_FRAME_END_CH17>, + <CSI_FE_INT_CTX7_FRAME_END_CH18>, + <CSI_FE_INT_CTX7_FRAME_END_CH19>, + <CSI_FE_INT_CTX7_FRAME_END_CH20>, + <CSI_FE_INT_CTX7_FRAME_END_CH21>, + <CSI_FE_INT_CTX7_FRAME_END_CH22>, + <CSI_FE_INT_CTX7_FRAME_END_CH23>, + <CSI_FE_INT_CTX7_FRAME_END_CH24>, + <CSI_FE_INT_CTX7_FRAME_END_CH25>, + <CSI_FE_INT_CTX7_FRAME_END_CH26>, + <CSI_FE_INT_CTX7_FRAME_END_CH27>, + <CSI_FE_INT_CTX7_FRAME_END_CH28>, + <CSI_FE_INT_CTX7_FRAME_END_CH29>, + <CSI_FE_INT_CTX7_FRAME_END_CH30>, + <CSI_FE_INT_CTX7_FRAME_END_CH31>; + }; + + csi_zsl_dma_ctx0_int: csi_zsl_dma-event-info@32 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x1408>; + irq-reset-reg = <0x0 0x1408>; + irq-mask-reg = <0x0 0x1404>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_LINE_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_LINE_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_LINE_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_LINE_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_START0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_START1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_START2>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_START3>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FIFO_FULL>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_QREQN_P>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_LASTDATA_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_LASTADDR_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_ABORT_DONE>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FSTART_IN_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FSTART_IN_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_OVERLAP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_OVERLAP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_OVERLAP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_OVERLAP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_DROP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_DROP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_DROP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_DROP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_C2COM_LOST_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_C2COM_LOST_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_C2COM_SLOW_RING>; + int-reg-bits = + <CSI_ZSL_DMA_INT_CTX0_LINE_END0>, + <CSI_ZSL_DMA_INT_CTX0_LINE_END1>, + <CSI_ZSL_DMA_INT_CTX0_LINE_END2>, + <CSI_ZSL_DMA_INT_CTX0_LINE_END3>, + <CSI_ZSL_DMA_INT_CTX0_FRAME_START0>, + <CSI_ZSL_DMA_INT_CTX0_FRAME_START1>, + <CSI_ZSL_DMA_INT_CTX0_FRAME_START2>, + <CSI_ZSL_DMA_INT_CTX0_FRAME_START3>, + <CSI_ZSL_DMA_INT_CTX0_FRAME_END0>, + <CSI_ZSL_DMA_INT_CTX0_FRAME_END1>, + <CSI_ZSL_DMA_INT_CTX0_FRAME_END2>, + <CSI_ZSL_DMA_INT_CTX0_FRAME_END3>, + <CSI_ZSL_DMA_INT_CTX0_FIFO_FULL>, + <CSI_ZSL_DMA_INT_CTX0_QREQN_P>, + <CSI_ZSL_DMA_INT_CTX0_LASTDATA_ERROR>, + <CSI_ZSL_DMA_INT_CTX0_LASTADDR_ERROR>, + <CSI_ZSL_DMA_INT_CTX0_ABORT_DONE>, + <CSI_ZSL_DMA_INT_CTX0_FSTART_IN_FLUSH_CH0>, + <CSI_ZSL_DMA_INT_CTX0_FSTART_IN_FLUSH_CH1>, + <CSI_ZSL_DMA_INT_CTX0_OVERLAP0>, + <CSI_ZSL_DMA_INT_CTX0_OVERLAP1>, + <CSI_ZSL_DMA_INT_CTX0_OVERLAP2>, + <CSI_ZSL_DMA_INT_CTX0_OVERLAP3>, + <CSI_ZSL_DMA_INT_CTX0_FRAME_DROP0>, + <CSI_ZSL_DMA_INT_CTX0_FRAME_DROP1>, + <CSI_ZSL_DMA_INT_CTX0_FRAME_DROP2>, + <CSI_ZSL_DMA_INT_CTX0_FRAME_DROP3>, + <CSI_ZSL_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH0>, + <CSI_ZSL_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH1>, + <CSI_ZSL_DMA_INT_CTX0_C2COM_SLOW_RING>; + }; + + csi_zsl_dma_ctx1_int: csi_zsl_dma-event-info@33 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x2408>; + irq-reset-reg = <0x0 0x2408>; + irq-mask-reg = <0x0 0x2404>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_LINE_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_LINE_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_LINE_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_LINE_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_START0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_START1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_START2>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_START3>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FIFO_FULL>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_QREQN_P>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_LASTDATA_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_LASTADDR_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_ABORT_DONE>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FSTART_IN_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FSTART_IN_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_OVERLAP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_OVERLAP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_OVERLAP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_OVERLAP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_DROP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_DROP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_DROP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_DROP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_C2COM_LOST_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_C2COM_LOST_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_C2COM_SLOW_RING>; + int-reg-bits = + <CSI_ZSL_DMA_INT_CTX1_LINE_END0>, + <CSI_ZSL_DMA_INT_CTX1_LINE_END1>, + <CSI_ZSL_DMA_INT_CTX1_LINE_END2>, + <CSI_ZSL_DMA_INT_CTX1_LINE_END3>, + <CSI_ZSL_DMA_INT_CTX1_FRAME_START0>, + <CSI_ZSL_DMA_INT_CTX1_FRAME_START1>, + <CSI_ZSL_DMA_INT_CTX1_FRAME_START2>, + <CSI_ZSL_DMA_INT_CTX1_FRAME_START3>, + <CSI_ZSL_DMA_INT_CTX1_FRAME_END0>, + <CSI_ZSL_DMA_INT_CTX1_FRAME_END1>, + <CSI_ZSL_DMA_INT_CTX1_FRAME_END2>, + <CSI_ZSL_DMA_INT_CTX1_FRAME_END3>, + <CSI_ZSL_DMA_INT_CTX1_FIFO_FULL>, + <CSI_ZSL_DMA_INT_CTX1_QREQN_P>, + <CSI_ZSL_DMA_INT_CTX1_LASTDATA_ERROR>, + <CSI_ZSL_DMA_INT_CTX1_LASTADDR_ERROR>, + <CSI_ZSL_DMA_INT_CTX1_ABORT_DONE>, + <CSI_ZSL_DMA_INT_CTX1_FSTART_IN_FLUSH_CH0>, + <CSI_ZSL_DMA_INT_CTX1_FSTART_IN_FLUSH_CH1>, + <CSI_ZSL_DMA_INT_CTX1_OVERLAP0>, + <CSI_ZSL_DMA_INT_CTX1_OVERLAP1>, + <CSI_ZSL_DMA_INT_CTX1_OVERLAP2>, + <CSI_ZSL_DMA_INT_CTX1_OVERLAP3>, + <CSI_ZSL_DMA_INT_CTX1_FRAME_DROP0>, + <CSI_ZSL_DMA_INT_CTX1_FRAME_DROP1>, + <CSI_ZSL_DMA_INT_CTX1_FRAME_DROP2>, + <CSI_ZSL_DMA_INT_CTX1_FRAME_DROP3>, + <CSI_ZSL_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH0>, + <CSI_ZSL_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH1>, + <CSI_ZSL_DMA_INT_CTX1_C2COM_SLOW_RING>; + }; + + csi_zsl_dma_ctx2_int: csi_zsl_dma-event-info@34 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x3408>; + irq-reset-reg = <0x0 0x3408>; + irq-mask-reg = <0x0 0x3404>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_LINE_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_LINE_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_LINE_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_LINE_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_START0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_START1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_START2>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_START3>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FIFO_FULL>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_QREQN_P>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_LASTDATA_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_LASTADDR_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_ABORT_DONE>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FSTART_IN_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FSTART_IN_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_OVERLAP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_OVERLAP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_OVERLAP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_OVERLAP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_DROP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_DROP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_DROP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_DROP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_C2COM_LOST_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_C2COM_LOST_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_C2COM_SLOW_RING>; + int-reg-bits = + <CSI_ZSL_DMA_INT_CTX2_LINE_END0>, + <CSI_ZSL_DMA_INT_CTX2_LINE_END1>, + <CSI_ZSL_DMA_INT_CTX2_LINE_END2>, + <CSI_ZSL_DMA_INT_CTX2_LINE_END3>, + <CSI_ZSL_DMA_INT_CTX2_FRAME_START0>, + <CSI_ZSL_DMA_INT_CTX2_FRAME_START1>, + <CSI_ZSL_DMA_INT_CTX2_FRAME_START2>, + <CSI_ZSL_DMA_INT_CTX2_FRAME_START3>, + <CSI_ZSL_DMA_INT_CTX2_FRAME_END0>, + <CSI_ZSL_DMA_INT_CTX2_FRAME_END1>, + <CSI_ZSL_DMA_INT_CTX2_FRAME_END2>, + <CSI_ZSL_DMA_INT_CTX2_FRAME_END3>, + <CSI_ZSL_DMA_INT_CTX2_FIFO_FULL>, + <CSI_ZSL_DMA_INT_CTX2_QREQN_P>, + <CSI_ZSL_DMA_INT_CTX2_LASTDATA_ERROR>, + <CSI_ZSL_DMA_INT_CTX2_LASTADDR_ERROR>, + <CSI_ZSL_DMA_INT_CTX2_ABORT_DONE>, + <CSI_ZSL_DMA_INT_CTX2_FSTART_IN_FLUSH_CH0>, + <CSI_ZSL_DMA_INT_CTX2_FSTART_IN_FLUSH_CH1>, + <CSI_ZSL_DMA_INT_CTX2_OVERLAP0>, + <CSI_ZSL_DMA_INT_CTX2_OVERLAP1>, + <CSI_ZSL_DMA_INT_CTX2_OVERLAP2>, + <CSI_ZSL_DMA_INT_CTX2_OVERLAP3>, + <CSI_ZSL_DMA_INT_CTX2_FRAME_DROP0>, + <CSI_ZSL_DMA_INT_CTX2_FRAME_DROP1>, + <CSI_ZSL_DMA_INT_CTX2_FRAME_DROP2>, + <CSI_ZSL_DMA_INT_CTX2_FRAME_DROP3>, + <CSI_ZSL_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH0>, + <CSI_ZSL_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH1>, + <CSI_ZSL_DMA_INT_CTX2_C2COM_SLOW_RING>; + }; + + csi_strp_dma_ctx0_int: csi_strp_dma-event-info@35 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x4408>; + irq-reset-reg = <0x0 0x4408>; + irq-mask-reg = <0x0 0x4404>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_LINE_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_LINE_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_LINE_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_LINE_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_START0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_START1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_START2>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_START3>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FIFO_FULL>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_QREQN_P>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_LASTDATA_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_LASTADDR_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_ABORT_DONE>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FSTART_IN_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FSTART_IN_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_OVERLAP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_OVERLAP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_OVERLAP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_OVERLAP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_DROP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_DROP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_DROP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_DROP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_C2COM_LOST_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_C2COM_LOST_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_C2COM_SLOW_RING>; + int-reg-bits = + <CSI_STRP_DMA_INT_CTX0_LINE_END0>, + <CSI_STRP_DMA_INT_CTX0_LINE_END1>, + <CSI_STRP_DMA_INT_CTX0_LINE_END2>, + <CSI_STRP_DMA_INT_CTX0_LINE_END3>, + <CSI_STRP_DMA_INT_CTX0_FRAME_START0>, + <CSI_STRP_DMA_INT_CTX0_FRAME_START1>, + <CSI_STRP_DMA_INT_CTX0_FRAME_START2>, + <CSI_STRP_DMA_INT_CTX0_FRAME_START3>, + <CSI_STRP_DMA_INT_CTX0_FRAME_END0>, + <CSI_STRP_DMA_INT_CTX0_FRAME_END1>, + <CSI_STRP_DMA_INT_CTX0_FRAME_END2>, + <CSI_STRP_DMA_INT_CTX0_FRAME_END3>, + <CSI_STRP_DMA_INT_CTX0_FIFO_FULL>, + <CSI_STRP_DMA_INT_CTX0_QREQN_P>, + <CSI_STRP_DMA_INT_CTX0_LASTDATA_ERROR>, + <CSI_STRP_DMA_INT_CTX0_LASTADDR_ERROR>, + <CSI_STRP_DMA_INT_CTX0_ABORT_DONE>, + <CSI_STRP_DMA_INT_CTX0_FSTART_IN_FLUSH_CH0>, + <CSI_STRP_DMA_INT_CTX0_FSTART_IN_FLUSH_CH1>, + <CSI_STRP_DMA_INT_CTX0_OVERLAP0>, + <CSI_STRP_DMA_INT_CTX0_OVERLAP1>, + <CSI_STRP_DMA_INT_CTX0_OVERLAP2>, + <CSI_STRP_DMA_INT_CTX0_OVERLAP3>, + <CSI_STRP_DMA_INT_CTX0_FRAME_DROP0>, + <CSI_STRP_DMA_INT_CTX0_FRAME_DROP1>, + <CSI_STRP_DMA_INT_CTX0_FRAME_DROP2>, + <CSI_STRP_DMA_INT_CTX0_FRAME_DROP3>, + <CSI_STRP_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH0>, + <CSI_STRP_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH1>, + <CSI_STRP_DMA_INT_CTX0_C2COM_SLOW_RING>; + }; + + csi_strp_dma_ctx1_int: csi_strp_dma-event-info@36 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x5408>; + irq-reset-reg = <0x0 0x5408>; + irq-mask-reg = <0x0 0x5404>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_LINE_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_LINE_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_LINE_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_LINE_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_START0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_START1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_START2>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_START3>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FIFO_FULL>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_QREQN_P>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_LASTDATA_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_LASTADDR_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_ABORT_DONE>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FSTART_IN_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FSTART_IN_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_OVERLAP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_OVERLAP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_OVERLAP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_OVERLAP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_DROP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_DROP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_DROP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_DROP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_C2COM_LOST_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_C2COM_LOST_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_C2COM_SLOW_RING>; + int-reg-bits = + <CSI_STRP_DMA_INT_CTX1_LINE_END0>, + <CSI_STRP_DMA_INT_CTX1_LINE_END1>, + <CSI_STRP_DMA_INT_CTX1_LINE_END2>, + <CSI_STRP_DMA_INT_CTX1_LINE_END3>, + <CSI_STRP_DMA_INT_CTX1_FRAME_START0>, + <CSI_STRP_DMA_INT_CTX1_FRAME_START1>, + <CSI_STRP_DMA_INT_CTX1_FRAME_START2>, + <CSI_STRP_DMA_INT_CTX1_FRAME_START3>, + <CSI_STRP_DMA_INT_CTX1_FRAME_END0>, + <CSI_STRP_DMA_INT_CTX1_FRAME_END1>, + <CSI_STRP_DMA_INT_CTX1_FRAME_END2>, + <CSI_STRP_DMA_INT_CTX1_FRAME_END3>, + <CSI_STRP_DMA_INT_CTX1_FIFO_FULL>, + <CSI_STRP_DMA_INT_CTX1_QREQN_P>, + <CSI_STRP_DMA_INT_CTX1_LASTDATA_ERROR>, + <CSI_STRP_DMA_INT_CTX1_LASTADDR_ERROR>, + <CSI_STRP_DMA_INT_CTX1_ABORT_DONE>, + <CSI_STRP_DMA_INT_CTX1_FSTART_IN_FLUSH_CH0>, + <CSI_STRP_DMA_INT_CTX1_FSTART_IN_FLUSH_CH1>, + <CSI_STRP_DMA_INT_CTX1_OVERLAP0>, + <CSI_STRP_DMA_INT_CTX1_OVERLAP1>, + <CSI_STRP_DMA_INT_CTX1_OVERLAP2>, + <CSI_STRP_DMA_INT_CTX1_OVERLAP3>, + <CSI_STRP_DMA_INT_CTX1_FRAME_DROP0>, + <CSI_STRP_DMA_INT_CTX1_FRAME_DROP1>, + <CSI_STRP_DMA_INT_CTX1_FRAME_DROP2>, + <CSI_STRP_DMA_INT_CTX1_FRAME_DROP3>, + <CSI_STRP_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH0>, + <CSI_STRP_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH1>, + <CSI_STRP_DMA_INT_CTX1_C2COM_SLOW_RING>; + }; + + csi_strp_dma_ctx2_int: csi_strp_dma-event-info@37 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x6408>; + irq-reset-reg = <0x0 0x6408>; + irq-mask-reg = <0x0 0x6404>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_LINE_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_LINE_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_LINE_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_LINE_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_START0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_START1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_START2>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_START3>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FIFO_FULL>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_QREQN_P>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_LASTDATA_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_LASTADDR_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_ABORT_DONE>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FSTART_IN_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FSTART_IN_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_OVERLAP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_OVERLAP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_OVERLAP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_OVERLAP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_DROP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_DROP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_DROP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_DROP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_C2COM_LOST_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_C2COM_LOST_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_C2COM_SLOW_RING>; + int-reg-bits = + <CSI_STRP_DMA_INT_CTX2_LINE_END0>, + <CSI_STRP_DMA_INT_CTX2_LINE_END1>, + <CSI_STRP_DMA_INT_CTX2_LINE_END2>, + <CSI_STRP_DMA_INT_CTX2_LINE_END3>, + <CSI_STRP_DMA_INT_CTX2_FRAME_START0>, + <CSI_STRP_DMA_INT_CTX2_FRAME_START1>, + <CSI_STRP_DMA_INT_CTX2_FRAME_START2>, + <CSI_STRP_DMA_INT_CTX2_FRAME_START3>, + <CSI_STRP_DMA_INT_CTX2_FRAME_END0>, + <CSI_STRP_DMA_INT_CTX2_FRAME_END1>, + <CSI_STRP_DMA_INT_CTX2_FRAME_END2>, + <CSI_STRP_DMA_INT_CTX2_FRAME_END3>, + <CSI_STRP_DMA_INT_CTX2_FIFO_FULL>, + <CSI_STRP_DMA_INT_CTX2_QREQN_P>, + <CSI_STRP_DMA_INT_CTX2_LASTDATA_ERROR>, + <CSI_STRP_DMA_INT_CTX2_LASTADDR_ERROR>, + <CSI_STRP_DMA_INT_CTX2_ABORT_DONE>, + <CSI_STRP_DMA_INT_CTX2_FSTART_IN_FLUSH_CH0>, + <CSI_STRP_DMA_INT_CTX2_FSTART_IN_FLUSH_CH1>, + <CSI_STRP_DMA_INT_CTX2_OVERLAP0>, + <CSI_STRP_DMA_INT_CTX2_OVERLAP1>, + <CSI_STRP_DMA_INT_CTX2_OVERLAP2>, + <CSI_STRP_DMA_INT_CTX2_OVERLAP3>, + <CSI_STRP_DMA_INT_CTX2_FRAME_DROP0>, + <CSI_STRP_DMA_INT_CTX2_FRAME_DROP1>, + <CSI_STRP_DMA_INT_CTX2_FRAME_DROP2>, + <CSI_STRP_DMA_INT_CTX2_FRAME_DROP3>, + <CSI_STRP_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH0>, + <CSI_STRP_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH1>, + <CSI_STRP_DMA_INT_CTX2_C2COM_SLOW_RING>; + }; + + csi_csis_dma_ctx0_int: csi_csis_dma-event-info@38 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x7408>; + irq-reset-reg = <0x0 0x7408>; + irq-mask-reg = <0x0 0x7404>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_LINE_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_LINE_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_LINE_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_LINE_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_START0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_START1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_START2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_START3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FIFO_FULL>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_QREQN_P>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_LASTDATA_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_LASTADDR_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_ABORT_DONE>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FSTART_IN_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FSTART_IN_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_OVERLAP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_OVERLAP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_OVERLAP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_OVERLAP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_DROP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_DROP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_DROP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_DROP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_C2COM_LOST_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_C2COM_LOST_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_C2COM_SLOW_RING>; + int-reg-bits = + <CSI_CSIS_DMA_INT_CTX0_LINE_END0>, + <CSI_CSIS_DMA_INT_CTX0_LINE_END1>, + <CSI_CSIS_DMA_INT_CTX0_LINE_END2>, + <CSI_CSIS_DMA_INT_CTX0_LINE_END3>, + <CSI_CSIS_DMA_INT_CTX0_FRAME_START0>, + <CSI_CSIS_DMA_INT_CTX0_FRAME_START1>, + <CSI_CSIS_DMA_INT_CTX0_FRAME_START2>, + <CSI_CSIS_DMA_INT_CTX0_FRAME_START3>, + <CSI_CSIS_DMA_INT_CTX0_FRAME_END0>, + <CSI_CSIS_DMA_INT_CTX0_FRAME_END1>, + <CSI_CSIS_DMA_INT_CTX0_FRAME_END2>, + <CSI_CSIS_DMA_INT_CTX0_FRAME_END3>, + <CSI_CSIS_DMA_INT_CTX0_FIFO_FULL>, + <CSI_CSIS_DMA_INT_CTX0_QREQN_P>, + <CSI_CSIS_DMA_INT_CTX0_LASTDATA_ERROR>, + <CSI_CSIS_DMA_INT_CTX0_LASTADDR_ERROR>, + <CSI_CSIS_DMA_INT_CTX0_ABORT_DONE>, + <CSI_CSIS_DMA_INT_CTX0_FSTART_IN_FLUSH_CH0>, + <CSI_CSIS_DMA_INT_CTX0_FSTART_IN_FLUSH_CH1>, + <CSI_CSIS_DMA_INT_CTX0_OVERLAP0>, + <CSI_CSIS_DMA_INT_CTX0_OVERLAP1>, + <CSI_CSIS_DMA_INT_CTX0_OVERLAP2>, + <CSI_CSIS_DMA_INT_CTX0_OVERLAP3>, + <CSI_CSIS_DMA_INT_CTX0_FRAME_DROP0>, + <CSI_CSIS_DMA_INT_CTX0_FRAME_DROP1>, + <CSI_CSIS_DMA_INT_CTX0_FRAME_DROP2>, + <CSI_CSIS_DMA_INT_CTX0_FRAME_DROP3>, + <CSI_CSIS_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH0>, + <CSI_CSIS_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH1>, + <CSI_CSIS_DMA_INT_CTX0_C2COM_SLOW_RING>; + }; + + csi_csis_dma_ctx1_int: csi_csis_dma-event-info@39 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x8408>; + irq-reset-reg = <0x0 0x8408>; + irq-mask-reg = <0x0 0x8404>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_LINE_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_LINE_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_LINE_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_LINE_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_START0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_START1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_START2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_START3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FIFO_FULL>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_QREQN_P>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_LASTDATA_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_LASTADDR_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_ABORT_DONE>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FSTART_IN_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FSTART_IN_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_OVERLAP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_OVERLAP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_OVERLAP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_OVERLAP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_DROP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_DROP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_DROP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_DROP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_C2COM_LOST_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_C2COM_LOST_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_C2COM_SLOW_RING>; + int-reg-bits = + <CSI_CSIS_DMA_INT_CTX1_LINE_END0>, + <CSI_CSIS_DMA_INT_CTX1_LINE_END1>, + <CSI_CSIS_DMA_INT_CTX1_LINE_END2>, + <CSI_CSIS_DMA_INT_CTX1_LINE_END3>, + <CSI_CSIS_DMA_INT_CTX1_FRAME_START0>, + <CSI_CSIS_DMA_INT_CTX1_FRAME_START1>, + <CSI_CSIS_DMA_INT_CTX1_FRAME_START2>, + <CSI_CSIS_DMA_INT_CTX1_FRAME_START3>, + <CSI_CSIS_DMA_INT_CTX1_FRAME_END0>, + <CSI_CSIS_DMA_INT_CTX1_FRAME_END1>, + <CSI_CSIS_DMA_INT_CTX1_FRAME_END2>, + <CSI_CSIS_DMA_INT_CTX1_FRAME_END3>, + <CSI_CSIS_DMA_INT_CTX1_FIFO_FULL>, + <CSI_CSIS_DMA_INT_CTX1_QREQN_P>, + <CSI_CSIS_DMA_INT_CTX1_LASTDATA_ERROR>, + <CSI_CSIS_DMA_INT_CTX1_LASTADDR_ERROR>, + <CSI_CSIS_DMA_INT_CTX1_ABORT_DONE>, + <CSI_CSIS_DMA_INT_CTX1_FSTART_IN_FLUSH_CH0>, + <CSI_CSIS_DMA_INT_CTX1_FSTART_IN_FLUSH_CH1>, + <CSI_CSIS_DMA_INT_CTX1_OVERLAP0>, + <CSI_CSIS_DMA_INT_CTX1_OVERLAP1>, + <CSI_CSIS_DMA_INT_CTX1_OVERLAP2>, + <CSI_CSIS_DMA_INT_CTX1_OVERLAP3>, + <CSI_CSIS_DMA_INT_CTX1_FRAME_DROP0>, + <CSI_CSIS_DMA_INT_CTX1_FRAME_DROP1>, + <CSI_CSIS_DMA_INT_CTX1_FRAME_DROP2>, + <CSI_CSIS_DMA_INT_CTX1_FRAME_DROP3>, + <CSI_CSIS_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH0>, + <CSI_CSIS_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH1>, + <CSI_CSIS_DMA_INT_CTX1_C2COM_SLOW_RING>; + }; + + csi_csis_dma_ctx2_int: csi_csis_dma-event-info@40 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x9408>; + irq-reset-reg = <0x0 0x9408>; + irq-mask-reg = <0x0 0x9404>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_LINE_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_LINE_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_LINE_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_LINE_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_START0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_START1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_START2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_START3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FIFO_FULL>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_QREQN_P>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_LASTDATA_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_LASTADDR_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_ABORT_DONE>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FSTART_IN_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FSTART_IN_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_OVERLAP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_OVERLAP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_OVERLAP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_OVERLAP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_DROP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_DROP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_DROP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_DROP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_C2COM_LOST_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_C2COM_LOST_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_C2COM_SLOW_RING>; + int-reg-bits = + <CSI_CSIS_DMA_INT_CTX2_LINE_END0>, + <CSI_CSIS_DMA_INT_CTX2_LINE_END1>, + <CSI_CSIS_DMA_INT_CTX2_LINE_END2>, + <CSI_CSIS_DMA_INT_CTX2_LINE_END3>, + <CSI_CSIS_DMA_INT_CTX2_FRAME_START0>, + <CSI_CSIS_DMA_INT_CTX2_FRAME_START1>, + <CSI_CSIS_DMA_INT_CTX2_FRAME_START2>, + <CSI_CSIS_DMA_INT_CTX2_FRAME_START3>, + <CSI_CSIS_DMA_INT_CTX2_FRAME_END0>, + <CSI_CSIS_DMA_INT_CTX2_FRAME_END1>, + <CSI_CSIS_DMA_INT_CTX2_FRAME_END2>, + <CSI_CSIS_DMA_INT_CTX2_FRAME_END3>, + <CSI_CSIS_DMA_INT_CTX2_FIFO_FULL>, + <CSI_CSIS_DMA_INT_CTX2_QREQN_P>, + <CSI_CSIS_DMA_INT_CTX2_LASTDATA_ERROR>, + <CSI_CSIS_DMA_INT_CTX2_LASTADDR_ERROR>, + <CSI_CSIS_DMA_INT_CTX2_ABORT_DONE>, + <CSI_CSIS_DMA_INT_CTX2_FSTART_IN_FLUSH_CH0>, + <CSI_CSIS_DMA_INT_CTX2_FSTART_IN_FLUSH_CH1>, + <CSI_CSIS_DMA_INT_CTX2_OVERLAP0>, + <CSI_CSIS_DMA_INT_CTX2_OVERLAP1>, + <CSI_CSIS_DMA_INT_CTX2_OVERLAP2>, + <CSI_CSIS_DMA_INT_CTX2_OVERLAP3>, + <CSI_CSIS_DMA_INT_CTX2_FRAME_DROP0>, + <CSI_CSIS_DMA_INT_CTX2_FRAME_DROP1>, + <CSI_CSIS_DMA_INT_CTX2_FRAME_DROP2>, + <CSI_CSIS_DMA_INT_CTX2_FRAME_DROP3>, + <CSI_CSIS_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH0>, + <CSI_CSIS_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH1>, + <CSI_CSIS_DMA_INT_CTX2_C2COM_SLOW_RING>; + }; + + csi_csis_dma_ctx3_int: csi_csis_dma-event-info@41 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0xa408>; + irq-reset-reg = <0x0 0xa408>; + irq-mask-reg = <0x0 0xa404>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_LINE_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_LINE_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_LINE_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_LINE_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_START0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_START1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_START2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_START3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_END0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_END1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_END2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_END3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FIFO_FULL>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_QREQN_P>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_LASTDATA_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_LASTADDR_ERROR>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_ABORT_DONE>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FSTART_IN_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FSTART_IN_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_OVERLAP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_OVERLAP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_OVERLAP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_OVERLAP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_DROP0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_DROP1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_DROP2>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_DROP3>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_C2COM_LOST_FLUSH_CH0>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_C2COM_LOST_FLUSH_CH1>, + <LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_C2COM_SLOW_RING>; + int-reg-bits = + <CSI_CSIS_DMA_INT_CTX3_LINE_END0>, + <CSI_CSIS_DMA_INT_CTX3_LINE_END1>, + <CSI_CSIS_DMA_INT_CTX3_LINE_END2>, + <CSI_CSIS_DMA_INT_CTX3_LINE_END3>, + <CSI_CSIS_DMA_INT_CTX3_FRAME_START0>, + <CSI_CSIS_DMA_INT_CTX3_FRAME_START1>, + <CSI_CSIS_DMA_INT_CTX3_FRAME_START2>, + <CSI_CSIS_DMA_INT_CTX3_FRAME_START3>, + <CSI_CSIS_DMA_INT_CTX3_FRAME_END0>, + <CSI_CSIS_DMA_INT_CTX3_FRAME_END1>, + <CSI_CSIS_DMA_INT_CTX3_FRAME_END2>, + <CSI_CSIS_DMA_INT_CTX3_FRAME_END3>, + <CSI_CSIS_DMA_INT_CTX3_FIFO_FULL>, + <CSI_CSIS_DMA_INT_CTX3_QREQN_P>, + <CSI_CSIS_DMA_INT_CTX3_LASTDATA_ERROR>, + <CSI_CSIS_DMA_INT_CTX3_LASTADDR_ERROR>, + <CSI_CSIS_DMA_INT_CTX3_ABORT_DONE>, + <CSI_CSIS_DMA_INT_CTX3_FSTART_IN_FLUSH_CH0>, + <CSI_CSIS_DMA_INT_CTX3_FSTART_IN_FLUSH_CH1>, + <CSI_CSIS_DMA_INT_CTX3_OVERLAP0>, + <CSI_CSIS_DMA_INT_CTX3_OVERLAP1>, + <CSI_CSIS_DMA_INT_CTX3_OVERLAP2>, + <CSI_CSIS_DMA_INT_CTX3_OVERLAP3>, + <CSI_CSIS_DMA_INT_CTX3_FRAME_DROP0>, + <CSI_CSIS_DMA_INT_CTX3_FRAME_DROP1>, + <CSI_CSIS_DMA_INT_CTX3_FRAME_DROP2>, + <CSI_CSIS_DMA_INT_CTX3_FRAME_DROP3>, + <CSI_CSIS_DMA_INT_CTX3_C2COM_LOST_FLUSH_CH0>, + <CSI_CSIS_DMA_INT_CTX3_C2COM_LOST_FLUSH_CH1>, + <CSI_CSIS_DMA_INT_CTX3_C2COM_SLOW_RING>; + }; + + csi_ebuf0_int: csi_ebuf-event-info@42 { + irq-reg-space = "csis-ebuf"; + irq-src-reg = <0x0 0xd0>; + irq-reset-reg = <0x0 0xd8>; + irq-mask-reg = <0x0 0xd4>; + + critical-irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF0_FULL>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF0_FULL>, + <LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF0_FAKE_FRAME_DONE>; + int-reg-bits = + <CSI_EBUF_INT_EBUF0_FULL>, + <CSI_EBUF_INT_EBUF0_FAKE_FRAME_DONE>; + }; + + csi_ebuf1_int: csi_ebuf-event-info@43 { + irq-reg-space = "csis-ebuf"; + irq-src-reg = <0x0 0xd0>; + irq-reset-reg = <0x0 0xd8>; + irq-mask-reg = <0x0 0xd4>; + + critical-irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF1_FULL>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF1_FULL>, + <LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF1_FAKE_FRAME_DONE>; + int-reg-bits = + <CSI_EBUF_INT_EBUF1_FULL>, + <CSI_EBUF_INT_EBUF1_FAKE_FRAME_DONE>; + }; + + csi_ebuf2_int: csi_ebuf-event-info@44 { + irq-reg-space = "csis-ebuf"; + irq-src-reg = <0x0 0xd0>; + irq-reset-reg = <0x0 0xd8>; + irq-mask-reg = <0x0 0xd4>; + + critical-irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF2_FULL>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF2_FULL>, + <LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF2_FAKE_FRAME_DONE>; + int-reg-bits = + <CSI_EBUF_INT_EBUF2_FULL>, + <CSI_EBUF_INT_EBUF2_FAKE_FRAME_DONE>; + }; + + csi_ebuf3_int: csi_ebuf-event-info@45 { + irq-reg-space = "csis-ebuf"; + irq-src-reg = <0x0 0xd0>; + irq-reset-reg = <0x0 0xd8>; + irq-mask-reg = <0x0 0xd4>; + + critical-irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF3_FULL>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF3_FULL>, + <LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF3_FAKE_FRAME_DONE>; + int-reg-bits = + <CSI_EBUF_INT_EBUF3_FULL>, + <CSI_EBUF_INT_EBUF3_FAKE_FRAME_DONE>; + }; + + /* + * G3AA Interrupt Event Definitions + */ + + g3aa_ctx0_interrupts: g3aa-event-info@0 { + irq-reg-space = "g3aa"; + irq-src-reg = <0x0 0x5c>; + irq-reset-reg = <0x0 0x60>; + irq-mask-reg = <0x0 0x58>; + irq-reg-bitwidth = <16>; + irq-events = + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_START_OF_FRAME>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_END_OF_FRAME>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_CDAF_PRIMARY>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_CDAF_WINDOWS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_AE_STATS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_AWB_STATS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_LSC_STATS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_FLICKER_STATS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_HISTOGRAM0>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_HISTOGRAM1>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_HISTOGRAM2>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_UAE_STATS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_MOTION_METERING>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_PDAF_START_OF_FRAME>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_PDAF_EARLY>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_PDAF_END_OF_FRAME>; + int-reg-bits = + <G3AA_INTERRUPTS_CTX0_BAYER_START_OF_FRAME>, + <G3AA_INTERRUPTS_CTX0_BAYER_END_OF_FRAME>, + <G3AA_INTERRUPTS_CTX0_BAYER_CDAF_PRIMARY>, + <G3AA_INTERRUPTS_CTX0_BAYER_CDAF_WINDOWS>, + <G3AA_INTERRUPTS_CTX0_BAYER_AE_STATS>, + <G3AA_INTERRUPTS_CTX0_BAYER_AWB_STATS>, + <G3AA_INTERRUPTS_CTX0_BAYER_LSC_STATS>, + <G3AA_INTERRUPTS_CTX0_BAYER_FLICKER_STATS>, + <G3AA_INTERRUPTS_CTX0_BAYER_HISTOGRAM0>, + <G3AA_INTERRUPTS_CTX0_BAYER_HISTOGRAM1>, + <G3AA_INTERRUPTS_CTX0_BAYER_HISTOGRAM2>, + <G3AA_INTERRUPTS_CTX0_BAYER_UAE_STATS>, + <G3AA_INTERRUPTS_CTX0_BAYER_MOTION_METERING>, + <G3AA_INTERRUPTS_CTX0_PDAF_START_OF_FRAME>, + <G3AA_INTERRUPTS_CTX0_PDAF_EARLY>, + <G3AA_INTERRUPTS_CTX0_PDAF_END_OF_FRAME>; + }; + + g3aa_ctx1_interrupts: g3aa-event-info@1 { + irq-reg-space = "g3aa"; + irq-src-reg = <0x0 0x6c>; + irq-reset-reg = <0x0 0x70>; + irq-mask-reg = <0x0 0x68>; + irq-reg-bitwidth = <16>; + irq-events = + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_START_OF_FRAME>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_END_OF_FRAME>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_CDAF_PRIMARY>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_CDAF_WINDOWS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_AE_STATS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_AWB_STATS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_LSC_STATS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_FLICKER_STATS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_HISTOGRAM0>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_HISTOGRAM1>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_HISTOGRAM2>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_UAE_STATS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_MOTION_METERING>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_PDAF_START_OF_FRAME>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_PDAF_EARLY>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_PDAF_END_OF_FRAME>; + int-reg-bits = + <G3AA_INTERRUPTS_CTX1_BAYER_START_OF_FRAME>, + <G3AA_INTERRUPTS_CTX1_BAYER_END_OF_FRAME>, + <G3AA_INTERRUPTS_CTX1_BAYER_CDAF_PRIMARY>, + <G3AA_INTERRUPTS_CTX1_BAYER_CDAF_WINDOWS>, + <G3AA_INTERRUPTS_CTX1_BAYER_AE_STATS>, + <G3AA_INTERRUPTS_CTX1_BAYER_AWB_STATS>, + <G3AA_INTERRUPTS_CTX1_BAYER_LSC_STATS>, + <G3AA_INTERRUPTS_CTX1_BAYER_FLICKER_STATS>, + <G3AA_INTERRUPTS_CTX1_BAYER_HISTOGRAM0>, + <G3AA_INTERRUPTS_CTX1_BAYER_HISTOGRAM1>, + <G3AA_INTERRUPTS_CTX1_BAYER_HISTOGRAM2>, + <G3AA_INTERRUPTS_CTX1_BAYER_UAE_STATS>, + <G3AA_INTERRUPTS_CTX1_BAYER_MOTION_METERING>, + <G3AA_INTERRUPTS_CTX1_PDAF_START_OF_FRAME>, + <G3AA_INTERRUPTS_CTX1_PDAF_EARLY>, + <G3AA_INTERRUPTS_CTX1_PDAF_END_OF_FRAME>; + }; + + g3aa_ctx2_interrupts: g3aa-event-info@2 { + irq-reg-space = "g3aa"; + irq-src-reg = <0x0 0x7c>; + irq-reset-reg = <0x0 0x80>; + irq-mask-reg = <0x0 0x78>; + irq-reg-bitwidth = <16>; + irq-events = + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_START_OF_FRAME>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_END_OF_FRAME>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_CDAF_PRIMARY>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_CDAF_WINDOWS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_AE_STATS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_AWB_STATS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_LSC_STATS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_FLICKER_STATS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_HISTOGRAM0>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_HISTOGRAM1>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_HISTOGRAM2>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_UAE_STATS>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_MOTION_METERING>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_PDAF_START_OF_FRAME>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_PDAF_EARLY>, + <LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_PDAF_END_OF_FRAME>; + int-reg-bits = + <G3AA_INTERRUPTS_CTX2_BAYER_START_OF_FRAME>, + <G3AA_INTERRUPTS_CTX2_BAYER_END_OF_FRAME>, + <G3AA_INTERRUPTS_CTX2_BAYER_CDAF_PRIMARY>, + <G3AA_INTERRUPTS_CTX2_BAYER_CDAF_WINDOWS>, + <G3AA_INTERRUPTS_CTX2_BAYER_AE_STATS>, + <G3AA_INTERRUPTS_CTX2_BAYER_AWB_STATS>, + <G3AA_INTERRUPTS_CTX2_BAYER_LSC_STATS>, + <G3AA_INTERRUPTS_CTX2_BAYER_FLICKER_STATS>, + <G3AA_INTERRUPTS_CTX2_BAYER_HISTOGRAM0>, + <G3AA_INTERRUPTS_CTX2_BAYER_HISTOGRAM1>, + <G3AA_INTERRUPTS_CTX2_BAYER_HISTOGRAM2>, + <G3AA_INTERRUPTS_CTX2_BAYER_UAE_STATS>, + <G3AA_INTERRUPTS_CTX2_BAYER_MOTION_METERING>, + <G3AA_INTERRUPTS_CTX2_PDAF_START_OF_FRAME>, + <G3AA_INTERRUPTS_CTX2_PDAF_EARLY>, + <G3AA_INTERRUPTS_CTX2_PDAF_END_OF_FRAME>; + }; + + g3aa_error_interrupts: g3aa-event-info@3 { + irq-reg-space = "g3aa"; + irq-src-reg = <0x0 0x5e>; + irq-reset-reg = <0x0 0x62>; + irq-mask-reg = <0x0 0x5a>; + irq-reg-bitwidth = <16>; + irq-events = + <LWIS_PLATFORM_EVENT_ID_G3AA_HW_TIMEOUT>, + <LWIS_PLATFORM_EVENT_ID_G3AA_BUS_ERROR>, + <LWIS_PLATFORM_EVENT_ID_G3AA_AXI_READ_DATA_OVERFLOW>, + <LWIS_PLATFORM_EVENT_ID_G3AA_AXI_WRITE_DATA_OVERFLOW>; + int-reg-bits = + <G3AA_ERROR_INTERRUPTS_HW_TIMEOUT>, + <G3AA_ERROR_INTERRUPTS_BUS_ERROR>, + <G3AA_ERROR_INTERRUPTS_AXI_READ_DATA_OVERFLOW>, + <G3AA_ERROR_INTERRUPTS_AXI_WRITE_DATA_OVERFLOW>; + }; + + /* + * GDC Interrupt Event Definitions + */ + gdc_int0: gdc-event-info@0 { + irq-reg-space = "gdc"; + irq-src-reg = <0x0 0x808>; + irq-reset-reg = <0x0 0x80c>; + irq-mask-reg = <0x0 0x804>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_GDC_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_GDC_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_GDC_CMDQ_HOLD>, + <LWIS_PLATFORM_EVENT_ID_GDC_SETTING_DONE>, + <LWIS_PLATFORM_EVENT_ID_GDC_C_LOADER_END>, + <LWIS_PLATFORM_EVENT_ID_GDC_COREX_END0>, + <LWIS_PLATFORM_EVENT_ID_GDC_COREX_END1>, + <LWIS_PLATFORM_EVENT_ID_GDC_ROW_COL>, + <LWIS_PLATFORM_EVENT_ID_GDC_FREEZE_ON_ROW_COL>, + <LWIS_PLATFORM_EVENT_ID_GDC_TRANS_STOP_DONE>, + <LWIS_PLATFORM_EVENT_ID_GDC_CMDQ_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_C_LOADER_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_COREX_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_CINFIFO0_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_CINFIFO0_OVERLAP_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_CINFIFO0_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_CINFIFO0_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_CINFIFO1_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_CINFIFO1_OVERLAP_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_CINFIFO1_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_CINFIFO1_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_COUTFIFO0_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_COUTFIFO0_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_COUTFIFO0_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_COUTFIFO1_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_COUTFIFO1_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_COUTFIFO1_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_VOTF_GLOBAL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GDC_VOTF_LOST_CONNECTION>, + <LWIS_PLATFORM_EVENT_ID_GDC_OTF_SEQ_ID_ERROR>; + int-reg-bits = + <GDC_INT0_FRAME_START>, + <GDC_INT0_FRAME_END>, + <GDC_INT0_CMDQ_HOLD>, + <GDC_INT0_SETTING_DONE>, + <GDC_INT0_C_LOADER_END>, + <GDC_INT0_COREX_END0>, + <GDC_INT0_COREX_END1>, + <GDC_INT0_ROW_COL>, + <GDC_INT0_FREEZE_ON_ROW_COL>, + <GDC_INT0_TRANS_STOP_DONE>, + <GDC_INT0_CMDQ_ERROR>, + <GDC_INT0_C_LOADER_ERROR>, + <GDC_INT0_COREX_ERROR>, + <GDC_INT0_CINFIFO0_OVERFLOW_ERROR>, + <GDC_INT0_CINFIFO0_OVERLAP_ERROR>, + <GDC_INT0_CINFIFO0_PIXEL_CNT_ERROR>, + <GDC_INT0_CINFIFO0_INPUT_PROTOCOL_ERROR>, + <GDC_INT0_CINFIFO1_OVERFLOW_ERROR>, + <GDC_INT0_CINFIFO1_OVERLAP_ERROR>, + <GDC_INT0_CINFIFO1_PIXEL_CNT_ERROR>, + <GDC_INT0_CINFIFO1_INPUT_PROTOCOL_ERROR>, + <GDC_INT0_COUTFIFO0_PIXEL_CNT_ERROR>, + <GDC_INT0_COUTFIFO0_INPUT_PROTOCOL_ERROR>, + <GDC_INT0_COUTFIFO0_OVERFLOW_ERROR>, + <GDC_INT0_COUTFIFO1_PIXEL_CNT_ERROR>, + <GDC_INT0_COUTFIFO1_INPUT_PROTOCOL_ERROR>, + <GDC_INT0_COUTFIFO1_OVERFLOW_ERROR>, + <GDC_INT0_VOTF_GLOBAL_ERROR>, + <GDC_INT0_VOTF_LOST_CONNECTION>, + <GDC_INT0_OTF_SEQ_ID_ERROR>; + }; + + gdc_int1: gdc-event-info@1 { + irq-reg-space = "gdc"; + irq-src-reg = <0x0 0x818>; + irq-reset-reg = <0x0 0x81c>; + irq-mask-reg = <0x0 0x814>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_GDC_VOTF_LOST_FLUSH>, + <LWIS_PLATFORM_EVENT_ID_GDC_COMP_ERR>; + int-reg-bits = + <GDC_INT1_VOTF_LOST_FLUSH>, + <GDC_INT1_COMP_ERR>; + }; + + gdc_cmdq_int: gdc-event-info@2 { + irq-reg-space = "gdc"; + irq-src-reg = <0x0 0x4f8>; + irq-reset-reg = <0x0 0x4fc>; + irq-mask-reg = <0x0 0x4f4>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_GDC_STOP_CRPT_OFF_CMDQ_EN>, + <LWIS_PLATFORM_EVENT_ID_GDC_PRELOAD_FLUSH>, + <LWIS_PLATFORM_EVENT_ID_GDC_QUE0_OVERFLOW>; + int-reg-bits = + <GDC_CMDQ_INT_STOP_CRPT_OFF_CMDQ_EN>, + <GDC_CMDQ_INT_PRELOAD_FLUSH>, + <GDC_CMDQ_INT_QUE0_OVERFLOW>; + }; + + /* + * GTNR-ALIGN Interrupt Event Definitions + */ + gtnr_align_int: gtnr_align-event-info@0 { + irq-reg-space = "tnr_align"; + irq-src-reg = <0x0 0x40>; + irq-reset-reg = <0x0 0x40>; + irq-mask-reg = <0x0 0x44>; + irq-mask-reg-toggle; + irq-events = + <LWIS_PLATFORM_EVENT_ID_GTNR_ALIGN_MSA_FRAME_DONE>, + <LWIS_PLATFORM_EVENT_ID_GTNR_ALIGN_NM_FRAME_DONE>, + <LWIS_PLATFORM_EVENT_ID_GTNR_ALIGN_FRO_DONE>; + int-reg-bits = + <GTNR_ALIGN_INT_MSA_FRAME_DONE>, + <GTNR_ALIGN_INT_NM_FRAME_DONE>, + <GTNR_ALIGN_INT_FRO_DONE>; + }; + + gtnr_align_secu_int_mute: gtnr_align-event-info@1 { + irq-reg-space = "tnr_align"; + irq-src-reg = <0x0 0xc0>; + irq-reset-reg = <0x0 0xc8>; + irq-mask-reg = <0x0 0xc4>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_GTNR_ALIGN_MUTE>, + <LWIS_PLATFORM_EVENT_ID_GTNR_ALIGN_UNMUTE>; + int-reg-bits = + <GTNR_ALIGN_SECU_INT_MUTE_MUTE>, + <GTNR_ALIGN_SECU_INT_MUTE_UNMUTE>; + }; + + /* + * GTNR-MERGE Interrupt Event Definitions + */ + gtnr_merge_int0: gtnr_merge-event-info@0 { + irq-reg-space = "tnr"; + irq-src-reg = <0x0 0x808>; + irq-reset-reg = <0x0 0x80c>; + irq-mask-reg = <0x0 0x804>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CMDQ_HOLD>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_SETTING_DONE>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_C_LOADER_END_INT>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COREX_END0>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COREX_END1>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_ROW_COL>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_FREEZE_ON_ROW_COL>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_TRANS_STOP_DONE>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CMDQ_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_C_CLOADER_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COREX_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CINFIFO0_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CINFIFO0_OVERLAP_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CINFIFO0_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CINFIFO0_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CINFIFO1_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CINFIFO1_OVERLAP_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CINFIFO1_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CINFIFO1_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COUTFIFO0_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COUTFIFO0_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COUTFIFO0_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COUTFIFO1_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COUTFIFO1_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COUTFIFO1_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_VOTF_SLOW_RING>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_VOTF_LOST_CONNECTION>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_OTF_SEQ_ID_ERROR>; + int-reg-bits = + <GTNR_MERGE_INT0_FRAME_START>, + <GTNR_MERGE_INT0_FRAME_END>, + <GTNR_MERGE_INT0_CMDQ_HOLD>, + <GTNR_MERGE_INT0_SETTING_DONE>, + <GTNR_MERGE_INT0_C_LOADER_END_INT>, + <GTNR_MERGE_INT0_COREX_END0>, + <GTNR_MERGE_INT0_COREX_END1>, + <GTNR_MERGE_INT0_ROW_COL>, + <GTNR_MERGE_INT0_FREEZE_ON_ROW_COL>, + <GTNR_MERGE_INT0_TRANS_STOP_DONE>, + <GTNR_MERGE_INT0_CMDQ_ERROR>, + <GTNR_MERGE_INT0_C_CLOADER_ERROR>, + <GTNR_MERGE_INT0_COREX_ERROR>, + <GTNR_MERGE_INT0_CINFIFO0_OVERFLOW_ERROR>, + <GTNR_MERGE_INT0_CINFIFO0_OVERLAP_ERROR>, + <GTNR_MERGE_INT0_CINFIFO0_PIXEL_CNT_ERROR>, + <GTNR_MERGE_INT0_CINFIFO0_INPUT_PROTOCOL_ERROR>, + <GTNR_MERGE_INT0_CINFIFO1_OVERFLOW_ERROR>, + <GTNR_MERGE_INT0_CINFIFO1_OVERLAP_ERROR>, + <GTNR_MERGE_INT0_CINFIFO1_PIXEL_CNT_ERROR>, + <GTNR_MERGE_INT0_CINFIFO1_INPUT_PROTOCOL_ERROR>, + <GTNR_MERGE_INT0_COUTFIFO0_PIXEL_CNT_ERROR>, + <GTNR_MERGE_INT0_COUTFIFO0_INPUT_PROTOCOL_ERROR>, + <GTNR_MERGE_INT0_COUTFIFO0_OVERFLOW_ERROR>, + <GTNR_MERGE_INT0_COUTFIFO1_PIXEL_CNT_ERROR>, + <GTNR_MERGE_INT0_COUTFIFO1_INPUT_PROTOCOL_ERROR>, + <GTNR_MERGE_INT0_COUTFIFO1_OVERFLOW_ERROR>, + <GTNR_MERGE_INT0_VOTF_SLOW_RING>, + <GTNR_MERGE_INT0_VOTF_LOST_CONNECTION>, + <GTNR_MERGE_INT0_OTF_SEQ_ID_ERROR>; + }; + + gtnr_merge_int1: gtnr_merge-event-info@1 { + irq-reg-space = "tnr"; + irq-src-reg = <0x0 0x818>; + irq-reset-reg = <0x0 0x81c>; + irq-mask-reg = <0x0 0x814>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_VOTF_LOST_FLUSH>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_SBWC_ERR_CUR0>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_SBWC_ERR_CUR1>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_SBWC_ERR_PRE0>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_SBWC_ERR_PRE1>; + int-reg-bits = + <GTNR_MERGE_INT1_VOTF_LOST_FLUSH>, + <GTNR_MERGE_INT1_SBWC_ERR_CUR0>, + <GTNR_MERGE_INT1_SBWC_ERR_CUR1>, + <GTNR_MERGE_INT1_SBWC_ERR_PRE0>, + <GTNR_MERGE_INT1_SBWC_ERR_PRE1>; + }; + gtnr_merge_cmdq_int: gtnr_merge-event-info@2 { + irq-reg-space = "tnr"; + irq-src-reg = <0x0 0x4f8>; + irq-reset-reg = <0x0 0x4fc>; + irq-mask-reg = <0x0 0x4f4>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_STOP_CRPT_OFF_CMDQ_EN>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_PRELOAD_FLUSH>, + <LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_QUE0_OVERFLOW>; + int-reg-bits = + <GTNR_MERGE_CMDQ_INT_STOP_CRPT_OFF_CMDQ_EN>, + <GTNR_MERGE_CMDQ_INT_PRELOAD_FLUSH>, + <GTNR_MERGE_CMDQ_INT_QUE0_OVERFLOW>; +}; + + + /* + * IPP Interrupt Event Definitions + */ + + ipp_ctx0_int1: ipp-event-info@0 { + irq-reg-space = "ipp0"; + irq-src-reg = <0x0 0x20c>; + irq-reset-reg = <0x0 0x210>; + irq-mask-reg = <0x0 0x208>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_FRAME_INT_ON_ROW_COL_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_IRQ_CORRUPTED>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COREX_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_P_SLVERR>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_PRE_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COUTFIFO_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COUTFIFO_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_STRP_OUT_DMA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_BDS_DATA_OUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_ZSL_OUT_DMA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_BCROP1_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_BCROP0_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_RGBY_HIST2_DMA_DONE>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_RGBYHIST_DATA_OUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_THSTAT_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_GP_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CINFIFO_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CINFIFO_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COREX_END_INT0>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COREX_END_INT1>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COUTFIFO_SIZE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COUTFIFO_LINE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COUTFIFO_COL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COUTFIFO_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CINFIFO_LINES_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CINFIFO_COLUMNS_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CINFIFO_STREAM_OVERFLOW_SIG>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_FRAME_START_BEFORE_FRAME_END_CORRUPTED>; + int-reg-bits = + <IPP_INT1_CTX0_FRAME_START>, + <IPP_INT1_CTX0_FRAME_END_INTERRUPT>, + <IPP_INT1_CTX0_FRAME_INT_ON_ROW_COL_INFO>, + <IPP_INT1_CTX0_IRQ_CORRUPTED>, + <IPP_INT1_CTX0_COREX_ERROR_INT>, + <IPP_INT1_CTX0_P_SLVERR>, + <IPP_INT1_CTX0_PRE_FRAME_END_INTERRUPT>, + <IPP_INT1_CTX0_COUTFIFO_DATA_OUT_END_INT>, + <IPP_INT1_CTX0_COUTFIFO_FRAME_OUT_END_INT>, + <IPP_INT1_CTX0_STRP_OUT_DMA_IN_LAST>, + <IPP_INT1_CTX0_BDS_DATA_OUT_LAST>, + <IPP_INT1_CTX0_ZSL_OUT_DMA_IN_LAST>, + <IPP_INT1_CTX0_BCROP1_DATA_IN_LAST>, + <IPP_INT1_CTX0_BCROP0_DATA_IN_LAST>, + <IPP_INT1_CTX0_RGBY_HIST2_DMA_DONE>, + <IPP_INT1_CTX0_RGBYHIST_DATA_OUT_LAST>, + <IPP_INT1_CTX0_THSTAT_DATA_IN_LAST>, + <IPP_INT1_CTX0_GP_DATA_IN_LAST>, + <IPP_INT1_CTX0_CINFIFO_DATA_OUT_END_INT>, + <IPP_INT1_CTX0_CINFIFO_FRAME_OUT_END_INT>, + <IPP_INT1_CTX0_COREX_END_INT0>, + <IPP_INT1_CTX0_COREX_END_INT1>, + <IPP_INT1_CTX0_COUTFIFO_SIZE_ERROR>, + <IPP_INT1_CTX0_COUTFIFO_LINE_ERROR>, + <IPP_INT1_CTX0_COUTFIFO_COL_ERROR>, + <IPP_INT1_CTX0_COUTFIFO_OVERFLOW_ERROR>, + <IPP_INT1_CTX0_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <IPP_INT1_CTX0_CINFIFO_LINES_ERROR_INT>, + <IPP_INT1_CTX0_CINFIFO_COLUMNS_ERROR_INT>, + <IPP_INT1_CTX0_CINFIFO_STREAM_OVERFLOW_SIG>, + <IPP_INT1_CTX0_FRAME_START_BEFORE_FRAME_END_CORRUPTED>; + }; + + ipp_ctx1_int1: ipp-event-info@1 { + irq-reg-space = "ipp1"; + irq-src-reg = <0x0 0x20c>; + irq-reset-reg = <0x0 0x210>; + irq-mask-reg = <0x0 0x208>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_FRAME_INT_ON_ROW_COL_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_IRQ_CORRUPTED>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COREX_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_P_SLVERR>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_PRE_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COUTFIFO_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COUTFIFO_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_STRP_OUT_DMA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_BDS_DATA_OUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_ZSL_OUT_DMA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_BCROP1_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_BCROP0_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_RGBY_HIST2_DMA_DONE>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_RGBYHIST_DATA_OUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_THSTAT_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_GP_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CINFIFO_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CINFIFO_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COREX_END_INT0>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COREX_END_INT1>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COUTFIFO_SIZE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COUTFIFO_LINE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COUTFIFO_COL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COUTFIFO_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CINFIFO_LINES_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CINFIFO_COLUMNS_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CINFIFO_STREAM_OVERFLOW_SIG>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_FRAME_START_BEFORE_FRAME_END_CORRUPTED>; + int-reg-bits = + <IPP_INT1_CTX1_FRAME_START>, + <IPP_INT1_CTX1_FRAME_END_INTERRUPT>, + <IPP_INT1_CTX1_FRAME_INT_ON_ROW_COL_INFO>, + <IPP_INT1_CTX1_IRQ_CORRUPTED>, + <IPP_INT1_CTX1_COREX_ERROR_INT>, + <IPP_INT1_CTX1_P_SLVERR>, + <IPP_INT1_CTX1_PRE_FRAME_END_INTERRUPT>, + <IPP_INT1_CTX1_COUTFIFO_DATA_OUT_END_INT>, + <IPP_INT1_CTX1_COUTFIFO_FRAME_OUT_END_INT>, + <IPP_INT1_CTX1_STRP_OUT_DMA_IN_LAST>, + <IPP_INT1_CTX1_BDS_DATA_OUT_LAST>, + <IPP_INT1_CTX1_ZSL_OUT_DMA_IN_LAST>, + <IPP_INT1_CTX1_BCROP1_DATA_IN_LAST>, + <IPP_INT1_CTX1_BCROP0_DATA_IN_LAST>, + <IPP_INT1_CTX1_RGBY_HIST2_DMA_DONE>, + <IPP_INT1_CTX1_RGBYHIST_DATA_OUT_LAST>, + <IPP_INT1_CTX1_THSTAT_DATA_IN_LAST>, + <IPP_INT1_CTX1_GP_DATA_IN_LAST>, + <IPP_INT1_CTX1_CINFIFO_DATA_OUT_END_INT>, + <IPP_INT1_CTX1_CINFIFO_FRAME_OUT_END_INT>, + <IPP_INT1_CTX1_COREX_END_INT0>, + <IPP_INT1_CTX1_COREX_END_INT1>, + <IPP_INT1_CTX1_COUTFIFO_SIZE_ERROR>, + <IPP_INT1_CTX1_COUTFIFO_LINE_ERROR>, + <IPP_INT1_CTX1_COUTFIFO_COL_ERROR>, + <IPP_INT1_CTX1_COUTFIFO_OVERFLOW_ERROR>, + <IPP_INT1_CTX1_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <IPP_INT1_CTX1_CINFIFO_LINES_ERROR_INT>, + <IPP_INT1_CTX1_CINFIFO_COLUMNS_ERROR_INT>, + <IPP_INT1_CTX1_CINFIFO_STREAM_OVERFLOW_SIG>, + <IPP_INT1_CTX1_FRAME_START_BEFORE_FRAME_END_CORRUPTED>; + }; + + ipp_ctx2_int1: ipp-event-info@2 { + irq-reg-space = "ipp2"; + irq-src-reg = <0x0 0x20c>; + irq-reset-reg = <0x0 0x210>; + irq-mask-reg = <0x0 0x208>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_FRAME_INT_ON_ROW_COL_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_IRQ_CORRUPTED>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COREX_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_P_SLVERR>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_PRE_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COUTFIFO_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COUTFIFO_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_STRP_OUT_DMA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_BDS_DATA_OUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_ZSL_OUT_DMA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_BCROP1_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_BCROP0_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_RGBY_HIST2_DMA_DONE>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_RGBYHIST_DATA_OUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_THSTAT_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_GP_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CINFIFO_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CINFIFO_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COREX_END_INT0>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COREX_END_INT1>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COUTFIFO_SIZE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COUTFIFO_LINE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COUTFIFO_COL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COUTFIFO_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CINFIFO_LINES_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CINFIFO_COLUMNS_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CINFIFO_STREAM_OVERFLOW_SIG>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_FRAME_START_BEFORE_FRAME_END_CORRUPTED>; + int-reg-bits = + <IPP_INT1_CTX2_FRAME_START>, + <IPP_INT1_CTX2_FRAME_END_INTERRUPT>, + <IPP_INT1_CTX2_FRAME_INT_ON_ROW_COL_INFO>, + <IPP_INT1_CTX2_IRQ_CORRUPTED>, + <IPP_INT1_CTX2_COREX_ERROR_INT>, + <IPP_INT1_CTX2_P_SLVERR>, + <IPP_INT1_CTX2_PRE_FRAME_END_INTERRUPT>, + <IPP_INT1_CTX2_COUTFIFO_DATA_OUT_END_INT>, + <IPP_INT1_CTX2_COUTFIFO_FRAME_OUT_END_INT>, + <IPP_INT1_CTX2_STRP_OUT_DMA_IN_LAST>, + <IPP_INT1_CTX2_BDS_DATA_OUT_LAST>, + <IPP_INT1_CTX2_ZSL_OUT_DMA_IN_LAST>, + <IPP_INT1_CTX2_BCROP1_DATA_IN_LAST>, + <IPP_INT1_CTX2_BCROP0_DATA_IN_LAST>, + <IPP_INT1_CTX2_RGBY_HIST2_DMA_DONE>, + <IPP_INT1_CTX2_RGBYHIST_DATA_OUT_LAST>, + <IPP_INT1_CTX2_THSTAT_DATA_IN_LAST>, + <IPP_INT1_CTX2_GP_DATA_IN_LAST>, + <IPP_INT1_CTX2_CINFIFO_DATA_OUT_END_INT>, + <IPP_INT1_CTX2_CINFIFO_FRAME_OUT_END_INT>, + <IPP_INT1_CTX2_COREX_END_INT0>, + <IPP_INT1_CTX2_COREX_END_INT1>, + <IPP_INT1_CTX2_COUTFIFO_SIZE_ERROR>, + <IPP_INT1_CTX2_COUTFIFO_LINE_ERROR>, + <IPP_INT1_CTX2_COUTFIFO_COL_ERROR>, + <IPP_INT1_CTX2_COUTFIFO_OVERFLOW_ERROR>, + <IPP_INT1_CTX2_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <IPP_INT1_CTX2_CINFIFO_LINES_ERROR_INT>, + <IPP_INT1_CTX2_CINFIFO_COLUMNS_ERROR_INT>, + <IPP_INT1_CTX2_CINFIFO_STREAM_OVERFLOW_SIG>, + <IPP_INT1_CTX2_FRAME_START_BEFORE_FRAME_END_CORRUPTED>; + }; + + ipp_ctx0_int2: ipp-event-info@3 { + irq-reg-space = "ipp0"; + irq-src-reg = <0x0 0x21c>; + irq-reset-reg = <0x0 0x220>; + irq-mask-reg = <0x0 0x218>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CDAF_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COUTFIFO_FRAME_OUT_START_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CINFIFO_FRAME_IN_END_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CINFIFO_FRAME_IN_START_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_THSTAT_STATISTICS_DONE>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_FRO_GROUP2>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_FRO_GROUP4>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX0_FRO_GROUP5>; + int-reg-bits = + <IPP_INT2_CTX0_CDAF_INT>, + <IPP_INT2_CTX0_COUTFIFO_FRAME_OUT_START_INFO>, + <IPP_INT2_CTX0_CINFIFO_FRAME_IN_END_INFO>, + <IPP_INT2_CTX0_CINFIFO_FRAME_IN_START_INFO>, + <IPP_INT2_CTX0_THSTAT_STATISTICS_DONE>, + <IPP_INT2_CTX0_FRO_GROUP2>, + <IPP_INT2_CTX0_FRO_GROUP4>, + <IPP_INT2_CTX0_FRO_GROUP5>; + }; + + ipp_ctx1_int2: ipp-event-info@4 { + irq-reg-space = "ipp1"; + irq-src-reg = <0x0 0x21c>; + irq-reset-reg = <0x0 0x220>; + irq-mask-reg = <0x0 0x218>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CDAF_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COUTFIFO_FRAME_OUT_START_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CINFIFO_FRAME_IN_END_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CINFIFO_FRAME_IN_START_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_THSTAT_STATISTICS_DONE>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_FRO_GROUP2>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_FRO_GROUP4>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX1_FRO_GROUP5>; + int-reg-bits = + <IPP_INT2_CTX1_CDAF_INT>, + <IPP_INT2_CTX1_COUTFIFO_FRAME_OUT_START_INFO>, + <IPP_INT2_CTX1_CINFIFO_FRAME_IN_END_INFO>, + <IPP_INT2_CTX1_CINFIFO_FRAME_IN_START_INFO>, + <IPP_INT2_CTX1_THSTAT_STATISTICS_DONE>, + <IPP_INT2_CTX1_FRO_GROUP2>, + <IPP_INT2_CTX1_FRO_GROUP4>, + <IPP_INT2_CTX1_FRO_GROUP5>; + }; + + ipp_ctx2_int2: ipp-event-info@5 { + irq-reg-space = "ipp2"; + irq-src-reg = <0x0 0x21c>; + irq-reset-reg = <0x0 0x220>; + irq-mask-reg = <0x0 0x218>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CDAF_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COUTFIFO_FRAME_OUT_START_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CINFIFO_FRAME_IN_END_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CINFIFO_FRAME_IN_START_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_THSTAT_STATISTICS_DONE>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_FRO_GROUP2>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_FRO_GROUP4>, + <LWIS_PLATFORM_EVENT_ID_IPP_CTX2_FRO_GROUP5>; + int-reg-bits = + <IPP_INT2_CTX2_CDAF_INT>, + <IPP_INT2_CTX2_COUTFIFO_FRAME_OUT_START_INFO>, + <IPP_INT2_CTX2_CINFIFO_FRAME_IN_END_INFO>, + <IPP_INT2_CTX2_CINFIFO_FRAME_IN_START_INFO>, + <IPP_INT2_CTX2_THSTAT_STATISTICS_DONE>, + <IPP_INT2_CTX2_FRO_GROUP2>, + <IPP_INT2_CTX2_FRO_GROUP4>, + <IPP_INT2_CTX2_FRO_GROUP5>; + }; + + ipp_fro_ctx0_int0: ipp_fro-event-info@6 { + irq-reg-space = "ipp0"; + irq-src-reg = <0x0 0x3dd0>; + irq-reset-reg = <0x0 0x3dc4>; + irq-mask-reg = <0x0 0x208>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_FRAME_INT_ON_ROW_COL_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_IRQ_CORRUPTED>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COREX_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_P_SLVERR>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_PRE_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COUTFIFO_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COUTFIFO_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_STRP_OUT_DMA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_BDS_DATA_OUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_ZSL_OUT_DMA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_BCROP1_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_BCROP0_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_RGBYHIST2DMA_DONE>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_RGBYHIST_DATA_OUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_THSTAT_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_GP_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CINFIFO_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CINFIFO_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COREX_END_INT0>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COREX_END_INT1>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COUTFIFO_SIZE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COUTFIFO_LINE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COUTFIFO_COL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COUTFIFO_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CINFIFO_LINES_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CINFIFO_COLUMNS_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CINFIFO_STREAM_OVERFLOW_SIG>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_FRM_START_BEFORE_END_CORRUPTED>; + int-reg-bits = + <IPP_FRO_INT0_CTX0_FRAME_START>, + <IPP_FRO_INT0_CTX0_FRAME_END_INTERRUPT>, + <IPP_FRO_INT0_CTX0_FRAME_INT_ON_ROW_COL_INFO>, + <IPP_FRO_INT0_CTX0_IRQ_CORRUPTED>, + <IPP_FRO_INT0_CTX0_COREX_ERROR_INT>, + <IPP_FRO_INT0_CTX0_P_SLVERR>, + <IPP_FRO_INT0_CTX0_PRE_FRAME_END_INTERRUPT>, + <IPP_FRO_INT0_CTX0_COUTFIFO_DATA_OUT_END_INT>, + <IPP_FRO_INT0_CTX0_COUTFIFO_FRAME_OUT_END_INT>, + <IPP_FRO_INT0_CTX0_STRP_OUT_DMA_IN_LAST>, + <IPP_FRO_INT0_CTX0_BDS_DATA_OUT_LAST>, + <IPP_FRO_INT0_CTX0_ZSL_OUT_DMA_IN_LAST>, + <IPP_FRO_INT0_CTX0_BCROP1_DATA_IN_LAST>, + <IPP_FRO_INT0_CTX0_BCROP0_DATA_IN_LAST>, + <IPP_FRO_INT0_CTX0_RGBYHIST2DMA_DONE>, + <IPP_FRO_INT0_CTX0_RGBYHIST_DATA_OUT_LAST>, + <IPP_FRO_INT0_CTX0_THSTAT_DATA_IN_LAST>, + <IPP_FRO_INT0_CTX0_GP_DATA_IN_LAST>, + <IPP_FRO_INT0_CTX0_CINFIFO_DATA_OUT_END_INT>, + <IPP_FRO_INT0_CTX0_CINFIFO_FRAME_OUT_END_INT>, + <IPP_FRO_INT0_CTX0_COREX_END_INT0>, + <IPP_FRO_INT0_CTX0_COREX_END_INT1>, + <IPP_FRO_INT0_CTX0_COUTFIFO_SIZE_ERROR>, + <IPP_FRO_INT0_CTX0_COUTFIFO_LINE_ERROR>, + <IPP_FRO_INT0_CTX0_COUTFIFO_COL_ERROR>, + <IPP_FRO_INT0_CTX0_COUTFIFO_OVERFLOW_ERROR>, + <IPP_FRO_INT0_CTX0_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <IPP_FRO_INT0_CTX0_CINFIFO_LINES_ERROR_INT>, + <IPP_FRO_INT0_CTX0_CINFIFO_COLUMNS_ERROR_INT>, + <IPP_FRO_INT0_CTX0_CINFIFO_STREAM_OVERFLOW_SIG>, + <IPP_FRO_INT0_CTX0_FRAME_START_BEFORE_FRAME_END_CORRUPTED>; + }; + + ipp_fro_ctx1_int0: ipp_fro-event-info@7 { + irq-reg-space = "ipp1"; + irq-src-reg = <0x0 0x3dd0>; + irq-reset-reg = <0x0 0x3dc4>; + irq-mask-reg = <0x0 0x208>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_FRAME_INT_ON_ROW_COL_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_IRQ_CORRUPTED>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COREX_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_P_SLVERR>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_PRE_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COUTFIFO_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COUTFIFO_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_STRP_OUT_DMA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_BDS_DATA_OUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_ZSL_OUT_DMA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_BCROP1_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_BCROP0_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_RGBYHIST2DMA_DONE>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_RGBYHIST_DATA_OUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_THSTAT_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_GP_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CINFIFO_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CINFIFO_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COREX_END_INT0>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COREX_END_INT1>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COUTFIFO_SIZE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COUTFIFO_LINE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COUTFIFO_COL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COUTFIFO_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CINFIFO_LINES_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CINFIFO_COLUMNS_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CINFIFO_STREAM_OVERFLOW_SIG>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_FRM_START_BEFORE_END_CORRUPTED>; + int-reg-bits = + <IPP_FRO_INT0_CTX1_FRAME_START>, + <IPP_FRO_INT0_CTX1_FRAME_END_INTERRUPT>, + <IPP_FRO_INT0_CTX1_FRAME_INT_ON_ROW_COL_INFO>, + <IPP_FRO_INT0_CTX1_IRQ_CORRUPTED>, + <IPP_FRO_INT0_CTX1_COREX_ERROR_INT>, + <IPP_FRO_INT0_CTX1_P_SLVERR>, + <IPP_FRO_INT0_CTX1_PRE_FRAME_END_INTERRUPT>, + <IPP_FRO_INT0_CTX1_COUTFIFO_DATA_OUT_END_INT>, + <IPP_FRO_INT0_CTX1_COUTFIFO_FRAME_OUT_END_INT>, + <IPP_FRO_INT0_CTX1_STRP_OUT_DMA_IN_LAST>, + <IPP_FRO_INT0_CTX1_BDS_DATA_OUT_LAST>, + <IPP_FRO_INT0_CTX1_ZSL_OUT_DMA_IN_LAST>, + <IPP_FRO_INT0_CTX1_BCROP1_DATA_IN_LAST>, + <IPP_FRO_INT0_CTX1_BCROP0_DATA_IN_LAST>, + <IPP_FRO_INT0_CTX1_RGBYHIST2DMA_DONE>, + <IPP_FRO_INT0_CTX1_RGBYHIST_DATA_OUT_LAST>, + <IPP_FRO_INT0_CTX1_THSTAT_DATA_IN_LAST>, + <IPP_FRO_INT0_CTX1_GP_DATA_IN_LAST>, + <IPP_FRO_INT0_CTX1_CINFIFO_DATA_OUT_END_INT>, + <IPP_FRO_INT0_CTX1_CINFIFO_FRAME_OUT_END_INT>, + <IPP_FRO_INT0_CTX1_COREX_END_INT0>, + <IPP_FRO_INT0_CTX1_COREX_END_INT1>, + <IPP_FRO_INT0_CTX1_COUTFIFO_SIZE_ERROR>, + <IPP_FRO_INT0_CTX1_COUTFIFO_LINE_ERROR>, + <IPP_FRO_INT0_CTX1_COUTFIFO_COL_ERROR>, + <IPP_FRO_INT0_CTX1_COUTFIFO_OVERFLOW_ERROR>, + <IPP_FRO_INT0_CTX1_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <IPP_FRO_INT0_CTX1_CINFIFO_LINES_ERROR_INT>, + <IPP_FRO_INT0_CTX1_CINFIFO_COLUMNS_ERROR_INT>, + <IPP_FRO_INT0_CTX1_CINFIFO_STREAM_OVERFLOW_SIG>, + <IPP_FRO_INT0_CTX1_FRAME_START_BEFORE_FRAME_END_CORRUPTED>; + }; + + ipp_fro_ctx2_int0: ipp_fro-event-info@8 { + irq-reg-space = "ipp2"; + irq-src-reg = <0x0 0x3dd0>; + irq-reset-reg = <0x0 0x3dc4>; + irq-mask-reg = <0x0 0x208>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_FRAME_INT_ON_ROW_COL_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_IRQ_CORRUPTED>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COREX_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_P_SLVERR>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_PRE_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COUTFIFO_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COUTFIFO_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_STRP_OUT_DMA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_BDS_DATA_OUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_ZSL_OUT_DMA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_BCROP1_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_BCROP0_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_RGBYHIST2DMA_DONE>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_RGBYHIST_DATA_OUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_THSTAT_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_GP_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CINFIFO_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CINFIFO_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COREX_END_INT0>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COREX_END_INT1>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COUTFIFO_SIZE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COUTFIFO_LINE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COUTFIFO_COL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COUTFIFO_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CINFIFO_LINES_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CINFIFO_COLUMNS_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CINFIFO_STREAM_OVERFLOW_SIG>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_FRM_START_BEFORE_END_CORRUPTED>; + int-reg-bits = + <IPP_FRO_INT0_CTX2_FRAME_START>, + <IPP_FRO_INT0_CTX2_FRAME_END_INTERRUPT>, + <IPP_FRO_INT0_CTX2_FRAME_INT_ON_ROW_COL_INFO>, + <IPP_FRO_INT0_CTX2_IRQ_CORRUPTED>, + <IPP_FRO_INT0_CTX2_COREX_ERROR_INT>, + <IPP_FRO_INT0_CTX2_P_SLVERR>, + <IPP_FRO_INT0_CTX2_PRE_FRAME_END_INTERRUPT>, + <IPP_FRO_INT0_CTX2_COUTFIFO_DATA_OUT_END_INT>, + <IPP_FRO_INT0_CTX2_COUTFIFO_FRAME_OUT_END_INT>, + <IPP_FRO_INT0_CTX2_STRP_OUT_DMA_IN_LAST>, + <IPP_FRO_INT0_CTX2_BDS_DATA_OUT_LAST>, + <IPP_FRO_INT0_CTX2_ZSL_OUT_DMA_IN_LAST>, + <IPP_FRO_INT0_CTX2_BCROP1_DATA_IN_LAST>, + <IPP_FRO_INT0_CTX2_BCROP0_DATA_IN_LAST>, + <IPP_FRO_INT0_CTX2_RGBYHIST2DMA_DONE>, + <IPP_FRO_INT0_CTX2_RGBYHIST_DATA_OUT_LAST>, + <IPP_FRO_INT0_CTX2_THSTAT_DATA_IN_LAST>, + <IPP_FRO_INT0_CTX2_GP_DATA_IN_LAST>, + <IPP_FRO_INT0_CTX2_CINFIFO_DATA_OUT_END_INT>, + <IPP_FRO_INT0_CTX2_CINFIFO_FRAME_OUT_END_INT>, + <IPP_FRO_INT0_CTX2_COREX_END_INT0>, + <IPP_FRO_INT0_CTX2_COREX_END_INT1>, + <IPP_FRO_INT0_CTX2_COUTFIFO_SIZE_ERROR>, + <IPP_FRO_INT0_CTX2_COUTFIFO_LINE_ERROR>, + <IPP_FRO_INT0_CTX2_COUTFIFO_COL_ERROR>, + <IPP_FRO_INT0_CTX2_COUTFIFO_OVERFLOW_ERROR>, + <IPP_FRO_INT0_CTX2_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <IPP_FRO_INT0_CTX2_CINFIFO_LINES_ERROR_INT>, + <IPP_FRO_INT0_CTX2_CINFIFO_COLUMNS_ERROR_INT>, + <IPP_FRO_INT0_CTX2_CINFIFO_STREAM_OVERFLOW_SIG>, + <IPP_FRO_INT0_CTX2_FRAME_START_BEFORE_FRAME_END_CORRUPTED>; + }; + + ipp_fro_ctx0_int1: ipp_fro-event-info@9 { + irq-reg-space = "ipp0"; + irq-src-reg = <0x0 0x3dd4>; + irq-reset-reg = <0x0 0x3dc8>; + irq-mask-reg = <0x0 0x218>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CDAF_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COUTFIFO_FRAME_OUT_START_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CINFIFO_FRAME_IN_END_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CINFIFO_FRAME_IN_START_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_THSTAT_STATISTICS_DONE>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_FRO_GROUP2_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_FRO_GROUP4_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_FRO_GROUP5_INT>; + int-reg-bits = + <IPP_FRO_INT1_CTX0_CDAF_INT>, + <IPP_FRO_INT1_CTX0_COUTFIFO_FRAME_OUT_START_INFO>, + <IPP_FRO_INT1_CTX0_CINFIFO_FRAME_IN_END_INFO>, + <IPP_FRO_INT1_CTX0_CINFIFO_FRAME_IN_START_INFO>, + <IPP_FRO_INT1_CTX0_THSTAT_STATISTICS_DONE>, + <IPP_FRO_INT1_CTX0_FRO_GROUP2_INT>, + <IPP_FRO_INT1_CTX0_FRO_GROUP4_INT>, + <IPP_FRO_INT1_CTX0_FRO_GROUP5_INT>; + }; + + ipp_fro_ctx1_int1: ipp_fro-event-info@10 { + irq-reg-space = "ipp1"; + irq-src-reg = <0x0 0x3dd4>; + irq-reset-reg = <0x0 0x3dc8>; + irq-mask-reg = <0x0 0x218>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CDAF_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COUTFIFO_FRAME_OUT_START_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CINFIFO_FRAME_IN_END_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CINFIFO_FRAME_IN_START_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_THSTAT_STATISTICS_DONE>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_FRO_GROUP2_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_FRO_GROUP4_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_FRO_GROUP5_INT>; + int-reg-bits = + <IPP_FRO_INT1_CTX1_CDAF_INT>, + <IPP_FRO_INT1_CTX1_COUTFIFO_FRAME_OUT_START_INFO>, + <IPP_FRO_INT1_CTX1_CINFIFO_FRAME_IN_END_INFO>, + <IPP_FRO_INT1_CTX1_CINFIFO_FRAME_IN_START_INFO>, + <IPP_FRO_INT1_CTX1_THSTAT_STATISTICS_DONE>, + <IPP_FRO_INT1_CTX1_FRO_GROUP2_INT>, + <IPP_FRO_INT1_CTX1_FRO_GROUP4_INT>, + <IPP_FRO_INT1_CTX1_FRO_GROUP5_INT>; + }; + + ipp_fro_ctx2_int1: ipp_fro-event-info@11 { + irq-reg-space = "ipp2"; + irq-src-reg = <0x0 0x3dd4>; + irq-reset-reg = <0x0 0x3dc8>; + irq-mask-reg = <0x0 0x218>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CDAF_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COUTFIFO_FRAME_OUT_START_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CINFIFO_FRAME_IN_END_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CINFIFO_FRAME_IN_START_INFO>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_THSTAT_STATISTICS_DONE>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_FRO_GROUP2_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_FRO_GROUP4_INT>, + <LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_FRO_GROUP5_INT>; + int-reg-bits = + <IPP_FRO_INT1_CTX2_CDAF_INT>, + <IPP_FRO_INT1_CTX2_COUTFIFO_FRAME_OUT_START_INFO>, + <IPP_FRO_INT1_CTX2_CINFIFO_FRAME_IN_END_INFO>, + <IPP_FRO_INT1_CTX2_CINFIFO_FRAME_IN_START_INFO>, + <IPP_FRO_INT1_CTX2_THSTAT_STATISTICS_DONE>, + <IPP_FRO_INT1_CTX2_FRO_GROUP2_INT>, + <IPP_FRO_INT1_CTX2_FRO_GROUP4_INT>, + <IPP_FRO_INT1_CTX2_FRO_GROUP5_INT>; + }; + + /* + * ITP Interrupt Event Definitions + */ + itp_itp_int0: itp-event-info@0 { + irq-reg-space = "itp"; + irq-src-reg = <0x0 0x808>; + irq-reset-reg = <0x0 0x80c>; + irq-mask-reg = <0x0 0x804>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_ITP_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_ITP_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_ITP_CMDQ_HOLD>, + <LWIS_PLATFORM_EVENT_ID_ITP_SETTING_DONE>, + <LWIS_PLATFORM_EVENT_ID_ITP_C_LOADER_END>, + <LWIS_PLATFORM_EVENT_ID_ITP_COREX_END0>, + <LWIS_PLATFORM_EVENT_ID_ITP_COREX_END1>, + <LWIS_PLATFORM_EVENT_ID_ITP_ROW_COL>, + <LWIS_PLATFORM_EVENT_ID_ITP_FREEZE_ON_ROW_COL>, + <LWIS_PLATFORM_EVENT_ID_ITP_TRANS_STOP_DONE>, + <LWIS_PLATFORM_EVENT_ID_ITP_CMDQ_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_C_LOADER_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_COREX_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_CINFIFO0_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_CINFIFO0_OVERLAP_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_CINFIFO0_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_CINFIFO0_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_CINFIFO1_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_CINFIFO1_OVERLAP_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_CINFIFO1_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_CINFIFO1_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_COUTFIFO0_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_COUTFIFO0_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_COUTFIFO0_OVERFLOW_ERROR>; + int-reg-bits = + <ITP_ITP_INT0_FRAME_START>, + <ITP_ITP_INT0_FRAME_END>, + <ITP_ITP_INT0_CMDQ_HOLD>, + <ITP_ITP_INT0_SETTING_DONE>, + <ITP_ITP_INT0_C_LOADER_END>, + <ITP_ITP_INT0_COREX_END0>, + <ITP_ITP_INT0_COREX_END1>, + <ITP_ITP_INT0_ROW_COL>, + <ITP_ITP_INT0_FREEZE_ON_ROW_COL>, + <ITP_ITP_INT0_TRANS_STOP_DONE>, + <ITP_ITP_INT0_CMDQ_ERROR>, + <ITP_ITP_INT0_C_LOADER_ERROR>, + <ITP_ITP_INT0_COREX_ERROR>, + <ITP_ITP_INT0_CINFIFO0_OVERFLOW_ERROR>, + <ITP_ITP_INT0_CINFIFO0_OVERLAP_ERROR>, + <ITP_ITP_INT0_CINFIFO0_PIXEL_CNT_ERROR>, + <ITP_ITP_INT0_CINFIFO0_INPUT_PROTOCOL_ERROR>, + <ITP_ITP_INT0_CINFIFO1_OVERFLOW_ERROR>, + <ITP_ITP_INT0_CINFIFO1_OVERLAP_ERROR>, + <ITP_ITP_INT0_CINFIFO1_PIXEL_CNT_ERROR>, + <ITP_ITP_INT0_CINFIFO1_INPUT_PROTOCOL_ERROR>, + <ITP_ITP_INT0_COUTFIFO0_PIXEL_CNT_ERROR>, + <ITP_ITP_INT0_COUTFIFO0_INPUT_PROTOCOL_ERROR>, + <ITP_ITP_INT0_COUTFIFO0_OVERFLOW_ERROR>; + }; + + itp_itp_cmdq_int: itp-event-info@1 { + irq-reg-space = "itp"; + irq-src-reg = <0x0 0x4f8>; + irq-reset-reg = <0x0 0x4fc>; + irq-mask-reg = <0x0 0x4f4>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_ITP_STOP_CRPT_OFF_CMDQ_EN>, + <LWIS_PLATFORM_EVENT_ID_ITP_PRELOAD_FLUSH>, + <LWIS_PLATFORM_EVENT_ID_ITP_QUE0_OVERFLOW>; + int-reg-bits = + <ITP_ITP_CMDQ_INT_STOP_CRPT_OFF_CMDQ_EN>, + <ITP_ITP_CMDQ_INT_PRELOAD_FLUSH>, + <ITP_ITP_CMDQ_INT_QUE0_OVERFLOW>; + }; + + itp_dns_int0: itp-event-info@2 { + irq-reg-space = "dns"; + irq-src-reg = <0x0 0x808>; + irq-reset-reg = <0x0 0x80c>; + irq-mask-reg = <0x0 0x804>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_CMDQ_HOLD>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_SETTING_DONE>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_C_LOADER_END>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COREX_END0>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COREX_END1>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_ROW_COL>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_FREEZE_ON_ROW_COL>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_TRANS_STOP_DONE>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_CMDQ_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_C_LOADER_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COREX_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_CINFIFO0_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_CINFIFO0_OVERLAP_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_CINFIFO0_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_CINFIFO0_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COUTFIFO0_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COUTFIFO0_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COUTFIFO0_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COUTFIFO1_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COUTFIFO1_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COUTFIFO1_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_VOTF_GLOBAL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_VOTF_LOST_CONNECTION>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS0_OTF_SEQ_ID_ERROR>; + int-reg-bits = + <ITP_DNS_INT0_DNS0_FRAME_START>, + <ITP_DNS_INT0_DNS0_FRAME_END>, + <ITP_DNS_INT0_DNS0_CMDQ_HOLD>, + <ITP_DNS_INT0_DNS0_SETTING_DONE>, + <ITP_DNS_INT0_DNS0_C_LOADER_END>, + <ITP_DNS_INT0_DNS0_COREX_END0>, + <ITP_DNS_INT0_DNS0_COREX_END1>, + <ITP_DNS_INT0_DNS0_ROW_COL>, + <ITP_DNS_INT0_DNS0_FREEZE_ON_ROW_COL>, + <ITP_DNS_INT0_DNS0_TRANS_STOP_DONE>, + <ITP_DNS_INT0_DNS0_CMDQ_ERROR>, + <ITP_DNS_INT0_DNS0_C_LOADER_ERROR>, + <ITP_DNS_INT0_DNS0_COREX_ERROR>, + <ITP_DNS_INT0_DNS0_CINFIFO0_OVERFLOW_ERROR>, + <ITP_DNS_INT0_DNS0_CINFIFO0_OVERLAP_ERROR>, + <ITP_DNS_INT0_DNS0_CINFIFO0_PIXEL_CNT_ERROR>, + <ITP_DNS_INT0_DNS0_CINFIFO0_INPUT_PROTOCOL_ERROR>, + <ITP_DNS_INT0_DNS0_COUTFIFO0_PIXEL_CNT_ERROR>, + <ITP_DNS_INT0_DNS0_COUTFIFO0_INPUT_PROTOCOL_ERROR>, + <ITP_DNS_INT0_DNS0_COUTFIFO0_OVERFLOW_ERROR>, + <ITP_DNS_INT0_DNS0_COUTFIFO1_PIXEL_CNT_ERROR>, + <ITP_DNS_INT0_DNS0_COUTFIFO1_INPUT_PROTOCOL_ERROR>, + <ITP_DNS_INT0_DNS0_COUTFIFO1_OVERFLOW_ERROR>, + <ITP_DNS_INT0_DNS0_VOTF_GLOBAL_ERROR>, + <ITP_DNS_INT0_DNS0_VOTF_LOST_CONNECTION>, + <ITP_DNS_INT0_DNS0_OTF_SEQ_ID_ERROR>; + }; + + itp_dns_int1: itp-event-info@3 { + irq-reg-space = "dns"; + irq-src-reg = <0x0 0x818>; + irq-reset-reg = <0x0 0x81c>; + irq-mask-reg = <0x0 0x814>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_ITP_DNS1_SBWC_ERR>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS1_VOTF_SLOW_RING>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS1_VOTF_LOST_CONNECTION>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS1_VOTF_LOST_FLUSH>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS1_COUTFIFO2_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS1_COUTFIFO2_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS1_COUTFIFO2_OVERFLOW_ERROR>; + int-reg-bits = + <ITP_DNS_INT1_DNS1_SBWC_ERR>, + <ITP_DNS_INT1_DNS1_VOTF_SLOW_RING>, + <ITP_DNS_INT1_DNS1_VOTF_LOST_CONNECTION>, + <ITP_DNS_INT1_DNS1_VOTF_LOST_FLUSH>, + <ITP_DNS_INT1_DNS1_COUTFIFO2_PIXEL_CNT_ERROR>, + <ITP_DNS_INT1_DNS1_COUTFIFO2_INPUT_PROTOCOL_ERROR>, + <ITP_DNS_INT1_DNS1_COUTFIFO2_OVERFLOW_ERROR>; + }; + + itp_dns_cmdq_int: itp-event-info@4 { + irq-reg-space = "dns"; + irq-src-reg = <0x0 0x4f8>; + irq-reset-reg = <0x0 0x4fc>; + irq-mask-reg = <0x0 0x4f4>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_ITP_DNS_STOP_CRPT_OFF_CMDQ_EN>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS_PRELOAD_FLUSH>, + <LWIS_PLATFORM_EVENT_ID_ITP_DNS_QUE0_OVERFLOW>; + int-reg-bits = + <ITP_DNS_CMDQ_INT_DNS_STOP_CRPT_OFF_CMDQ_EN>, + <ITP_DNS_CMDQ_INT_DNS_PRELOAD_FLUSH>, + <ITP_DNS_CMDQ_INT_DNS_QUE0_OVERFLOW>; + }; + + itp_itsc_int0: itp-event-info@5 { + irq-reg-space = "itsc"; + irq-src-reg = <0x0 0x808>; + irq-reset-reg = <0x0 0x80c>; + irq-mask-reg = <0x0 0x804>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CMDQ_HOLD>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_SETTING_DONE>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_C_LOADER_END>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COREX_END0>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COREX_END1>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_ROW_COL>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_FREEZE_ON_ROW_COL>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_TRANS_STOP_DONE>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CMDQ_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_C_LOADER_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COREX_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CINFIFO0_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CINFIFO0_OVERLAP_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CINFIFO0_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CINFIFO0_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CINFIFO1_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CINFIFO1_OVERLAP_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CINFIFO1_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CINFIFO1_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COUTFIFO0_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COUTFIFO0_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COUTFIFO0_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COUTFIFO1_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COUTFIFO1_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COUTFIFO1_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_VOTF_GLOBAL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_VOTF_LOST_CONNECTION>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_OTF_SEQ_ID_ERROR>; + int-reg-bits = + <ITP_ITSC_INT0_ITSC0_FRAME_START>, + <ITP_ITSC_INT0_ITSC0_FRAME_END>, + <ITP_ITSC_INT0_ITSC0_CMDQ_HOLD>, + <ITP_ITSC_INT0_ITSC0_SETTING_DONE>, + <ITP_ITSC_INT0_ITSC0_C_LOADER_END>, + <ITP_ITSC_INT0_ITSC0_COREX_END0>, + <ITP_ITSC_INT0_ITSC0_COREX_END1>, + <ITP_ITSC_INT0_ITSC0_ROW_COL>, + <ITP_ITSC_INT0_ITSC0_FREEZE_ON_ROW_COL>, + <ITP_ITSC_INT0_ITSC0_TRANS_STOP_DONE>, + <ITP_ITSC_INT0_ITSC0_CMDQ_ERROR>, + <ITP_ITSC_INT0_ITSC0_C_LOADER_ERROR>, + <ITP_ITSC_INT0_ITSC0_COREX_ERROR>, + <ITP_ITSC_INT0_ITSC0_CINFIFO0_OVERFLOW_ERROR>, + <ITP_ITSC_INT0_ITSC0_CINFIFO0_OVERLAP_ERROR>, + <ITP_ITSC_INT0_ITSC0_CINFIFO0_PIXEL_CNT_ERROR>, + <ITP_ITSC_INT0_ITSC0_CINFIFO0_INPUT_PROTOCOL_ERROR>, + <ITP_ITSC_INT0_ITSC0_CINFIFO1_OVERFLOW_ERROR>, + <ITP_ITSC_INT0_ITSC0_CINFIFO1_OVERLAP_ERROR>, + <ITP_ITSC_INT0_ITSC0_CINFIFO1_PIXEL_CNT_ERROR>, + <ITP_ITSC_INT0_ITSC0_CINFIFO1_INPUT_PROTOCOL_ERROR>, + <ITP_ITSC_INT0_ITSC0_COUTFIFO0_PIXEL_CNT_ERROR>, + <ITP_ITSC_INT0_ITSC0_COUTFIFO0_INPUT_PROTOCOL_ERROR>, + <ITP_ITSC_INT0_ITSC0_COUTFIFO0_OVERFLOW_ERROR>, + <ITP_ITSC_INT0_ITSC0_COUTFIFO1_PIXEL_CNT_ERROR>, + <ITP_ITSC_INT0_ITSC0_COUTFIFO1_INPUT_PROTOCOL_ERROR>, + <ITP_ITSC_INT0_ITSC0_COUTFIFO1_OVERFLOW_ERROR>, + <ITP_ITSC_INT0_ITSC0_VOTF_GLOBAL_ERROR>, + <ITP_ITSC_INT0_ITSC0_VOTF_LOST_CONNECTION>, + <ITP_ITSC_INT0_ITSC0_OTF_SEQ_ID_ERROR>; + }; + + itp_itsc_int1: itp-event-info@6 { + irq-reg-space = "itsc"; + irq-src-reg = <0x0 0x818>; + irq-reset-reg = <0x0 0x81c>; + irq-mask-reg = <0x0 0x814>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC1_VOTF_LOST_FLUSH>; + int-reg-bits = + <ITP_ITSC_INT1_ITSC1_VOTF_LOST_FLUSH>; + }; + + itp_itsc_cmdq_int: itp-event-info@7 { + irq-reg-space = "itsc"; + irq-src-reg = <0x0 0x4f8>; + irq-reset-reg = <0x0 0x4fc>; + irq-mask-reg = <0x0 0x4f4>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC_STOP_CRPT_OFF_CMDQ_EN>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC_PRELOAD_FLUSH>, + <LWIS_PLATFORM_EVENT_ID_ITP_ITSC_QUE0_OVERFLOW>; + int-reg-bits = + <ITP_ITSC_CMDQ_INT_ITSC_STOP_CRPT_OFF_CMDQ_EN>, + <ITP_ITSC_CMDQ_INT_ITSC_PRELOAD_FLUSH>, + <ITP_ITSC_CMDQ_INT_ITSC_QUE0_OVERFLOW>; + }; + + /* + * MCSC Interrupt Event Definitions + */ + mcsc_int0: mcsc-event-info@0 { + irq-reg-space = "mcsc"; + irq-src-reg = <0x0 0x808>; + irq-reset-reg = <0x0 0x80c>; + irq-mask-reg = <0x0 0x804>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_MCSC_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_MCSC_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_MCSC_CMDQ_HOLD>, + <LWIS_PLATFORM_EVENT_ID_MCSC_SETTING_DONE>, + <LWIS_PLATFORM_EVENT_ID_MCSC_C_LOADER_END>, + <LWIS_PLATFORM_EVENT_ID_MCSC_COREX_END0>, + <LWIS_PLATFORM_EVENT_ID_MCSC_COREX_END1>, + <LWIS_PLATFORM_EVENT_ID_MCSC_ROW_COL>, + <LWIS_PLATFORM_EVENT_ID_MCSC_FREEZE_ON_ROW_COL>, + <LWIS_PLATFORM_EVENT_ID_MCSC_TRANS_STOP_DONE>, + <LWIS_PLATFORM_EVENT_ID_MCSC_CMDQ_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_C_LOADER_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_COREX_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_CINFIFO0_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_CINFIFO0_OVERLAP_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_CINFIFO0_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_CINFIFO0_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_CINFIFO1_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_CINFIFO1_OVERLAP_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_CINFIFO1_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_CINFIFO1_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_COUTFIFO0_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_COUTFIFO0_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_COUTFIFO0_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_COUTFIFO1_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_COUTFIFO1_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_COUTFIFO1_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_VOTF_GLOBAL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_VOTF_LOST_CONNECTION>, + <LWIS_PLATFORM_EVENT_ID_MCSC_OTF_SEQ_ID_ERROR>; + int-reg-bits = + <MCSC_INT0_FRAME_START>, + <MCSC_INT0_FRAME_END>, + <MCSC_INT0_CMDQ_HOLD>, + <MCSC_INT0_SETTING_DONE>, + <MCSC_INT0_C_LOADER_END>, + <MCSC_INT0_COREX_END0>, + <MCSC_INT0_COREX_END1>, + <MCSC_INT0_ROW_COL>, + <MCSC_INT0_FREEZE_ON_ROW_COL>, + <MCSC_INT0_TRANS_STOP_DONE>, + <MCSC_INT0_CMDQ_ERROR>, + <MCSC_INT0_C_LOADER_ERROR>, + <MCSC_INT0_COREX_ERROR>, + <MCSC_INT0_CINFIFO0_OVERFLOW_ERROR>, + <MCSC_INT0_CINFIFO0_OVERLAP_ERROR>, + <MCSC_INT0_CINFIFO0_PIXEL_CNT_ERROR>, + <MCSC_INT0_CINFIFO0_INPUT_PROTOCOL_ERROR>, + <MCSC_INT0_CINFIFO1_OVERFLOW_ERROR>, + <MCSC_INT0_CINFIFO1_OVERLAP_ERROR>, + <MCSC_INT0_CINFIFO1_PIXEL_CNT_ERROR>, + <MCSC_INT0_CINFIFO1_INPUT_PROTOCOL_ERROR>, + <MCSC_INT0_COUTFIFO0_PIXEL_CNT_ERROR>, + <MCSC_INT0_COUTFIFO0_INPUT_PROTOCOL_ERROR>, + <MCSC_INT0_COUTFIFO0_OVERFLOW_ERROR>, + <MCSC_INT0_COUTFIFO1_PIXEL_CNT_ERROR>, + <MCSC_INT0_COUTFIFO1_INPUT_PROTOCOL_ERROR>, + <MCSC_INT0_COUTFIFO1_OVERFLOW_ERROR>, + <MCSC_INT0_VOTF_GLOBAL_ERROR>, + <MCSC_INT0_VOTF_LOST_CONNECTION>, + <MCSC_INT0_OTF_SEQ_ID_ERROR>; + }; + + mcsc_int1: mcsc-event-info@1 { + irq-reg-space = "mcsc"; + irq-src-reg = <0x0 0x818>; + irq-reset-reg = <0x0 0x81c>; + irq-mask-reg = <0x0 0x814>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_MCSC_RDMA_M0_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_WDMA_M0_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_WDMA_M1_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_WDMA_M2_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_WDMA_M3_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_WDMA_M4_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_RDMA_VOTF_LOST_CONNECTION>, + <LWIS_PLATFORM_EVENT_ID_MCSC_COMP_DEC_ERROR>, + <LWIS_PLATFORM_EVENT_ID_MCSC_DJAG_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_SC0_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_SC1_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_SC2_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_SC3_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_SC4_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_PC0_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_PC1_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_PC2_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_PC3_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_PC4_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_CONV4200_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_CONV4201_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_CONV4202_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_CONV4203_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_CONV4204_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_BCHS0_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_BCHS1_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_BCHS2_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_BCHS3_FINISH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_BCHS4_FINISH>; + int-reg-bits = + <MCSC_INT1_RDMA_M0_FINISH>, + <MCSC_INT1_WDMA_M0_FINISH>, + <MCSC_INT1_WDMA_M1_FINISH>, + <MCSC_INT1_WDMA_M2_FINISH>, + <MCSC_INT1_WDMA_M3_FINISH>, + <MCSC_INT1_WDMA_M4_FINISH>, + <MCSC_INT1_RDMA_VOTF_LOST_CONNECTION>, + <MCSC_INT1_COMP_DEC_ERROR>, + <MCSC_INT1_DJAG_FINISH>, + <MCSC_INT1_SC0_FINISH>, + <MCSC_INT1_SC1_FINISH>, + <MCSC_INT1_SC2_FINISH>, + <MCSC_INT1_SC3_FINISH>, + <MCSC_INT1_SC4_FINISH>, + <MCSC_INT1_PC0_FINISH>, + <MCSC_INT1_PC1_FINISH>, + <MCSC_INT1_PC2_FINISH>, + <MCSC_INT1_PC3_FINISH>, + <MCSC_INT1_PC4_FINISH>, + <MCSC_INT1_CONV4200_FINISH>, + <MCSC_INT1_CONV4201_FINISH>, + <MCSC_INT1_CONV4202_FINISH>, + <MCSC_INT1_CONV4203_FINISH>, + <MCSC_INT1_CONV4204_FINISH>, + <MCSC_INT1_BCHS0_FINISH>, + <MCSC_INT1_BCHS1_FINISH>, + <MCSC_INT1_BCHS2_FINISH>, + <MCSC_INT1_BCHS3_FINISH>, + <MCSC_INT1_BCHS4_FINISH>; + }; + + mcsc_cmdq_int: mcsc-event-info@2 { + irq-reg-space = "mcsc"; + irq-src-reg = <0x0 0x4f8>; + irq-reset-reg = <0x0 0x4fc>; + irq-mask-reg = <0x0 0x4f4>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_MCSC_STOP_CRPT_OFF_CMDQ_EN>, + <LWIS_PLATFORM_EVENT_ID_MCSC_PRELOAD_FLUSH>, + <LWIS_PLATFORM_EVENT_ID_MCSC_QUE0_OVERFLOW>; + int-reg-bits = + <MCSC_CMDQ_INT_STOP_CRPT_OFF_CMDQ_EN>, + <MCSC_CMDQ_INT_PRELOAD_FLUSH>, + <MCSC_CMDQ_INT_QUE0_OVERFLOW>; + }; + + /* + * PDP Interrupt Event Definitions + */ + + pdp_ctx0_int_src1: pdp-event-info@0 { + irq-reg-space = "pdp-core0"; + irq-src-reg = <0x0 0x10c>; + irq-reset-reg = <0x0 0x110>; + irq-mask-reg = <0x0 0x108>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_FRAME_INT_ON_ROW_COL_INFO>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_IRQ_CORRUPTED>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COREX_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_PRE_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_LIC_INPUT_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_LIC_OUTPUT_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_AFIDENT_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_RCB_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_MPD_IR_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_YEXT_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_BPC_IR_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_REORDER_IR_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_GAMMA0_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_GAMMA1_IR_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_ALC_IR_LAST_G3AAY_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COREX_END_INT0>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COREX_END_INT1>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAB_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAB_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAY_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAY_FRAME_OUT_END_INT>; + int-reg-bits = + <PDP_INT_SRC1_CTX0_FRAME_START>, + <PDP_INT_SRC1_CTX0_FRAME_END_INTERRUPT>, + <PDP_INT_SRC1_CTX0_FRAME_INT_ON_ROW_COL_INFO>, + <PDP_INT_SRC1_CTX0_IRQ_CORRUPTED>, + <PDP_INT_SRC1_CTX0_COREX_ERROR_INT>, + <PDP_INT_SRC1_CTX0_PRE_FRAME_END_INTERRUPT>, + <PDP_INT_SRC1_CTX0_LIC_INPUT_FRAME_END>, + <PDP_INT_SRC1_CTX0_LIC_OUTPUT_FRAME_END>, + <PDP_INT_SRC1_CTX0_AFIDENT_DATA_IN_LAST>, + <PDP_INT_SRC1_CTX0_COUTFIFO_DATA_OUT_END_INT>, + <PDP_INT_SRC1_CTX0_COUTFIFO_FRAME_OUT_END_INT>, + <PDP_INT_SRC1_CTX0_RCB_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX0_MPD_IR_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX0_YEXT_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX0_BPC_IR_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX0_REORDER_IR_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX0_GAMMA0_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX0_GAMMA1_IR_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX0_ALC_IR_LAST_G3AAY_FRAME_OUT_END_INT>, + <PDP_INT_SRC1_CTX0_COREX_END_INT0>, + <PDP_INT_SRC1_CTX0_COREX_END_INT1>, + <PDP_INT_SRC1_CTX0_COUTFIFO_G3AAB_DATA_OUT_END_INT>, + <PDP_INT_SRC1_CTX0_COUTFIFO_G3AAB_FRAME_OUT_END_INT>, + <PDP_INT_SRC1_CTX0_COUTFIFO_G3AAY_DATA_OUT_END_INT>, + <PDP_INT_SRC1_CTX0_COUTFIFO_G3AAY_FRAME_OUT_END_INT>; + }; + + pdp_ctx1_int_src1: pdp-event-info@1 { + irq-reg-space = "pdp-core1"; + irq-src-reg = <0x0 0x10c>; + irq-reset-reg = <0x0 0x110>; + irq-mask-reg = <0x0 0x108>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_FRAME_INT_ON_ROW_COL_INFO>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_IRQ_CORRUPTED>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COREX_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_PRE_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_LIC_INPUT_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_LIC_OUTPUT_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_AFIDENT_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_RCB_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_MPD_IR_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_YEXT_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_BPC_IR_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_REORDER_IR_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_GAMMA0_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_GAMMA1_IR_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_ALC_IR_LAST_G3AAY_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COREX_END_INT0>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COREX_END_INT1>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAB_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAB_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAY_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAY_FRAME_OUT_END_INT>; + int-reg-bits = + <PDP_INT_SRC1_CTX1_FRAME_START>, + <PDP_INT_SRC1_CTX1_FRAME_END_INTERRUPT>, + <PDP_INT_SRC1_CTX1_FRAME_INT_ON_ROW_COL_INFO>, + <PDP_INT_SRC1_CTX1_IRQ_CORRUPTED>, + <PDP_INT_SRC1_CTX1_COREX_ERROR_INT>, + <PDP_INT_SRC1_CTX1_PRE_FRAME_END_INTERRUPT>, + <PDP_INT_SRC1_CTX1_LIC_INPUT_FRAME_END>, + <PDP_INT_SRC1_CTX1_LIC_OUTPUT_FRAME_END>, + <PDP_INT_SRC1_CTX1_AFIDENT_DATA_IN_LAST>, + <PDP_INT_SRC1_CTX1_COUTFIFO_DATA_OUT_END_INT>, + <PDP_INT_SRC1_CTX1_COUTFIFO_FRAME_OUT_END_INT>, + <PDP_INT_SRC1_CTX1_RCB_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX1_MPD_IR_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX1_YEXT_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX1_BPC_IR_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX1_REORDER_IR_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX1_GAMMA0_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX1_GAMMA1_IR_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX1_ALC_IR_LAST_G3AAY_FRAME_OUT_END_INT>, + <PDP_INT_SRC1_CTX1_COREX_END_INT0>, + <PDP_INT_SRC1_CTX1_COREX_END_INT1>, + <PDP_INT_SRC1_CTX1_COUTFIFO_G3AAB_DATA_OUT_END_INT>, + <PDP_INT_SRC1_CTX1_COUTFIFO_G3AAB_FRAME_OUT_END_INT>, + <PDP_INT_SRC1_CTX1_COUTFIFO_G3AAY_DATA_OUT_END_INT>, + <PDP_INT_SRC1_CTX1_COUTFIFO_G3AAY_FRAME_OUT_END_INT>; + }; + + pdp_ctx2_int_src1: pdp-event-info@2 { + irq-reg-space = "pdp-core2"; + irq-src-reg = <0x0 0x10c>; + irq-reset-reg = <0x0 0x110>; + irq-mask-reg = <0x0 0x108>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_FRAME_INT_ON_ROW_COL_INFO>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_IRQ_CORRUPTED>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COREX_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_PRE_FRAME_END_INTERRUPT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_LIC_INPUT_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_LIC_OUTPUT_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_AFIDENT_DATA_IN_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_RCB_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_MPD_IR_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_YEXT_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_BPC_IR_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_REORDER_IR_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_GAMMA0_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_GAMMA1_IR_OUTPUT_LAST>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_ALC_IR_LAST_G3AAY_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COREX_END_INT0>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COREX_END_INT1>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAB_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAB_FRAME_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAY_DATA_OUT_END_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAY_FRAME_OUT_END_INT>; + int-reg-bits = + <PDP_INT_SRC1_CTX2_FRAME_START>, + <PDP_INT_SRC1_CTX2_FRAME_END_INTERRUPT>, + <PDP_INT_SRC1_CTX2_FRAME_INT_ON_ROW_COL_INFO>, + <PDP_INT_SRC1_CTX2_IRQ_CORRUPTED>, + <PDP_INT_SRC1_CTX2_COREX_ERROR_INT>, + <PDP_INT_SRC1_CTX2_PRE_FRAME_END_INTERRUPT>, + <PDP_INT_SRC1_CTX2_LIC_INPUT_FRAME_END>, + <PDP_INT_SRC1_CTX2_LIC_OUTPUT_FRAME_END>, + <PDP_INT_SRC1_CTX2_AFIDENT_DATA_IN_LAST>, + <PDP_INT_SRC1_CTX2_COUTFIFO_DATA_OUT_END_INT>, + <PDP_INT_SRC1_CTX2_COUTFIFO_FRAME_OUT_END_INT>, + <PDP_INT_SRC1_CTX2_RCB_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX2_MPD_IR_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX2_YEXT_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX2_BPC_IR_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX2_REORDER_IR_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX2_GAMMA0_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX2_GAMMA1_IR_OUTPUT_LAST>, + <PDP_INT_SRC1_CTX2_ALC_IR_LAST_G3AAY_FRAME_OUT_END_INT>, + <PDP_INT_SRC1_CTX2_COREX_END_INT0>, + <PDP_INT_SRC1_CTX2_COREX_END_INT1>, + <PDP_INT_SRC1_CTX2_COUTFIFO_G3AAB_DATA_OUT_END_INT>, + <PDP_INT_SRC1_CTX2_COUTFIFO_G3AAB_FRAME_OUT_END_INT>, + <PDP_INT_SRC1_CTX2_COUTFIFO_G3AAY_DATA_OUT_END_INT>, + <PDP_INT_SRC1_CTX2_COUTFIFO_G3AAY_FRAME_OUT_END_INT>; + }; + + pdp_ctx0_int_src2: pdp-event-info@3 { + irq-reg-space = "pdp-core0"; + irq-src-reg = <0x0 0x11c>; + irq-reset-reg = <0x0 0x120>; + irq-mask-reg = <0x0 0x118>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_FRAME_OUT_START_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_VOTF_LOST_FLUSH_IMG>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_VOTF_LOST_FLUSH_AF>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_C2SER_SLOW_RING>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_PDAF_STAT_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_SBWC_ERR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_VOTF_LOSTCON_IMG>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_VOTF_LOSTCON_AF>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AA_BFRAME_OUT_START_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AA_YFRAME_OUT_START_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_SIZE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_LINE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_COL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_CINFIFO_LINES_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_CINFIFO_COLUMNS_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_CINFIFO_STREAM_OVERFLOW_SIG>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAB_SIZE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAB_LINE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAB_COL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAB_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAY_SIZE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAY_LINE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAY_COL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAY_OVERFLOW_ERROR>; + int-reg-bits = + <PDP_INT_SRC2_CTX0_COUTFIFO_FRAME_OUT_START_INT>, + <PDP_INT_SRC2_CTX0_VOTF_LOST_FLUSH_IMG>, + <PDP_INT_SRC2_CTX0_VOTF_LOST_FLUSH_AF>, + <PDP_INT_SRC2_CTX0_C2SER_SLOW_RING>, + <PDP_INT_SRC2_CTX0_PDAF_STAT_INT>, + <PDP_INT_SRC2_CTX0_SBWC_ERR>, + <PDP_INT_SRC2_CTX0_VOTF_LOSTCON_IMG>, + <PDP_INT_SRC2_CTX0_VOTF_LOSTCON_AF>, + <PDP_INT_SRC2_CTX0_COUTFIFO_G3AA_BFRAME_OUT_START_INT>, + <PDP_INT_SRC2_CTX0_COUTFIFO_G3AA_YFRAME_OUT_START_INT>, + <PDP_INT_SRC2_CTX0_COUTFIFO_SIZE_ERROR>, + <PDP_INT_SRC2_CTX0_COUTFIFO_LINE_ERROR>, + <PDP_INT_SRC2_CTX0_COUTFIFO_COL_ERROR>, + <PDP_INT_SRC2_CTX0_COUTFIFO_OVERFLOW_ERROR>, + <PDP_INT_SRC2_CTX0_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <PDP_INT_SRC2_CTX0_CINFIFO_LINES_ERROR_INT>, + <PDP_INT_SRC2_CTX0_CINFIFO_COLUMNS_ERROR_INT>, + <PDP_INT_SRC2_CTX0_CINFIFO_STREAM_OVERFLOW_SIG>, + <PDP_INT_SRC2_CTX0_COUTFIFO_G3AAB_SIZE_ERROR>, + <PDP_INT_SRC2_CTX0_COUTFIFO_G3AAB_LINE_ERROR>, + <PDP_INT_SRC2_CTX0_COUTFIFO_G3AAB_COL_ERROR>, + <PDP_INT_SRC2_CTX0_COUTFIFO_G3AAB_OVERFLOW_ERROR>, + <PDP_INT_SRC2_CTX0_COUTFIFO_G3AAY_SIZE_ERROR>, + <PDP_INT_SRC2_CTX0_COUTFIFO_G3AAY_LINE_ERROR>, + <PDP_INT_SRC2_CTX0_COUTFIFO_G3AAY_COL_ERROR>, + <PDP_INT_SRC2_CTX0_COUTFIFO_G3AAY_OVERFLOW_ERROR>; + }; + + pdp_ctx1_int_src2: pdp-event-info@4 { + irq-reg-space = "pdp-core1"; + irq-src-reg = <0x0 0x11c>; + irq-reset-reg = <0x0 0x120>; + irq-mask-reg = <0x0 0x118>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_FRAME_OUT_START_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_VOTF_LOST_FLUSH_IMG>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_VOTF_LOST_FLUSH_AF>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_C2SER_SLOW_RING>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_PDAF_STAT_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_SBWC_ERR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_VOTF_LOSTCON_IMG>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_VOTF_LOSTCON_AF>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AA_BFRAME_OUT_START_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AA_YFRAME_OUT_START_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_SIZE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_LINE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_COL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_CINFIFO_LINES_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_CINFIFO_COLUMNS_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_CINFIFO_STREAM_OVERFLOW_SIG>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAB_SIZE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAB_LINE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAB_COL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAB_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAY_SIZE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAY_LINE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAY_COL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAY_OVERFLOW_ERROR>; + int-reg-bits = + <PDP_INT_SRC2_CTX1_COUTFIFO_FRAME_OUT_START_INT>, + <PDP_INT_SRC2_CTX1_VOTF_LOST_FLUSH_IMG>, + <PDP_INT_SRC2_CTX1_VOTF_LOST_FLUSH_AF>, + <PDP_INT_SRC2_CTX1_C2SER_SLOW_RING>, + <PDP_INT_SRC2_CTX1_PDAF_STAT_INT>, + <PDP_INT_SRC2_CTX1_SBWC_ERR>, + <PDP_INT_SRC2_CTX1_VOTF_LOSTCON_IMG>, + <PDP_INT_SRC2_CTX1_VOTF_LOSTCON_AF>, + <PDP_INT_SRC2_CTX1_COUTFIFO_G3AA_BFRAME_OUT_START_INT>, + <PDP_INT_SRC2_CTX1_COUTFIFO_G3AA_YFRAME_OUT_START_INT>, + <PDP_INT_SRC2_CTX1_COUTFIFO_SIZE_ERROR>, + <PDP_INT_SRC2_CTX1_COUTFIFO_LINE_ERROR>, + <PDP_INT_SRC2_CTX1_COUTFIFO_COL_ERROR>, + <PDP_INT_SRC2_CTX1_COUTFIFO_OVERFLOW_ERROR>, + <PDP_INT_SRC2_CTX1_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <PDP_INT_SRC2_CTX1_CINFIFO_LINES_ERROR_INT>, + <PDP_INT_SRC2_CTX1_CINFIFO_COLUMNS_ERROR_INT>, + <PDP_INT_SRC2_CTX1_CINFIFO_STREAM_OVERFLOW_SIG>, + <PDP_INT_SRC2_CTX1_COUTFIFO_G3AAB_SIZE_ERROR>, + <PDP_INT_SRC2_CTX1_COUTFIFO_G3AAB_LINE_ERROR>, + <PDP_INT_SRC2_CTX1_COUTFIFO_G3AAB_COL_ERROR>, + <PDP_INT_SRC2_CTX1_COUTFIFO_G3AAB_OVERFLOW_ERROR>, + <PDP_INT_SRC2_CTX1_COUTFIFO_G3AAY_SIZE_ERROR>, + <PDP_INT_SRC2_CTX1_COUTFIFO_G3AAY_LINE_ERROR>, + <PDP_INT_SRC2_CTX1_COUTFIFO_G3AAY_COL_ERROR>, + <PDP_INT_SRC2_CTX1_COUTFIFO_G3AAY_OVERFLOW_ERROR>; + }; + + pdp_ctx2_int_src2: pdp-event-info@5 { + irq-reg-space = "pdp-core2"; + irq-src-reg = <0x0 0x11c>; + irq-reset-reg = <0x0 0x120>; + irq-mask-reg = <0x0 0x118>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_FRAME_OUT_START_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_VOTF_LOST_FLUSH_IMG>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_VOTF_LOST_FLUSH_AF>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_C2SER_SLOW_RING>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_PDAF_STAT_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_SBWC_ERR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_VOTF_LOSTCON_IMG>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_VOTF_LOSTCON_AF>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AA_BFRAME_OUT_START_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AA_YFRAME_OUT_START_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_SIZE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_LINE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_COL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_CINFIFO_LINES_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_CINFIFO_COLUMNS_ERROR_INT>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_CINFIFO_STREAM_OVERFLOW_SIG>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAB_SIZE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAB_LINE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAB_COL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAB_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAY_SIZE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAY_LINE_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAY_COL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAY_OVERFLOW_ERROR>; + int-reg-bits = + <PDP_INT_SRC2_CTX2_COUTFIFO_FRAME_OUT_START_INT>, + <PDP_INT_SRC2_CTX2_VOTF_LOST_FLUSH_IMG>, + <PDP_INT_SRC2_CTX2_VOTF_LOST_FLUSH_AF>, + <PDP_INT_SRC2_CTX2_C2SER_SLOW_RING>, + <PDP_INT_SRC2_CTX2_PDAF_STAT_INT>, + <PDP_INT_SRC2_CTX2_SBWC_ERR>, + <PDP_INT_SRC2_CTX2_VOTF_LOSTCON_IMG>, + <PDP_INT_SRC2_CTX2_VOTF_LOSTCON_AF>, + <PDP_INT_SRC2_CTX2_COUTFIFO_G3AA_BFRAME_OUT_START_INT>, + <PDP_INT_SRC2_CTX2_COUTFIFO_G3AA_YFRAME_OUT_START_INT>, + <PDP_INT_SRC2_CTX2_COUTFIFO_SIZE_ERROR>, + <PDP_INT_SRC2_CTX2_COUTFIFO_LINE_ERROR>, + <PDP_INT_SRC2_CTX2_COUTFIFO_COL_ERROR>, + <PDP_INT_SRC2_CTX2_COUTFIFO_OVERFLOW_ERROR>, + <PDP_INT_SRC2_CTX2_CINFIFO_TOTAL_SIZE_ERROR_INT>, + <PDP_INT_SRC2_CTX2_CINFIFO_LINES_ERROR_INT>, + <PDP_INT_SRC2_CTX2_CINFIFO_COLUMNS_ERROR_INT>, + <PDP_INT_SRC2_CTX2_CINFIFO_STREAM_OVERFLOW_SIG>, + <PDP_INT_SRC2_CTX2_COUTFIFO_G3AAB_SIZE_ERROR>, + <PDP_INT_SRC2_CTX2_COUTFIFO_G3AAB_LINE_ERROR>, + <PDP_INT_SRC2_CTX2_COUTFIFO_G3AAB_COL_ERROR>, + <PDP_INT_SRC2_CTX2_COUTFIFO_G3AAB_OVERFLOW_ERROR>, + <PDP_INT_SRC2_CTX2_COUTFIFO_G3AAY_SIZE_ERROR>, + <PDP_INT_SRC2_CTX2_COUTFIFO_G3AAY_LINE_ERROR>, + <PDP_INT_SRC2_CTX2_COUTFIFO_G3AAY_COL_ERROR>, + <PDP_INT_SRC2_CTX2_COUTFIFO_G3AAY_OVERFLOW_ERROR>; + }; + + /* + * SCSC Interrupt Event Definitions + */ + scsc_int0: scsc-event-info@0 { + irq-reg-space = "scsc"; + irq-src-reg = <0x0 0x808>; + irq-reset-reg = <0x0 0x80c>; + irq-mask-reg = <0x0 0x804>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_SCSC_FRAME_START>, + <LWIS_PLATFORM_EVENT_ID_SCSC_FRAME_END>, + <LWIS_PLATFORM_EVENT_ID_SCSC_CMDQ_HOLD>, + <LWIS_PLATFORM_EVENT_ID_SCSC_SETTING_DONE>, + <LWIS_PLATFORM_EVENT_ID_SCSC_C_LOADER_END>, + <LWIS_PLATFORM_EVENT_ID_SCSC_COREX_END0>, + <LWIS_PLATFORM_EVENT_ID_SCSC_COREX_END1>, + <LWIS_PLATFORM_EVENT_ID_SCSC_ROW_COL>, + <LWIS_PLATFORM_EVENT_ID_SCSC_FREEZE_ON_ROW_COL>, + <LWIS_PLATFORM_EVENT_ID_SCSC_TRANS_STOP_DONE>, + <LWIS_PLATFORM_EVENT_ID_SCSC_CMDQ_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_C_LOADER_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_COREX_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_CINFIFO0_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_CINFIFO0_OVERLAP_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_CINFIFO0_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_CINFIFO0_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_CINFIFO1_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_CINFIFO1_OVERLAP_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_CINFIFO1_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_CINFIFO1_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_COUTFIFO0_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_COUTFIFO0_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_COUTFIFO0_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_COUTFIFO1_PIXEL_CNT_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_COUTFIFO1_INPUT_PROTOCOL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_COUTFIFO1_OVERFLOW_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_VOTF_GLOBAL_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_VOTF_LOST_CONNECTION>, + <LWIS_PLATFORM_EVENT_ID_SCSC_OTF_SEQ_ID_ERROR>; + int-reg-bits = + <SCSC_INT0_FRAME_START>, + <SCSC_INT0_FRAME_END>, + <SCSC_INT0_CMDQ_HOLD>, + <SCSC_INT0_SETTING_DONE>, + <SCSC_INT0_C_LOADER_END>, + <SCSC_INT0_COREX_END0>, + <SCSC_INT0_COREX_END1>, + <SCSC_INT0_ROW_COL>, + <SCSC_INT0_FREEZE_ON_ROW_COL>, + <SCSC_INT0_TRANS_STOP_DONE>, + <SCSC_INT0_CMDQ_ERROR>, + <SCSC_INT0_C_LOADER_ERROR>, + <SCSC_INT0_COREX_ERROR>, + <SCSC_INT0_CINFIFO0_OVERFLOW_ERROR>, + <SCSC_INT0_CINFIFO0_OVERLAP_ERROR>, + <SCSC_INT0_CINFIFO0_PIXEL_CNT_ERROR>, + <SCSC_INT0_CINFIFO0_INPUT_PROTOCOL_ERROR>, + <SCSC_INT0_CINFIFO1_OVERFLOW_ERROR>, + <SCSC_INT0_CINFIFO1_OVERLAP_ERROR>, + <SCSC_INT0_CINFIFO1_PIXEL_CNT_ERROR>, + <SCSC_INT0_CINFIFO1_INPUT_PROTOCOL_ERROR>, + <SCSC_INT0_COUTFIFO0_PIXEL_CNT_ERROR>, + <SCSC_INT0_COUTFIFO0_INPUT_PROTOCOL_ERROR>, + <SCSC_INT0_COUTFIFO0_OVERFLOW_ERROR>, + <SCSC_INT0_COUTFIFO1_PIXEL_CNT_ERROR>, + <SCSC_INT0_COUTFIFO1_INPUT_PROTOCOL_ERROR>, + <SCSC_INT0_COUTFIFO1_OVERFLOW_ERROR>, + <SCSC_INT0_VOTF_GLOBAL_ERROR>, + <SCSC_INT0_VOTF_LOST_CONNECTION>, + <SCSC_INT0_OTF_SEQ_ID_ERROR>; + }; + + scsc_int1: scsc-event-info@1 { + irq-reg-space = "scsc"; + irq-src-reg = <0x0 0x818>; + irq-reset-reg = <0x0 0x81c>; + irq-mask-reg = <0x0 0x814>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_SCSC_RDMA_M0_FINISH>, + <LWIS_PLATFORM_EVENT_ID_SCSC_WDMA_M0_FINISH>, + <LWIS_PLATFORM_EVENT_ID_SCSC_WDMA_M1_FINISH>, + <LWIS_PLATFORM_EVENT_ID_SCSC_RDMA_VOTF_LOST_CONNECTION>, + <LWIS_PLATFORM_EVENT_ID_SCSC_COMP_DEC_ERROR>, + <LWIS_PLATFORM_EVENT_ID_SCSC_DJAG_FINISH>, + <LWIS_PLATFORM_EVENT_ID_SCSC_SC0_FINISH>, + <LWIS_PLATFORM_EVENT_ID_SCSC_SC1_FINISH>, + <LWIS_PLATFORM_EVENT_ID_SCSC_PC0_FINISH>, + <LWIS_PLATFORM_EVENT_ID_SCSC_PC1_FINISH>, + <LWIS_PLATFORM_EVENT_ID_SCSC_CONV4200_FINISH>, + <LWIS_PLATFORM_EVENT_ID_SCSC_CONV4201_FINISH>, + <LWIS_PLATFORM_EVENT_ID_SCSC_BCHS0_FINISH>, + <LWIS_PLATFORM_EVENT_ID_SCSC_BCHS1_FINISH>; + int-reg-bits = + <SCSC_INT1_RDMA_M0_FINISH>, + <SCSC_INT1_WDMA_M0_FINISH>, + <SCSC_INT1_WDMA_M1_FINISH>, + <SCSC_INT1_RDMA_VOTF_LOST_CONNECTION>, + <SCSC_INT1_COMP_DEC_ERROR>, + <SCSC_INT1_DJAG_FINISH>, + <SCSC_INT1_SC0_FINISH>, + <SCSC_INT1_SC1_FINISH>, + <SCSC_INT1_PC0_FINISH>, + <SCSC_INT1_PC1_FINISH>, + <SCSC_INT1_CONV4200_FINISH>, + <SCSC_INT1_CONV4201_FINISH>, + <SCSC_INT1_BCHS0_FINISH>, + <SCSC_INT1_BCHS1_FINISH>; + }; + + scsc_cmdq_int: scsc-event-info@2 { + irq-reg-space = "scsc"; + irq-src-reg = <0x0 0x4f8>; + irq-reset-reg = <0x0 0x4fc>; + irq-mask-reg = <0x0 0x4f4>; + + irq-events = + <LWIS_PLATFORM_EVENT_ID_SCSC_STOP_CRPT_OFF_CMDQ_EN>, + <LWIS_PLATFORM_EVENT_ID_SCSC_PRELOAD_FLUSH>, + <LWIS_PLATFORM_EVENT_ID_SCSC_QUE0_OVERFLOW>; + int-reg-bits = + <SCSC_CMDQ_INT_STOP_CRPT_OFF_CMDQ_EN>, + <SCSC_CMDQ_INT_PRELOAD_FLUSH>, + <SCSC_CMDQ_INT_QUE0_OVERFLOW>; + }; +};
diff --git a/dts/gs201-isp.dtsi b/dts/gs201-isp.dtsi new file mode 100644 index 0000000..30c2a6b --- /dev/null +++ b/dts/gs201-isp.dtsi
@@ -0,0 +1,987 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 ISP device tree source + * + * Copyright 2021 Google LLC. + */ + +#include <dt-bindings/clock/gs201.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/gs201.h> +#include "gs201-isp-event-info.dtsi" + +/ { + sysreg_csis_reset: system-controller@1A420500 { + compatible = "samsung,exynos-csis", "syscon"; + reg = <0x0 0x1A420500 0x8>; + }; + + mipi_phy_csis0_m0s4s4s4s4s4: dcphy_m0s4s4s4s4s4_csi0@1A4F1300 { + /* DPHY 4.5 Gbps 4lane */ + /* CPHY 2.5 Gbps 3lane */ + compatible = "samsung,mipi-phy-m0s4s4s4s4s4"; + samsung,pmu-syscon = <&pmu_system_controller>; + isolation = <0x3ebc>; /* PMU address offset */ + samsung,reset-sysreg = <&sysreg_csis_reset>; + reset = <0>; /* reset bit */ + reg = <0x0 0x1A4F1300 0x500>; + owner = <1>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + mipi_phy_csis1_m0s4s4s4s4s4: dcphy_m0s4s4s4s4s4_csi0@1A4F1B00 { + /* DPHY 4.5 Gbps 4lane */ + /* CPHY 2.5 Gbps 3lane */ + compatible = "samsung,mipi-phy-m0s4s4s4s4s4"; + samsung,pmu-syscon = <&pmu_system_controller>; + isolation = <0x3ebc>; /* PMU address offset */ + samsung,reset-sysreg = <&sysreg_csis_reset>; + reset = <1>; /* reset bit */ + reg = <0x0 0x1A4F1B00 0x500>; + owner = <1>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + mipi_phy_csis2_m0s4s4s4s4s4: dcphy_m0s4s4s4s4s4_csi0@1A4F2300 { + /* DPHY 4.5 Gbps 2lane */ + /* CPHY 2.5 Gbps 2lane */ + compatible = "samsung,mipi-phy-m0s4s4s4s4s4"; + samsung,pmu-syscon = <&pmu_system_controller>; + isolation = <0x3ebc>; /* PMU address offset */ + samsung,reset-sysreg = <&sysreg_csis_reset>; + reset = <2>; /* reset bit */ + reg = <0x0 0x1A4F2300 0x300>; + owner = <1>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + mipi_phy_csis3_m0s4s4s4s4s4: dcphy_m0s4s4s4s4s4_csi0@1A4F2600 { + /* DPHY 4.5 Gbps 2lane */ + /* CPHY 2.5 Gbps 1lane */ + compatible = "samsung,mipi-phy-m0s4s4s4s4s4"; + samsung,pmu-syscon = <&pmu_system_controller>; + isolation = <0x3ebc>; /* PMU address offset */ + samsung,reset-sysreg = <&sysreg_csis_reset>; + reset = <3>; /* reset bit */ + reg = <0x0 0x1A4F2600 0x300>; + owner = <1>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + mipi_phy_csis4_m0s4s4s4s4s4: dcphy_m0s4s4s4s4s4_csi0@1A4F2B00 { + /* DPHY 4.5 Gbps 2lane */ + /* CPHY 2.5 Gbps 2lane */ + compatible = "samsung,mipi-phy-m0s4s4s4s4s4"; + samsung,pmu-syscon = <&pmu_system_controller>; + isolation = <0x3ebc>; /* PMU address offset */ + samsung,reset-sysreg = <&sysreg_csis_reset>; + reset = <4>; /* reset bit */ + reg = <0x0 0x1A4F2B00 0x300>; + owner = <1>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + mipi_phy_csis5_m0s4s4s4s4s4: dcphy_m0s4s4s4s4s4_csi0@1A4F2E00 { + /* DPHY 4.5 Gbps 2lane */ + /* CPHY 2.5 Gbps 1lane */ + compatible = "samsung,mipi-phy-m0s4s4s4s4s4"; + samsung,pmu-syscon = <&pmu_system_controller>; + isolation = <0x3ebc>; /* PMU address offset */ + samsung,reset-sysreg = <&sysreg_csis_reset>; + reset = <5>; /* reset bit */ + reg = <0x0 0x1A4F2E00 0x300>; + owner = <1>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + mipi_phy_csis6_m0s4s4s4s4s4: dcphy_m0s4s4s4s4s4_csi0@1A4F3300 { + /* DPHY 4.5 Gbps 2lane */ + /* CPHY 2.5 Gbps 2lane */ + compatible = "samsung,mipi-phy-m0s4s4s4s4s4"; + samsung,pmu-syscon = <&pmu_system_controller>; + isolation = <0x3ebc>; /* PMU address offset */ + samsung,reset-sysreg = <&sysreg_csis_reset>; + reset = <6>; /* reset bit */ + reg = <0x0 0x1A4F3300 0x300>; + owner = <1>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + mipi_phy_csis7_m0s4s4s4s4s4: dcphy_m0s4s4s4s4s4_csi0@1A4F3600 { + /* DPHY 4.5 Gbps 2lane */ + /* CPHY 2.5 Gbps 1lane */ + compatible = "samsung,mipi-phy-m0s4s4s4s4s4"; + samsung,pmu-syscon = <&pmu_system_controller>; + isolation = <0x3ebc>; /* PMU address offset */ + samsung,reset-sysreg = <&sysreg_csis_reset>; + reset = <7>; /* reset bit */ + reg = <0x0 0x1A4F3600 0x300>; + owner = <1>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + lwis_top: lwis_top@0 { + compatible = "google,lwis-top-device"; + + /* Device node name */ + node-name = "top"; + }; + + lwis_dpm: lwis_dpm@0 { + compatible = "google,lwis-dpm-device"; + + /* Device node name */ + node-name = "dpm"; + }; + + lwis_csi: lwis_csi@1A440000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "csi"; + + /* Register space */ + reg = + <0x0 0x1A440000 0x1000>, /* MIPI-CSIS0 */ + <0x0 0x1A450000 0x1000>, /* MIPI-CSIS1 */ + <0x0 0x1A460000 0x1000>, /* MIPI-CSIS2 */ + <0x0 0x1A470000 0x1000>, /* MIPI-CSIS3 */ + <0x0 0x1A480000 0x1000>, /* MIPI-CSIS4 */ + <0x0 0x1A490000 0x1000>, /* MIPI-CSIS5 */ + <0x0 0x1A4A0000 0x1000>, /* MIPI-CSIS6 */ + <0x0 0x1A4B0000 0x1000>, /* MIPI-CSIS7 */ + <0x0 0x1A4C0000 0x100>, /* CSIS EBUF */ + <0x0 0x1A4D0000 0x10000>, /* CSIS DMA */ + <0x0 0x1A4F0000 0x10000>, /* CSIS PHY */ + <0x0 0x1A420000 0x10000>; /* SYSREG CSIS */ + + reg-names = + "csis-link0", + "csis-link1", + "csis-link2", + "csis-link3", + "csis-link4", + "csis-link5", + "csis-link6", + "csis-link7", + "csis-ebuf", + "csis-dma", + "csis-phy", + "csis-sysreg"; + + /* Clocks */ + clocks = + <&clock UMUX_CLKCMU_CSIS_NOC>, + <&clock GATE_DFTMUX_CMU_CIS_CLK0>, + <&clock GATE_DFTMUX_CMU_CIS_CLK1>, + <&clock GATE_DFTMUX_CMU_CIS_CLK2>, + <&clock GATE_DFTMUX_CMU_CIS_CLK3>, + <&clock GATE_DFTMUX_CMU_CIS_CLK4>, + <&clock GATE_DFTMUX_CMU_CIS_CLK5>, + <&clock GATE_DFTMUX_CMU_CIS_CLK6>, + <&clock GATE_DFTMUX_CMU_CIS_CLK7>, + <&clock CIS_CLK0>, + <&clock CIS_CLK1>, + <&clock CIS_CLK2>, + <&clock CIS_CLK3>, + <&clock CIS_CLK4>, + <&clock CIS_CLK5>, + <&clock CIS_CLK6>, + <&clock CIS_CLK7>; + clock-names = + "UMUX_CLKCMU_CSIS_NOC", + "GATE_DFTMUX_CMU_CIS_CLK0", + "GATE_DFTMUX_CMU_CIS_CLK1", + "GATE_DFTMUX_CMU_CIS_CLK2", + "GATE_DFTMUX_CMU_CIS_CLK3", + "GATE_DFTMUX_CMU_CIS_CLK4", + "GATE_DFTMUX_CMU_CIS_CLK5", + "GATE_DFTMUX_CMU_CIS_CLK6", + "GATE_DFTMUX_CMU_CIS_CLK7", + "CIS_CLK0", + "CIS_CLK1", + "CIS_CLK2", + "CIS_CLK3", + "CIS_CLK4", + "CIS_CLK5", + "CIS_CLK6", + "CIS_CLK7"; + clock-rates = <0>; + + clock-family = <CAMERA_CLOCK_FAMILY_CAM>; + bts-scenario = "camera_default"; + + interrupts = + <0 IRQ_CSIS0_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS0_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS0_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS0_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS1_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS1_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS1_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS1_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS2_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS2_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS2_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS2_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS3_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS3_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS3_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS3_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS4_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS4_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS4_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS4_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS5_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS5_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS5_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS5_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS6_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS6_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS6_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS6_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS7_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS7_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS7_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS7_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_ZSL_DMA0_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_ZSL_DMA1_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_ZSL_DMA2_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_STRP_DMA0_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_STRP_DMA1_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_STRP_DMA2_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS_DMA0_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS_DMA1_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS_DMA2_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS_DMA3_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_EBUF_OVERFLOW0_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_EBUF_OVERFLOW1_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_EBUF_OVERFLOW2_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_EBUF_OVERFLOW3_CSIS IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "csi-link0-src0", + "csi-link0-src1", + "csi-link0-fs", + "csi-link0-fe", + "csi-link1-src0", + "csi-link1-src1", + "csi-link1-fs", + "csi-link1-fe", + "csi-link2-src0", + "csi-link2-src1", + "csi-link2-fs", + "csi-link2-fe", + "csi-link3-src0", + "csi-link3-src1", + "csi-link3-fs", + "csi-link3-fe", + "csi-link4-src0", + "csi-link4-src1", + "csi-link4-fs", + "csi-link4-fe", + "csi-link5-src0", + "csi-link5-src1", + "csi-link5-fs", + "csi-link5-fe", + "csi-link6-src0", + "csi-link6-src1", + "csi-link6-fs", + "csi-link6-fe", + "csi-link7-src0", + "csi-link7-src1", + "csi-link7-fs", + "csi-link7-fe", + "zsl-dma0", + "zsl-dma1", + "zsl-dma2", + "strp-dma0", + "strp-dma1", + "strp-dma2", + "csis-dma0", + "csis-dma1", + "csis-dma2", + "csis-dma3", + "csi-ebuf0", + "csi-ebuf1", + "csi-ebuf2", + "csi-ebuf3"; + interrupt-event-infos = + <&csi_ctx0_csis_int0>, + <&csi_ctx0_csis_int1>, + <&csi_ctx0_fs_int>, + <&csi_ctx0_fe_int>, + <&csi_ctx1_csis_int0>, + <&csi_ctx1_csis_int1>, + <&csi_ctx1_fs_int>, + <&csi_ctx1_fe_int>, + <&csi_ctx2_csis_int0>, + <&csi_ctx2_csis_int1>, + <&csi_ctx2_fs_int>, + <&csi_ctx2_fe_int>, + <&csi_ctx3_csis_int0>, + <&csi_ctx3_csis_int1>, + <&csi_ctx3_fs_int>, + <&csi_ctx3_fe_int>, + <&csi_ctx4_csis_int0>, + <&csi_ctx4_csis_int1>, + <&csi_ctx4_fs_int>, + <&csi_ctx4_fe_int>, + <&csi_ctx5_csis_int0>, + <&csi_ctx5_csis_int1>, + <&csi_ctx5_fs_int>, + <&csi_ctx5_fe_int>, + <&csi_ctx6_csis_int0>, + <&csi_ctx6_csis_int1>, + <&csi_ctx6_fs_int>, + <&csi_ctx6_fe_int>, + <&csi_ctx7_csis_int0>, + <&csi_ctx7_csis_int1>, + <&csi_ctx7_fs_int>, + <&csi_ctx7_fe_int>, + <&csi_zsl_dma_ctx0_int>, + <&csi_zsl_dma_ctx1_int>, + <&csi_zsl_dma_ctx2_int>, + <&csi_strp_dma_ctx0_int>, + <&csi_strp_dma_ctx1_int>, + <&csi_strp_dma_ctx2_int>, + <&csi_csis_dma_ctx0_int>, + <&csi_csis_dma_ctx1_int>, + <&csi_csis_dma_ctx2_int>, + <&csi_csis_dma_ctx3_int>, + <&csi_ebuf0_int>, + <&csi_ebuf1_int>, + <&csi_ebuf2_int>, + <&csi_ebuf3_int>; + + phys = + <&mipi_phy_csis0_m0s4s4s4s4s4 0>, + <&mipi_phy_csis1_m0s4s4s4s4s4 0>, + <&mipi_phy_csis2_m0s4s4s4s4s4 0>, + <&mipi_phy_csis3_m0s4s4s4s4s4 0>, + <&mipi_phy_csis4_m0s4s4s4s4s4 0>, + <&mipi_phy_csis5_m0s4s4s4s4s4 0>, + <&mipi_phy_csis6_m0s4s4s4s4s4 0>, + <&mipi_phy_csis7_m0s4s4s4s4s4 0>; + phy-names = + "csis0_dcphy", + "csis1_dcphy", + "csis2_dcphy", + "csis3_dcphy", + "csis4_dcphy", + "csis5_dcphy", + "csis6_dcphy", + "csis7_dcphy"; + + iommus = + <&sysmmu_csis0>, + <&sysmmu_csis1>; + power-domains = <&pd_pdp>; + samsung,iommu-group = <&iommu_group_isp>; + lwis,iommu-best-fit-algo; + samsung,tzmp = "true"; + }; + + lwis_pdp: lwis_pdp@1AA40000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "pdp"; + + /* Register space */ + reg = + <0x0 0x1AA40000 0x10000>, /* PDP CORE0 */ + <0x0 0x1AA50000 0x10000>, /* PDP CORE1 */ + <0x0 0x1AA60000 0x10000>, /* PDP CORE2 */ + <0x0 0x1AA20000 0x10000>, /* SYSREG PDP */ + <0x0 0x1A820400 0x4>, /* SYSREG G3AA */ + <0x0 0x1AC40000 0x10000>, /* IPP CORE0 */ + <0x0 0x1AC50000 0x10000>, /* IPP CORE1 */ + <0x0 0x1AC60000 0x10000>, /* IPP CORE2 */ + <0x0 0x1A840000 0x20000>, /* G3AA */ + <0x0 0x1A800000 0x10000>; /* G3AA CMU*/ + reg-names = + "pdp-core0", + "pdp-core1", + "pdp-core2", + "sysreg-pdp", + "sysreg-g3aa", + "ipp-core0", + "ipp-core1", + "ipp-core2", + "g3aa-core", + "g3aa-cmu"; + + clocks = + <&clock UMUX_CLKCMU_PDP_NOC>, + <&clock UMUX_CLKCMU_PDP_VRA>; + clock-names = + "UMUX_CLKCMU_PDP_NOC", + "UMUX_CLKCMU_PDP_VRA"; + clock-rates = <0>; + + clock-family = <CAMERA_CLOCK_FAMILY_CAM>; + + interrupts = + <0 IRQ_PDP_TOP0_PDP IRQ_TYPE_LEVEL_HIGH>, /* PDP_CORE0 */ + <0 IRQ_PDP_TOP1_PDP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_PDP_TOP2_PDP IRQ_TYPE_LEVEL_HIGH>, /* PDP_CORE1 */ + <0 IRQ_PDP_TOP3_PDP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_PDP_TOP4_PDP IRQ_TYPE_LEVEL_HIGH>, /* PDP_CORE2 */ + <0 IRQ_PDP_TOP5_PDP IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "pdp-ctx0-src1", + "pdp-ctx0-src2", + "pdp-ctx1-src1", + "pdp-ctx1-src2", + "pdp-ctx2-src1", + "pdp-ctx2-src2"; + interrupt-event-infos = + <&pdp_ctx0_int_src1>, + <&pdp_ctx0_int_src2>, + <&pdp_ctx1_int_src1>, + <&pdp_ctx1_int_src2>, + <&pdp_ctx2_int_src1>, + <&pdp_ctx2_int_src2>; + + iommus = + <&sysmmu_csis1>, + <&sysmmu_ipp>, + <&sysmmu_g3aa>; + power-domains = <&pd_pdp>; + samsung,iommu-group = <&iommu_group_isp>; + }; + + lwis_ipp: lwis_ipp@1AC40000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "ipp"; + + /* Register space */ + reg = + <0x0 0x1AC40000 0x10000>, /* IPP0 */ + <0x0 0x1AC50000 0x10000>, /* IPP1 */ + <0x0 0x1AC60000 0x10000>; /* IPP2 */ + reg-names = + "ipp0", + "ipp1", + "ipp2"; + + clocks = <&clock UMUX_CLKCMU_IPP_NOC>; + clock-names = "UMUX_CLKCMU_IPP_NOC"; + clock-rates = <0>; + clock-family = <CAMERA_CLOCK_FAMILY_CAM>; + + interrupts = + <0 IRQ_IPP_CH0_0_IPP IRQ_TYPE_LEVEL_HIGH>, /* IPP0 */ + <0 IRQ_IPP_CH0_1_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_IPP_CH0_0_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_IPP_CH0_1_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_IPP_CH1_0_IPP IRQ_TYPE_LEVEL_HIGH>, /* IPP1 */ + <0 IRQ_IPP_CH1_1_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_IPP_CH1_0_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_IPP_CH1_1_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_IPP_CH2_0_IPP IRQ_TYPE_LEVEL_HIGH>, /* IPP2 */ + <0 IRQ_IPP_CH2_1_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_IPP_CH2_0_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_IPP_CH2_1_IPP IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "ipp0-int1", + "ipp0-int2", + "ipp0_fro_int0", + "ipp0_fro_int1", + "ipp1-int1", + "ipp1-int2", + "ipp1_fro_int0", + "ipp1_fro_int1", + "ipp2-int1", + "ipp2-int2", + "ipp2_fro_int0", + "ipp2_fro_int1"; + interrupt-event-infos = + <&ipp_ctx0_int1>, + <&ipp_ctx0_int2>, + <&ipp_fro_ctx0_int0>, + <&ipp_fro_ctx0_int1>, + <&ipp_ctx1_int1>, + <&ipp_ctx1_int2>, + <&ipp_fro_ctx1_int0>, + <&ipp_fro_ctx1_int1>, + <&ipp_ctx2_int1>, + <&ipp_ctx2_int2>, + <&ipp_fro_ctx2_int0>, + <&ipp_fro_ctx2_int1>; + + iommus = <&sysmmu_ipp>; + samsung,iommu-group = <&iommu_group_isp>; + + /* Adjust Thread priority */ + transaction-thread-priority = <99>; + }; + + lwis_gtnr_align: lwis_gtnr_align@1AC80000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "gtnr-align"; + + /* Register space */ + reg = + <0x0 0x1AC80000 0x10000>, /* TNR_ALIGN */ + <0x0 0x1AC03100 0x4>, /* TNR_A_CLOCK */ + <0x0 0x1AEB4400 0x88>, /* TNR_ALIGN_M0 */ + <0x0 0x1AEC4400 0x88>; /* TNR_ALIGN_M4 */ + reg-names = + "tnr_align", + "tnr_a_clock", + "tnr_align_m0", + "tnr_align_m4"; + + clocks = + <&clock UMUX_CLKCMU_IPP_NOC>, + <&clock UMUX_CLKCMU_DNS_NOC>; + clock-names = + "UMUX_CLKCMU_IPP_NOC", + "UMUX_CLKCMU_DNS_NOC"; + clock-rates = <0>; + clock-family = <CAMERA_CLOCK_FAMILY_CAM>; + + interrupts = + <0 IRQ_TNR_A_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MUTE_GTNR_ALIGN_IPP IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "gtnr-align-int", + "gtnr-align-mute"; + interrupt-event-infos = + <>nr_align_int>, + <>nr_align_secu_int_mute>; + + iommus = + <&sysmmu_ipp>, + <&sysmmu_dns>; + samsung,iommu-group = <&iommu_group_isp>; + }; + + lwis_gtnr_merge: lwis_gtnr_merge@1BC40000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "gtnr-merge"; + + /* Register space */ + reg = + <0x0 0x1BC40000 0x10000>, /* TNR */ + <0x0 0x1BE84000 0xA00>, /* TNR SSMT D0 */ + <0x0 0x1BE94000 0xA00>, /* TNR SSMT D1 */ + <0x0 0x1BEA4000 0xA00>, /* TNR SSMT D2 */ + <0x0 0x1BEB4000 0xA00>, /* TNR SSMT D3 */ + <0x0 0x1BEC4000 0xA00>, /* TNR SSMT D4 */ + <0x0 0x1BED4000 0xA00>, /* TNR SSMT D5 */ + <0x0 0x1BEE4000 0xA00>, /* TNR SSMT D6 */ + <0x0 0x1BEF4000 0xA00>, /* TNR SSMT D7 */ + <0x0 0x1BC030E4 0x8>, /* TNR_QCH */ + <0x0 0x1BC20400 0x4>; /* TNR SYSREG */ + reg-names = + "tnr", + "tnr_ssmt_d0", + "tnr_ssmt_d1", + "tnr_ssmt_d2", + "tnr_ssmt_d3", + "tnr_ssmt_d4", + "tnr_ssmt_d5", + "tnr_ssmt_d6", + "tnr_ssmt_d7", + "tnr_qch", + "tnr_sysreg"; + + clocks = <&clock UMUX_CLKCMU_TNR_NOC>; + clock-names = "UMUX_CLKCMU_TNR_NOC"; + clock-rates = <0>; + + clock-family = <CAMERA_CLOCK_FAMILY_TNR>; + + interrupts = + <0 IRQ_TNR_0_TNR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_TNR_1_TNR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_TNR_0_TNR IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "gtnr-merge-int0", + "gtnr-merge-int1", + "gtnr-merge-cmdq-int"; + interrupt-event-infos = + <>nr_merge_int0>, + <>nr_merge_int1>, + <>nr_merge_cmdq_int>; + + iommus = + <&sysmmu_tnr0>, + <&sysmmu_tnr1>, + <&sysmmu_tnr2>, + <&sysmmu_tnr3>, + <&sysmmu_tnr4>; + samsung,iommu-group = <&iommu_group_isp>; + }; + + lwis_g3aa: lwis_g3aa@1A840000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "g3aa"; + + /* Register space */ + reg = + <0x0 0x1A840000 0x20000>, /* G3AA */ + <0x0 0x1A820000 0x10000>, /* SYSREG_G3AA */ + <0x0 0x1A860000 0x10000>; /* LINEBUFFER_G3AA */ + reg-names = + "g3aa", + "sysreg-g3aa", + "linebuffer-g3aa"; + + clocks = <&clock UMUX_CLKCMU_G3AA_G3AA>; + clock-names = "UMUX_CLKCMU_G3AA_G3AA"; + clock-rates = <0>; + clock-family = <CAMERA_CLOCK_FAMILY_CAM>; + + interrupts = + <0 IRQ_G3AA_G3AA IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_G3AA_G3AA IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_G3AA_G3AA IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_G3AA_G3AA IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "g3aa-ctx0-int", + "g3aa-ctx1-int", + "g3aa-ctx2-int", + "g3aa-err-int"; + interrupt-event-infos = + <&g3aa_ctx0_interrupts>, + <&g3aa_ctx1_interrupts>, + <&g3aa_ctx2_interrupts>, + <&g3aa_error_interrupts>; + + iommus = <&sysmmu_g3aa>; + samsung,iommu-group = <&iommu_group_isp>; + + /* Adjust Thread priority */ + transaction-thread-priority = <99>; + }; + + lwis_itp: lwis_itp@1B450000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "itp"; + + /* Register space */ + reg = + <0x0 0x1B450000 0x10000>, /* ITP */ + <0x0 0x1B040000 0x10000>, /* DNS */ + <0x0 0x1B740000 0x10000>, /* ITSC */ + <0x0 0x1B020000 0x10000>, /* SYSREG DNS */ + <0x0 0x1B894000 0xA00>; /* SSMT D0 ITSC */ + reg-names = + "itp", + "dns", + "itsc", + "sysreg_dns", + "ssmt_d0_itsc"; + + clocks = + <&clock UMUX_CLKCMU_ITP_NOC>, + <&clock UMUX_CLKCMU_DNS_NOC>, + <&clock UMUX_CLKCMU_MCSC_ITSC>; + clock-names = + "UMUX_CLKCMU_ITP_NOC", + "UMUX_CLKCMU_DNS_NOC", + "UMUX_CLKCMU_MCSC_ITSC"; + clock-rates = <0>; + + clock-family = <CAMERA_CLOCK_FAMILY_INTCAM>; + + interrupts = + <0 INTREQ_ITP_0_ITP IRQ_TYPE_LEVEL_HIGH>, + <0 INTREQ_ITP_0_ITP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_DNS_0_DNS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_DNS_1_DNS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_DNS_0_DNS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_ITSC_0_MCSC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_ITSC_1_MCSC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_ITSC_0_MCSC IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "itp-itp-int0", + "itp-itp-cmdq-int", + "itp-dns-int0", + "itp-dns-int1", + "itp-dns-cmdq-int", + "itp-itsc-int0", + "itp-itsc-int1", + "itp-itsc-cmdq-int"; + interrupt-event-infos = + <&itp_itp_int0>, + <&itp_itp_cmdq_int>, + <&itp_dns_int0>, + <&itp_dns_int1>, + <&itp_dns_cmdq_int>, + <&itp_itsc_int0>, + <&itp_itsc_int1>, + <&itp_itsc_cmdq_int>; + + iommus = + <&sysmmu_dns>, + <&sysmmu_mcsc0>; + samsung,iommu-group = <&iommu_group_isp>; + samsung,tzmp = "true"; + + transaction-thread-priority = <99>; + }; + + lwis_mcsc: lwis_mcsc@1B760000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "mcsc"; + + /* Register space */ + reg = + <0x0 0x1B760000 0x10000>, /* MCSC */ + <0x0 0x1B8C4000 0xA00>; /* SSMT D0 MCSC */ + reg-names = + "mcsc", + "ssmt_d0_mcsc"; + + clocks = <&clock UMUX_CLKCMU_MCSC_MCSC>; + clock-names = "UMUX_CLKCMU_MCSC_MCSC"; + clock-rates = <0>; + + clock-family = <CAMERA_CLOCK_FAMILY_INTCAM>; + + interrupts = + <0 IRQ_MCSC_0_MCSC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MCSC_1_MCSC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MCSC_0_MCSC IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "mcsc-int0", + "mcsc-int1", + "mcsc-cmdq-int"; + interrupt-event-infos = + <&mcsc_int0>, + <&mcsc_int1>, + <&mcsc_cmdq_int>; + + iommus = + <&sysmmu_mcsc1>, + <&sysmmu_mcsc2>; + samsung,iommu-group = <&iommu_group_isp>; + samsung,tzmp = "true"; + }; + + lwis_scsc: lwis_scsc@1D080000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "scsc"; + + /* Register space */ + reg = + <0x0 0x1D080000 0x10000>, /* SCSC */ + <0x0 0x1D204000 0xA00>; /* SSMT SCSC */ + reg-names = + "scsc", + "ssmt_d0_scsc"; + + clocks = <&clock UMUX_CLKCMU_GDC_SCSC>; + clock-names = "UMUX_CLKCMU_GDC_SCSC"; + clock-rates = <0>; + + clock-family = <CAMERA_CLOCK_FAMILY_INTCAM>; + + interrupts = + <0 IRQ_SCSC_IRQ_0_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SCSC_IRQ_1_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SCSC_IRQ_0_GDC IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "scsc-int0", + "scsc-int1", + "scsc-cmdq-int"; + interrupt-event-infos = + <&scsc_int0>, + <&scsc_int1>, + <&scsc_cmdq_int>; + + iommus = <&sysmmu_gdc2>; + samsung,iommu-group = <&iommu_group_isp>; + samsung,tzmp = "true"; + }; + + lwis_gdc0: lwis_gdc@1D040000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "gdc0"; + + /* Register space */ + reg = + <0x0 0x1D040000 0x10000>, /* GDC0 */ + <0x0 0x1D134000 0xA00>; /* GDC0 SSMT */ + reg-names = + "gdc", + "gdc_ssmt"; + + clocks = <&clock UMUX_CLKCMU_GDC_GDC0>; + clock-names = "UMUX_CLKCMU_GDC_GDC0"; + clock-rates = <0>; + + clock-family = <CAMERA_CLOCK_FAMILY_INTCAM>; + + interrupts = + <0 IRQ_GDC0_IRQ_0_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_GDC0_IRQ_1_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_GDC0_IRQ_0_GDC IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "gdc-int0", + "gdc-int1", + "gdc-cmdq-int"; + interrupt-event-infos = + <&gdc_int0>, + <&gdc_int1>, + <&gdc_cmdq_int>; + + iommus = <&sysmmu_gdc0>; + samsung,iommu-group = <&iommu_group_isp>; + samsung,tzmp = "true"; + }; + + lwis_gdc1: lwis_gdc@1D060000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "gdc1"; + + /* Register space */ + reg = + <0x0 0x1D060000 0x10000>, /* GDC1 */ + <0x0 0x1D144000 0xA00>; /* GDC1 SSMT */ + reg-names = + "gdc", + "gdc_ssmt"; + + clocks = <&clock UMUX_CLKCMU_GDC_GDC1>; + clock-names = "UMUX_CLKCMU_GDC_GDC1"; + clock-rates = <0>; + clock-family = <CAMERA_CLOCK_FAMILY_INTCAM>; + + interrupts = + <0 IRQ_GDC1_IRQ_0_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_GDC1_IRQ_1_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_GDC1_IRQ_0_GDC IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "gdc-int0", + "gdc-int1", + "gdc-cmdq-int"; + interrupt-event-infos = + <&gdc_int0>, + <&gdc_int1>, + <&gdc_cmdq_int>; + + iommus = <&sysmmu_gdc1>; + samsung,iommu-group = <&iommu_group_isp>; + samsung,tzmp = "true"; + }; + + lwis_votf: lwis_votf@1A4E0000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "votf"; + + /* Register space */ + reg = + <0x0 0x1A4E0000 0x10000>, /* CSIS C2SERV */ + <0x0 0x1AA70000 0x10000>, /* PDP C2SERV */ + <0x0 0x1B050000 0x10000>, /* DNS C2SERV */ + <0x0 0x1BC50000 0x10000>, /* TNR C2SERV */ + <0x0 0x1B750000 0x10000>, /* ITSC C2SERV */ + <0x0 0x1B770000 0x10000>, /* MCSC C2SERV */ + <0x0 0x1D050000 0x10000>, /* GDC0 C2SERV */ + <0x0 0x1D070000 0x10000>, /* GDC1 C2SERV */ + <0x0 0x1D090000 0x10000>; /* SCSC C2SERV */ + reg-names = + "csis-c2serv", + "pdp-c2serv", + "dns-c2serv", + "tnr-c2serv", + "itsc-c2serv", + "mcsc-c2serv", + "gdc0-c2serv", + "gdc1-c2serv", + "scsc-c2serv"; + + clocks = + <&clock UMUX_CLKCMU_CSIS_NOC>, + <&clock UMUX_CLKCMU_PDP_NOC>, + <&clock UMUX_CLKCMU_DNS_NOC>, + <&clock UMUX_CLKCMU_TNR_NOC>, + <&clock UMUX_CLKCMU_ITP_NOC>, + <&clock UMUX_CLKCMU_MCSC_ITSC>, + <&clock UMUX_CLKCMU_GDC_GDC0>, + <&clock UMUX_CLKCMU_GDC_GDC1>, + <&clock UMUX_CLKCMU_GDC_SCSC>; + clock-names = + "UMUX_CLKCMU_CSIS_NOC", + "UMUX_CLKCMU_PDP_NOC", + "UMUX_CLKCMU_DNS_NOC", + "UMUX_CLKCMU_TNR_NOC", + "UMUX_CLKCMU_ITP_NOC", + "UMUX_CLKCMU_MCSC_NOC", + "UMUX_CLKCMU_GDC_GDC0", + "UMUX_CLKCMU_GDC_GDC1", + "UMUX_CLKCMU_GDC_SCSC"; + clock-rates = <0>; + + iommus = + <&sysmmu_gdc0>, + <&sysmmu_gdc1>, + <&sysmmu_gdc2>, + <&sysmmu_ipp>, + <&sysmmu_dns>, + <&sysmmu_mcsc0>, + <&sysmmu_mcsc1>, + <&sysmmu_mcsc2>, + <&sysmmu_tnr0>, + <&sysmmu_tnr1>, + <&sysmmu_tnr2>, + <&sysmmu_tnr3>, + <&sysmmu_tnr4>, + <&sysmmu_csis0>, + <&sysmmu_csis1>; + samsung,iommu-group = <&iommu_group_isp>; + + power-domains = + <&pd_pdp>, + <&pd_csis>, + <&pd_gdc>, + <&pd_itp>, + <&pd_mcsc>, + <&pd_tnr>; + }; + + lwis_slc: lwis_slc@0 { + compatible = "google,lwis-slc-device"; + + /* Device node name */ + node-name = "slc"; + + /* SLC partitions */ + pt_id = + "CAMERA2WAY", + "CAMERA4WAY0", + "CAMERA4WAY1", + "CAMERA4WAY2", + "CAMERA6WAY0", + "CAMERA6WAY1", + "CAMERA6WAY2", + "CAMERA8WAY0"; + + pt_size = <512 1024 1024 1024 1536 1536 1536 2048>; + }; +};
diff --git a/dts/gs201-ldaf.dtsi b/dts/gs201-ldaf.dtsi new file mode 100644 index 0000000..3fab09e --- /dev/null +++ b/dts/gs201-ldaf.dtsi
@@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * gs201 ldaf(Laser Detection Auto Focus) device tree source + * Copyright 2021 Google LLC. + * + */ + +#include <dt-bindings/gpio/gpio.h> + +&pinctrl_1 { + ldaf_irq: ldaf-irq { + samsung,pins = "gpa6-5"; /* XEINT_5 */ + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; +}; + +&hsi2c_1 { + /* VL53L1 */ + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + stmvl53l1: stmvl53l1@29 { + compatible = "st,stmvl53l1"; + reg = <0x29>; + /* XAPC_MCLK8: GPP17[0] */ + xsdn-gpio = <&gpp17 0 GPIO_ACTIVE_LOW>; + /* XAPC_USI4_CTSn_CSn: GPP8[3] */ + pwren-gpio = <&gpp8 3 GPIO_ACTIVE_HIGH>; + /* XEINT_5: GPA6[5] */ + intr-gpio = <&gpa6 5 GPIO_ACTIVE_LOW>; + + vio-type = "regulator"; + vio-supply = <&s_ldo12_reg>; + vio-voltage = <1800000>; + + pinctrl-names = "default"; + pinctrl-0 = <&ldaf_irq>; + + status = "ok"; + }; +};
diff --git a/dts/gs201-max20339-ovp.dtsi b/dts/gs201-max20339-ovp.dtsi new file mode 100644 index 0000000..0973295 --- /dev/null +++ b/dts/gs201-max20339-ovp.dtsi
@@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021, Google LLC + * + * MAX20339 OVP device node. + */ +#include <dt-bindings/gpio/gpio.h> +#include <arm64/exynos/exynos-pinctrl.h> + +&hsi2c_13{ + #address-cells = <1>; + #size-cells = <0>; + + max20339_ovp: max20339ovp@35 { + status = "okay"; + compatible = "max20339ovp"; + reg = <0x35>; + + /* OVP interrupt on MW pmic GPIO6 */ + max20339,irq-gpio = <&max777x9_gpio 5 GPIO_ACTIVE_LOW>; + + /* LoadSwitch 1 and LoadSwitch 2 mapped as gpios. */ + max20339_gpio: max20339_gpio { + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + }; +}; + +&max77759tcpc { + /delete-property/ ovp-present; + in-switch-gpio = <&max20339_gpio 4 GPIO_ACTIVE_HIGH>; + max20339,ovp = <&max20339_ovp>; +};
diff --git a/dts/gs201-mfc.dtsi b/dts/gs201-mfc.dtsi new file mode 100644 index 0000000..992a0dd --- /dev/null +++ b/dts/gs201-mfc.dtsi
@@ -0,0 +1,464 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SAMSUNG EXYNOS SoC mfc device tree source + * + * Copyright (c) 2020 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + */ + +#include <dt-bindings/interrupt-controller/gs201.h> + +/ { + mfc: mfc { + /* Basic setting */ + compatible = "samsung,exynos-mfc"; + + /* for vb2 device */ + iommus = <&sysmmu_mfc0>, <&sysmmu_mfc1>; + samsung,iommu-group = <&iommu_group_mfc>; + samsung,iommu-reserved-map = <0x0 0x0 0x10000000>, + <0x0 0x10000000 0x100000>; + /* Enable if there is vOTF */ + /* samsung,iommu-identity-map = <0x0 0x15E1F000 0x10000>; */ + + samsung,tzmp; + + /* MFC version */ + /* ip_ver is set in gs101-a0.dts and gs101-b0.dts */ + + /* Debug mode (disable needs sysmmu,async-fault) */ + debug_mode = <0>; + + /* NAL-Q size */ + nal_q_entry_size = <512>; + nal_q_dump_size = <376>; + + /* Features <on/off version> */ + nal_q = <1 0x0>; + skype = <1 0x0>; + black_bar = <0 0x0>; + color_aspect_dec = <1 0x0>; + static_info_dec = <1 0x0>; + color_aspect_enc = <1 0x0>; + static_info_enc = <1 0x180314>; + hdr10_plus = <1 0x180709>; + vp9_stride_align = <1 0x0>; + sbwc_uncomp = <1 0x190702>; + mem_clear = <1 0x0>; + /* Support from v11.0 (except 11.2) */ + wait_fw_status = <1 0x190122>; + wait_nalq_status = <1 0x191107>; + /* DRM switch predict for cache flush */ + drm_switch_predict = <1 0x0>; + /* Support SBWC per-frame control for encoder src */ + sbwc_enc_src_ctrl = <1 0x200110>; + average_qp = <1 0x201030>; + mv_search_mode = <1 0x201118>; + enc_idr_flag = <1 0x210614>; + min_quality_mode = <1 0x210629>; + hevc_pic_output_flag = <1 0x221109>; + /* Use metadata interface */ + metadata_interface = <1 0x200910>; + /* Support HDR10+ full data */ + hdr10_plus_full = <1 0x200910>; + + /* AV1 Decoder */ + support_av1_dec = <0>; + /* Support AV1 Film Grain Feature */ + av1_film_grain = <0 0>; + + /* Default 10bit format for decoding (1: P010, 0: 8+2) */ + P010_decoding = <1>; + /* Dithering option for 8bit display device */ + dithering_enable = <0>; + /* Decoder stride align (default: 16) */ + stride_align = <64>; + /* Decoder stride calculation type (new: 1, old: 0) */ + stride_type = <1>; + /* Encoder 8K entropy mode (0: CABAC fix, 1: selectable) */ + support_8K_cavlc = <1>; + + /* Formats */ + support_10bit = <1>; + support_422 = <1>; + support_rgb = <1>; + + /* SBWC */ + support_sbwc = <1>; + support_sbwcl = <1>; + support_afbc = <1>; + + /* SBWC decoder max resolution */ + sbwc_dec_max_width = <1920>; + sbwc_dec_max_height = <1088>; + sbwc_dec_hdr10_off = <1>; + + /* HDR10+ num max window */ + max_hdr_win = <1>; + + /* error type for sync_point display */ + /* (1: concealment display, 2: error display, 3: error no display) */ + display_err_type = <2>; + + /* FW base security ctrl */ + /* security_ctrl is set in gs101-a0.dts and gs101-b0.dts */ + + /* Encoder min bit count control */ + enc_min_bit_cnt = <1>; + + /* Encoder default parameter: max number is 100 */ + enc_param_num = <25>; + enc_param_addr = <0xF7B4 0xF7B8 0xF7B0 0xF798 0xFA2C + 0xF790 0xFA34 0xFA38 0xFA3C 0xF7C0 + 0xF7C8 0xF7CC 0xFA60 0xFDD4 0xFDDC + 0xFB54 0xFB58 0xFBA8 0xFD90 0xFD94 + 0xFD40 0xFD48 0xFD4C 0xFD50 0xFD80>; + enc_param_val = <0x100 0x100 0x0 0x4000 0x3FD00 + 0x0 0x0 0x2710 0x3E8 0x0 + 0x0 0x0 0x0 0x8050F215 0x0 + 0x3011 0x0 0x0 0x2D 0xA00 + 0x1D 0xF4240 0x33003300 0x2 0x1>; + + /* BW <peak, read, write> : KB/UHD frame */ + bw_enc_h264 = <45456 56112 11170>; + bw_enc_hevc = <46756 52766 9763>; + bw_enc_hevc_10bit = <53865 64753 12556>; + bw_enc_vp8 = <64000 67318 22518>; + bw_enc_vp9 = <72326 59726 16530>; + bw_enc_vp9_10bit = <149085 114928 31419>; + bw_enc_mpeg4 = <44647 55324 9531>; + bw_dec_h264 = <32605 34381 21263>; + bw_dec_hevc = <29973 28851 17538>; + bw_dec_hevc_10bit = <52859 46245 31351>; + bw_dec_vp8 = <28672 30468 22324>; + bw_dec_vp9 = <18351 18947 16877>; + bw_dec_vp9_10bit = <42384 34452 31766>; + bw_dec_av1 = <23787 19570 15856>; + bw_dec_av1_10bit = <41407 35490 29699>; + bw_dec_mpeg4 = <31540 25368 15770>; + + /* BW <peak, read, write> : KB/UHD frame. For SBWC format */ + /* It is valid when only support_sbwc = <1> */ + sbwc_bw_enc_h264 = <31622 32183 7065>; + sbwc_bw_enc_hevc = <24044 27526 5888>; + sbwc_bw_enc_hevc_10bit = <32666 37594 8841>; + sbwc_bw_enc_vp8 = <32666 37594 8841>; + sbwc_bw_enc_vp9 = <23276 26884 8702>; + sbwc_bw_enc_vp9_10bit = <42302 41116 14052>; + sbwc_bw_enc_mpeg4 = <32666 37594 8841>; + sbwc_bw_dec_h264 = <23757 18603 13620>; + sbwc_bw_dec_hevc = <15309 15387 10279>; + sbwc_bw_dec_hevc_10bit = <20808 20602 14868>; + sbwc_bw_dec_vp8 = <17203 18281 13394>; + sbwc_bw_dec_vp9 = <11121 9691 8999>; + sbwc_bw_dec_vp9_10bit = <17787 15582 14413>; + sbwc_bw_dec_mpeg4 = <18924 15221 9462>; + + /* BW <peak, read, write> : KB/UHD frame. For recon DPB only SBWC format */ + /* It is valid when only support_sbwc = <1> */ + dpb_sbwc_bw_enc_h264 = <36230 36791 7065>; + dpb_sbwc_bw_enc_hevc = <28662 32144 5888>; + dpb_sbwc_bw_enc_hevc_10bit = <46613 51541 8841>; + dpb_sbwc_bw_enc_vp9 = <26747 31502 8702>; + dpb_sbwc_bw_enc_vp9_10bit = <42302 55063 14052>; + + /* QoS bitrate */ + num_mfc_freq = <5>; + mfc_freqs = <134000 267000 400000 534000 666000>; + /* spec: H264(240M) VP8(80M) */ + max_Kbps = <245760 81920>; + + /* QoS weight (%) */ + qos_weight_h264_hevc = <100>; + qos_weight_vp8_vp9 = <100>; + qos_weight_other_codec = <25>; + qos_weight_3plane = <80>; + qos_weight_10bit = <75>; + qos_weight_422 = <70>; + qos_weight_bframe = <50>; + qos_weight_num_of_ref = <60>; + qos_weight_gpb = <50>; + qos_weight_num_of_tile = <75>; + qos_weight_super64_bframe = <60>; + + /* core balance(%) for resource managing */ + core_balance = <100>; + + /* MFC IOVA threshold (MB) */ + iova_threshold = <0>; + + /* need control for mfc idle clock */ + idle_clk_ctrl = <0>; + + /* Encoder RGB CSC formula by VUI from F/W */ + enc_rgb_csc_by_fw = <1>; + + /* Sub nodes for MFC core */ + #address-cells = <2>; + #size-cells = <1>; + ranges; + + /* MFC core device */ + mfc_core0: MFC-0 { + /* Basic setting */ + compatible = "samsung,exynos-mfc-core"; + id = <0>; + reg = <0x0 0x1C8D0000 0x10000>; + interrupts = <0 IRQ_MFC_MFC IRQ_TYPE_LEVEL_HIGH>; + clock-names = "aclk_mfc"; + clocks = <&clock GATE_MFC>; + iommus = <&sysmmu_mfc0>, <&sysmmu_mfc1>; + samsung,iommu-group = <&iommu_group_mfc>; + samsung,iommu-reserved-map = <0x0 0x10000000 0x100000>; + /* samsung,iommu-identity-map = <0x0 0x15E1F000 0x10000> */ + + samsung,tzmp; + samsung,imgloader-s2mpu-support; + + /* MFC version */ + /* ip_ver is set in gs101-a0.dts and gs101-b0.dts */ + + /* Sysmmu check */ + share_sysmmu = <0>; + axid_mask = <0xFFFF>; + mfc_fault_num = <0x0>; + trans_info_offset = <0x1004>; + + /* LLC (Last Level Cache) */ + llc = <0>; + need_llc_flush = <0>; + + /* SLC (System Level Cache) */ + pt_id = "MFC"; + + /* vOTF */ + /* mfc_votf_base = <0x16650000>; */ + /* gdc_votf_base = <0x15E1F000>; */ + /* dpu_votf_base = <0x19CAF000>; */ + + /* QoS */ + num_default_qos_steps = <8>; + num_encoder_qos_steps = <8>; + max_mb = <5480873>; + mfc_freq_control = <1>; + mo_control = <1>; + bw_control = <1>; + + /* Device virtual address */ + #dma-address-cells = <1>; + #dma-size-cells = <1>; + dma-window = <0x0 0xFFFFFFFF>; + + /* Sub nodes for sysmmu, hwfc and mmcache */ + #address-cells = <2>; + #size-cells = <1>; + ranges; + + iommu { + reg = <0x0 0x1C870000 0x9000>, + <0x0 0x1C8A0000 0x9000>; + }; + ssmt { + reg = <0x0 0x1C8E4000 0x100>, + <0x0 0x1C8F4000 0x100>; + }; + sysreg { + reg = <0x0 0x1C820000 0x500>; + }; + + /* Default QoS table */ + mfc_default_qos_table { + mfc_d_qos_variant_0 { + thrd_mb = <0>; + freq_mfc = <134000>; + freq_int = <100000>; + freq_mif = <421000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <2058>; + }; + mfc_d_qos_variant_1 { + thrd_mb = <265147>; + freq_mfc = <267000>; + freq_int = <200000>; + freq_mif = <421000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <1379>; + }; + mfc_d_qos_variant_2 { + thrd_mb = <551811>; + freq_mfc = <267000>; + freq_int = <200000>; + freq_mif = <676000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <1046>; + }; + mfc_d_qos_variant_3 { + thrd_mb = <1202239>; + freq_mfc = <356000>; + freq_int = <332000>; + freq_mif = <1014000>; + mo_value = <1>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <732>; + }; + mfc_d_qos_variant_4 { + thrd_mb = <1887335>; + freq_mfc = <465000>; + freq_int = <332000>; + freq_mif = <1014000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <655>; + }; + mfc_d_qos_variant_5 { + thrd_mb = <2088750>; + freq_mfc = <664000>; + freq_int = <332000>; + freq_mif = <1539000>; + mo_value = <1>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "mfc_uhd"; + time_fw = <479>; + }; + mfc_d_qos_variant_6 { + thrd_mb = <3197754>; + freq_mfc = <664000>; + freq_int = <533000>; + freq_mif = <1539000>; + mo_value = <0>; + mo_10bit_value = <1>; + mo_uhd_enc60_value = <0>; + bts_scen = "mfc_uhd_10bit"; + time_fw = <445>; + }; + mfc_d_qos_variant_7 { + thrd_mb = <4385292>; + freq_mfc = <711000>; + freq_int = <533000>; + freq_mif = <1539000>; + mo_value = <0>; + mo_10bit_value = <1>; + mo_uhd_enc60_value = <0>; + bts_scen = "mfc_8k_dec30"; + time_fw = <445>; + }; + }; + + /* Encoder QoS table */ + mfc_encoder_qos_table { + mfc_e_qos_variant_0 { + thrd_mb = <0>; + freq_mfc = <134000>; + freq_int = <100000>; + freq_mif = <421000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <2058>; + }; + mfc_e_qos_variant_1 { + thrd_mb = <265147>; + freq_mfc = <267000>; + freq_int = <200000>; + freq_mif = <421000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <1379>; + }; + mfc_e_qos_variant_2 { + thrd_mb = <551811>; + freq_mfc = <267000>; + freq_int = <200000>; + freq_mif = <676000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <1046>; + }; + mfc_e_qos_variant_3 { + thrd_mb = <1202239>; + freq_mfc = <356000>; + freq_int = <332000>; + freq_mif = <1014000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <732>; + }; + mfc_e_qos_variant_4 { + thrd_mb = <1887335>; + freq_mfc = <465000>; + freq_int = <332000>; + freq_mif = <1014000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <655>; + }; + mfc_e_qos_variant_5 { + thrd_mb = <2088750>; + freq_mfc = <533000>; + freq_int = <200000>; + freq_mif = <1539000>; + mo_value = <1>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <559>; + }; + mfc_e_qos_variant_6 { + thrd_mb = <2625764>; + freq_mfc = <664000>; + freq_int = <332000>; + freq_mif = <1539000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <1>; + bts_scen = "mfc_uhd"; + time_fw = <479>; + }; + mfc_e_qos_variant_7 { + thrd_mb = <3197754>; + freq_mfc = <664000>; + freq_int = <533000>; + freq_mif = <1539000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <1>; + bts_scen = "mfc_uhd_10bit"; + time_fw = <445>; + }; + }; + /* QoS table for performance boost mode */ + mfc_perf_boost_table { + num_cluster = <3>; + freq_cluster = <1742000 1898000 1456000>; + freq_mfc = <711000>; + freq_int = <533000>; + freq_mif = <2730000>; + bts_scen = "mfc_8k_dec30"; + }; + }; + }; +};
diff --git a/dts/gs201-mmc.dtsi b/dts/gs201-mmc.dtsi new file mode 100644 index 0000000..9c0c1b9 --- /dev/null +++ b/dts/gs201-mmc.dtsi
@@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Samsung's SoC MMC device tree source + * + * Copyright (C) 2020 Samsung Electronics Co., Ltd + * + */ + +/{ + aliases { + mshc2 = &dwmmc_2; + }; + + dwmmc_2: dwmmc2@14620000 { + compatible = "samsung,exynos-dw-mshc"; + reg = <0x0 0x14620000 0x2000>; + reg-names = "dw_mmc"; + interrupts = <GIC_SPI IRQ_MMC_CARD_HSI2 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + /* + * clocks = <&clock MMC_CARD>, <&clock GATE_MMC_CARD>; + * clock-names = "ciu", "ciu_gate"; + */ + status = "disabled"; + num-slots = <1>; + fixed_voltage; + non-removable; + supports-4bit; + supports-cmd23; + supports-erase; + supports-highspeed; + bypass-for-allpass; + use-fine-tuning; + /* + * card-init-hwacg-ctrl; + */ + fifo-depth = <0x40>; + desc-size = <4>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + clock-frequency = <800000000>; + samsung,dw-mshc-sdr-timing = <3 0 2 0>; + samsung,dw-mshc-ddr-timing = <3 0 2 1>; + num-ref-clks = <9>; + ciu_clkin = <25 50 50 25 50 100 200 50 50>; + /* Swapping clock drive strength */ + clk-drive-number = <6>; + slot@0 { + reg = <0>; + bus-width = <4>; + disable-wp; + }; + }; +};
diff --git a/dts/gs201-pantah-charging.dtsi b/dts/gs201-pantah-charging.dtsi new file mode 100644 index 0000000..7710221 --- /dev/null +++ b/dts/gs201-pantah-charging.dtsi
@@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Battery device tree entries specific to panther/cheetah + * + * Copyright 2021 Google,LLC + * + */ + +/ { + fragment@charging { + target-path = "/"; + __overlay__ { + + google_cpm: google,cpm { + status = "okay"; + compatible = "google,cpm"; + #cooling-cells = <2>; + + google,chg-power-supplies = "main-charger", // out-0 + "pca94xx-mains"; // out-1 + + /* S2MPG12X01 -> GPIO_1 -> CHARGE_PUMP_EN */ + google,dc-en = <&s2mpg12_gpio 1 0>; + /* DC enabled by default */ + google,dc-en-value; + google,dc_limit-demand = <560000>; + google,dc_limit-vbatt = <4350000>; + google,dc_limit-vbatt_min = <3400000>; + + google,tcpm-power-supply = <&max77759tcpc>; // in=0 + google,wlc_dc-power-supply = "wireless"; // in=1 + google,pps-awake; + }; + + google_charger: google,charger { + status = "okay"; + compatible = "google,charger"; + #cooling-cells = <2>; + + google,chg-power-supply = "gcpm"; + google,bat-power-supply = "battery"; + google,usb-power-supply = "usb"; + google,tcpm-power-supply = <&max77759tcpc>; + + google,fv-max-uv = <4450000>; + + google,wlc-thermal-mitigation = <1100000 500000 250000 110000>; + google,therm-wlc-overrides-fcc; + + /* b/170700459 thresholds, updated in b/191070950 */ + google,bd-resume-abs-temp = <280>; + google,bd-resume-soc = <50>; + google,bd-resume-time = <14400>; /* 4 hours */ + google,bd-resume-temp = <290>; + google,bd-trigger-time = <21600>; /* 6 hours */ + google,bd-trigger-temp = <350>; + google,bd-trigger-voltage = <4270000>; + google,bd-recharge-voltage = <4250000>; + google,bd-drainto-soc = <80>; + google,bd-recharge-soc = <79>; + /* Enable TEMP-DEFEND */ + google,bd-temp-enable; + google,bd-temp-dry-run; + + google,chg-termination-5v; + }; + + google_bms { + nvmem = <&pack_bee>; + }; + + google_wlc_charger: google,wlc_charger { + #cooling-cells = <2>; + }; + + google_wlc_fcc_charger: google,wlc_fcc_charger { + #cooling-cells = <2>; + }; + + google_mdis_charger: google,mdis_charger { + #cooling-cells = <2>; + }; + + }; + }; +}; + +&pinctrl_0 { + + dc_charger_irq: dc-charger-irq { + samsung,pins = "gpa9-0"; /* XEINT_20 (PLC_INT_L) */ + samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + }; +}; + + +&max77759_chg { + max77759,psy-name = "main-charger"; +}; + +&hsi2c_13 { + + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + clock-frequency = <400000>; + + pca9468_dc: pca9468@57 { + compatible = "nxp,pca9468"; + reg = <0x57>; + + pca9468,psy_name = "pca94xx-mains"; + + pinctrl-names = "default"; + pinctrl-0 = <&dc_charger_irq>; + + interrupt-parent = <&gpa9>; + pca9468,irq-gpio = <&gpa9 0 GPIO_ACTIVE_LOW>; /* PLC_INT_L */ + + pca9468,float-voltage = <4300000>; /* 4.3V */ + + pca9468,input-itopoff = <500000>; /* 500mA */ + pca9468,switching-frequency = <3>; /* 980KHz */ + + /* disable USBC NTC */ + pca9468,ntc-threshold = <0>; /* disabled */ + + /* USBC thermal zone */ + google,usb-port-tz-name = "usbc-therm-adc"; + + pca9468,google_cpm = <&google_cpm>; + + pca9468,ta-max-cur-mult = <2>; /* has cap div */ + }; + +};
diff --git a/dts/gs201-pantah-pmic.dtsi b/dts/gs201-pantah-pmic.dtsi new file mode 100644 index 0000000..a95369e --- /dev/null +++ b/dts/gs201-pantah-pmic.dtsi
@@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Pantah pmic device tree source + * + * Copyright 2021 Google LLC. + * + */ + +&m_ldo23_reg { + schematic-name = "L23M_SPARE"; + subsys-name = "Spare"; +}; + +&m_ldo24_reg { + schematic-name = "L24M_SPARE"; + subsys-name = "Spare"; +}; + +&s_ldo4_reg { + schematic-name = "L4S_SPARE"; + subsys-name = "Spare"; +}; + +&s_ldo6_reg { + schematic-name = "L6S_SPARE"; + subsys-name = "Spare"; +}; + +&s_ldo7_reg { + schematic-name = "L7S_SENSORS"; +}; + +&s_ldo8_reg { + schematic-name = "L8S_SPARE"; + subsys-name = "Spare"; +}; + +&s_ldo12_reg { + schematic-name = "L12S_CAMIO"; + subsys-name = "Multimedia"; +}; + +&s_ldo14_reg { + schematic-name = "L14S_ALIVE"; + subsys-name = "Alive"; +}; + +&s_ldo15_reg { + schematic-name = "L15S_UDFPS_AVDD"; +}; + +&s_ldo20_reg { + schematic-name = "L20S_DMIC2"; + subsys-name = "DMIC"; +}; + +&s_ldo22_reg { + schematic-name = "L22S_SPARE"; + subsys-name = "Spare"; +}; + +&s_ldo26_reg { + schematic-name = "L26S_SPARE"; + subsys-name = "Spare"; +}; + +&s_ldo27_reg { + schematic-name = "L27S_SPARE"; + subsys-name = "Spare"; +}; + +&s_ldo28_reg { + schematic-name = "L28S_SPARE"; + subsys-name = "Spare"; +}; +
diff --git a/dts/gs201-pcie.dtsi b/dts/gs201-pcie.dtsi new file mode 100644 index 0000000..32cb131 --- /dev/null +++ b/dts/gs201-pcie.dtsi
@@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PCIe device tree source code for gs101 SoC + * + * Copyright (C) 2020 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include <dt-bindings/pci/pci.h> +/ { + /* HSI1 GEN4_0 */ + pcie_0: pcie@11920000 { + compatible = "samsung,exynos-pcie-rc"; + gpios = <&gph0 0 0x1 /* PERST */>; + reg = <0x0 0x11920000 0x2000 /* elbi base */ + 0x0 0x11960000 0xD000 /* udbg base */ + 0x0 0x11950000 0x2000 /* phy base */ + 0x0 0x11820000 0x2000 /* sysreg base */ + 0x0 0x11C00000 0x301000 /* DBI base */ + 0x0 0x11940000 0x1000 /* phy pcs base */ + 0x0 0x40FFE000 0x2000 /* configuration space */ + 0x0 0x11900000 0x1000>; /* I/A space */ + reg-names = "elbi", "udbg", "phy", "sysreg", "dbi", "pcs", "config", "ia"; + interrupts = <GIC_SPI IRQ_PCIE_GEN4A_0_HSI1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_PCIE_GEN4A_MSI_0_HSI1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_PCIE_GEN4A_MSI_1_HSI1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_PCIE_GEN4A_MSI_2_HSI1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_PCIE_GEN4A_MSI_3_HSI1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_PCIE_GEN4A_MSI_4_HSI1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + samsung,syscon-phandle = <&pmu_system_controller>; + pinctrl-names = "active"; + pinctrl-0 = <&pcie0_clkreq &pcie0_perst>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + /* non-prefetchable memory */ + ranges = <0x82000000 0 0x14E00000 0 0x40000000 0 0xFF0000>; + ip-ver = <0x984500>; /* gs101 */ + num-lanes = <2>; + ch-num = <0>; + pcie-clk-num = <0>; + phy-clk-num = <0>; + pcie-pm-qos-int = <200000>; + separated-msi = <1>; + use-cache-coherency = "false"; + use-pcieon-sleep = "false"; + use-msi = "false"; + use-sicd = "false"; + use-sysmmu = "false"; + use-ia = "false"; + use-l1ss = "false"; + use-secure-atu = "false"; + pmu-offset = <0x3ec0>; + max-link-speed = <LINK_SPEED_GEN3>; + status = "disabled"; + }; + sysmmu_hsi1: sysmmu@11860000 { + compatible = "samsung,pcie-sysmmu"; + reg = <0x0 0x11860000 0x10000>; + interrupts = <0 IRQ_SYSMMU_HSI1_S1_NS_HSI1 IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + port-name = "PCIe_CH0"; + hsi-block-num = <1>; + pcie-vid-num = <0>; + #iommu-cells = <0>; + use-map-once = "false"; + status = "okay"; + }; + + /* HSI2 GEN4_1 */ + pcie_1: pcie@14520000 { + compatible = "samsung,exynos-pcie-rc"; + gpios = <&gph2 0 0x1 /* PERST */>; + reg = <0x0 0x14520000 0x2000 /* elbi base */ + 0x0 0x14560000 0xD000 /* udbg base */ + 0x0 0x14550000 0x2000 /* phy base */ + 0x0 0x14420000 0x2000 /* sysreg base */ + 0x0 0x14800000 0x301000 /* DBI base */ + 0x0 0x14540000 0x1000 /* phy pcs base */ + 0x0 0x60FFE000 0x2000 /* configuration space */ + 0x0 0x14500000 0x1000>; /* I/A space */ + reg-names = "elbi", "udbg", "phy", "sysreg", "dbi", "pcs", "config", "ia"; + interrupts = <GIC_SPI IRQ_PCIE_GEN4A_1_HSI2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_PCIE_GEN4A_1_MSI_0_HSI2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_PCIE_GEN4A_1_MSI_1_HSI2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_PCIE_GEN4A_1_MSI_2_HSI2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_PCIE_GEN4A_1_MSI_3_HSI2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_PCIE_GEN4A_1_MSI_4_HSI2 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 IRQ_PCIE_GEN4A_1_HSI2 0x4>; + samsung,syscon-phandle = <&pmu_system_controller>; + pinctrl-names = "active"; + pinctrl-0 = <&pcie1_clkreq &pcie1_perst>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + /* non-prefetchable memory */ + ranges = <0x82000000 0 0x60000000 0 0x60000000 0 0xFF0000>; + ip-ver = <0x984500>; /* gs101 */ + num-lanes = <2>; + ch-num = <1>; + pcie-clk-num = <0>; + phy-clk-num = <0>; + pcie-pm-qos-int = <200000>; + use-cache-coherency = "false"; + use-pcieon-sleep = "false"; + use-msi = "false"; + use-sicd = "false"; + use-sysmmu = "false"; + use-ia = "false"; + use-l1ss = "false"; + use-secure-atu = "false"; + pmu-offset = <0x3ec4>; + max-link-speed = <LINK_SPEED_GEN3>; + status = "disabled"; + }; + + sysmmu_hsi2: sysmmu@145C0000 { + compatible = "samsung,pcie-sysmmu"; + reg = <0x0 0x145C0000 0x10000>; + interrupts = <0 IRQ_SYSMMU_HSI2_S1_NS_HSI2 IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + port-name = "PCIe_CH1"; + hsi-block-num = <2>; + pcie-vid-num = <1>; + #iommu-cells = <0>; + use-map-once = "false"; + status = "okay"; + }; +};
diff --git a/dts/gs201-pinctrl.dtsi b/dts/gs201-pinctrl.dtsi new file mode 100644 index 0000000..b720725 --- /dev/null +++ b/dts/gs201-pinctrl.dtsi
@@ -0,0 +1,1198 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2021 Google LLC. + * + */ + +#include <dt-bindings/interrupt-controller/gs201.h> +#include <arm64/exynos/exynos-pinctrl.h> +#include "gs101-pinctrl.h" + +/ { + /* GPIO_ALIVE */ + pinctrl@180D0000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI IRQ_ALIVE_EINT0 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT1 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT2 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT3 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT4 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT5 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT6 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT7 ITLH>; + }; + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI IRQ_ALIVE_EINT8 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT9 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT10 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT11 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT12 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT13 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT14 ITLH>; + }; + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI IRQ_ALIVE_EINT15 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT16 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT17 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT18 ITLH>; + }; + gpa3: gpa3 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI IRQ_ALIVE_EINT20 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT21 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT22 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT23 ITLH>; + }; + gpa4: gpa4 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI IRQ_ALIVE_EINT24 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT25 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT26 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT27 ITLH>; + }; + gpa5: gpa5 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_SPI IRQ_ALIVE_EINT28 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT29 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT30 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT31 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT32 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT33 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT34 ITLH>; + }; + gpa9: gpa9 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_SPI IRQ_ALIVE_EINT35 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT36 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT37 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT38 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT39 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT40 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT41 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT42 ITLH>; + }; + gpa10: gpa10 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_SPI IRQ_ALIVE_EINT43 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT44 ITLH>; + }; + + uart17_bus: uart17-bus { + samsung,pins = "gpa2-2", "gpa2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + uart18_bus: uart18-bus { + samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + uart18_bus_rts: uart1-bus-rts { + samsung,pins = "gpa3-2"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-val = <1>; + }; + + uart18_bus_tx_dat: uart1-bus-tx-dat { + samsung,pins = "gpa3-1"; + samsung,pin-val = <1>; + }; + + uart18_bus_tx_con: uart1-bus-tx-con { + samsung,pins = "gpa3-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + }; + + uart19_bus: uart19-bus { + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2", "gpa4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + spi17_bus: spi17-bus { + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + + spi17_cs: spi17-cs { + samsung,pins = "gpa4-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + }; + /* GPIO_FAR_ALIVE */ + pinctrl@180E0000 { + gpa6: gpa6 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI IRQ_ALIVE_EINT45 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT46 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT47 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT48 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT49 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT50 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT51 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT52 ITLH>; + }; + gpa7: gpa7 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI IRQ_ALIVE_EINT53 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT54 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT55 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT56 ITLH>; + }; + gpa8: gpa8 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI IRQ_ALIVE_EINT57 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT58 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT59 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT60 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT61 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT62 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT63 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT64 ITLH>; + }; + gpa11: gpa11 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI IRQ_ALIVE_EINT65 ITLH>, + <GIC_SPI IRQ_ALIVE_EINT66 ITLH>; + }; + + }; + /* GPIO_GSACORE */ + pinctrl@17A80000 { + gps0: gps0 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gps1: gps1 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gps2: gps2 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; + /* GPIO_GSACTRL */ + pinctrl@17940000 { + gps3: gps3 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; + /* GPIO_HSI1 */ + pinctrl@11840000 { + gph0: gph0 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gph1: gph1 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + pcie0_clkreq: pcie0_clkreq { + samsung,pins = "gph0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <3>; + }; + pcie0_perst: pcie0_perst { + samsung,pins = "gph0-0"; + samsung,pin-function = <1>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-con-pdn = <3>; + }; + }; + /* GPIO_HSI2 */ + pinctrl@14440000 { + gph2: gph2 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gph4: gph4 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gph4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gph4-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gph4-3", "gph4-4", "gph4-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; + }; + + sd2_clk_fast_slew_rate_1x: sd2-clk_fast_slew_rate_1x { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + + sd2_clk_fast_slew_rate_2x: sd2-clk_fast_slew_rate_2x { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; + }; + + sd2_clk_fast_slew_rate_3x: sd2-clk_fast_slew_rate_3x { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>; + }; + + sd2_clk_fast_slew_rate_4x: sd2-clk_fast_slew_rate_4x { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; + }; + pcie1_clkreq: pcie1_clkreq { + samsung,pins = "gph2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <3>; + }; + pcie1_perst: pcie1_perst { + samsung,pins = "gph2-0"; + samsung,pin-function = <1>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <3>; + }; + }; + /* GPIO_PERIC0 */ + pinctrl@10840000 { + gpp0: gpp0 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp1: gpp1 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp2: gpp2 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp3: gpp3 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp4: gpp4 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp5: gpp5 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp6: gpp6 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp7: gpp7 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp8: gpp8 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp9: gpp9 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp10: gpp10 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp11: gpp11 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp12: gpp12 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp13: gpp13 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp14: gpp14 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp15: gpp15 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp16: gpp16 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp17: gpp17 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp18: gpp18 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp19: gpp19 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + /* USI_PERIC0_UART_DBG */ + uart0_bus: uart0-bus { + samsung,pins = "gpp1-2", "gpp1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + disp_te_pri_on: disp-te-pri-on { + samsung,pins = "gpp0-3"; + samsung,pin-function = <0xf>; + }; + + disp_te_pri_off: disp-te-pri-off { + samsung,pins = "gpp0-3"; + samsung,pin-function = <0>; + }; + + disp_te_sec_on: disp-te-sec-on { + samsung,pins = "gpp0-4"; + samsung,pin-function = <0xf>; + }; + + disp_te_sec_off: disp-te-sec-off { + samsung,pins = "gpp0-4"; + samsung,pin-function = <0>; + }; + + sensor_mclk1_out: sensor-mclk1-out { + samsung,pins = "gpp3-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + sensor_mclk1_fn: sensor-mclk1-fn { + samsung,pins = "gpp3-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + sensor_mclk2_out: sensor-mclk2-out { + samsung,pins = "gpp5-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + sensor_mclk2_fn: sensor-mclk2-fn { + samsung,pins = "gpp5-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + sensor_mclk3_out: sensor-mclk3-out { + samsung,pins = "gpp7-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + sensor_mclk3_fn: sensor-mclk3-fn { + samsung,pins = "gpp7-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + sensor_mclk4_out: sensor-mclk4-out { + samsung,pins = "gpp9-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + sensor_mclk4_fn: sensor-mclk4-fn { + samsung,pins = "gpp9-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + sensor_mclk5_out: sensor-mclk5-out { + samsung,pins = "gpp11-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; + }; + sensor_mclk5_fn: sensor-mclk5-fn { + samsung,pins = "gpp11-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; + }; + sensor_mclk6_out: sensor-mclk6-out { + samsung,pins = "gpp13-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; + }; + sensor_mclk6_fn: sensor-mclk6-fn { + samsung,pins = "gpp13-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; + }; + sensor_mclk7_out: sensor-mclk7-out { + samsung,pins = "gpp15-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; + }; + sensor_mclk7_fn: sensor-mclk7-fn { + samsung,pins = "gpp15-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; + }; + sensor_mclk8_out: sensor-mclk8-out { + samsung,pins = "gpp17-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; + }; + sensor_mclk8_fn: sensor-mclk8-fn { + samsung,pins = "gpp17-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_5_MA>; + }; + hsi2c14_bus: hsi2c14-bus { + samsung,pins = "gpp18-0", "gpp18-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + uart14_bus_single: uart14-bus { + samsung,pins = "gpp18-0", "gpp18-1", + "gpp18-2", "gpp18-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi14_bus: spi14-bus { + samsung,pins = "gpp18-0", "gpp18-1", "gpp18-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi14_cs: spi14-cs { + samsung,pins = "gpp18-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi14_cs_func: spi14-cs-func { + samsung,pins = "gpp18-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + hsi2c8_bus: hsi2c8-bus { + samsung,pins = "gpp16-0", "gpp16-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PDN_OUT0>; + }; + uart8_bus_single: uart8-bus { + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2", + "gpp16-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi8_bus: spi8-bus { + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi8_cs: spi8-cs { + samsung,pins = "gpp16-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi8_cs_func: spi8-cs-func { + samsung,pins = "gpp16-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + hsi2c7_bus: hsi2c7-bus { + samsung,pins = "gpp14-0", "gpp14-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + uart7_bus_single: uart7-bus { + samsung,pins = "gpp14-0", "gpp14-1", + "gpp14-2", "gpp14-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi7_bus: spi7-bus { + samsung,pins = "gpp14-0", "gpp14-1", "gpp14-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi7_cs: spi7-cs { + samsung,pins = "gpp14-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi7_cs_func: spi7-cs-func { + samsung,pins = "gpp14-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + hsi2c6_bus: hsi2c6-bus { + samsung,pins = "gpp12-0", "gpp12-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + uart6_bus_single: uart6-bus { + samsung,pins = "gpp12-0", "gpp12-1", + "gpp12-2", "gpp12-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi6_bus: spi6-bus { + samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi6_cs: spi6-cs { + samsung,pins = "gpp12-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi6_cs_func: spi6-cs-func { + samsung,pins = "gpp12-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + hsi2c5_bus: hsi2c5-bus { + samsung,pins = "gpp10-0", "gpp10-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + uart5_bus_single: uart5-bus { + samsung,pins = "gpp10-0", "gpp10-1", + "gpp10-2", "gpp10-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi5_bus: spi5-bus { + samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2"; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; + spi5_cs_func: spi5-cs-func { + samsung,pins = "gpp10-3"; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; + hsi2c4_bus: hsi2c4-bus { + samsung,pins = "gpp8-0", "gpp8-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + uart4_bus_single: uart4-bus { + samsung,pins = "gpp8-0", "gpp8-1", + "gpp8-2", "gpp8-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi4_bus: spi4-bus { + samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi4_cs: spi4-cs { + samsung,pins = "gpp8-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi4_cs_func: spi4-cs-func { + samsung,pins = "gpp8-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + hsi2c3_bus: hsi2c3-bus { + samsung,pins = "gpp6-0", "gpp6-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + uart3_bus_single: uart3-bus { + samsung,pins = "gpp6-0", "gpp6-1", + "gpp6-2", "gpp6-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi3_bus: spi3-bus { + samsung,pins = "gpp6-0", "gpp6-1", "gpp6-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi3_cs: spi3-cs { + samsung,pins = "gpp6-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi3_cs_func: spi3-cs-func { + samsung,pins = "gpp6-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + hsi2c2_bus: hsi2c2-bus { + samsung,pins = "gpp4-0", "gpp4-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + uart2_bus_single: uart2-bus { + samsung,pins = "gpp4-0", "gpp4-1", + "gpp4-2", "gpp4-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi2_bus: spi2-bus { + samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi2_cs: spi2-cs { + samsung,pins = "gpp4-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi2_cs_func: spi2-cs-func { + samsung,pins = "gpp4-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + hsi2c1_bus: hsi2c1-bus { + samsung,pins = "gpp2-0", "gpp2-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + uart1_bus_single: uart1-bus { + samsung,pins = "gpp2-0", "gpp2-1", + "gpp2-2", "gpp2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi1_bus: spi1-bus { + samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi1_cs: spi1-cs { + samsung,pins = "gpp2-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi1_cs_func: spi1-cs-func { + samsung,pins = "gpp2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + }; + /* GPIO_PERIC1 */ + pinctrl@10C40000 { + gpp20: gpp20 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp21: gpp21 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp22: gpp22 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp23: gpp23 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp24: gpp24 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp25: gpp25 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp26: gpp26 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp27: gpp27 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + hsi2c16_bus: hsi2c16-bus { + samsung,pins = "gpp26-0", "gpp26-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + uart16_bus_single: uart16-bus { + samsung,pins = "gpp26-0", "gpp26-1", + "gpp26-2", "gpp26-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi16_bus: spi16-bus { + samsung,pins = "gpp26-0", "gpp26-1", "gpp26-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi16_cs: spi16-cs { + samsung,pins = "gpp26-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi16_cs_func: spi16-cs-func { + samsung,pins = "gpp26-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + hsi2c15_bus: hsi2c15-bus { + samsung,pins = "gpp24-0", "gpp24-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; + uart15_bus_single: uart15-bus { + samsung,pins = "gpp24-0", "gpp24-1", + "gpp24-2", "gpp24-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi15_bus: spi15-bus { + samsung,pins = "gpp24-0", "gpp24-1", "gpp24-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi15_cs: spi15-cs { + samsung,pins = "gpp24-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi15_cs_func: spi15-cs-func { + samsung,pins = "gpp24-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + hsi2c13_bus: hsi2c13-bus { + samsung,pins = "gpp25-0", "gpp25-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + uart13_bus_single: uart13-bus { + samsung,pins = "gpp25-0", "gpp25-1", + "gpp25-2", "gpp25-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi13_bus: spi13-bus { + samsung,pins = "gpp25-0", "gpp25-1", "gpp25-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi13_cs: spi13-cs { + samsung,pins = "gpp25-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi13_cs_func: spi13-cs-func { + samsung,pins = "gpp25-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + hsi2c12_bus: hsi2c12-bus { + samsung,pins = "gpp23-4", "gpp23-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + uart12_bus_single: uart12-bus { + samsung,pins = "gpp23-4", "gpp23-5", + "gpp23-6", "gpp23-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi12_bus: spi12-bus { + samsung,pins = "gpp23-4", "gpp23-5", "gpp23-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi14_cs2: spi14-cs2 { + samsung,pins = "gpp23-6"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi12_cs: spi12-cs { + samsung,pins = "gpp23-7"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi12_cs_func: spi12-cs-func { + samsung,pins = "gpp23-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + hsi2c11_bus: hsi2c11-bus { + samsung,pins = "gpp23-0", "gpp23-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + uart11_bus_single: uart11-bus { + samsung,pins = "gpp23-0", "gpp23-1", + "gpp23-2", "gpp23-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi11_bus: spi11-bus { + samsung,pins = "gpp23-0", "gpp23-1", "gpp23-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi11_cs: spi11-cs { + samsung,pins = "gpp23-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi11_cs_func: spi11-cs-func { + samsung,pins = "gpp23-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + hsi2c10_bus: hsi2c10-bus { + samsung,pins = "gpp21-0", "gpp21-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + uart10_bus_single: uart10-bus { + samsung,pins = "gpp21-0", "gpp21-1", + "gpp21-2", "gpp21-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi10_bus: spi10-bus { + samsung,pins = "gpp21-0", "gpp21-1", "gpp21-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi10_cs: spi10-cs { + samsung,pins = "gpp21-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi10_cs_func: spi10-cs-func { + samsung,pins = "gpp21-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + hsi2c9_bus: hsi2c9-bus { + samsung,pins = "gpp20-4", "gpp20-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + uart9_bus_single: uart9-bus { + samsung,pins = "gpp20-4", "gpp20-5", + "gpp20-6", "gpp20-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi9_bus: spi9-bus { + samsung,pins = "gpp20-4", "gpp20-5", "gpp20-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi9_cs: spi9-cs { + samsung,pins = "gpp20-7"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi9_cs_func: spi9-cs-func { + samsung,pins = "gpp20-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + hsi2c0_bus: hsi2c0-bus { + samsung,pins = "gpp20-0", "gpp20-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + uart0_bus_single: uart0-bus { + samsung,pins = "gpp20-0", "gpp20-1", + "gpp20-2", "gpp20-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi0_bus: spi0-bus { + samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi0_cs: spi0-cs { + samsung,pins = "gpp20-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + spi0_cs_func: spi0-cs-func { + samsung,pins = "gpp20-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; + }; + /* GPIO_HSI2UFS */ + pinctrl@14460000 { + gph3: gph3 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + ufs_rst_n: ufs-rst-n { + samsung,pins = "gph3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + ufs_refclk_out: ufs-refclk-out { + samsung,pins = "gph3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + }; +};
diff --git a/dts/gs201-pm-domains.dtsi b/dts/gs201-pm-domains.dtsi new file mode 100644 index 0000000..5b995c2 --- /dev/null +++ b/dts/gs201-pm-domains.dtsi
@@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS201 SoC PM Domains device tree source + * + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * GS201 SoC PM domains device nodes are listed in this file. + * GS201 based board files can include this file and provide + * values for board specific bindings. + * + */ + +#include <dt-bindings/power/exynos-power.h> + +/ { + /* NOTICE: The order matters! + * If one domain depends on another domain, make sure the dependency is + * before the dependent. For example, put pd-g3d before pd-embedded_g3d. + * This to prevent deferred probing from happening. The reason is that + * pkvm-s2mpu devices are only probed during module init. If the modules + * that pkvm-s2mpu depends on are not ready at that time, then those + * modules will be skipped and never probed again. To prevent that from + * happening, make sure all the domains will not be deferred as well. + */ + + pd_aoc: pd-aoc@18061880 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18061880 0x20>; + cal_id = <0xB1380000>; + need_smc = <0x1A010204>; + cmu_id = <0x1A000000>; + status = "disabled"; + #power-domain-cells = <0>; + }; + + pd_eh: pd-eh@18061C00 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18061C00 0x20>; + cal_id = <0xB1380005>; + need_smc = <0x17010204>; + cmu_id = <0x17000000>; + status = "okay"; + skip-idle-ip; + #power-domain-cells = <0>; + }; + + pd_g3d: pd-g3d@18061E00 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18061E00 0x20>; + cal_id = <0xB1380007>; + need_smc = <0x27F10204>; + cmu_id = <0x27F00000>; + status = "okay"; + skip-idle-ip; + #power-domain-cells = <0>; + }; + + pd_embedded_g3d: pd-embedded_g3d@18062000 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062000 0x20>; + cal_id = <0xB1380006>; + status = "okay"; + skip-idle-ip; + power-domains = <&pd_g3d>; + #power-domain-cells = <0>; + }; + + pd_hsi0: pd-hsi0@18062080 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062080 0x20>; + cal_id = <0xB1380008>; + need_smc = <0x11010204>; + cmu_id = <0x11000000>; + status = "okay"; + #power-domain-cells = <0>; + power-down-ok = <PD_OK_USB>; + skip-idle-ip; + }; + + pd_hsi2: pd-hsi2@18062180 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062180 0x20>; + cal_id = <0xB1380009>; + need_smc = <0x14410204>; + cmu_id = <0x14400000>; + status = "disabled"; + #power-domain-cells = <0>; + }; + + pd_disp: pd-disp@18062280 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062280 0x20>; + cal_id = <0xB138000B>; + need_smc = <0x1C210204>; + cmu_id = <0x1C200000>; + status = "okay"; + #power-domain-cells = <0>; + skip-idle-ip; + }; + + pd_dpu: pd-dpu@18062200 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062200 0x20>; + cal_id = <0xB138000A>; + need_smc = <0x1C010204>; + cmu_id = <0x1C000000>; + status = "okay"; + power-domains = <&pd_disp>; + #power-domain-cells = <0>; + skip-idle-ip; + }; + + pd_g2d: pd-g2d@18062300 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062300 0x20>; + cal_id = <0xB138000C>; + need_smc = <0x1C610204>; + cmu_id = <0x1C600000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_mfc: pd-mfc@18062380 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062380 0x20>; + cal_id = <0xB138000D>; + need_smc = <0x1C810204>; + cmu_id = <0x1C800000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_csis: pd-csis@18062400 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062400 0x20>; + cal_id = <0xB138000E>; + need_smc = <0x1A410204>; + cmu_id = <0x1A400000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_pdp: pd-pdp@18062480 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062480 0x20>; + cal_id = <0xB138000F>; + need_smc = <0x1AA10204>; + cmu_id = <0x1AA00000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_g3aa: pd-g3aa@18062580 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062580 0x20>; + cal_id = <0xB1380011>; + need_smc = <0x1A810204>; + cmu_id = <0x1A800000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_ipp: pd-ipp@18062600 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062600 0x20>; + cal_id = <0xB1380012>; + need_smc = <0x1AC10204>; + cmu_id = <0x1AC00000>; + status = "okay"; + power-domains = <&pd_pdp>; + #power-domain-cells = <0>; + }; + + pd_itp: pd-itp@18062680 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062680 0x20>; + cal_id = <0xB1380013>; + need_smc = <0x1B410204>; + cmu_id = <0x1B400000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_dns: pd-dns@18062500 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062500 0x20>; + cal_id = <0xB1380010>; + need_smc = <0x1B010204>; + cmu_id = <0x1B000000>; + status = "okay"; + power-domains = <&pd_itp>; + #power-domain-cells = <0>; + }; + + pd_mcsc: pd-mcsc@18062700 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062700 0x20>; + cal_id = <0xB1380014>; + need_smc = <0x1B710204>; + cmu_id = <0x1B700000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_gdc: pd-gdc@18062780 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062780 0x20>; + cal_id = <0xB1380015>; + need_smc = <0x1D010204>; + cmu_id = <0x1D000000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_tnr: pd-tnr@18062800 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062800 0x20>; + cal_id = <0xB1380016>; + need_smc = <0x1BC10204>; + cmu_id = <0x1BC00000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_bo: pd-bo@18062880 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062880 0x20>; + cal_id = <0xB1380017>; + need_smc = <0x1CA10204>; + cmu_id = <0x1CA00000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_tpu: pd-tpu@18062900 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062900 0x20>; + cal_id = <0xB1380018>; + need_smc = <0x1CC10204>; + cmu_id = <0x1CC00000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_aur: pd-aur@18062980 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062980 0x20>; + cal_id = <0xB1380019>; + need_smc = <0x25A10204>; + cmu_id = <0x25A00000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + dbgdev-pd-aoc { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_aoc>; + }; + + dbgdev-pd-eh { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_eh>; + }; + + dbgdev-pd-embedded_g3d { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_embedded_g3d>; + }; + + dbgdev-pd-g3d { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_g3d>; + }; + + dbgdev-pd-hsi0 { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_hsi0>; + }; + + dbgdev-pd-hsi2 { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_hsi2>; + }; + + dbgdev-pd-dpu { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_dpu>; + }; + + dbgdev-pd-disp { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_disp>; + }; + + dbgdev-pd-g2d { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_g2d>; + }; + + dbgdev-pd-mfc { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_mfc>; + }; + + dbgdev-pd-csis { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_csis>; + }; + + dbgdev-pd-pdp { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_pdp>; + }; + + dbgdev-pd-dns { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_dns>; + }; + + dbgdev-pd-g3aa { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_g3aa>; + }; + + dbgdev-pd-ipp { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_ipp>; + }; + + dbgdev-pd-itp { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_itp>; + }; + + dbgdev-pd-mcsc { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_mcsc>; + }; + + dbgdev-pd-gdc { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_gdc>; + }; + + dbgdev-pd-tnr { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_tnr>; + }; + + dbgdev-pd-bo { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_bo>; + }; + + dbgdev-pd-tpu { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_tpu>; + }; + + dbgdev-pd-aur { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_aur>; + }; +};
diff --git a/dts/gs201-pmic.dtsi b/dts/gs201-pmic.dtsi new file mode 100644 index 0000000..13fe9bd --- /dev/null +++ b/dts/gs201-pmic.dtsi
@@ -0,0 +1,1373 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * gs201 pmic device tree source + * + * Copyright 2021 Google LLC. + * + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/gs201.h> +#include <dt-bindings/regulator/samsung,s2mpg-regulator.h> +#include <dt-bindings/power/google-power.h> +#include <arm64/exynos/exynos-pinctrl.h> +#include "gs101-pinctrl.h" + +&pinctrl_0 { + m_pmic_irq: m-pmic-irq { + samsung,pins = "gpa0-6"; + samsung,pin-pud = <0>; + }; + + s_pmic_irq: s-pmic-irq { + samsung,pins = "gpa0-7"; + samsung,pin-pud = <0>; + }; + + smpl_warn: smpl-warn { + samsung,pins = "gpa5-0"; /* SMPL_WARN_R_L */ + samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; + }; +}; + +&acpm_mfd_bus0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + s2mpg12mfd: s2mpg12mfd@1f { + compatible = "samsung,s2mpg12mfd"; + acpm-ipc-channel = <2>; + s2mpg12,wakeup = "enabled"; + reg = <0x1f>; + interrupts = <GIC_SPI IRQ_INTCOMB_VGPIO2AP_ALIVE IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + pinctrl-names = "default"; + pinctrl-0 = <&m_pmic_irq &smpl_warn>; + gpios = <&gpa5 0 0>, /* SMPL_WARN_R_L */ + <&gpa5 1 0>, /* OCP_WARN_CPUCL1_R */ + <&gpa5 2 0>, /* OCP_WARN_CPUCL2_R */ + <&gpa5 3 0>, /* SOFT_OCP_WARN_CPUCL1_R */ + <&gpa5 4 0>, /* SOFT_OCP_WARN_CPUCL2_R */ + <&gpp19 1 0>, /* OCP_WARN_TPU_R */ + <&gpp19 3 0>; /* SOFT_OCP_WARN_TPU_R */ + #thermal-sensor-cells = <1>; + + /* SMPL_WARN */ + smpl_warn_en = <1>; /* 1 : enable , 0 : disable */ + smpl_warn_vth = <SMPL_2_9V>; + /* SMPL_Hys[4:3] */ + /* 00(Reserved), 01(200mV), 10(300mV), 11(Reserved) */ + smpl_warn_hys = <SMPL_HYST_200MV>; + + /* OCP WARN */ + b2_ocp_warn_en = <1>; /* 1 : enable, 0 : disable */ + /* ocp warn reset timing control */ + b2_ocp_warn_cnt = <0>; /* 0 : 2 clock, 1 : 32 clock */ + /* ocp warn mask when dvs */ + b2_ocp_warn_dvs_mask = <0>; /* 0 : not masked, 1 : masked */ + b2_ocp_warn_lvl = <0>; /* 12.0A */ + + b3_ocp_warn_en = <1>; /* 1 : enable, 0 : disable */ + b3_ocp_warn_cnt = <0>; /* 0 : 2 clock, 1 : 32 clock */ + b3_ocp_warn_dvs_mask = <0>; /* 0 : not masked, 1 : masked */ + b3_ocp_warn_lvl = <0>; /* 8.0A */ + + b10_ocp_warn_en = <1>; /* 1 : enable, 0 : disable */ + b10_ocp_warn_cnt = <0>; /* 0 : 2 clock, 1 : 32 clock */ + b10_ocp_warn_dvs_mask = <0>;/* 0 : not masked, 1 : masked */ + b10_ocp_warn_lvl = <0>; /* 12A */ + + b2_soft_ocp_warn_en = <0>; /* 1 : enable, 0 : disable */ + b2_soft_ocp_warn_cnt = <0>; /* 0 : 2 clock, 1 : 32 clock */ + b2_soft_ocp_warn_dvs_mask = <0>;/* 0 : not masked, 1 : masked */ + b2_soft_ocp_warn_lvl = <20>; /* 9.0A */ + + b3_soft_ocp_warn_en = <0>; /* 1 : enable, 0 : disable */ + b3_soft_ocp_warn_cnt = <0>; /* 0 : 2 clock, 1 : 32 clock */ + b3_soft_ocp_warn_dvs_mask = <0>;/* 0 : not masked, 1 : masked */ + b3_soft_ocp_warn_lvl = <0>; /* 7.0A */ + + b10_soft_ocp_warn_en = <0>; /* 1 : enable, 0 : disable */ + b10_soft_ocp_warn_cnt = <0>; /* 0 : 2 clock, 1 : 32 clock */ + b10_soft_ocp_warn_dvs_mask = <0>; /* 0 : not masked, 1 : masked */ + b10_soft_ocp_warn_lvl = <0>; /* 8.5A */ + + /* BUCK OCP Detection */ + buck_ocp_ctrl1 = <0xBB>; + buck_ocp_ctrl2 = <0xBB>; + buck_ocp_ctrl3 = <0xBB>; + buck_ocp_ctrl4 = <0xBB>; + buck_ocp_ctrl5 = <0xBB>; + + /* RTC: wtsr/smpl */ + wtsr_en = "enabled"; /* enable */ + coldrst_en = "disabled"; + smpl_en = "disabled"; /* disable */ + wtsr_timer_val = <3>; /* 1000ms */ + coldrst_timer_val = <3>; /* 256ms */ + smpl_timer_val = <4>; /* 500ms */ + sub_smpl_en = "disabled"; /* disable */ + check_jigon = <0>; /* do not check jigon */ + + /* RTC: If first boot, reset rtc to 1/1/2020 12:00:00(Wed) */ + init_time,sec = <0>; + init_time,min = <0>; + init_time,hour = <12>; + init_time,mday = <1>; + init_time,mon = <0>; + init_time,year = <120>; + init_time,wday = <3>; + + /* PCTRLSEL(VGPIO) 1~14 (CONTROL_SEL#) */ + sel_vgpio = <0xC2 0x0B 0x22 0xA2 0x2D 0x2F 0x55 0x55 + 0x0B 0x7D 0x32 0x3C 0x80 0x80>; + + s2mpg12-keys { + button@1 { + label = "pmic-keys: KEY_POWER"; + linux,code = <116>; + wakeup = <1>; + }; + }; + + regulators { + m_buck1_reg: BUCK1M { + regulator-name = "S2MPG12_BUCK1"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x1>; + schematic-name = "S1M_VDD_MIF"; + subsys-name = "MIF"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x1>; + }; + + m_buck2_reg: BUCK2M { + regulator-name = "S2MPG12_BUCK2"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x2>; + schematic-name = "S2M_VDD_CPUCL2"; + subsys-name = "CPU(BIG)"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x2>; + odpm_disable_in_sleep; + }; + + m_buck3_reg: BUCK3M { + regulator-name = "S2MPG12_BUCK3"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x3>; + schematic-name = "S3M_VDD_CPUCL1"; + subsys-name = "CPU(MID)"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x4>; + odpm_disable_in_sleep; + }; + + m_buck4_reg: BUCK4M { + regulator-name = "S2MPG12_BUCK4"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x4>; + schematic-name = "S4M_VDD_CPUCL0"; + subsys-name = "CPU(LITTLE)"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x8>; + odpm_disable_in_sleep; + }; + + m_buck5_reg: BUCK5M { + regulator-name = "S2MPG12_BUCK5"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x5>; + schematic-name = "S5M_VDD_INT"; + subsys-name = "INT"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x10>; + odpm_disable_in_sleep; + }; + + m_buck6_reg: BUCK6M { + regulator-name = "S2MPG12_BUCK6"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x6>; + schematic-name = "S6M_LLDO1"; + subsys-name = "LDO"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x20>; + odpm_disable_in_sleep; + }; + + m_buck7_reg: BUCK7M { + regulator-name = "S2MPG12_BUCK7"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x7>; + schematic-name = "S7M_VDD_INT_M"; + subsys-name = "INT"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x40>; + odpm_disable_in_sleep; + }; + + m_buck8_reg: BUCK8M { + regulator-name = "S2MPG12_BUCK8"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x8>; + schematic-name = "S8M_LLDO2"; + subsys-name = "LDO"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x80>; + }; + + m_buck9_reg: BUCK9M { + regulator-name = "S2MPG12_BUCK9"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x9>; + schematic-name = "S9M_LLDO3"; + subsys-name = "LDO"; + buck_rail; + channel-en-byte-offset = <1>; + channel-en-index = <0x1>; + }; + + m_buck10_reg: BUCK10M { + regulator-name = "S2MPG12_BUCK10"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0xA>; + schematic-name = "S10M_VDD_TPU"; + subsys-name = "TPU"; + buck_rail; + channel-en-byte-offset = <1>; + channel-en-index = <0x2>; + odpm_disable_in_sleep; + }; + + m_ldo1_reg: LDO1M { + regulator-name = "S2MPG12_LDO1"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x21>; + schematic-name = "L1M_ALIVE"; + subsys-name = "Alive"; + }; + + m_ldo2_reg: LDO2M { + regulator-name = "S2MPG12_LDO2"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x22>; + schematic-name = "L2M_ALIVE"; + subsys-name = "Alive"; + }; + + m_ldo3_reg: LDO3M { + regulator-name = "S2MPG12_LDO3"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x23>; + schematic-name = "L3M_VDD_AOC_RET"; + subsys-name = "AOC"; + }; + + m_ldo4_reg: LDO4M { + regulator-name = "S2MPG12_LDO4"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x24>; + schematic-name = "L4M_HSI"; + subsys-name = "IO"; + }; + + m_ldo5_reg: LDO5M { + regulator-name = "S2MPG12_LDO5"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x25>; + schematic-name = "L5M_TCXO"; + subsys-name = "PLL"; + }; + + m_ldo6_reg: LDO6M { + regulator-name = "S2MPG12_LDO6"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x26>; + schematic-name = "L6M_PLL"; + subsys-name = "PLL"; + }; + + m_ldo7_reg: LDO7M { + regulator-name = "S2MPG12_LDO7"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x27>; + schematic-name = "L7M_VDD_HSI"; + subsys-name = "IO"; + }; + + m_ldo8_reg: LDO8M { + regulator-name = "S2MPG12_LDO8"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x28>; + schematic-name = "L8M_USB"; + subsys-name = "USB"; + }; + + m_ldo9_reg: LDO9M { + regulator-name = "S2MPG12_LDO9"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x29>; + schematic-name = "L9M_USB"; + subsys-name = "USB"; + }; + + m_ldo10_reg: LDO10M { + regulator-name = "S2MPG12_LDO10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3350000>; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x2A>; + schematic-name = "L10M_USB"; + subsys-name = "USB"; + }; + + m_ldo11_reg: LDO11M { + regulator-name = "S2MPG12_LDO11"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x2B>; + schematic-name = "L11M_VDD_CPUCL1_M"; + subsys-name = "CPU(MID)"; + }; + + m_ldo12_reg: LDO12M { + regulator-name = "S2MPG12_LDO12"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x2C>; + schematic-name = "L12M_VDD_CPUCL0_M"; + subsys-name = "CPU(LITTLE)"; + }; + + m_ldo13_reg: LDO13M { + regulator-name = "S2MPG12_LDO13"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x2D>; + schematic-name = "L13M_VDD_TPU_M"; + subsys-name = "TPU"; + }; + + m_ldo14_reg: LDO14M { + regulator-name = "S2MPG12_LDO14"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x2E>; + schematic-name = "L14M_TCXO"; + subsys-name = "PLL"; + }; + + m_ldo15_reg: LDO15M { + regulator-name = "S2MPG12_LDO15"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x2F>; + schematic-name = "L15M_VDD_SLC_M"; + subsys-name = "SLC"; + }; + + m_ldo16_reg: LDO16M { + regulator-name = "S2MPG12_LDO16"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x30>; + schematic-name = "L16M_PCIE0"; + subsys-name = "PCIE"; + }; + + m_ldo17_reg: LDO17M { + regulator-name = "S2MPG12_LDO17"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x31>; + schematic-name = "L17M_VDD_CPUCL2_M"; + subsys-name = "CPU(BIG)"; + }; + + m_ldo18_reg: LDO18M { + regulator-name = "S2MPG12_LDO18"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x32>; + schematic-name = "L18M_PCIE0"; + subsys-name = "PCIE"; + }; + + m_ldo19_reg: LDO19M { + regulator-name = "S2MPG12_LDO19"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x33>; + schematic-name = "L19M_SPARE"; + subsys-name = "Spare"; + }; + + m_ldo20_reg: LDO20M { + regulator-name = "S2MPG12_LDO20"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x34>; + schematic-name = "L20M_DMIC1"; + subsys-name = "DMIC"; + }; + + m_ldo21_reg: LDO21M { + regulator-name = "S2MPG12_LDO21"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x35>; + schematic-name = "L21M_GSC"; + subsys-name = "GSC"; + }; + + m_ldo22_reg: LDO22M { + regulator-name = "S2MPG12_LDO22"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x36>; + schematic-name = "L22M_SPARE"; + subsys-name = "Spare"; + }; + + m_ldo23_reg: LDO23M { + regulator-name = "S2MPG12_LDO23"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x37>; + schematic-name = "L23M_DMIC2"; + subsys-name = "DMIC"; + }; + + m_ldo24_reg: LDO24M { + regulator-name = "S2MPG12_LDO24"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x38>; + schematic-name = "L24M_DISP_VDDI"; + subsys-name = "Display"; + }; + + m_ldo25_reg: LDO25M { + regulator-name = "S2MPG12_LDO25"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x39>; + schematic-name = "L25M_TSP_DVDD"; + subsys-name = "TSP"; + }; + + m_ldo26_reg: LDO26M { + regulator-name = "S2MPG12_LDO26"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x3A>; + schematic-name = "L26M_TS_AVDD"; + subsys-name = "TS"; + }; + + m_ldo27_reg: LDO27M { + regulator-name = "S2MPG12_LDO27"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x3B>; + schematic-name = "L27M_DISP_VCI"; + subsys-name = "Display"; + }; + + m_ldo28_reg: LDO28M { + regulator-name = "S2MPG12_LDO28"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x3C>; + schematic-name = "L28M_DISP"; + subsys-name = "Display"; + }; + }; + + odpm { + chip-name = "S2MPG12"; + sample-rate-uhz = <125000000>; + sample-rate-external-uhz = <31250000>; + + /* 120 minutes was selected as the spec + * for the sample rate (125sps) + * + * Note, this can be verified based on the + * number of bits in the ACC registers. + * ACC_COUNT is 20 bits. Thus, + * 2^20 - 1 = 1048575 ==> 8388.6 seconds + * ==> 139.81 minutes + */ + max-refresh-time-ms = <(120 * 60 * 1000)>; + + channels { + ch1: channel@0 { + rail-name = "VSEN_C1"; + channel_enabled; + }; + + ch2: channel@1 { + rail-name = "VSEN_C2"; + channel_enabled; + }; + + ch3: channel@2 { + rail-name = "VSEN_C3"; + channel_enabled; + }; + + ch4: channel@3 { + rail-name = "BUCK1M"; + channel_enabled; + }; + + ch5: channel@4 { + rail-name = "BUCK2M"; + channel_enabled; + }; + + ch6: channel@5 { + rail-name = "BUCK3M"; + channel_enabled; + }; + + ch7: channel@6 { + rail-name = "BUCK4M"; + channel_enabled; + }; + + ch8: channel@7 { + rail-name = "BUCK5M"; + channel_enabled; + }; + + ch9: channel@8 { + rail-name = "BUCK8M"; + channel_enabled; + }; + + ch10: channel@9 { + rail-name = "LDO15M"; + channel_enabled; + }; + + ch11: channel@10 { + rail-name = "BUCK10M"; + channel_enabled; + }; + + ch12: channel@11 { + rail-name = "BUCK6M"; + channel_enabled; + }; + }; + + rails { + use-regulators-as-rails; + + /* Additional rails */ + /* Note; VSEN_P is not supported */ + + m_ext4_rail: VSEN_C1 { + external_rail; + channel-en-index = <1>; + channel-mux-selection = <0x5C>; + shunt-res-uohms = <10000>; + schematic-name = "VSYS_PWR_MMWAVE"; + subsys-name = "Cellular"; + }; + + m_ext5_rail: VSEN_C2 { + external_rail; + channel-en-index = <2>; + channel-mux-selection = <0x5D>; + shunt-res-uohms = <5000>; + schematic-name = "VSYS_PWR_MODEM"; + subsys-name = "Modem"; + }; + + m_ext6_rail: VSEN_C3 { + external_rail; + channel-en-index = <4>; + channel-mux-selection = <0x5E>; + shunt-res-uohms = <5000>; + schematic-name = "VSYS_PWR_RFFE"; + subsys-name = "Cellular"; + }; + }; + }; + + s2mpg12_gpio: s2mpg12_gpio { + gpio-controller; + #gpio-cells = <2>; + ngpios = <6>; + gpio-ranges = <&s2mpg12_pinctrl 0 0 6>; + }; + + s2mpg12_pinctrl: s2mpg12_pinctrl { + }; + }; +}; + +&acpm_mfd_bus1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + s2mpg13mfd: s2mpg13mfd@2f { + compatible = "samsung,s2mpg13mfd"; + acpm-ipc-channel = <2>; + s2mpg13,wakeup = "enabled"; + reg = <0x2f>; + interrupts = <1 0 0>, // OCP_WARN_GPU + <1 0 1>; // SOFT_OCP_WARN_GPU + interrupt-parent = <&gpa0>; + pinctrl-names = "default"; + pinctrl-0 = <&s_pmic_irq>; + gpios = <&gpp19 0 0>, + <&gpp19 2 0>; + #thermal-sensor-cells = <1>; + + b2_ocp_warn_en = <1>; /* 1 : enable, 0 : disable */ + b2_ocp_warn_cnt = <0>; /* 0 : 2 clock, 1 : 32 clock */ + b2_ocp_warn_dvs_mask = <0>; /* 0 : not masked, 1 : masked */ + b2_ocp_warn_lvl = <0>; /* 12.0A */ + + b2_soft_ocp_warn_en = <0>; /* 1 : enable, 0 : disable */ + b2_soft_ocp_warn_cnt = <0>; /* 0 : 2 clock, 1 : 32 clock */ + b2_soft_ocp_warn_dvs_mask = <0>;/* 0 : not masked, 1 : masked */ + b2_soft_ocp_warn_lvl = <0>; /* 12.0A */ + + /* BUCK OCP Detection */ + buck_ocp_ctrl1 = <0xBB>; + buck_ocp_ctrl2 = <0xBB>; + buck_ocp_ctrl3 = <0xBB>; + buck_ocp_ctrl4 = <0xBB>; + buck_ocp_ctrl5 = <0xBB>; + buck_ocp_ctrl6 = <0xBB>; + buck_ocp_ctrl7 = <0x0B>; + + /* PCTRLSEL(VGPIO) 1~11 (CONTROL_SEL#) */ + sel_vgpio = <0x92 0x92 0x69 0x0A 0x9A 0x12 + 0xCA 0x81 0x08 0x00 0x8A>; + + regulators { + s_buck1_reg: BUCK1S { + regulator-name = "S2MPG13_BUCK1"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x1>; + schematic-name = "S1S_VDD_CAM"; + subsys-name = "Multimedia"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x1>; + odpm_disable_in_sleep; + }; + + s_buck2_reg: BUCK2S { + regulator-name = "S2MPG13_BUCK2"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x2>; + schematic-name = "S2S_VDD_G3D"; + subsys-name = "GPU"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x2>; + odpm_disable_in_sleep; + }; + + s_buck3_reg: BUCK3S { + regulator-name = "S2MPG13_BUCK3"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x3>; + schematic-name = "S3S_LLDO1"; + subsys-name = "LDO"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x4>; + }; + + s_buck4_reg: BUCK4S { + regulator-name = "S2MPG13_BUCK4"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x4>; + schematic-name = "S4S_VDD2H_MEM"; + subsys-name = "DDR"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x8>; + }; + + s_buck5_reg: BUCK5S { + regulator-name = "S2MPG13_BUCK5"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x5>; + schematic-name = "S5S_VDDQ_MEM"; + subsys-name = "DDR"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x10>; + }; + + s_buck6_reg: BUCK6S { + regulator-name = "S2MPG13_BUCK6"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x6>; + schematic-name = "S6S_LLDO2"; + subsys-name = "LDO"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x20>; + }; + + s_buck7_reg: BUCK7S { + regulator-name = "S2MPG13_BUCK7"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2200000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x7>; + schematic-name = "S7S_MLDO"; + subsys-name = "LDO"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x40>; + }; + + s_buck8_reg: BUCK8S { + regulator-name = "S2MPG13_BUCK8"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x8>; + schematic-name = "S8S_VDD_G3D_L2"; + subsys-name = "GPU"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x80>; + odpm_disable_in_sleep; + }; + + s_buck9_reg: BUCK9S { + regulator-name = "S2MPG13_BUCK9"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x9>; + schematic-name = "S9S_VDD_AOC"; + subsys-name = "AOC"; + buck_rail; + channel-en-byte-offset = <1>; + channel-en-index = <0x1>; + }; + + s_buck10_reg: BUCK10S { + regulator-name = "S2MPG13_BUCK10"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0xA>; + schematic-name = "S10S_LLDO3"; + subsys-name = "LDO"; + buck_rail; + channel-en-byte-offset = <1>; + channel-en-index = <0x2>; + }; + + s_bucka_reg: BUCKA { + regulator-name = "S2MPG13_BUCKA"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2100000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0xC>; + schematic-name = "SA"; + subsys-name = "IO"; + buck_rail; + channel-en-byte-offset = <1>; + channel-en-index = <0x8>; + }; + + s_buckboost_reg: BUCKBOOST { + regulator-name = "S2MPG13_BUCKBOOST"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x10>; + schematic-name = "BB_HLDO"; + subsys-name = "LDO"; + buck_rail; + channel-en-byte-offset = <1>; + channel-en-index = <0x10>; + }; + + s_buckc_reg: BUCKC { + regulator-name = "S2MPG13_BUCKC"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0xD>; + schematic-name = "SC"; + subsys-name = "IO"; + buck_rail; + channel-en-byte-offset = <1>; + channel-en-index = <0x8>; + }; + + s_buckd_reg: BUCKD { + regulator-name = "S2MPG13_BUCKD"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0xB>; + schematic-name = "SD"; + subsys-name = "IO"; + buck_rail; + channel-en-byte-offset = <1>; + channel-en-index = <0x4>; + }; + + s_ldo1_reg: LDO1S { + regulator-name = "S2MPG13_LDO1"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x21>; + schematic-name = "L1S_VDD_G3D_M"; + subsys-name = "GPU"; + }; + + s_ldo2_reg: LDO2S { + regulator-name = "S2MPG13_LDO2"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x22>; + schematic-name = "L2S_PLL_MIPI_UFS"; + subsys-name = "PLL"; + }; + + s_ldo3_reg: LDO3S { + regulator-name = "S2MPG13_LDO3"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x23>; + schematic-name = "L3S_PCIE1"; + subsys-name = "PCIE"; + }; + + s_ldo4_reg: LDO4S { + regulator-name = "S2MPG13_LDO4"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x24>; + schematic-name = "L4S_HS_AMP"; + subsys-name = "Audio"; + }; + + s_ldo5_reg: LDO5S { + regulator-name = "S2MPG13_LDO5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x25>; + schematic-name = "L5S_PROX"; + subsys-name = "Prox"; + }; + + s_ldo6_reg: LDO6S { + regulator-name = "S2MPG13_LDO6"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x26>; + schematic-name = "L6S_DISP2_VCI"; + subsys-name = "Display"; + }; + + s_ldo7_reg: LDO7S { + regulator-name = "S2MPG13_LDO7"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x27>; + schematic-name = "L7S_SENSORS_FPS"; + subsys-name = "Sensors"; + }; + + s_ldo8_reg: LDO8S { + regulator-name = "S2MPG13_LDO8"; + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1275000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x28>; + schematic-name = "L8S_UFS_VCCQ"; + subsys-name = "UFS"; + }; + + s_ldo9_reg: LDO9S { + regulator-name = "S2MPG13_LDO9"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x29>; + schematic-name = "L9S_GNSS_CORE"; + subsys-name = "GPS"; + }; + + s_ldo10_reg: LDO10S { + regulator-name = "S2MPG13_LDO10"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x2A>; + schematic-name = "L10S_GNSS_RF"; + subsys-name = "GPS"; + }; + + s_ldo11_reg: LDO11S { + regulator-name = "S2MPG13_LDO11"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x2B>; + schematic-name = "L11S_GNSS_AUX"; + subsys-name = "GPS"; + }; + + s_ldo12_reg: LDO12S { + regulator-name = "S2MPG13_LDO12"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x2C>; + schematic-name = "L12S_TS2_DVDD"; + subsys-name = "Touch"; + }; + + s_ldo13_reg: LDO13S { + regulator-name = "S2MPG13_LDO13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3350000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x2D>; + schematic-name = "L13S_DPAUX"; + subsys-name = "Display"; + }; + + s_ldo14_reg: LDO14S { + regulator-name = "S2MPG13_LDO14"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x2E>; + schematic-name = "L14S_NFC"; + subsys-name = "NFC"; + }; + + s_ldo15_reg: LDO15S { + regulator-name = "S2MPG13_LDO15"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x2F>; + schematic-name = "L15S_UDFPS"; + subsys-name = "FPS"; + }; + + s_ldo16_reg: LDO16S { + regulator-name = "S2MPG13_LDO16"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x30>; + schematic-name = "L16S_UWB"; + subsys-name = "UWB"; + }; + + s_ldo17_reg: LDO17S { + regulator-name = "S2MPG13_LDO17"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x31>; + schematic-name = "L17S_UWB"; + subsys-name = "UWB"; + }; + + s_ldo18_reg: LDO18S { + regulator-name = "S2MPG13_LDO18"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_SUSPEND>; + channel-mux-selection = <0x32>; + schematic-name = "L18S_PCIE1"; + subsys-name = "PCIE"; + }; + + s_ldo19_reg: LDO19S { + regulator-name = "S2MPG13_LDO19"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x33>; + schematic-name = "L19S_DMIC3"; + subsys-name = "DMIC"; + }; + + s_ldo20_reg: LDO20S { + regulator-name = "S2MPG13_LDO20"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x34>; + schematic-name = "L20S_DMIC45"; + subsys-name = "DMIC"; + }; + + s_ldo21_reg: LDO21S { + regulator-name = "S2MPG13_LDO21"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = <SEC_OPMODE_ON>; + channel-mux-selection = <0x35>; + schematic-name = "L21S_VDD2L_MEM"; + subsys-name = "DDR"; + }; + + s_ldo22_reg: LDO22S { + regulator-name = "S2MPG13_LDO22"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x36>; + schematic-name = "L22S_UDFPS"; + subsys-name = "FPS"; + }; + + s_ldo23_reg: LDO23S { + regulator-name = "S2MPG13_LDO23"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x37>; + schematic-name = "L23S_SPARE"; + subsys-name = "Spare"; + }; + + s_ldo24_reg: LDO24S { + regulator-name = "S2MPG13_LDO24"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x38>; + schematic-name = "L24S_SPARE"; + subsys-name = "Spare"; + }; + + s_ldo25_reg: LDO25S { + regulator-name = "S2MPG13_LDO25"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x39>; + schematic-name = "L25S_SPARE"; + subsys-name = "Spare"; + }; + + s_ldo26_reg: LDO26S { + regulator-name = "S2MPG13_LDO26"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x3A>; + schematic-name = "L26S_S5910"; + subsys-name = "S5910"; + }; + + s_ldo27_reg: LDO27S { + regulator-name = "S2MPG13_LDO27"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x3B>; + schematic-name = "L27S_S5910"; + subsys-name = "S5910"; + }; + + s_ldo28_reg: LDO28S { + regulator-name = "S2MPG13_LDO28"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <SEC_OPMODE_OFF>; + channel-mux-selection = <0x3C>; + schematic-name = "L28S_HS_AMP"; + subsys-name = "Audio"; + }; + }; + + odpm { + chip-name = "S2MPG13"; + sample-rate-uhz = <125000000>; + sample-rate-external-uhz = <31250000>; + + /* 120 minutes was selected as the spec + * for the sample rate (125sps) + * + * Note, this can be verified based on the + * number of bits in the ACC registers. + * ACC_COUNT is 20 bits. Thus, + * 2^20 - 1 = 1048575 ==> 8388.6 seconds + * ==> 139.81 minutes + */ + max-refresh-time-ms = <(120 * 60 * 1000)>; + + channels { + ch13: channel@0 { + rail-name = "VSEN_C4"; + channel_enabled; + }; + + ch14: channel@1 { + rail-name = "VSEN_C5"; + channel_enabled; + }; + + ch15: channel@2 { + rail-name = "LDO9S"; + channel_enabled; + }; + + ch16: channel@3 { + rail-name = "BUCK1S"; + channel_enabled; + }; + + ch17: channel@4 { + rail-name = "BUCK2S"; + channel_enabled; + }; + + ch18: channel@5 { + rail-name = "BUCK4S"; + channel_enabled; + }; + + ch19: channel@6 { + rail-name = "BUCK5S"; + channel_enabled; + }; + + ch20: channel@7 { + rail-name = "BUCK8S"; + channel_enabled; + }; + + ch21: channel@8 { + rail-name = "BUCK9S"; + channel_enabled; + }; + + ch22: channel@9 { + rail-name = "LDO7S"; + channel_enabled; + }; + + ch23: channel@10 { + rail-name = "LDO14S"; + channel_enabled; + }; + + ch24: channel@11 { + rail-name = "LDO2S"; + channel_enabled; + }; + }; + + rails { + use-regulators-as-rails; + + /* Additional rails */ + /* Note; VSEN_P is not supported */ + + s_ext4_rail: VSEN_C4 { + external_rail; + channel-en-index = <1>; + channel-mux-selection = <0x5C>; + shunt-res-uohms = <10000>; + schematic-name = "VSYS_PWR_DISPLAY"; + subsys-name = "Display"; + }; + + s_ext5_rail: VSEN_C5 { + external_rail; + channel-en-index = <2>; + channel-mux-selection = <0x5D>; + shunt-res-uohms = <10000>; + schematic-name = "VSYS_PWR_WLAN_BT"; + subsys-name = "WLAN-BT"; + }; + + s_ext6_rail: VSEN_C6 { + external_rail; + channel-en-index = <4>; + channel-mux-selection = <0x5E>; + shunt-res-uohms = <5000>; + schematic-name = "VSEN_C6_NC"; + subsys-name = "Spare"; + }; + }; + }; + + s2mpg13_gpio: s2mpg13_gpio { + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + gpio-ranges = <&s2mpg13_pinctrl 0 0 8>; + }; + + s2mpg13_pinctrl: s2mpg13_pinctrl { + }; + }; +}; + +&acpm_mbox_test { + main-pmic = <&s2mpg12mfd>; + sub-pmic = <&s2mpg13mfd>; + acpm-ipc-channel = <2>; +};
diff --git a/dts/gs201-ppmu.dtsi b/dts/gs201-ppmu.dtsi new file mode 100644 index 0000000..02157ea --- /dev/null +++ b/dts/gs201-ppmu.dtsi
@@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS201 PPMU device tree source + * + * Copyright (c) 2021 Google LLC. + * + */ + +#include <dt-bindings/soc/google/exynos-bcm_dbg.h> + +/ { + gs201-ppmu { + compatible = "samsung,exynos-bcm_dbg"; + + pd-name = "pd-csis", "pd-ipp", "pd-tnr", "pd-bo", "pd-g2d", + "pd-misc", "pd-dpu", "pd-pdp", "pd-g3aa", "pd-dns", + "pd-mcsc", "pd-gdc", "pd-mfc", "pd-hsi2", "pd-eh", + "pd-tpu", "pd-gsa", "pd-aoc", "pd-hsi0", "pd-hsi1", + "pd-aur", "pd-itp"; + + max_define_event = <PRE_DEFINE_EVT_MAX>; + /* define_event_index ev0 ev1 ev2 ev3 ev4 ev5 ev6 ev7 */ + define_events = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, + <LATENCY_FMT_EVT 0x4 0x2 0x26 0x24 0x5 0x3 0x27 0x25>, + <MO_FMT_EVT 0x4 0x0 0x24 0x24 0x5 0x1 0x25 0x25>, + <BURST_LENGTH_FMT_EVT 0x4 0x2 0x4 0x26 0x5 0x3 0x5 0x27>, + <REQ_BLOCK_FMT_EVT 0x2 0x10 0x10 0x26 0x3 0x11 0x11 0x27>, + <DATA_BLOCK_FMT_EVT 0x4 0x12 0x12 0x6 0x5 0x13 0x13 0x14>, + <REQ_TYPE_FMT_EVT 0x2 0x15 0x18 0x1B 0x3 0x16 0x19 0x1C>; + default_define_event = <LATENCY_FMT_EVT>; + + /* sm_id_mask sm_id_value */ + define_filter_id = <NO_PRE_DEFINE_EVT 0x0 0x0>, + <LATENCY_FMT_EVT 0x0 0x0>, + <MO_FMT_EVT 0x0 0x0>, + <BURST_LENGTH_FMT_EVT 0x0 0x0>, + <REQ_BLOCK_FMT_EVT 0x0 0x0>, + <DATA_BLOCK_FMT_EVT 0x0 0x0>, + <REQ_TYPE_FMT_EVT 0x0 0x0>; + /* ev0 ev1 ev2 ev3 ev4 ev5 ev6 ev7 */ + define_filter_id_active = + <NO_PRE_DEFINE_EVT 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, + <LATENCY_FMT_EVT 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, + <MO_FMT_EVT 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, + <BURST_LENGTH_FMT_EVT 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, + <REQ_BLOCK_FMT_EVT 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, + <DATA_BLOCK_FMT_EVT 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, + <REQ_TYPE_FMT_EVT 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + /* sm_other_type0 sm_other_mask0 sm_other_value0 */ + define_filter_other_0 = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0>, + <LATENCY_FMT_EVT 0x0 0x0 0x0>, + <MO_FMT_EVT 0x0 0x0 0x0>, + <BURST_LENGTH_FMT_EVT 0x0 0x0 0x0>, + <REQ_BLOCK_FMT_EVT 0x0 0x0 0x0>, + <DATA_BLOCK_FMT_EVT 0x0 0x0 0x0>, + <REQ_TYPE_FMT_EVT 0x0 0x0 0x0>; + /* sm_other_type1 sm_other_mask1 sm_other_value1 */ + define_filter_other_1 = <NO_PRE_DEFINE_EVT 0x0 0x0 0x0>, + <LATENCY_FMT_EVT 0x0 0x0 0x0>, + <MO_FMT_EVT 0x0 0x0 0x0>, + <BURST_LENGTH_FMT_EVT 0x0 0x0 0x0>, + <REQ_BLOCK_FMT_EVT 0x0 0x0 0x0>, + <DATA_BLOCK_FMT_EVT 0x0 0x0 0x0>, + <REQ_TYPE_FMT_EVT 0x0 0x0 0x0>; + /* ev0 ev1 ev2 ev3 ev4 ev5 ev6 ev7 */ + define_filter_other_active = + <NO_PRE_DEFINE_EVT 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, + <LATENCY_FMT_EVT 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, + <MO_FMT_EVT 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, + <BURST_LENGTH_FMT_EVT 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, + <REQ_BLOCK_FMT_EVT 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, + <DATA_BLOCK_FMT_EVT 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, + <REQ_TYPE_FMT_EVT 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + + /* peak_mask peak_id */ + define_sample_id = <NO_PRE_DEFINE_EVT 0x0 0x0>, + <LATENCY_FMT_EVT 0x0 0x0>, + <MO_FMT_EVT 0x0 0x0>, + <BURST_LENGTH_FMT_EVT 0x0 0x0>, + <REQ_BLOCK_FMT_EVT 0x0 0x0>, + <DATA_BLOCK_FMT_EVT 0x0 0x0>, + <REQ_TYPE_FMT_EVT 0x0 0x0>; + /* ev0 ev1 ev2 ev3 ev4 ev5 ev6 ev7 */ + define_sample_id_enable = + <NO_PRE_DEFINE_EVT 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, + <LATENCY_FMT_EVT 0x0 0x0 0x1 0x0 0x0 0x0 0x1 0x0>, + <MO_FMT_EVT 0x0 0x0 0x1 0x0 0x0 0x0 0x1 0x0>, + <BURST_LENGTH_FMT_EVT 0x0 0x0 0x1 0x1 0x0 0x0 0x1 0x1>, + <REQ_BLOCK_FMT_EVT 0x0 0x0 0x1 0x1 0x0 0x0 0x1 0x1>, + <DATA_BLOCK_FMT_EVT 0x0 0x0 0x1 0x0 0x0 0x0 0x1 0x0>, + <REQ_TYPE_FMT_EVT 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + + bcm_ip_nr = <84>; + bcm_ip_print_nr = <10>; + + ip-name = "csis_d1", "csis_d0", "ipp", "msa", "d8_tnr", "d7_tnr", + "d6_tnr", "d5_tnr", "d4_tnr", "d3_tnr", "d2_tnr", + "d1_tnr", "d0_tnr", "bo", "d2_g2d", "d1_g2d", + "d0_g2d", "misc", "dpu2", "dpu1", "dpu0", + "pdp_vra", "g3aa", "d1_dns", "d0-dns", "d1_mcsc", "d0_mcsc", + "d1_itsc", "d0_itsc", "d3_gdc", "d2_gdc", "d1_gdc", "d0_gdc", "d2_scsc", + "d1_scsc", "d0_scsc", "d1_mfc", "d0_mfc", "hsi2", "tpu", + "gpu0", "gpu1", "gpu2", "gpu3", "bus2_m0", + "bus2_m1", "bus2_m2", "bus2_m3", "gsacore", "aoc", + "usb", "hsi0_bus0", "hsi0_aoc", "hsi1", "ace_cpucl1", + "ace_cpucl0", "cpu0", "cpu1", "cpu2", "cpu3", + "core_m0", "core_m1", "core_m2", "core_m3", "core_cci", + "core_dp", "bus0_m0", + "slc_ch0_1", "slc_ch0_0", "slc_ch1_1", "slc_ch1_0", "slc_ch2_1", + "slc_ch2_0", "slc_ch3_1", "slc_ch3_0", "slc_bcast_1", "slc_bcast_0", + "bus1_m0", "bus1_m1", "bus1_m2", "bus1_m3", "aur0", "aur1", "itp"; + + initial_run_bcm_ip = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>, + <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>, <20>, + <21>, <22>, <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>, + <31>, <32>, <33>, <34>, <35>, <36>, <37>, <38>, <39>, <40>, + <41>, <42>, <43>, <44>, <45>, <46>, <47>, + <51>, <52>, <53>, <54>, <55>, <56>, <57>, <58>, <59>, <60>, + <61>, <62>, <63>, <64>, <65>, <66>, <67>, <68>, <69>, <70>, + <71>, <72>, <73>, <74>, <77>, <78>, <79>, <80>, + <81>, <82>, <83>; + + initial_bcm_run = <BCM_STOP>; + /* usec (max 1000000 usec) */ + initial_period = <1000>; + initial_bcm_mode = <BCM_MODE_INTERVAL>; + available_stop_owner = <PANIC_HANDLE CAMERA_DRIVER MODEM_IF ITMON_HANDLE>; + buff_size = <0x100000>; + + ipc_bcm_event { + plugin-len = <5>; + plugin-name = "BCM"; + }; + }; +};
diff --git a/dts/gs201-pwm.dtsi b/dts/gs201-pwm.dtsi new file mode 100644 index 0000000..fe33df7 --- /dev/null +++ b/dts/gs201-pwm.dtsi
@@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Samsung's SoC PWM device tree source + * + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/ { + sec_pwm: pwm@10DF0000 { + compatible = "samsung,s3c6400-pwm"; + reg = <0x00000000 0x10DF0000 0x00001000>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>, <4>; + #pwm-cells = <3>; + clocks = <&clock GATE_PERIC1_TOP0_PWM>, <&clock OSCCLK>; + clock-names = "pwm_pclk", "pwm_sclk"; + status = "disabled"; + }; +};
diff --git a/dts/gs201-ravenclaw-fingerprint.dtsi b/dts/gs201-ravenclaw-fingerprint.dtsi new file mode 100644 index 0000000..c8939ed --- /dev/null +++ b/dts/gs201-ravenclaw-fingerprint.dtsi
@@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Goodix fps device tree source + * + * Copyright 2021 Google,LLC. + */ + +&pinctrl_4 { + goodixfp_pins: goodixfp_pins { + samsung,pins = "gpp1-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; +}; + +&odm { + goodixfp { + status = "okay"; + compatible = "goodix,fingerprint"; + interrupt-parent = <&gpa9>; + interrupts = <2 0>; + spi-max-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&goodixfp_pins>; + fp-gpio-irq = <&gpa9 2 GPIO_ACTIVE_HIGH>; + fp-gpio-reset = <&gpp1 1 GPIO_ACTIVE_LOW>; + }; + + fps_touch_handler: fps_touch_handler { + status = "okay"; + compatible = "google,fps-touch-handler"; + }; +};
diff --git a/dts/gs201-ravenclaw-uwb.dtsi b/dts/gs201-ravenclaw-uwb.dtsi new file mode 100644 index 0000000..e2445c1 --- /dev/null +++ b/dts/gs201-ravenclaw-uwb.dtsi
@@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS201 Board device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com +*/ + +#include <dt-bindings/gpio/gpio.h> +#include <arm64/exynos/exynos-pinctrl.h> +#include "gs101-pinctrl.h" + +&pinctrl_1 { + dw3xxx_irq: dw3xxx-irq { + samsung,pins = "gpa6-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PDN_PREV>; + }; +}; + + +&pinctrl_4 { + dw3xxx_ap_rst: dw3xxx-ap-rst { + samsung,pins = "gpp2-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PDN_PREV>; + }; +}; + +&spi_16 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpp26 3 GPIO_ACTIVE_LOW>; + num-cs = <1>; + + dw3xxx_prod@0 { + compatible = "decawave,dw3000"; + reg = <0>; + + interrupt-parent = <&gpa6>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi16_cs &dw3xxx_irq &dw3xxx_ap_rst>; + spi-max-frequency = <40000000>; + + uwbhal,reset-gpio = <&aoc_gpiochip 0 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + power_reg_2p5-supply = <&s_ldo16_reg>; + power_reg_1p8-supply = <&s_ldo17_reg>; + + decawave,eui64 = /bits/ 64 <0>; + decawave,panid = /bits/ 16 <0>; + + min_clamp = <900>; + + status = "okay"; + + }; +}; + +&spi16_bus { + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; +}; + +&spi16_cs { + samsung,pin-drv = <GS101_PIN_DRV_10_MA>; +}; +
diff --git a/dts/gs201-rmem.dtsi b/dts/gs201-rmem.dtsi new file mode 100644 index 0000000..0f55db0 --- /dev/null +++ b/dts/gs201-rmem.dtsi
@@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS201 SoC reserved memory + * + * Copyright 2021 Google LLC + */ + +#include <dt-bindings/soc/google/debug-snapshot-def.h> +#include <dt-bindings/soc/google/exynos-seclog.h> + +/ { + + bootloader_log { + compatible = "google,bldr_log"; + reg = <0x0 0xfd800000 0x80000>, <0x0 0xfd880000 0x80000>; + reg-names = "bl_log", "bl_old_log"; + memory-region = <&bldr_log_reserved>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + ect_binary: ect_binary { + compatible = "exynos,ect_rmem"; + reg = <0x0 0x90000000 0x0003A000>; + }; + + gsa_reserved_protected: gsa@90200000 { + reg = <0x0 0x90200000 0x400000>; + no-map; + }; + + tpu_fw_ctx_reserved: tpu_ctx@91E00000 { + reg = <0x0 0x91E00000 0x1200000>; + no-map; + }; + + tpu_fw_reserved: tpu_fw@93000000 { + reg = <0x0 0x93000000 0x1000000>; + no-map; + }; + + aoc_reserve: aoc@94000000 { + reg = <0x0 0x94000000 0x03000000>; + no-map; + }; + + gxp_fw_reserved: gxp_fw@98000000 { + reg = <0x0 0x98000000 0x0400000>; + no-map; + }; + + gxp_scratchpad_reserved: gxp_scratchpad@98400000 { + reg = <0x0 0x98400000 0x00100000>; + no-map; + }; + + abl_reserved: abl@f8800000 { + reg = <0x0 0xf8800000 0x02000000>; + no-map; + }; + + dss_log_reserved: dss_log_reserved@fd3f0000 { + reg = <0 0xfd3f0000 0x0000e000>; + no-map; + }; + + debug_kinfo_reserved: debug_kinfo_reserved@fd3fe000 { + reg = <0 0xfd3fe000 0x00001000>; + no-map; + }; + + suspend_diag_log_reserved: suspend_diag_log_reserved@fd90c000 { + reg = <0 0xfd90c000 0x00001000>; + no-map; + }; + + ramoops_mem@fd3ff000 { + compatible = "ramoops"; + reg = <0 0xfd3ff000 0x400000>; + console-size = <0x200000>; + pmsg-size = <0x200000>; + }; + + bldr_log_reserved: bldr_log_reserved@fd800000 { + reg = <0 0xfd800000 0x00100000>; + no-map; + }; + + cp_rmem: cp_rmem { + compatible = "exynos,modem_if"; + reg = <0x0 0xEA400000 0x00800000>; + rmem_index = <0>; + }; + + cp_msi_rmem: cp_msi_rmem { + compatible = "exynos,modem_if"; + reg = <0x0 0xF6200000 0x00001000>; + rmem_index = <1>; + }; + + cp_rmem_1: cp_rmem_1 { + compatible = "exynos,modem_if"; + reg = <0x0 0xE8000000 0x02000000>; + rmem_index = <2>; + }; + + cp_aoc_rmem: cp_aoc_rmem { + compatible = "exynos,modem_if"; + reg = <0x0 0x197FD000 0x00003000>; + rmem_index = <3>; + }; + + header: header { + reg = <0 DSS_HEADER_ADDR DSS_HEADER_SIZE>; + no-map; + }; + log_kevents: log_kevents { + reg = <0 DSS_LOG_KEVENTS_ADDR + DSS_LOG_KEVENTS_SIZE>; + no-map; + }; + log_bcm: log_bcm { + reg = <0 DSS_LOG_BCM_ADDR DSS_LOG_BCM_SIZE>; + no-map; + }; + log_s2d: log_s2d { + reg = <0 DSS_LOG_S2D_ADDR DSS_LOG_S2D_SIZE>; + no-map; + }; + log_arrdumpreset: log_array_reset { + reg = <0 DSS_LOG_ARRAYRESET_ADDR + DSS_LOG_ARRAYRESET_SIZE>; + no-map; + }; + log_arrdumppanic: log_array_panic { + reg = <0 DSS_LOG_ARRAYPANIC_ADDR + DSS_LOG_ARRAYPANIC_SIZE>; + no-map; + }; + log_slcdump: log_slcdump { + reg = <0 DSS_LOG_SLCDUMP_ADDR + DSS_LOG_SLCDUMP_SIZE>; + no-map; + }; + log_preslcdump: log_preslcdump { + reg = <0 DSS_LOG_PRE_SLCDUMP_ADDR + DSS_LOG_SLCDUMP_SIZE>; + no-map; + }; + log_itmon: log_itmon { + reg = <0 DSS_LOG_ITMON_ADDR DSS_LOG_ITMON_SIZE>; + no-map; + }; + + seclog_mem: seclog_mem { + compatible = "exynos,seclog"; + reg = <0 SECLOG_LOG_BUF_BASE SECLOG_LOG_BUF_TOTAL_SIZE>; + }; + }; +};
diff --git a/dts/gs201-s2mpu.dtsi b/dts/gs201-s2mpu.dtsi new file mode 100644 index 0000000..6e61a08 --- /dev/null +++ b/dts/gs201-s2mpu.dtsi
@@ -0,0 +1,257 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Google LLC. + * + */ + +/ { + s2mpu_aur_idma: s2mpu_aur_idma@25a70000 { + compatible = "google,s2mpu"; + reg = <0x0 0x25a70000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_S2_AUR0_AUR IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_aur>; + }; + + s2mpu_aur_inst_data: s2mpu_aur_inst_data@25aa0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x25aa0000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_S2_AUR1_AUR IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_aur>; + }; + + s2mpu_bo: s2mpu_bo@1ca60000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1ca60000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_S2_BO_BO IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_bo>; + }; + + s2mpu_cpucl0: s2mpu_cpucl0@20c70000 { + compatible = "google,s2mpu"; + reg = <0x0 0x20c70000 0x10000>; + interrupts = <GIC_SPI INTREQ_SYSMMU_S2_CPUCL0_CPUCL0 IRQ_TYPE_LEVEL_HIGH>; + always-on; + }; + + s2mpu_csis0: s2mpu_csis0@1a520000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1a520000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D0_CSIS_S2_CSIS IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_csis>; + }; + + s2mpu_csis1: s2mpu_csis1@1a550000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1a550000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D1_CSIS_S2_CSIS IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_csis>; + }; + + s2mpu_dns: s2s2mpu_dnsmpu@1b0a0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1b0a0000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_DNS_S2_DNS IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_dns>; + }; + + s2mpu_dpu0: s2mpu_dpu0@1c160000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1c160000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_DPUD0_S2_DPU IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_dpu>; + }; + + s2mpu_dpu1: s2mpu_dpu1@1c170000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1c170000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_DPUD1_S2_DPU IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_dpu>; + }; + + s2mpu_dpu2: s2mpu_dpu2@1c180000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1c180000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_DPUD2_S2_DPU IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_dpu>; + }; + + s2mpu_eh: s2mpu_eh@17040000 { + compatible = "google,s2mpu"; + reg = <0x0 0x17040000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_S2_EH_EH IRQ_TYPE_LEVEL_HIGH>; + }; + + s2mpu_g2d0: s2mpu_g2d0@1c680000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1c680000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D0_G2D_interrupt_s2_G2D IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_g2d>; + }; + + s2mpu_g2d1: s2mpu_g2d1@1c6b0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1c6b0000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D1_G2D_interrupt_s2_G2D IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_g2d>; + }; + + s2mpu_g2d2: s2mpu_g2d2@1c730000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1c730000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D2_G2D_interrupt_s2_G2D IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_g2d>; + }; + + s2mpu_g3aa: s2mpu_g3aa@1a8a0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1a8a0000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_G3AA_S2_G3AA IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_g3aa>; + }; + + s2mpu_g3d: s2mpu_g3d@20080000 { + compatible = "google,s2mpu"; + reg = <0x0 0x20080000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_G3D_NONSECURE_NOCL1A IRQ_TYPE_LEVEL_HIGH>; + always-on; + }; + + s2mpu_gdc0: s2mpu_gdc0@1d0c0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1d0c0000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D0_GDC_S2_GDC IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_gdc>; + }; + + s2mpu_gdc1: s2mpu_gdc1@1d0f0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1d0f0000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D1_GDC_S2_GDC IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_gdc>; + }; + + s2mpu_gdc2: s2mpu_gdc2@1d120000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1d120000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D2_GDC_S2_GDC IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_gdc>; + }; + + s2mpu_hsi0: s2mpu_hsi0@11070000 { + compatible = "google,s2mpu"; + reg = <0x0 0x11070000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_USB_S2_HSI0 IRQ_TYPE_LEVEL_HIGH>; + }; + + s2mpu_hsi1: s2mpu_hsi1@11880000 { + compatible = "google,s2mpu"; + reg = <0x0 0x11880000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_HSI1_S2_HSI1 IRQ_TYPE_LEVEL_HIGH>; + always-on; + }; + + s2mpu_hsi2: s2mpu_hsi2@145e0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x145e0000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_HSI2_S2_HSI2 IRQ_TYPE_LEVEL_HIGH>; + always-on; + }; + + s2mpu_gsa: s2mpu_gsa@17c60000 { + compatible = "google,s2mpu"; + reg = <0x0 0x17c60000 0x10000>; + interrupts = <GIC_SPI SYSMMU_S2MPU__INTERRUPT_GSA IRQ_TYPE_LEVEL_HIGH>; + off-at-boot; + }; + + s2mpu_ipp: s2mpu_ipp@1ad20000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1ad20000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_IPP_S2_IPP IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_ipp>; + }; + + s2mpu_mcsc0: s2mpu_mcsc0@1b7a0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1b7a0000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D0_MCSC_S2_MCSC IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_mcsc>; + }; + + s2mpu_mcsc1: s2mpu_mcsc1@1b7d0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1b7d0000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D1_MCSC_S2_MCSC IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_mcsc>; + }; + + s2mpu_mcsc2: s2mpu_mcsc2@1b800000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1b800000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D2_MCSC_S2_MCSC IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_mcsc>; + }; + + s2mpu_mfc0: s2mpu_mfc0@1c890000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1c890000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D0_MFC_interrupt_s2_MFC IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_mfc>; + }; + + s2mpu_mfc1: s2mpu_mfc1@1c8c0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1c8c0000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D1_MFC_interrupt_s2_MFC IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_mfc>; + }; + + s2mpu_misc: s2mpu_misc@101e0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x101e0000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_S2_MISC_MISC IRQ_TYPE_LEVEL_HIGH>; + always-on; + }; + + s2mpu_tnr0: s2mpu_tnr0@1bc90000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1bc90000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D0_TNR_S2_TNR IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_tnr>; + }; + + s2mpu_tnr1: s2mpu_tnr1@1bcc0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1bcc0000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D1_TNR_S2_TNR IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_tnr>; + }; + + s2mpu_tnr2: s2mpu_tnr2@1bcf0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1bcf0000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D2_TNR_S2_TNR IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_tnr>; + }; + + s2mpu_tnr3: s2mpu_tnr3@1bd20000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1bd20000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D3_TNR_S2_TNR IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_tnr>; + }; + + s2mpu_tnr4: s2mpu_tnr4@1bd50000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1bd50000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_D4_TNR_S2_TNR IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_tnr>; + }; + + s2mpu_tpu: s2mpu_tpu@1cc60000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1cc60000 0x10000>; + interrupts = <GIC_SPI IRQ_SYSMMU_S2_TPU_TPU IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_tpu>; + }; +};
diff --git a/dts/gs201-sysmmu.dtsi b/dts/gs201-sysmmu.dtsi new file mode 100644 index 0000000..ccc1d2d --- /dev/null +++ b/dts/gs201-sysmmu.dtsi
@@ -0,0 +1,721 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Google LLC. + * + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/gs201.h> +#include <dt-bindings/soc/samsung,sysmmu-v8.h> + +/ { + iommu_group_dpu: iommu_group_dpu { + compatible = "samsung,sysmmu-group"; + }; + + iommu_group_isp: iommu_group_isp { + compatible = "samsung,sysmmu-group"; + }; + + iommu_group_bo: iommu_group_bo { + compatible = "samsung,sysmmu-group"; + }; + + iommu_group_mfc: iommu_group_mfc { + compatible = "samsung,sysmmu-group"; + }; + + iommu_group_aoc: iommu_group_aoc { + compatible = "samsung,sysmmu-group"; + }; + + iommu_group_g2d: iommu_group_g2d { + compatible = "samsung,sysmmu-group"; + }; + + iommu_group_smfc: iommu_group_smfc { + compatible = "samsung,sysmmu-group"; + }; + + iommu_group_tpu: iommu_group_tpu { + compatible = "samsung,sysmmu-group"; + }; + + iommu_group_aur: iommu_group_aur { + compatible = "samsung,sysmmu-group"; + }; + + sysmmu_asoc: sysmmu@1A090000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1A090000 0x10000>; + interrupts = <0 IRQ_SYSMMU_AOC_S1_NS_AOC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_AOC_S1_S_AOC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1A0A0000>; + port-name = "ASOC"; + #iommu-cells = <0>; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0x10, 0x30)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0x8, 0x3C)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0xC, 0x3C)>, + <4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0x0, 0x3C)>; + }; + + sysmmu_bo: sysmmu@1CA40000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1CA40000 0x10000>; + interrupts = <0 IRQ_SYSMMU_S1_NS_BO_BO IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_S1_S_BO_BO IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1CA50000>; + port-name = "BO"; + #iommu-cells = <0>; + power-domains = <&pd_bo>; + s2mpus = <&s2mpu_bo>; + sysmmu,no-s2pf; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0x1F)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x3, 0x1F)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xE, 0x1F)>, + <4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x15, 0x1F)>, + <5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x17, 0x1F)>; + }; + + sysmmu_csis0: sysmmu@1A510000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1A510000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D0_CSIS_S1_NS_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D0_CSIS_S1_S_CSIS IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1A500000>; + port-name = "CSIS0"; + #iommu-cells = <0>; + power-domains = <&pd_csis>; + s2mpus = <&s2mpu_csis0>; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0x7E)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0x7E)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x8, 0x7E)>, + <4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xC, 0x7E)>, + <5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x10, 0x7E)>, + <6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x12, 0x7E)>, + <7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x14, 0x7E)>, + <8 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x18, 0x7E)>, + <9 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x1C, 0x7E)>, + <10 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x20, 0x7E)>, + <11 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x22, 0x7E)>, + <12 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x30, 0x7E)>, + <13 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x32, 0x7E)>, + <14 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x40, 0x7E)>, + <15 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x42, 0x7E)>; + sysmmu,async-fault; + }; + + sysmmu_csis1: sysmmu@1A540000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1A540000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D1_CSIS_S1_NS_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D1_CSIS_S1_S_CSIS IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1A530000>; + port-name = "CSIS1"; + #iommu-cells = <0>; + power-domains = <&pd_csis>; + s2mpus = <&s2mpu_csis1>; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0xFE)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0xFE)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x8, 0xFE)>, + <4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xC, 0xFE)>, + <5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x10, 0xFE)>, + <6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x12, 0xFE)>, + <7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x14, 0xFE)>, + <8 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x18, 0xFE)>, + <9 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x1C, 0xFE)>, + <10 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x20, 0xFE)>, + <11 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x22, 0xFE)>, + <12 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x30, 0xFE)>, + <13 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x32, 0xFE)>, + <14 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x40, 0xFE)>, + <15 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x42, 0xFE)>, + <16 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x80, 0xFE)>, + <17 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x82, 0xFE)>, + <18 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x84, 0xFE)>, + <19 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x86, 0xFE)>, + <20 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x88, 0xFE)>, + <21 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x8C, 0xFE)>, + <22 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x84, 0xFE)>; + sysmmu,async-fault; + }; + + sysmmu_dns: sysmmu@1B080000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1B080000 0x10000>; + interrupts = <0 IRQ_SYSMMU_DNS_S1_NS_DNS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_DNS_S1_S_DNS IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1B090000>; + port-name = "DNS"; + #iommu-cells = <0>; + power-domains = <&pd_dns>; + s2mpus = <&s2mpu_dns>; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = < 1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0xFE)>, + < 2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x0, 0xFE)>, + < 3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0xFE)>, + < 4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x40, 0xFE)>, + < 5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x40, 0xFE)>, + < 6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x42, 0xFE)>, + < 7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x46, 0xFE)>, + < 8 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4A, 0xFE)>, + < 9 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4E, 0xFE)>, + <10 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x52, 0xFE)>, + <11 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x42, 0xFE)>, + <12 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xC0, 0xFE)>, + <13 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xC4, 0xFE)>, + <14 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xC8, 0xFE)>, + <15 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xC2, 0xFE)>, + <16 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xD0, 0xFE)>, + <17 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xD4, 0xFE)>, + <18 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xD8, 0xFE)>, + <19 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xD2, 0xFE)>, + <20 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xD6, 0xFE)>; + sysmmu,async-fault; + }; + + sysmmu_dpu0: sysmmu@1C100000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1C100000 0x10000>; + interrupts = <0 IRQ_SYSMMU_DPUD0_S1_NS_DPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_DPUD0_S1_S_DPU IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1C130000>; + port-name = "DPU L0/L1"; + #iommu-cells = <0>; + power-domains = <&pd_dpu>; + s2mpus = <&s2mpu_dpu0>; + sysmmu,default_tlb = <TLB_CFG(BL16, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0x7)>, + <2 TLB_CFG(BL32, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0x7)>, + <3 TLB_CFG(BL32, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x5, 0x7)>, + <4 TLB_CFG(BL8, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x6, 0x7)>, + <5 TLB_CFG(BL8, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x7, 0x7)>; + panic-action = <GO_S2D_ID>; + }; + + sysmmu_dpu1: sysmmu@1C110000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1C110000 0x10000>; + interrupts = <0 IRQ_SYSMMU_DPUD1_S1_NS_DPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_DPUD1_S1_S_DPU IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1C140000>; + port-name = "DPU L2/L3"; + #iommu-cells = <0>; + power-domains = <&pd_dpu>; + s2mpus = <&s2mpu_dpu1>; + sysmmu,default_tlb = <TLB_CFG(BL16, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0x7)>, + <2 TLB_CFG(BL32, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0x7)>, + <3 TLB_CFG(BL32, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x5, 0x7)>, + <4 TLB_CFG(BL8, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x6, 0x7)>, + <5 TLB_CFG(BL8, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x7, 0x7)>; + panic-action = <GO_S2D_ID>; + }; + + sysmmu_dpu2: sysmmu@1C120000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1C120000 0x10000>; + interrupts = <0 IRQ_SYSMMU_DPUD2_S1_NS_DPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_DPUD2_S1_S_DPU IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1C150000>; + port-name = "DPU L4/L5/W"; + #iommu-cells = <0>; + power-domains = <&pd_dpu>; + s2mpus = <&s2mpu_dpu2>; + sysmmu,default_tlb = <TLB_CFG(BL16, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0x7)>, + <2 TLB_CFG(BL32, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0x7)>, + <3 TLB_CFG(BL32, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x5, 0x7)>, + <4 TLB_CFG(BL8, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x6, 0x7)>, + <5 TLB_CFG(BL8, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x7, 0x7)>, + <6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x0, 0x7)>, + <7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x1, 0x7)>, + <8 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0x7)>, + <9 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x3, 0x7)>; + panic-action = <GO_S2D_ID>; + }; + + sysmmu_g2d0: sysmmu@1C660000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1C660000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D0_G2D_interrupt_s1_ns_G2D IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D0_G2D_interrupt_s1_s_G2D IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1C670000>; + port-name = "G2D0"; + #iommu-cells = <0>; + power-domains = <&pd_g2d>; + s2mpus = <&s2mpu_g2d0>; + sysmmu,default_tlb = <TLB_CFG(BL32, PREFETCH_PREDICTION)>; + }; + + sysmmu_g2d1: sysmmu@1C690000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1C690000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D1_G2D_interrupt_s1_ns_G2D IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D1_G2D_interrupt_s1_s_G2D IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1C6A0000>; + port-name = "G2D1"; + #iommu-cells = <0>; + power-domains = <&pd_g2d>; + s2mpus = <&s2mpu_g2d1>; + sysmmu,default_tlb = <TLB_CFG(BL32, PREFETCH_PREDICTION)>; + }; + + sysmmu_g2d2: sysmmu@1C710000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1C710000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D2_G2D_interrupt_s1_ns_G2D IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D2_G2D_interrupt_s1_s_G2D IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1C720000>; + port-name = "JPEG"; + #iommu-cells = <0>; + power-domains = <&pd_g2d>; + s2mpus = <&s2mpu_g2d2>; + sysmmu,default_tlb = <TLB_CFG(BL8, PREFETCH_NONE)>; + }; + + sysmmu_g3aa: sysmmu@1A880000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1A880000 0x10000>; + interrupts = <0 IRQ_SYSMMU_G3AA_S1_NS_G3AA IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_G3AA_S1_S_G3AA IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1A890000>; + port-name = "G3AA"; + #iommu-cells = <0>; + power-domains = <&pd_g3aa>; + s2mpus = <&s2mpu_g3aa>; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x8, 0x38)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x10, 0x38)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x18, 0x38)>, + <4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x20, 0x38)>, + <5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x28, 0x38)>, + <6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x30, 0x38)>, + <7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x38, 0x38)>; + sysmmu,async-fault; + }; + + sysmmu_gdc0: sysmmu@1D0A0000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1D0A0000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D0_GDC_S1_NS_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D0_GDC_S1_S_GDC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1D0B0000>; + port-name = "GDC0"; + #iommu-cells = <0>; + power-domains = <&pd_gdc>; + s2mpus = <&s2mpu_gdc0>; + sysmmu,default_tlb = <TLB_CFG(BL32, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL32, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x8, 0xE)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0xE)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0xA, 0xE)>, + <4 TLB_CFG(BL16, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x0, 0xE)>, + <5 TLB_CFG(BL16, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0xE)>, + <6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0xE)>, + <7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x6, 0xE)>; + sysmmu,async-fault; + }; + + sysmmu_gdc1: sysmmu@1D0D0000{ + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1D0D0000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D1_GDC_S1_NS_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D1_GDC_S1_S_GDC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1D0E0000>; + port-name = "GDC1"; + #iommu-cells = <0>; + power-domains = <&pd_gdc>; + s2mpus = <&s2mpu_gdc1>; + sysmmu,default_tlb = <TLB_CFG(BL32, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL32, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x8, 0xE)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0xE)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0xA, 0xE)>, + <4 TLB_CFG(BL16, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x0, 0xE)>, + <5 TLB_CFG(BL16, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0xE)>, + <6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0xE)>, + <7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x6, 0xE)>; + sysmmu,async-fault; + }; + + sysmmu_gdc2: sysmmu@1D100000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1D100000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D2_GDC_S1_NS_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D2_GDC_S1_S_GDC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1D110000>; + port-name = "SCSC"; + #iommu-cells = <0>; + power-domains = <&pd_gdc>; + s2mpus = <&s2mpu_gdc2>; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = < 1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0x1E)>, + < 2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x8, 0x1E)>, + < 3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0x1E)>, + < 4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x6, 0x1E)>, + < 5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x0, 0x1E)>, + < 6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0x1E)>, + < 7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x8, 0x1E)>, + < 8 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0x1E)>, + < 9 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x6, 0x1E)>, + <10 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x10, 0x1E)>, + <11 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x14, 0x1E)>, + <12 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x18, 0x1E)>, + <13 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x12, 0x1E)>, + <14 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x16, 0x1E)>; + sysmmu,async-fault; + }; + +#if 0 + /* + * When GSA is in power collapse SysMMU block below is not accessible. + * Linux kernel driver need to coordinate access to this block with GSA + * if this block needs to be programmed, although, currently, there is + * no usecase that would require this. Disable it for now. + */ + sysmmu_gsa: sysmmu@17C40000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x17C40000 0x10000>; + interrupts = <0 SYSMMU_NS__INTERRUPT_GSA IRQ_TYPE_LEVEL_HIGH>, + <0 SYSMMU_S__INTERRUPT_GSA IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x17C50000>; + port-name = "GSA"; + #iommu-cells = <0>; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0x0, 0x6F)>; + }; +#endif + + sysmmu_ipp: sysmmu@1AD00000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1AD00000 0x10000>; + interrupts = <0 IRQ_SYSMMU_IPP_S1_NS_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_IPP_S1_S_IPP IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1AD10000>; + port-name = "IPP"; + #iommu-cells = <0>; + power-domains = <&pd_ipp>; + s2mpus = <&s2mpu_ipp>; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = < 1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x10, 0x3FE)>, + < 2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x20, 0x3FE)>, + < 3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x80, 0x3FE)>, + < 4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x84, 0x3FE)>, + < 5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x88, 0x3FE)>, + < 6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x90, 0x3FE)>, + < 7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x94, 0x3FE)>, + < 8 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x98, 0x3FE)>, + < 9 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xA0, 0x3FE)>, + <10 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xA4, 0x3FE)>, + <11 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xA8, 0x3FE)>, + <12 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x100, 0x3FE)>, + <13 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x190, 0x3FE)>, + <14 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x220, 0x3FE)>, + <15 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x40, 0x3FE)>, + <16 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x50, 0x3FE)>, + <17 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x60, 0x3FE)>, + <18 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xC0, 0x3FE)>, + <19 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xD0, 0x3FE)>, + <20 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xE0, 0x3FE)>, + <21 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x140, 0x3FE)>, + <22 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x150, 0x3FE)>, + <23 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x160, 0x3FE)>, + <24 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x1C0, 0x3FE)>, + <25 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x1D0, 0x3FE)>, + <26 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x1E0, 0x3FE)>, + <27 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x240, 0x3FE)>, + <28 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x250, 0x3FE)>, + <29 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x260, 0x3FE)>, + <30 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2E0, 0x3FE)>, + <31 TLB_CFG(BL8, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2C0, 0x3E0)>; + sysmmu,async-fault; + }; + + sysmmu_mcsc0: sysmmu@1B780000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1B780000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D0_MCSC_S1_NS_MCSC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D0_MCSC_S1_S_MCSC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1B790000>; + port-name = "ITSC"; + #iommu-cells = <0>; + power-domains = <&pd_mcsc>; + s2mpus = <&s2mpu_mcsc0>; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0xE)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x8, 0xE)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0xE)>, + <4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x6, 0xE)>; + sysmmu,async-fault; + }; + + sysmmu_mcsc1: sysmmu@1B7B0000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1B7B0000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D1_MCSC_S1_NS_MCSC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D1_MCSC_S1_S_MCSC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1B7C0000>; + port-name = "MCSC"; + #iommu-cells = <0>; + power-domains = <&pd_mcsc>; + s2mpus = <&s2mpu_mcsc1>; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0x3E)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x8, 0x3E)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0x3E)>, + <4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x6, 0x3E)>, + <5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x0, 0x3E)>, + <6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0x3E)>, + <7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x8, 0x3E)>, + <8 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0x3E)>, + <9 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x6, 0x3E)>, + <10 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x10, 0x3E)>, + <11 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x14, 0x3E)>, + <12 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x18, 0x3E)>, + <13 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x20, 0x3E)>, + <14 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x24, 0x3E)>, + <15 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x28, 0x3E)>; + sysmmu,async-fault; + }; + + sysmmu_mcsc2: sysmmu@1B7E0000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1B7E0000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D2_MCSC_S1_NS_MCSC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D2_MCSC_S1_S_MCSC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1B7F0000>; + port-name = "MCSC"; + #iommu-cells = <0>; + power-domains = <&pd_mcsc>; + s2mpus = <&s2mpu_mcsc2>; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0x3E)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x8, 0x3E)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0x3E)>, + <4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x6, 0x3E)>, + <5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x10, 0x3E)>, + <6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x14, 0x3E)>, + <7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x18, 0x3E)>; + sysmmu,async-fault; + }; + + sysmmu_mfc0: sysmmu@1C870000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1C870000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D0_MFC_interrupt_s1_ns_MFC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D0_MFC_interrupt_s1_s_MFC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,async-fault; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1C880000>; + port-name = "MFC0"; + #iommu-cells = <0>; + power-domains = <&pd_mfc>; + s2mpus = <&s2mpu_mfc0>; + sysmmu,default_tlb = <TLB_CFG(BL8, PREFETCH_NONE)>; + }; + + sysmmu_mfc1: sysmmu@1C8A0000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1C8A0000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D1_MFC_interrupt_s1_ns_MFC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D1_MFC_interrupt_s1_s_MFC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,async-fault; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1C8B0000>; + port-name = "MFC1"; + #iommu-cells = <0>; + power-domains = <&pd_mfc>; + s2mpus = <&s2mpu_mfc1>; + sysmmu,default_tlb = <TLB_CFG(BL8, PREFETCH_NONE)>; + }; + + sysmmu_tnr0: sysmmu@1BC70000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1BC70000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D0_TNR_S1_NS_TNR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D0_TNR_S1_S_TNR IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1BC80000>; + port-name = "TNR0"; + #iommu-cells = <0>; + power-domains = <&pd_tnr>; + s2mpus = <&s2mpu_tnr0>; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0x4, 0x7C)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x40, 0x7C)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x44, 0x7C)>; + sysmmu,async-fault; + }; + + sysmmu_tnr1: sysmmu@1BCA0000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1BCA0000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D1_TNR_S1_NS_TNR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D1_TNR_S1_S_TNR IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1BCB0000>; + port-name = "TNR1"; + #iommu-cells = <0>; + power-domains = <&pd_tnr>; + s2mpus = <&s2mpu_tnr1>; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0x3C)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x0, 0x3C)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0x3C)>; + sysmmu,async-fault; + }; + + sysmmu_tnr2: sysmmu@1BCD0000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1BCD0000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D2_TNR_S1_NS_TNR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D2_TNR_S1_S_TNR IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1BCE0000>; + port-name = "TNR2"; + #iommu-cells = <0>; + power-domains = <&pd_tnr>; + s2mpus = <&s2mpu_tnr2>; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0x3C)>; + sysmmu,async-fault; + }; + + sysmmu_tnr3: sysmmu@1BD00000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1BD00000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D3_TNR_S1_NS_TNR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D3_TNR_S1_S_TNR IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1BD10000>; + port-name = "TNR3"; + #iommu-cells = <0>; + power-domains = <&pd_tnr>; + s2mpus = <&s2mpu_tnr3>; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0x3C)>; + sysmmu,async-fault; + }; + + sysmmu_tnr4: sysmmu@1BD30000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1BD30000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D4_TNR_S1_NS_TNR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D4_TNR_S1_S_TNR IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1BD40000>; + port-name = "TNR4"; + #iommu-cells = <0>; + power-domains = <&pd_tnr>; + s2mpus = <&s2mpu_tnr4>; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0x80, 0xC0)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x0, 0xC0)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0xC0)>; + sysmmu,async-fault; + }; + + sysmmu_tpu: sysmmu@1CC40000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1CC40000 0x10000>; + interrupts = <0 IRQ_SYSMMU_S1_NS_TPU_TPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_S1_S_TPU_TPU IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1CC50000>; + port-name = "TPU"; + #iommu-cells = <0>; + power-domains = <&pd_tpu>; + s2mpus = <&s2mpu_tpu>; + sysmmu,no-s2pf; + sysmmu,default_tlb = <TLB_CFG(BL1, PREFETCH_PREDICTION)>; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0xC)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0x8, 0xC)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0xC, 0xC)>; + sysmmu,async-fault; + }; + + /* Often referred to as "sysmmu_aur0" in documentation */ + sysmmu_aur_idma: sysmmu@25A50000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x25A50000 0x10000>; + interrupts = <0 IRQ_SYSMMU_S1_NS_AUR0_AUR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_S1_S_AUR0_AUR IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x25A60000>; + port-name = "AUR_IDMA"; + #iommu-cells = <0>; + power-domains = <&pd_aur>; + s2mpus = <&s2mpu_aur_idma>; + sysmmu,no-s2pf; + sysmmu,async-fault; + }; + + /* Often referred to as "sysmmu_aur1" in documentation */ + sysmmu_aur_inst_data: sysmmu@25A80000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x25A80000 0x10000>; + interrupts = <0 IRQ_SYSMMU_S1_NS_AUR1_AUR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_S1_S_AUR1_AUR IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x25A90000>; + port-name = "AUR_INST_DATA"; + #iommu-cells = <0>; + power-domains = <&pd_aur>; + s2mpus = <&s2mpu_aur_inst_data>; + sysmmu,no-s2pf; + sysmmu,async-fault; + }; +};
diff --git a/dts/gs201-sysmmu_sync.dtsi b/dts/gs201-sysmmu_sync.dtsi new file mode 100644 index 0000000..e00f58a --- /dev/null +++ b/dts/gs201-sysmmu_sync.dtsi
@@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2022 Google LLC. + * + */ + +/ { + sysmmu_sync_aur_idma: sysmmu_sync_aur_idma@25b10000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x25b10000 0x10000>; + }; + + sysmmu_sync_aur_inst_data: sysmmu_sync_aur_inst_data@25b20000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x25b20000 0x10000>; + }; + + sysmmu_sync_bo: sysmmu_sync_bo@1caa0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1caa0000 0x10000>; + }; + + sysmmu_sync_cpucl0: sysmmu_sync_cpucl0@20cd0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x20cd0000 0x10000>; + }; + + sysmmu_sync_csis0: sysmmu_sync_csis0@1a560000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1a560000 0x10000>; + }; + + sysmmu_sync_csis1: sysmmu_sync_csis1@1a570000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1a570000 0x10000>; + }; + + sysmmu_sync_dns: sysmmu_sync_dns@1b060000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1b060000 0x10000>; + }; + + sysmmu_sync_dpu0: sysmmu_sync_dpu0@1c040000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1c040000 0x10000>; + }; + + sysmmu_sync_dpu1: sysmmu_sync_dpu1@1c050000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1c050000 0x10000>; + }; + + sysmmu_sync_dpu2: sysmmu_sync_dpu2@1c060000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1c060000 0x10000>; + }; + + sysmmu_sync_eh: sysmmu_sync_eh@17070000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x17070000 0x10000>; + }; + + sysmmu_sync_g2d0: sysmmu_sync_g2d0@1c6e0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1c6e0000 0x10000>; + }; + + sysmmu_sync_g2d1: sysmmu_sync_g2d1@1c6f0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1c6f0000 0x10000>; + }; + + sysmmu_sync_g2d2: sysmmu_sync_g2d2@1c750000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1c750000 0x10000>; + }; + + sysmmu_sync_g3aa: sysmmu_sync_g3aa@1a8b0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1a8b0000 0x10000>; + }; + + sysmmu_sync_g3d0: sysmmu_sync_g3d0@20090000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x20090000 0x10000>; + }; + + sysmmu_sync_g3d1: sysmmu_sync_g3d1@200a0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x200a0000 0x10000>; + }; + + sysmmu_sync_g3d2: sysmmu_sync_g3d2@200b0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x200b0000 0x10000>; + }; + + sysmmu_sync_g3d3: sysmmu_sync_g3d3@201f0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x201f0000 0x10000>; + }; + + sysmmu_sync_gdc0: sysmmu_sync_gdc0@1d2d0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1d2d0000 0x10000>; + }; + + sysmmu_sync_gdc1: sysmmu_sync_gdc1@1d2e0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1d2e0000 0x10000>; + }; + + sysmmu_sync_gdc2: sysmmu_sync_gdc2@1d2f0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1d2f0000 0x10000>; + }; + + sysmmu_sync_gsa: sysmmu_sync_gsa@17c70000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x17c70000 0x10000>; + }; + + sysmmu_sync_hsi0: sysmmu_sync_hsi0@11110000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x11110000 0x10000>; + }; + + sysmmu_sync_hsi1: sysmmu_sync_hsi1@118b0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x118b0000 0x10000>; + }; + + sysmmu_sync_hsi2: sysmmu_sync_hsi2@145f0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x145f0000 0x10000>; + }; + + sysmmu_sync_ipp: sysmmu_sync_ipp@1acf0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1acf0000 0x10000>; + }; + + sysmmu_sync_mcsc0: sysmmu_sync_mcsc0@1b990000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1b990000 0x10000>; + }; + + sysmmu_sync_mcsc1: sysmmu_sync_mcsc1@1b9a0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1b9a0000 0x10000>; + }; + + sysmmu_sync_mcsc2: sysmmu_sync_mcsc2@1b9b0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1b9b0000 0x10000>; + }; + + sysmmu_sync_mfc0: sysmmu_sync_mfc0@1c900000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1c900000 0x10000>; + }; + + sysmmu_sync_mfc1: sysmmu_sync_mfc1@1c910000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1c910000 0x10000>; + }; + + sysmmu_sync_misc: sysmmu_sync_misc@101f0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x101f0000 0x10000>; + }; + + sysmmu_sync_tnr0: sysmmu_sync_tnr0@1bf00000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1bf00000 0x10000>; + }; + + sysmmu_sync_tnr1: sysmmu_sync_tnr1@1bf10000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1bf10000 0x10000>; + }; + + sysmmu_sync_tnr2: sysmmu_sync_tnr2@1bf20000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1bf20000 0x10000>; + }; + + sysmmu_sync_tnr3: sysmmu_sync_tnr3@1bf30000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1bf30000 0x10000>; + }; + + sysmmu_sync_tnr4: sysmmu_sync_tnr4@1bf40000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1bf40000 0x10000>; + }; +};
diff --git a/dts/gs201-tpu.dtsi b/dts/gs201-tpu.dtsi new file mode 100644 index 0000000..e816f3c --- /dev/null +++ b/dts/gs201-tpu.dtsi
@@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Edge TPU device tree source + * + * Copyright 2021 Google,LLC + * + */ + +/ { + /* TPU */ + edgetpu: janeiro@1CE00000 { + compatible = "google,darwinn"; + #dma-address-cells = <1>; + #dma-size-cells = <1>; + /* TPU uses regions under 0x18000000 for special purpose */ + dma-window = <0x18000000 0xE7FFF000>; + reg = <0x0 0x1CE00000 0x200000 + 0x0 0x1CCF0000 0x10000>; + reg-names = "tpu", "ssmt"; + interrupts = <0 IRQ_MAILBOX_TPU2AP_NS_TPU_0_TPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MAILBOX_TPU2AP_NS_TPU_1_TPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MAILBOX_TPU2AP_NS_TPU_2_TPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MAILBOX_TPU2AP_NS_TPU_3_TPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MAILBOX_TPU2AP_NS_TPU_4_TPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MAILBOX_TPU2AP_NS_TPU_5_TPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MAILBOX_TPU2AP_NS_TPU_6_TPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MAILBOX_TPU2AP_NS_TPU_7_TPU IRQ_TYPE_LEVEL_HIGH>; + /* TODO(b/195608852): Enable coherency */ + iommus = <&sysmmu_tpu>; + samsung,iommu-group = <&iommu_group_tpu>; + status = "okay"; + memory-region = <&tpu_fw_reserved>, <&tpu_fw_ctx_reserved>; + edgetpu,shareability = <0x1cc20000>; + gsa-device = <&gsa>; + tpu_dvfs_table_size = <7 2>; /*<row col>*/ + /* + * DVFS values calculated from average power with real-world workloads + */ + tpu_dvfs_table = < + /* when updating tpu_dvfs_table, update tpu_dvfs_table_size as well + * freq power(mW) + *---------------------------------- + * TODO(b/192394098): update these with more accurate numbers for PRO + */ + 1066000 4420 + 967000 4101 + 845000 2578 + 712000 1982 + 627000 1749 + 455000 1277 + 226000 0 + >; + }; + tpu_cooling: tpu-cooling { + #cooling-cells = <2>; + }; +};
diff --git a/dts/gs201-ufs.dtsi b/dts/gs201-ufs.dtsi new file mode 100644 index 0000000..9d99bd6 --- /dev/null +++ b/dts/gs201-ufs.dtsi
@@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Samsung's SoC UFS device tree source + * + * Copyright (c) 2020 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include <dt-bindings/ufs/ufs.h> + +/ { + sysreg_hsi2_system_controller: system-controller@14420000 { + compatible = "google,gs201-sysreg-hsi2", "syscon"; + reg = <0x0 0x14420000 0x1000>; + }; + + ufs: ufs@14700000 { + /* ----------------------- */ + /* 1. SYSTEM CONFIGURATION */ + /* ----------------------- */ + compatible ="samsung,exynos-ufs"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + reg = + <0x0 0x14700000 0x200>, /* HCI standard */ + <0x0 0x14701100 0x200>, /* Vendor specificed */ + <0x0 0x14780000 0xa000>, /* UNIPRO */ + <0x0 0x14600000 0x100>, /* UFS protector */ + <0x0 0x14704000 0x3000>, /* phy */ + <0x0 0x14708000 0x804>; /* cport */ + interrupts = <GIC_SPI IRQ_UFS_EMBD_HSI2 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; + clocks = + /* aclk clock */ + <&clock GATE_UFS_EMBD>, + /* unipro clocks */ + <&clock UFS_EMBD>; + + clock-names = + /* aclk clocks */ + "GATE_UFS_EMBD", + /* unipro clocks */ + "UFS_EMBD"; + + /* ----------------------- */ + /* 2. UFS COMMON */ + /* ----------------------- */ + freq-table-hz = <0 0>, <0 0>; + + vcc-supply = <&ufs_fixed_vcc>; + vcc-fixed-regulator; + + /* ----------------------- */ + /* 3. UFS EXYNOS */ + /* ----------------------- */ + /* power mode change */ + ufs,pmd-attr-lane = /bits/ 8 <2>; + ufs,pmd-attr-gear = /bits/ 8 <4>; + + /* evt version for UFS CAL */ + evt-ver = /bits/ 8 <0>; + + /* board type for UFS CAL */ + brd-for-cal = /bits/ 8 <1>; /* (1:SMDK, 16:UNIV) board */ + + /* DMA coherent callback, should be coupled with 'ufs-sys' */ + dma-coherent; + + /* UFS IO coherency */ + samsung,sysreg-phandle = <&sysreg_hsi2_system_controller>; + + fmp-id = <0>; + smu-id = <0>; + + /* GSA (KDN) device */ + gsa-device = <&gsa>; + + /* UTRD bug fixed */ + fixed-prdt-req_list-ocs; + + /* ----------------------- */ + /* 4. ADDITIONAL NODES */ + /* ----------------------- */ + ufs-phy-iso { + offset = <0x3ec8>; + mask = <0x1>; + val = <0x1>; + }; + ufs-iocc { + offset = <0x710>; + mask = <0x3>; + val = <0x3>; + }; + ufs-perf { + active = <0>; + + freq-cluster1 = <1066000>; + freq-cluster0 = <1794000>; + chunk = <128>; + count-b = <40>; + count-l = <48>; + period-in-ms-b = <160>; + period-in-ms-l = <3>; + reset-delay-in-ms = <30>; + }; + }; + + ufs_fixed_vcc: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "ufs-vcc"; + gpio = <&gpp0 1 0>; + regulator-boot-on; + enable-active-high; + }; + +};
diff --git a/dts/gs201-usi.dtsi b/dts/gs201-usi.dtsi new file mode 100644 index 0000000..1c96a5e --- /dev/null +++ b/dts/gs201-usi.dtsi
@@ -0,0 +1,1138 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Google LLC. + * + */ + +/ { + aliases { + i2c0 = &hsi2c_0; + i2c1 = &hsi2c_1; + i2c2 = &hsi2c_2; + i2c3 = &hsi2c_3; + i2c4 = &hsi2c_4; + i2c5 = &hsi2c_5; + i2c6 = &hsi2c_6; + i2c7 = &hsi2c_7; + i2c8 = &hsi2c_8; + i2c9 = &hsi2c_9; + i2c10 = &hsi2c_10; + i2c11 = &hsi2c_11; + i2c12 = &hsi2c_12; + i2c13 = &hsi2c_13; + i2c14 = &hsi2c_14; + i2c15 = &hsi2c_15; + i2c16 = &hsi2c_16; + // i2c20 is assigned to acpm_mfd_bus0 + // i2c21 is assigned to acpm_mfd_bus1 + + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; + spi5 = &spi_5; + spi6 = &spi_6; + spi7 = &spi_7; + spi8 = &spi_8; + spi9 = &spi_9; + spi10 = &spi_10; + spi11 = &spi_11; + spi12 = &spi_12; + spi13 = &spi_13; + spi14 = &spi_14; + spi15 = &spi_15; + spi16 = &spi_16; + spi17 = &spi_17; + uart1 = &serial_1; + uart2 = &serial_2; + uart3 = &serial_3; + uart4 = &serial_4; + uart5 = &serial_5; + uart6 = &serial_6; + uart7 = &serial_7; + uart8 = &serial_8; + uart9 = &serial_9; + uart10 = &serial_10; + uart11 = &serial_11; + uart12 = &serial_12; + uart13 = &serial_13; + uart14 = &serial_14; + uart15 = &serial_15; + uart16 = &serial_16; + uart17 = &serial_17; + uart18 = &serial_18; + uart19 = &serial_19; + }; + + sysreg_peric0: syscon@10821000 { + compatible = "samsung,exynos-sysreg", "syscon"; + reg = <0x0 0x10821000 0x1000>; + }; + + sysreg_peric1: syscon@10C21000 { + compatible = "samsung,exynos-sysreg", "syscon"; + reg = <0x0 0x10C21000 0x1000>; + }; + + sysreg_apm: syscon@180204E0 { + compatible = "samsung,exynos-sysreg", "syscon"; + reg = <0x0 0x180204e0 0x1000>; + }; + + hsi2c_1: hsi2c@10900000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,no_lose_arbitration; + samsung,usi-i2c-v2; + interrupts = <GIC_SPI IRQ_USI1_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c1_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI1_USI>, <&clock GATE_PERIC0_TOP0_USI1_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp2 0 0x1>; + gpio_sda= <&gpp2 1 0x1>; + samsung,usi-offset = <0x00000000>; + reg = <0x00000000 0x10900000 0x00001000>; + status = "disabled"; + }; + hsi2c_2: hsi2c@10910000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,no_lose_arbitration; + samsung,usi-i2c-v2; + interrupts = <GIC_SPI IRQ_USI2_USI_PERIC0 ITLH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c2_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI2_USI>, <&clock GATE_PERIC0_TOP0_USI2_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp4 0 0x1>; + gpio_sda= <&gpp4 1 0x1>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000004>; + reg = <0x00000000 0x10910000 0x00001000>; + status = "disabled"; + }; + hsi2c_3: hsi2c@10920000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,no_lose_arbitration; + samsung,usi-i2c-v2; + interrupts = <GIC_SPI IRQ_USI3_USI_PERIC0 ITLH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c3_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI3_USI>, <&clock GATE_PERIC0_TOP0_USI3_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp6 0 0x1>; + gpio_sda= <&gpp6 1 0x1>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000008>; + reg = <0x00000000 0x10920000 0x00001000>; + status = "disabled"; + }; + hsi2c_4: hsi2c@10930000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,no_lose_arbitration; + samsung,usi-i2c-v2; + interrupts = <GIC_SPI IRQ_USI4_USI_PERIC0 ITLH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c4_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI4_USI>, <&clock GATE_PERIC0_TOP0_USI4_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp8 0 0x1>; + gpio_sda= <&gpp8 1 0x1>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x0000000c>; + reg = <0x00000000 0x10930000 0x00001000>; + status = "disabled"; + }; + hsi2c_5: hsi2c@10940000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = <GIC_SPI IRQ_USI5_USI_PERIC0 ITLH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c5_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI5_USI>, <&clock GATE_PERIC0_TOP0_USI5_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp10 0 0x1>; + gpio_sda= <&gpp10 1 0x1>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000010>; + reg = <0x00000000 0x10940000 0x00001000>; + status = "disabled"; + }; + hsi2c_6: hsi2c@10950000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = <GIC_SPI IRQ_USI6_USI_PERIC0 ITLH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c6_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI6_USI>, <&clock GATE_PERIC0_TOP0_USI6_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp12 0 0x1>; + gpio_sda= <&gpp12 1 0x1>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000014>; + reg = <0x00000000 0x10950000 0x00001000>; + status = "disabled"; + }; + hsi2c_7: hsi2c@10960000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = <GIC_SPI IRQ_USI7_USI_PERIC0 ITLH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c7_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI7_USI>, <&clock GATE_PERIC0_TOP0_USI7_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp14 0 0x1>; + gpio_sda= <&gpp14 1 0x1>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000018>; + reg = <0x00000000 0x10960000 0x00001000>; + status = "disabled"; + }; + hsi2c_8: hsi2c@10970000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,no_lose_arbitration; + samsung,usi-i2c-v2; + interrupts = <GIC_SPI IRQ_USI8_USI_PERIC0 ITLH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c8_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI8_USI>, <&clock GATE_PERIC0_TOP0_USI8_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp16 0 0x1>; + gpio_sda= <&gpp16 1 0x1>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x0000001c>; + reg = <0x00000000 0x10970000 0x00001000>; + status = "disabled"; + }; + hsi2c_14: hsi2c@10A20000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = <GIC_SPI IRQ_USI14_USI_PERIC0 ITLH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c14_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI14_USI>, <&clock GATE_PERIC0_TOP1_USI14_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp18 0 0x1>; + gpio_sda= <&gpp18 1 0x1>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000028>; + reg = <0x00000000 0x10a20000 0x00001000>; + status = "disabled"; + }; + hsi2c_0: hsi2c@10D10000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = <GIC_SPI IRQ_USI0_USI_PERIC1 ITLH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c0_bus>; + clocks = <&clock VDOUT_CLK_PERIC1_USI0_USI>, <&clock GATE_PERIC1_TOP0_USI0_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp20 0 0x1>; + gpio_sda= <&gpp20 1 0x1>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000000>; + reg = <0x00000000 0x10d10000 0x00001000>; + status = "disabled"; + }; + hsi2c_9: hsi2c@10D20000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = <GIC_SPI IRQ_USI9_USI_PERIC1 ITLH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c9_bus>; + clocks = <&clock VDOUT_CLK_PERIC1_USI9_USI>, <&clock GATE_PERIC1_TOP0_USI9_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp20 4 0x1>; + gpio_sda= <&gpp20 5 0x1>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000004>; + reg = <0x00000000 0x10d20000 0x00001000>; + status = "disabled"; + }; + hsi2c_10: hsi2c@10D30000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = <GIC_SPI IRQ_USI10_USI_PERIC1 ITLH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c10_bus>; + clocks = <&clock VDOUT_CLK_PERIC1_USI10_USI>, <&clock GATE_PERIC1_TOP0_USI10_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp21 0 0x1>; + gpio_sda= <&gpp21 1 0x1>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000008>; + reg = <0x00000000 0x10d30000 0x00001000>; + status = "disabled"; + }; + hsi2c_11: hsi2c@10D40000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = <GIC_SPI IRQ_USI11_USI_PERIC1 ITLH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c11_bus>; + clocks = <&clock VDOUT_CLK_PERIC1_USI11_USI>, <&clock GATE_PERIC1_TOP0_USI11_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp23 0 0x1>; + gpio_sda= <&gpp23 1 0x1>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x0000000c>; + reg = <0x00000000 0x10d40000 0x00001000>; + status = "disabled"; + }; + hsi2c_12: hsi2c@10D50000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = <GIC_SPI IRQ_USI12_USI_PERIC1 ITLH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c12_bus>; + clocks = <&clock VDOUT_CLK_PERIC1_USI12_USI>, <&clock GATE_PERIC1_TOP0_USI12_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp23 4 0x1>; + gpio_sda= <&gpp23 5 0x1>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000010>; + reg = <0x00000000 0x10d50000 0x00001000>; + status = "disabled"; + }; + hsi2c_13: hsi2c@10D60000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = <GIC_SPI IRQ_USI13_USI_PERIC1 ITLH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c13_bus>; + clocks = <&clock VDOUT_CLK_PERIC1_USI13_USI>, <&clock GATE_PERIC1_TOP0_USI13_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp25 0 0x1>; + gpio_sda= <&gpp25 1 0x1>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000014>; + reg = <0x00000000 0x10d60000 0x00001000>; + status = "disabled"; + }; + hsi2c_15: hsi2c@10DA0000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,no_lose_arbitration; + samsung,usi-i2c-v2; + interrupts = <GIC_SPI IRQ_USI15_USI_PERIC1 ITLH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c15_bus>; + clocks = <&clock VDOUT_CLK_PERIC1_USI15_USI>, <&clock GATE_PERIC1_TOP0_USI15_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp24 0 0x1>; + gpio_sda= <&gpp24 1 0x1>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000018>; + reg = <0x00000000 0x10da0000 0x00001000>; + status = "disabled"; + }; + hsi2c_16: hsi2c@10DB0000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = <GIC_SPI IRQ_USI16_USI_PERIC1 ITLH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c16_bus>; + clocks = <&clock VDOUT_CLK_PERIC1_USI16_USI>, <&clock GATE_PERIC1_TOP0_USI16_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp26 0 0x1>; + gpio_sda= <&gpp26 1 0x1>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x0000001c>; + reg = <0x00000000 0x10db0000 0x00001000>; + status = "disabled"; + }; + spi_1: spi@10900000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 2 &pdma0 3>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI1_USI>, <&clock GATE_PERIC0_TOP0_USI1_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + interrupts = <GIC_SPI IRQ_USI1_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000000>; + reg = <0x00000000 0x10900000 0x00001000>; + status = "disabled"; + }; + spi_2: spi@10910000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 4 &pdma0 5>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI2_USI>, <&clock GATE_PERIC0_TOP0_USI2_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + interrupts = <GIC_SPI IRQ_USI2_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000004>; + reg = <0x00000000 0x10910000 0x00001000>; + status = "disabled"; + }; + spi_3: spi@10920000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 6 &pdma0 7>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI3_USI>, <&clock GATE_PERIC0_TOP0_USI3_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_bus>; + interrupts = <GIC_SPI IRQ_USI3_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000008>; + reg = <0x00000000 0x10920000 0x00001000>; + status = "disabled"; + }; + spi_4: spi@10930000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 8 &pdma0 9>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI4_USI>, <&clock GATE_PERIC0_TOP0_USI4_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_bus>; + interrupts = <GIC_SPI IRQ_USI4_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x0000000c>; + reg = <0x00000000 0x10930000 0x00001000>; + status = "disabled"; + }; + spi_5: spi@10940000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 10 &pdma0 11>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI5_USI>, <&clock GATE_PERIC0_TOP0_USI5_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_bus>; + interrupts = <GIC_SPI IRQ_USI5_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000010>; + reg = <0x00000000 0x10940000 0x00001000>; + status = "disabled"; + }; + spi_6: spi@10950000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 12 &pdma0 13>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI6_USI>, <&clock GATE_PERIC0_TOP0_USI6_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi6_bus>; + interrupts = <GIC_SPI IRQ_USI6_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000014>; + reg = <0x00000000 0x10950000 0x00001000>; + status = "disabled"; + }; + spi_7: spi@10960000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 14 &pdma0 15>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI7_USI>, <&clock GATE_PERIC0_TOP0_USI7_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi7_bus>; + interrupts = <GIC_SPI IRQ_USI7_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000018>; + reg = <0x00000000 0x10960000 0x00001000>; + status = "disabled"; + }; + spi_8: spi@10970000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 16 &pdma0 17>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI8_USI>, <&clock GATE_PERIC0_TOP0_USI8_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi8_bus>; + interrupts = <GIC_SPI IRQ_USI8_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x0000001c>; + reg = <0x00000000 0x10970000 0x00001000>; + status = "disabled"; + }; + spi_14: spi@10A20000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 28 &pdma0 29>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI14_USI>, <&clock GATE_PERIC0_TOP1_USI14_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi14_bus>; + interrupts = <GIC_SPI IRQ_USI14_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000028>; + reg = <0x00000000 0x10a20000 0x00001000>; + status = "disabled"; + }; + spi_0: spi@10D10000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 0 &pdma0 1>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC1_USI0_USI>, <&clock GATE_PERIC1_TOP0_USI0_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + interrupts = <GIC_SPI IRQ_USI0_USI_PERIC1 ITLH>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000000>; + reg = <0x00000000 0x10d10000 0x00001000>; + status = "disabled"; + }; + spi_9: spi@10D20000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 18 &pdma0 19>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC1_USI9_USI>, <&clock GATE_PERIC1_TOP0_USI9_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi9_bus>; + interrupts = <GIC_SPI IRQ_USI9_USI_PERIC1 ITLH>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000004>; + reg = <0x00000000 0x10d20000 0x00001000>; + status = "disabled"; + }; + spi_10: spi@10D30000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 20 &pdma0 21>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC1_USI10_USI>, <&clock GATE_PERIC1_TOP0_USI10_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi10_bus>; + interrupts = <GIC_SPI IRQ_USI10_USI_PERIC1 ITLH>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000008>; + reg = <0x00000000 0x10d30000 0x00001000>; + status = "disabled"; + }; + spi_11: spi@10D40000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 22 &pdma0 23>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC1_USI11_USI>, <&clock GATE_PERIC1_TOP0_USI11_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi11_bus>; + interrupts = <GIC_SPI IRQ_USI11_USI_PERIC1 ITLH>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x0000000c>; + reg = <0x00000000 0x10d40000 0x00001000>; + status = "disabled"; + }; + spi_12: spi@10D50000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 24 &pdma0 25>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC1_USI12_USI>, <&clock GATE_PERIC1_TOP0_USI12_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi12_bus>; + interrupts = <GIC_SPI IRQ_USI12_USI_PERIC1 ITLH>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000010>; + reg = <0x00000000 0x10d50000 0x00001000>; + status = "disabled"; + }; + spi_13: spi@10D60000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma1 0 &pdma1 1>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC1_USI13_USI>, <&clock GATE_PERIC1_TOP0_USI13_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi13_bus>; + interrupts = <GIC_SPI IRQ_USI13_USI_PERIC1 ITLH>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000014>; + reg = <0x00000000 0x10d60000 0x00001000>; + status = "disabled"; + }; + spi_15: spi@10DA0000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma1 2 &pdma1 3>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC1_USI15_USI>, <&clock GATE_PERIC1_TOP0_USI15_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi15_bus>; + interrupts = <GIC_SPI IRQ_USI15_USI_PERIC1 ITLH>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000018>; + reg = <0x00000000 0x10da0000 0x00001000>; + status = "disabled"; + }; + spi_16: spi@10DB0000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 26 &pdma0 27>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC1_USI16_USI>, <&clock GATE_PERIC1_TOP0_USI16_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi16_bus>; + interrupts = <GIC_SPI IRQ_USI16_USI_PERIC1 ITLH>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x0000001c>; + reg = <0x00000000 0x10db0000 0x00001000>; + status = "disabled"; + }; + /* BLK_PERIC0 USI1_USI */ + serial_1: serial@10900000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP0_USI1_USI>, <&clock VDOUT_CLK_PERIC0_USI1_USI>; + clock-names = "gate_uart_clk1", "ipclk_uart1"; + interrupts = <GIC_SPI IRQ_USI1_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000000>; + reg = <0x00000000 0x10900000 0x00001000>; + status = "disabled"; + }; + serial_2: serial@10910000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP0_USI2_USI>, <&clock VDOUT_CLK_PERIC0_USI2_USI>; + clock-names = "gate_uart_clk2", "ipclk_uart2"; + interrupts = <GIC_SPI IRQ_USI2_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000004>; + reg = <0x00000000 0x10910000 0x00001000>; + status = "disabled"; + }; + serial_3: serial@10920000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP0_USI3_USI>, <&clock VDOUT_CLK_PERIC0_USI3_USI>; + clock-names = "gate_uart_clk3", "ipclk_uart3"; + interrupts = <GIC_SPI IRQ_USI3_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000008>; + reg = <0x00000000 0x10920000 0x00001000>; + status = "disabled"; + }; + serial_4: serial@10930000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP0_USI4_USI>, <&clock VDOUT_CLK_PERIC0_USI4_USI>; + clock-names = "gate_uart_clk4", "ipclk_uart4"; + interrupts = <GIC_SPI IRQ_USI4_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x0000000c>; + reg = <0x00000000 0x10930000 0x00001000>; + status = "disabled"; + }; + serial_5: serial@10940000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart5_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP0_USI5_USI>, <&clock VDOUT_CLK_PERIC0_USI5_USI>; + clock-names = "gate_uart_clk5", "ipclk_uart5"; + interrupts = <GIC_SPI IRQ_USI5_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000010>; + reg = <0x00000000 0x10940000 0x00001000>; + status = "disabled"; + }; + serial_6: serial@10950000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart6_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP0_USI6_USI>, <&clock VDOUT_CLK_PERIC0_USI6_USI>; + clock-names = "gate_uart_clk6", "ipclk_uart6"; + interrupts = <GIC_SPI IRQ_USI6_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000014>; + reg = <0x00000000 0x10950000 0x00001000>; + status = "disabled"; + }; + serial_7: serial@10960000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart7_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP0_USI7_USI>, <&clock VDOUT_CLK_PERIC0_USI7_USI>; + clock-names = "gate_uart_clk7", "ipclk_uart7"; + interrupts = <GIC_SPI IRQ_USI7_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000018>; + reg = <0x00000000 0x10960000 0x00001000>; + status = "disabled"; + }; + serial_8: serial@10970000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart8_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP0_USI8_USI>, <&clock VDOUT_CLK_PERIC0_USI8_USI>; + clock-names = "gate_uart_clk8", "ipclk_uart8"; + interrupts = <GIC_SPI IRQ_USI8_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x0000001c>; + reg = <0x00000000 0x10970000 0x00001000>; + status = "disabled"; + }; + serial_14: serial@10A20000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart14_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP1_USI14_USI>, <&clock VDOUT_CLK_PERIC0_USI14_USI>; + clock-names = "gate_uart_clk14", "ipclk_uart14"; + interrupts = <GIC_SPI IRQ_USI14_USI_PERIC0 ITLH>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000028>; + reg = <0x00000000 0x10a20000 0x00001000>; + status = "disabled"; + }; + /* BLK_PERIC1 USI0_USI */ + serial_usi0: serial@10D10000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP1_USI0_UART>, <&clock VDOUT_CLK_PERIC0_USI0_UART>; + clock-names = "gate_uart_clk15", "ipclk_uart15"; + interrupts = <GIC_SPI IRQ_USI0_USI_PERIC1 ITLH>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000000>; + reg = <0x00000000 0x10d10000 0x00001000>; + status = "disabled"; + }; + serial_9: serial@10D20000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart9_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC1_TOP0_USI9_USI>, <&clock VDOUT_CLK_PERIC1_USI9_USI>; + clock-names = "gate_uart_clk9", "ipclk_uart9"; + interrupts = <GIC_SPI IRQ_USI9_USI_PERIC1 ITLH>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000004>; + reg = <0x00000000 0x10d20000 0x00001000>; + status = "disabled"; + }; + serial_10: serial@10D30000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart10_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC1_TOP0_USI10_USI>, <&clock VDOUT_CLK_PERIC1_USI10_USI>; + clock-names = "gate_uart_clk10", "ipclk_uart10"; + interrupts = <GIC_SPI IRQ_USI10_USI_PERIC1 ITLH>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000008>; + reg = <0x00000000 0x10d30000 0x00001000>; + status = "disabled"; + }; + serial_11: serial@10D40000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart11_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC1_TOP0_USI11_USI>, <&clock VDOUT_CLK_PERIC1_USI11_USI>; + clock-names = "gate_uart_clk11", "ipclk_uart11"; + interrupts = <GIC_SPI IRQ_USI11_USI_PERIC1 ITLH>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x0000000c>; + reg = <0x00000000 0x10d40000 0x00001000>; + status = "disabled"; + }; + serial_12: serial@10D50000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart12_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC1_TOP0_USI12_USI>, <&clock VDOUT_CLK_PERIC1_USI12_USI>; + clock-names = "gate_uart_clk12", "ipclk_uart12"; + interrupts = <GIC_SPI IRQ_USI12_USI_PERIC1 ITLH>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000010>; + reg = <0x00000000 0x10d50000 0x00001000>; + status = "disabled"; + }; + serial_13: serial@10D60000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart13_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC1_TOP0_USI13_USI>, <&clock VDOUT_CLK_PERIC1_USI13_USI>; + clock-names = "gate_uart_clk13", "ipclk_uart13"; + interrupts = <GIC_SPI IRQ_USI13_USI_PERIC1 ITLH>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000014>; + reg = <0x00000000 0x10d60000 0x00001000>; + status = "disabled"; + }; + serial_15: serial@10DA0000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart15_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC1_TOP0_USI15_USI>, <&clock VDOUT_CLK_PERIC1_USI15_USI>; + clock-names = "gate_uart_clk15", "ipclk_uart15"; + interrupts = <GIC_SPI IRQ_USI15_USI_PERIC1 ITLH>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000018>; + reg = <0x00000000 0x10da0000 0x00001000>; + status = "disabled"; + }; + serial_16: serial@10DB0000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart16_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC1_TOP0_USI16_USI>, <&clock VDOUT_CLK_PERIC1_USI16_USI>; + clock-names = "gate_uart_clk16", "ipclk_uart16"; + interrupts = <GIC_SPI IRQ_USI16_USI_PERIC1 ITLH>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x0000001c>; + reg = <0x00000000 0x10db0000 0x00001000>; + status = "disabled"; + }; + /* BLK_ALIVE APM_USI0_UART */ + serial_17: serial@181A0000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <256>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart17_bus>; /* or _bus_dual */ + clocks = <&clock MUX_APM_FUNC>, <&clock DOUT_CLK_APM_USI0_UART>; + clock-names = "gate_uart_clk17", "ipclk_uart17"; + interrupts = <GIC_SPI IRQ_APM_USI0_UART_ALIVE ITLH>; + samsung,usi-phandle = <&sysreg_apm>; + samsung,usi-offset = <0x00000000>; + reg = <0x00000000 0x181a0000 0x00001000>; + status = "disabled"; + }; + /* BLK_ALIVE APM_USI1_UART */ + serial_18: serial@181B0000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <256>; + samsung,rts-trig-level = <0x01>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + samsung,rts-alive-control; + samsung,uart-logging; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default", "rts", "tx_dat"; + pinctrl-0 = <&uart18_bus>; /* or _bus_dual */ + pinctrl-1 = <&uart18_bus_rts &uart18_bus_tx_con>; + pinctrl-2 = <&uart18_bus_tx_dat>; + clocks = <&clock MUX_APM_FUNC>, <&clock DOUT_CLK_APM_USI1_UART>; + clock-names = "gate_uart_clk18", "ipclk_uart18"; + interrupts = <GIC_SPI IRQ_APM_USI1_UART_ALIVE ITLH>; + samsung,usi-phandle = <&sysreg_apm>; + samsung,usi-offset = <0x00000004>; + reg = <0x00000000 0x181b0000 0x00001000>; + status = "disabled"; + }; + /* BLK_ALIVE APM_USI0_USI */ + serial_19: serial@181C0000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart19_bus>; /* or _bus_dual */ + clocks = <&clock MUX_APM_FUNC>, <&clock DOUT_CLK_APM_USI0_USI>; + clock-names = "gate_uart_clk19", "ipclk_uart19"; + interrupts = <GIC_SPI IRQ_APM_USI0_USI_ALIVE ITLH>; + samsung,usi-phandle = <&sysreg_apm>; + samsung,usi-offset = <0x00000008>; + reg = <0x00000000 0x181c0000 0x00001000>; + status = "disabled"; + }; + /* BLK_ALIVE APM_USI0_USI */ + spi_17: spi@181C0000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + dma-names = "tx", "rx"; + clocks = <&clock MUX_APM_FUNC>, <&clock DOUT_CLK_APM_USI0_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + interrupts = <GIC_SPI IRQ_APM_USI0_USI_ALIVE ITLH>; + samsung,usi-phandle = <&sysreg_apm>; + samsung,usi-offset = <0x00000008>; + reg = <0x00000000 0x181c0000 0x00001000>; + status = "disabled"; + }; +};
diff --git a/dts/gs201.dtsi b/dts/gs201.dtsi new file mode 100644 index 0000000..085a741 --- /dev/null +++ b/dts/gs201.dtsi
@@ -0,0 +1,1697 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Google LLC. + * + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/gs201.h> +#include <dt-bindings/clock/gs201.h> +#include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/soc/google/gs201-dm.h> +#include <dt-bindings/soc/google/gs201-devfreq.h> +#include <dt-bindings/soc/google/gs201-pm-qos.h> +#include "gs201-rmem.dtsi" +#include "gs101-trusty.dtsi" +#include "gs201-bts.dtsi" +#include "gs101-cp-tm.dtsi" +#include "gs201-cpu.dtsi" +#include "gs201-dit.dtsi" +#include "gs201-drm-dpu.dtsi" +#include "gs201-gpu.dtsi" +#include "gs201-aoc.dtsi" +#include "gs101-audio.dtsi" +#include "gs201-gsa.dtsi" +#include "gs201-pinctrl.dtsi" +#include "gs201-pm-domains.dtsi" +#include "gs201-sysmmu.dtsi" +#include "gs201-usi.dtsi" +#include "gs201-s2mpu.dtsi" +#include "gs201-ufs.dtsi" +#include "gs201-mmc.dtsi" +#include "gs201-tpu.dtsi" +#include "gs201-gxp.dtsi" +#include "gs101-dma-heap.dtsi" +#include "gs201-isp.dtsi" +#include "gs201-debug.dtsi" +#include "gs201-pcie.dtsi" +#include "gs201-bigo.dtsi" +#include "gs201-mfc.dtsi" +#include "gs201-pwm.dtsi" + +/ { + compatible = "google,gs201"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <1>; + + aliases { + i2c20 = &acpm_mfd_bus0; + i2c21 = &acpm_mfd_bus1; + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + pinctrl4 = &pinctrl_4; + pinctrl5 = &pinctrl_5; + pinctrl6 = &pinctrl_6; + pinctrl7 = &pinctrl_7; + pinctrl8 = &pinctrl_8; + uart0 = &serial_0; + + }; + + ect { + parameter_address = <0x90000000>; + parameter_size = <0x53000>; + }; + + exynos-ect { + compatible = "samsung,exynos-ect"; + memory-region = <&ect_binary>; + }; + + chipid@10000000 { + compatible = "google,gs201-chipid"; + reg = <0x0 0x10000000 0xD000>; + }; + + chosen: chosen { + bootargs = "earlycon=exynos4210,mmio32,0x10A00000 console=ttySAC0,115200n8 clocksource=arch_sys_counter root=/dev/ram0 rw ramdisk_size=65536 androidboot.hardware.platform=gs201 androidboot.debug_level=0x4948 firmware_class.path=/vendor/firmware reserve-fimc=0xffffff90f9fe0000 clk_ignore_unused loop.max_part=7 coherent_pool=4M no_console_suspend softlockup_panic=1 maxcpus=8 sysrq_always_enabled kasan_multi_shot ehld.noehld=1 kvm-arm.protected_modules=exynos-pd,pkvm_s2mpu"; + }; + + odm: odm { + compatible = "simple-bus"; + ranges; + + /* reserved for overlay by ODM */ + }; + + gic: interrupt-controller@10400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x10400000 0x10000>, /* GICD */ + <0x0 0x10440000 0x100000>; /* GICR * 8 */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <24576000>; + }; + + ext_24_5m: ext_24_5m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + clock-output-names = "ext-24_5m"; + }; + + ext_100m: ext_100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "ext-100m"; + }; + + ext_200m: ext_200m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "ext-200m"; + }; + + ext_26m: ext_26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "ext-26m"; + }; + + ext_1m: ext_1m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "ext-1m"; + }; + + mct: mct@10050000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x0 0x10050000 0x800>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&mct_map>; + interrupts = <0>, <1>, <2>, <3>, + <4>, <5>, <6>, <7>, + <8>, <9>, <10>, <11>; + clocks = <&clock OSCCLK>, <&clock GATE_MCT>; + clock-names = "fin_pll", "mct"; + + mct_map: mct-map { + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0 &gic 0 IRQ_MCT_G0_MISC IRQ_TYPE_LEVEL_HIGH>, + <1 &gic 0 IRQ_MCT_G1_MISC IRQ_TYPE_LEVEL_HIGH>, + <2 &gic 0 IRQ_MCT_G2_MISC IRQ_TYPE_LEVEL_HIGH>, + <3 &gic 0 IRQ_MCT_G3_MISC IRQ_TYPE_LEVEL_HIGH>, + <4 &gic 0 IRQ_MCT_L0_MISC IRQ_TYPE_LEVEL_HIGH>, + <5 &gic 0 IRQ_MCT_L1_MISC IRQ_TYPE_LEVEL_HIGH>, + <6 &gic 0 IRQ_MCT_L2_MISC IRQ_TYPE_LEVEL_HIGH>, + <7 &gic 0 IRQ_MCT_L3_MISC IRQ_TYPE_LEVEL_HIGH>, + <8 &gic 0 IRQ_MCT_L4_MISC IRQ_TYPE_LEVEL_HIGH>, + <9 &gic 0 IRQ_MCT_L5_MISC IRQ_TYPE_LEVEL_HIGH>, + <10 &gic 0 IRQ_MCT_L6_MISC IRQ_TYPE_LEVEL_HIGH>, + <11 &gic 0 IRQ_MCT_L7_MISC IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + eh: eh@17100000 { + compatible = "google,eh"; + reg = <0x0 0x17100000 0x1000>; + interrupts = <GIC_SPI IRQ_EH_0_EH IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_EH_1_EH IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_EH_2_EH IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_EH_3_EH IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_EH_4_EH IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_EH_5_EH IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_EH_6_EH IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_EH_7_EH IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_EH_8_EH IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_EH_9_EH IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock DOUT_CLK_EH_NOCP>; + clock-names = "eh-clock"; + power-domains = <&pd_eh>; + google,eh,ignore-gctrl-reset; + s2mpus = <&s2mpu_eh>; + }; + + serial_0: uart@10A00000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + samsung,dbg-uart-ch; + samsung,dbg-uart-baud = <115200>; + samsung,dbg-word-len = <8>; + reg-io-width = <4>; + reg = <0x0 0x10A00000 0x100>; + samsung,fifo-size = <256>; + interrupts = <GIC_SPI IRQ_USI0_UART_PERIC0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock GATE_PERIC0_TOP1_USI0_UART>, <&clock VDOUT_CLK_PERIC0_USI0_UART>; + clock-names = "gate_uart_clk0", "ipclk_uart0"; + status = "disabled"; + }; + + /* GPIO_ALIVE */ + pinctrl_0: pinctrl@180D0000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x180d0000 0x00001000>; + interrupts = <GIC_SPI IRQ_ALIVE_EINT0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT23 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT44 IRQ_TYPE_LEVEL_HIGH>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + }; + }; + + /* DMA */ + amba: amba { + #address-cells = <2>; + #size-cells = <1>; + compatible = "arm,amba-bus"; + interrupt-parent = <&gic>; + ranges; + pdma0: pdma0@10110000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x10110000 0x1000>; + interrupts = <GIC_SPI IRQ_PDMA0_MISC IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ext_100m>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + #dma-multi-irq = <1>; + dma-arwrapper = <0x10114400>, + <0x10114420>, + <0x10114440>, + <0x10114460>, + <0x10114480>, + <0x101144A0>, + <0x101144C0>, + <0x101144E0>; + dma-awwrapper = <0x10114404>, + <0x10114424>, + <0x10114444>, + <0x10114464>, + <0x10114484>, + <0x101144A4>, + <0x101144C4>, + <0x101144E4>; + dma-instwrapper = <0x10114500>; + dma-mask-bit = <36>; + coherent-mask-bit = <36>; + }; + }; + + /* GPIO_FAR_ALIVE */ + pinctrl_1: pinctrl@180E0000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x180e0000 0x00001000>; + interrupts = <GIC_SPI IRQ_ALIVE_EINT45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT63 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_ALIVE_EINT66 IRQ_TYPE_LEVEL_HIGH>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + }; + }; + + /* GPIO_GSACORE */ + pinctrl_2: pinctrl@17A80000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x17a80000 0x00001000>; + }; + /* GPIO_GSACTRL */ + pinctrl_3: pinctrl@17940000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x17940000 0x00001000>; + }; + /* GPIO_PERIC0 */ + pinctrl_4: pinctrl@10840000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x10840000 0x00001000>; + interrupts = <GIC_SPI IRQ_GPIO_PERIC0_PERIC0 IRQ_TYPE_LEVEL_HIGH>; + }; + /* GPIO_PERIC1 */ + pinctrl_5: pinctrl@10C40000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x10C40000 0x00001000>; + interrupts = <GIC_SPI IRQ_GPIO_PERIC1_PERIC1 IRQ_TYPE_LEVEL_HIGH>; + }; + /* GPIO_HSI1 */ + pinctrl_6: pinctrl@11840000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x11840000 0x00001000>; + interrupts = <GIC_SPI IRQ_GPIO_HSI1_HSI1 IRQ_TYPE_LEVEL_HIGH>; + }; + /* GPIO_HSI2 */ + pinctrl_7: pinctrl@14440000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x14440000 0x00001000>; + interrupts = <GIC_SPI IRQ_GPIO_HSI2_HSI2 IRQ_TYPE_LEVEL_HIGH>; + }; + /* GPIO_HSI2UFS */ + pinctrl_8: pinctrl@14460000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x14460000 0x00001000>; + interrupts = <GIC_SPI IRQ_GPIO_HSI2UFS_HSI2 IRQ_TYPE_LEVEL_HIGH>; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + exynos-pm { + compatible = "samsung,exynos-pm"; + reg = <0x0 0x180D0000 0x1000>, + <0x0 0x180E0000 0x1000>, + <0x0 0x10540204 0x100>, + <0x0 0x18300000 0x100>, /* GS_MAILBOX_AP_AOCA3_HOST */ + <0x0 0x18320000 0x100>; /* GS_MAILBOX_AP_AOCF1_HOST */ + reg-names = "gpio_alive_base", + "gpio_far_alive_base", + "gicd_ispendrn_base", + "mailbox_ap_aoca3_host", + "mailbox_ap_aocf1_host"; + num-eint = <64>; /* EINT_0 ~ 44 */ + num-eint-far = <32>; /* EINT_45 ~ 66 */ + gpa-use = <8>, <7>, <5>, <4>, <4>, <7>, <8>, <2>, <8>, <4>, <8>, <2>; + num-gic = <30>; + suspend_mode_idx = <8>; + + pcieon_suspend_available = <1>; + pcieon_suspend_mode_idx = <13>; + + /* WAKEUP_STAT, WAKEUP2_STAT */ + wakeup_stat_offset = <0x3950>, <0x3970>; + wakeup_int_en_offset = <0x3944>, <0x3964>; + wakeup_int_en = <0x1001f0bf>, <0x01f0>; + + eint_wakeup_mask_offset = <0x3a80>, <0x3a84>, <0x3a88>; + wakeup-stat-eint = <0x30>; + wakeup-stat-rtc = <0>; + + wake_lock = <0>; /* 1: held wake_lock */ + + wakeup_stats { + wakeup_stat { + ws-name = + "RTC_ALARM", /* [ 0] */ + "RTC_TICK", /* [ 1] */ + "TRTC_ALARM", /* [ 2] */ + "TRTC_TICK", /* [ 3] */ + "EINT", /* [ 4] */ + "EINT_FAR", /* [ 5] */ + "MAILBOX_APM2AP", /* [ 6] */ + "MAILBOX_AOC2AP", /* [ 7] */ + "L1SUB_PCIE_GEN4A_0", /* [ 8] */ + "L1SUB_PCIE_GEN4B_0", /* [ 9] */ + "L1SUB_PCIE_GEN4A_1", /* [10] */ + "L1SUB_PCIE_GEN4B_1", /* [11] */ + "EXT_PCIE_GEN4A_0", /* [12] */ + "EXT_PCIE_GEN4B_0", /* [13] */ + "EXT_PCIE_GEN4A_1", /* [14] */ + "EXT_PCIE_GEN4B_1", /* [15] */ + "USB_REWA", /* [16] */ + "USBDP", /* [17] */ + "MMC_CARD", /* [18] */ + "TIMER", /* [19] */ + "CLUSTER0_CPU0_nIRQOUT",/* [20] */ + "CLUSTER0_CPU1_nIRQOUT",/* [21] */ + "CLUSTER0_CPU2_nIRQOUT",/* [22] */ + "CLUSTER0_CPU3_nIRQOUT",/* [23] */ + "CLUSTER1_CPU0_nIRQOUT",/* [24] */ + "CLUSTER1_CPU1_nIRQOUT",/* [25] */ + "CLUSTER2_CPU0_nIRQOUT",/* [26] */ + "CLUSTER2_CPU1_nIRQOUT",/* [27] */ + "INTREQ_PCIE_GEN4A_0", /* [28] */ + "INTREQ_PCIE_GEN4B_0", /* [29] */ + "INTREQ_PCIE_GEN4A_1", /* [30] */ + "INTREQ_PCIE_GEN4B_1"; /* [31] */ + }; + + wakeup_stat2 { + ws-name = + "RESERVED", /* [ 0] */ + "RESERVED", /* [ 1] */ + "USB20_PHY_FS_VMINUS_WAKEUP",/* [ 2] */ + "USB20_PHY_FS_VPLUS_WAKEUP", /* [ 3] */ + "MAILBOX_APM2AP", /* [ 4] */ + "MAILBOX_AOCA322AP", /* [ 5] */ + "MAILBOX_AOCF12AP", /* [ 6] */ + "MAILBOX_AOCP62AP", /* [ 7] */ + "MAILBOX_DBGCORE2AP", /* [ 8] */ + "MAILBOX_AUR02AP", /* [ 9] */ + "MAILBOX_AUR12AP", /* [10] */ + "MAILBOX_AUR22AP", /* [11] */ + "MAILBOX_AUR32AP", /* [12] */ + "VGPIO2PMU_EINT", /* [13] */ + "RESERVED", /* [14] */ + "RESERVED", /* [15] */ + "RESERVED", /* [16] */ + "RESERVED", /* [17] */ + "RESERVED", /* [18] */ + "RESERVED", /* [19] */ + "RESERVED", /* [20] */ + "RESERVED", /* [21] */ + "RESERVED", /* [22] */ + "RESERVED", /* [23] */ + "RESERVED", /* [24] */ + "RESERVED", /* [25] */ + "RESERVED", /* [26] */ + "RESERVED", /* [27] */ + "RESERVED", /* [28] */ + "RESERVED", /* [29] */ + "RESERVED", /* [30] */ + "RESERVED"; /* [31] */ + }; + }; + }; + + exynos-pmu { + compatible = "samsung,exynos-pmu"; + samsung,syscon-phandle = <&pmu_system_controller>; + reg = <0x0 0x18060000 0x10000>; + reg-names = "pmu_alive"; + }; + + pmu_system_controller: system-controller@18060000 { + compatible = "samsung,gs101-pmu", "syscon"; + reg = <0x0 0x18060000 0x10000>; + }; + + dsu-pmu-0 { + compatible = "arm,dsu-pmu"; + interrupts = <GIC_SPI IRQ_CPUCL0_CLUSTERPMUIRQ_CPUCL0 IRQ_TYPE_LEVEL_HIGH>; + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + pixel-reboot { + compatible = "google,pixel-reboot"; + syscon = <&pmu_system_controller>; + reboot-cmd-offset = <0x0810>; + force-warm-reboot-on-thermal-shutdown; + }; + + gpio_keys: gpio_keys { + compatible = "gpio-keys"; + }; + + cal_if { + compatible = "samsung,exynos_cal_if"; + reg = <0x0 0x1e080000 0x8000>; + acpm-ipc-channel = <0>; + }; + + clock: clock-controller@1e080000 { + compatible = "samsung,gs201-clock"; + reg = <0x0 0x1e080000 0x8000>; + #clock-cells = <1>; + acpm-ipc-channel = <0>; + }; + + acpm_flexpmu_dbg { + compatible = "google,acpm-flexpmu-dbg"; + }; + + acpm_mbox_test: mbox { + compatible = "google,acpm-mbox-test"; + mfd-regulator-list-main = + <0x118 0x11A 0x11C 0x11E + 0x120 0x124 0x12A 0x136 + 0x137 0x138 0x13A 0x13C>; + mfd-regulator-list-sub = + <0x110 0x112 0x116 0x118 + 0x11E 0x120 0x12C>; + }; + + acpm { + compatible = "google,gs-acpm"; + #address-cells = <2>; + #size-cells = <1>; + acpm-ipc-channel = <4>; + reg = <0x0 0x18040000 0x1000>; /* TIMER_APM */ + reg-names = "timer_apm"; + peritimer-cnt = <0xFFFF>; + }; + + acpm_ipc { + compatible = "google,gs-acpm-ipc"; + #address-cells = <2>; + #size-cells = <1>; + interrupts = <GIC_SPI IRQ_MAILBOX_APM2AP_ALIVE IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x18210000 0x01000>, /* AP2APM MAILBOX */ + <0x0 0x18500000 0x48000>, /* APM SRAM */ + <0x0 0x1802048C 0x00014>; /* ALIVE_FRC_CTRL */ + initdata-base = <0xA000>; + debug-log-level = <0>; + logging-period = <500>; + dump-base = <0x18505000>; + dump-size = <0x43000>; /* 268KB(= 288 - 20) */ + acpm-ipc-channel = <12>; + fvmap_addr = <0x31000>; + panic-action = <GO_PANIC_ID>; + }; + + acpm_stats { + compatible = "google,power-stats"; + timer-frequency-hz = <49152000>; + }; + + slc-dummy { + compatible = "google,pt"; + dummy { + id_size_priority = < 0x5 0x1001 0x1000 0x8002>; + }; + }; + + slc-acpm { + compatible = "google,slc-acpm"; + acpm-ipc-channel = <10>; + pt_id = "AoC_Sleep"; /* for testing */ + async { + acpm-ipc-channel = <11>; + }; + BYPASS { + /* vptid 0, size 0, priority 15 (lowest), pbha 0 */ + id_size_priority = < 0x0 0x1 0xf 0x0 >; + }; + LEFTOVER { + /* vptid 1, all size, priority 15 (lowest), pbha 1 */ + id_size_priority = < 0x1 0xffffffff 0xf 0x1 >; + }; + AoC_Sleep { + /* vptid 2, size 0, priority 0 (highest), pbha 2 */ + id_size_priority = < 0x2 0xffffffff 0x0 0x2 >; + }; + /* vptid 40 breakdown: + * bit[0-2] default (0) + * bit[3] force write allocate (1) + * bit[4] prevent read allocate (0) + * bit[5] special vptid (1) + * bit[6] don't force optimal fetch on read (0) + * bit[7] don't force optimal fetch on write (0) + */ + gpu_g0_p0 { + /* vptid 40, max size 256KB, priority 0, pbha 5 */ + id_size_priority = <0x28 0x00001001 0x0 0x5>; + }; + gpu_g0_p1 { + /* vptid 40, max size 512KB, priority 0, pbha 5 */ + id_size_priority = <0x28 0x00005001 0x0 0x5>; + }; + gpu_g0_p2 { + /* vptid 40, max size 768KB, priority 0, pbha 5 */ + id_size_priority = <0x28 0x0000d001 0x0 0x5>; + }; + gpu_g0_p3 { + /* vptid 40, max size 1024KB, priority 0, pbha 5 */ + id_size_priority = <0x28 0x0001d001 0x0 0x5>; + }; + gpu_g0_p4 { + /* vptid 40, max size 1536KB, priority 0, pbha 5 */ + id_size_priority = <0x28 0x0003d001 0x0 0x5>; + }; + gpu_g0_p5 { + /* vptid 40, max size 2048KB, priority 0, pbha 5 */ + id_size_priority = <0x28 0x0007d001 0x0 0x5>; + }; + gpu_g0_p6 { + /* vptid 40, max size 3072KB, priority 0, pbha 5 */ + id_size_priority = <0x28 0x000fd001 0x0 0x5>; + }; + gpu_g0_p7 { + /* vptid 40, max size 4096KB, priority 0, pbha 5 */ + id_size_priority = <0x28 0x001fd001 0x0 0x5>; + }; + gpu_g0_p8 { + /* vptid 40, max size 6144KB, priority 0, pbha 5 */ + id_size_priority = <0x28 0x003fd001 0x0 0x5>; + }; + gpu_g0_p9 { + /* vptid 40, max size 8192KB, priority 0, pbha 5 */ + id_size_priority = <0x28 0x007fd001 0x0 0x5>; + }; + gpu_g1_p0 { + /* vptid 2, max size 8192KB, priority 0, pbha 6 */ + id_size_priority = <0x2 0xffffffff 0x0 0x6>; + }; + CAMERA2WAY { + /* vptid 3, size 512KB, priority 0 (highest), pbha 0 */ + id_size_priority = < 0x3 0x00002001 0x0 0x0 >; + }; + CAMERA4WAY0 { + /* vptid 3, size 1024KB, priority 0 (highest), pbha 0 */ + id_size_priority = < 0x3 0x00010001 0x0 0x0 >; + }; + CAMERA4WAY1 { + /* vptid 3, size 1024KB, priority 0 (highest), pbha 0 */ + id_size_priority = < 0x3 0x00010001 0x0 0x0 >; + }; + CAMERA4WAY2 { + /* vptid 3, size 1024KB, priority 0 (highest), pbha 0 */ + id_size_priority = < 0x3 0x00010001 0x0 0x0 >; + }; + CAMERA6WAY0 { + /* vptid 3, size 1536KB, priority 0 (highest), pbha 0 */ + id_size_priority = < 0x3 0x00020001 0x0 0x0 >; + }; + CAMERA6WAY1 { + /* vptid 3, size 1536KB, priority 0 (highest), pbha 0 */ + id_size_priority = < 0x3 0x00020001 0x0 0x0 >; + }; + CAMERA6WAY2 { + /* vptid 3, size 1536KB, priority 0 (highest), pbha 0 */ + id_size_priority = < 0x3 0x00020001 0x0 0x0 >; + }; + CAMERA8WAY0 { + /* vptid 4, size 2048KB, priority 0 (highest), pbha 0 */ + id_size_priority = < 0x4 0x00040001 0x0 0x0 >; + }; + bigocean { + /* vptid 3, 1536-256KB size, priority 0, pbha 0 */ + id_size_priority = < 0x3 0x0003f001 0x0 0x0 >; + }; + MFC { + /* vptid 9, 2*256KB, priority 0 (highest), pbha ? */ + id_size_priority = < 0x9 0x00002001 0x0 0x0>; + }; + }; + + acpm_mfd_bus0: acpm_mfd_bus@18100000 { + compatible = "google,i2c-acpm"; + status = "okay"; + }; + + acpm_mfd_bus1: acpm_mfd_bus@18110000 { + compatible = "google,i2c-acpm"; + status = "okay"; + }; + + smfc: smfc@1C700000 { + compatible = "samsung,exynos8890-jpeg"; + reg = <0x0 0x1C700000 0x1000>; + interrupts = <0 IRQ_JPEG_G2D IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock GATE_JPEG>; + clock-names = "gate"; + power-domains = <&pd_g2d>; + samsung,iommu-group = <&iommu_group_smfc>; + iommus = <&sysmmu_g2d2>; + dma-coherent; + smfc,int_qos_minlock = <533000>; + }; + + udc: usb@11210000 { + compatible = "samsung,exynos9-dwusb"; + clocks = <&clock GATE_USB31DRD_SLV_LINK>, + <&clock MUX_HSI0_USB20_REF>, + <&clock VDOUT_CLK_TOP_HSI0_NOC>; + //clock-names = "aclk", "sclk"; + clock-names = "aclk", "sclk", "bus"; + reg = <0x0 0x11210000 0x10000>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + power-domains = <&pd_hsi0>; + status = "okay"; + + interrupts = <GIC_SPI IRQ_USB31DRD_GIC_0_HSI0 IRQ_TYPE_LEVEL_HIGH>; + tx-fifo-resize = <0>; + adj-sof-accuracy = <0>; + is_not_vbus_pad = <1>; + enable_sprs_transfer = <1>; + phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; + phy-names = "usb2-phy", "usb3-phy"; + /* check susphy support */ + //suspend_clk_freq = <19200000>; + /* INT min lock support */ + usb-pm-qos-int = <200000>; + usb_host_device_timeout = <0x7ff>; /* Max value */ + + usbdrd_dwc3: dwc3 { + compatible = "synopsys,dwc3"; + clocks = <&clock GATE_USB31DRD_SLV_LINK>, + <&clock MUX_HSI0_USB20_REF>; + clock-names = "aclk", "sclk"; + reg = <0x0 0x11210000 0x10000>; + interrupts = <GIC_SPI IRQ_USB31DRD_GIC_0_HSI0 IRQ_TYPE_LEVEL_HIGH>; + memory-region = <&xhci_dma>; + dr_mode = "peripheral"; + phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; + phy-names = "usb2-phy", "usb3-phy"; + /* support usb offloading, 0: disabled, 1: audio */ + offload = <1>; + direct-usb-access; + }; + }; + + usbdrd_phy0: phy@11200000 { + compatible = "samsung,exynos-usbdrd-phy"; + reg = <0x0 0x11200000 0x200>, + <0x0 0x110F0000 0x2800>, + <0x0 0x11100000 0x800>, + <0x0 0x11210000 0x10000>; + power-domains = <&pd_hsi0>; + interrupts = <GIC_SPI IRQ_USB2_REMOTE_WAKEUP_GIC_HSI0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI IRQ_USB2_REMOTE_CONNECT_GIC_HSI0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock MUX_HSI0_USB20_REF>, + <&clock GATE_USB31DRD_SLV_LINK>; + clock-names = "phy_ref", "aclk"; + samsung,pmu-syscon = <&pmu_system_controller>; + pmu_mask = <0x0>; + /*pmu_mask_pll = <0x1>;*/ + pmu_offset = <0x3EB0>; + pmu_offset_dp = <0x3EB4>; + /* USBDP combo phy version - 0x200 */ + phy_version = <0x301>; + /* if it doesn't need phy user mux, */ + /* you should write "none" */ + /* but refclk shouldn't be omitted */ + phyclk_mux = "none"; + phy_refclk = "phy_ref"; + phy_ref_clock = <19200000>; + s2mpus = <&s2mpu_hsi0>; + + /* + * if Main phy has the other phy, + * it must be set to 1 just for usbphy_info + */ + has_other_phy = <0>; + /* + * if combo phy is used, it must be set to 1. + * usbphy_sub_info is enabled + */ + has_combo_phy = <1>; + sub_phy_version = <0x404>; + + /* ip type */ + /* USB3DRD = 0 */ + /* USB3HOST = 1 */ + /* USB2DRD = 2 */ + /* USB2HOST = 3 */ + ip_type = <0x0>; + + /* for PHY CAL */ + /* choice only one item */ + phy_refsel_clockcore = <1>; + phy_refsel_ext_osc = <0>; + phy_refsel_xtal = <0>; + phy_refsel_diff_pad = <0>; + phy_refsel_diff_internal = <0>; + phy_refsel_diff_single = <0>; + + /* true : 1 , false : 0 */ + use_io_for_ovc = <0>; + common_block_disable = <1>; + is_not_vbus_pad = <1>; + used_phy_port = <0>; + + status = "okay"; + + #phy-cells = <1>; + ranges; + }; + + sub_pd_hsi0: sub-pd-hsi0 { + compatible = "exynos-pd-hsi0"; + power-domains = <&pd_hsi0>; + status = "okay"; + }; + + exynos_dm: exynos-dm@17000000 { + compatible = "samsung,exynos-dvfs-manager"; + reg = <0x0 0x17000000 0x0>; + acpm-ipc-channel = <1>; + dm_domains { + cpufreq_cl0 { + dm-index = <DM_CPU_CL0>; + available = "true"; + cal_id = <ACPM_DVFS_CPUCL0>; + dm_type_name = "dm_cpu_cl0"; + }; + cpufreq_cl1 { + dm-index = <DM_CPU_CL1>; + available = "true"; + cal_id = <ACPM_DVFS_CPUCL1>; + dm_type_name = "dm_cpu_cl1"; + }; + cpufreq_cl2 { + dm-index = <DM_CPU_CL2>; + available = "true"; + cal_id = <ACPM_DVFS_CPUCL2>; + dm_type_name = "dm_cpu_cl2"; + }; + devfreq_mif { + dm-index = <DM_MIF>; + available = "true"; + policy_use = "true"; + cal_id = <ACPM_DVFS_MIF>; + dm_type_name = "dm_mif"; + }; + devfreq_int { + dm-index = <DM_INT>; + available = "true"; + policy_use = "true"; + cal_id = <ACPM_DVFS_INT>; + dm_type_name = "dm_int"; + }; + devfreq_intcam { + dm-index = <DM_INTCAM>; + available = "true"; + cal_id = <ACPM_DVFS_INTCAM>; + dm_type_name = "dm_intcam"; + }; + devfreq_cam { + dm-index = <DM_CAM>; + available = "true"; + cal_id = <ACPM_DVFS_CAM>; + dm_type_name = "dm_cam"; + }; + devfreq_tpu { + dm-index = <DM_TPU>; + available = "true"; + cal_id = <ACPM_DVFS_TPU>; + dm_type_name = "dm_tpu"; + }; + devfreq_tnr { + dm-index = <DM_TNR>; + available = "true"; + cal_id = <ACPM_DVFS_TNR>; + dm_type_name = "dm_tnr"; + }; + devfreq_disp { + dm-index = <DM_DISP>; + available = "true"; + cal_id = <ACPM_DVFS_DISP>; + dm_type_name = "dm_disp"; + }; + devfreq_mfc { + dm-index = <DM_MFC>; + available = "true"; + cal_id = <ACPM_DVFS_MFC>; + dm_type_name = "dm_mfc"; + }; + devfreq_bo { + dm-index = <DM_BO>; + available = "true"; + cal_id = <ACPM_DVFS_BO>; + dm_type_name = "dm_BO"; + }; + }; + }; + + exynos_devfreq { + compatible = "samsung,exynos-devfreq-root"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + devfreq_0: devfreq_mif@17000010 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000010 0x0>; + devfreq_type = <DEVFREQ_MIF>; + devfreq_domain_name = "MIF"; + pm_qos_class = <PM_QOS_BUS_THROUGHPUT>; + pm_qos_class_max = <PM_QOS_BUS_THROUGHPUT_MAX>; + ess_flag = <ESS_FLAG_MIF>; + dm-index = <DM_MIF>; + clocks = <&clock UMUX_MIF_DDRPHY2X>; + clock-names = "DEVFREQ"; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <421000 421000 421000 421000 3172000 1014000>; + /* initial_freq, default_qos, suspend_freq, min_freq, max_freq reboot_freq */ + + /* governor data */ + governor = <SIMPLE_INTERACTIVE>; + + /* boot_info */ + boot_info = <60 2730000>; + + dfs_id = <ACPM_DVFS_MIF>; + acpm-ipc-channel = <1>; + use_acpm = "true"; + + /* ALT-DVFS */ + use_get_dev = "true"; + um_count = <2 4 4>; + um_list = < + /* PPC_CPUCL0_D0_EVENT PPC_CPUCL0_D1_EVENT */ + 0x1E110000 0x1E120000 + /* PPC_CCI_M0_EVENT PPC_CCI_M1_EVENT */ + 0x1E130000 0x1E140000 + /* PPC_CCI_M2_EVENT PPC_CCI_M3_EVENT */ + 0x1E150000 0x1E160000 + /* PPC_BUS2_M0_EVENT PPC_BUS2_M1_EVENT */ + 0x1E170000 0x1E180000 + /* PPC_BUS2_M2_EVENT PPC_BUS2_M3_EVENT */ + 0x1E190000 0x1E1A0000 + >; + + use_alt_dvfs; + polling_ms = <0>; + target_load = <60 10 40>; + min_sample_time = <20>; + hold_sample_time = <60>; + hispeed_load = <100>; + hispeed_freq = <1352000>; + + /* MIF to INT mapping table used in ALT DVFS */ + mif_int_map = < + /* + * mif_clk int_clk + *----------------- + */ + 3172000 533000 + 2730000 465000 + 2028000 332000 + 1539000 267000 + 1352000 200000 + 1014000 155000 + 546000 100000 + >; + }; + + devfreq_1: devfreq_int@17000020 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000020 0x0>; + devfreq_type = <DEVFREQ_INT>; + devfreq_domain_name = "INT"; + pm_qos_class = <PM_QOS_DEVICE_THROUGHPUT>; + pm_qos_class_max = <PM_QOS_DEVICE_THROUGHPUT_MAX>; + ess_flag = <ESS_FLAG_INT>; + dm-index = <DM_INT>; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <100000 100000 100000 100000 533000 533000>; + /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */ + + /* boot_info */ + boot_info = <60 465000>; + + /* governor data */ + governor = <SIMPLE_INTERACTIVE>; + + bts_update = "false"; + dfs_id = <ACPM_DVFS_INT>; + acpm-ipc-channel = <1>; + use_acpm = "true"; + }; + + devfreq_2: devfreq_intcam@17000030 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000030 0x0>; + devfreq_type = <DEVFREQ_INTCAM>; + devfreq_domain_name = "INTCAM"; + pm_qos_class = <PM_QOS_INTCAM_THROUGHPUT>; + pm_qos_class_max = <PM_QOS_INTCAM_THROUGHPUT_MAX>; + ess_flag = <ESS_FLAG_INTCAM>; + dm-index = <DM_INTCAM>; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <67000 67000 67000 67000 664000 664000>; + /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */ + + /* governor data */ + governor = <SIMPLE_INTERACTIVE>; + + bts_update = "false"; + dfs_id = <ACPM_DVFS_INTCAM>; + }; + + devfreq_3: devfreq_disp@17000040 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000040 0x0>; + devfreq_type = <DEVFREQ_DISP>; + devfreq_domain_name = "DISP"; + pm_qos_class = <PM_QOS_DISPLAY_THROUGHPUT>; + pm_qos_class_max = <PM_QOS_DISPLAY_THROUGHPUT_MAX>; + ess_flag = <ESS_FLAG_DISP>; + dm-index = <DM_DISP>; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <134000 134000 134000 134000 664000 664000>; + /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */ + + /* governor data */ + governor = <SIMPLE_INTERACTIVE>; + + bts_update = "false"; + dfs_id = <ACPM_DVFS_DISP>; + }; + + devfreq_4: devfreq_cam@17000050 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000050 0x0>; + devfreq_type = <DEVFREQ_CAM>; + devfreq_domain_name = "CAM"; + pm_qos_class = <PM_QOS_CAM_THROUGHPUT>; + pm_qos_class_max = <PM_QOS_CAM_THROUGHPUT_MAX>; + ess_flag = <ESS_FLAG_ISP>; + dm-index = <DM_CAM>; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <67000 67000 67000 67000 664000 664000>; + /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */ + + /* governor data */ + governor = <SIMPLE_INTERACTIVE>; + + bts_update = "false"; + + dfs_id = <ACPM_DVFS_CAM>; + }; + + devfreq_5: devfreq_tnr@17000060 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000060 0x0>; + devfreq_type = <DEVFREQ_TNR>; + devfreq_domain_name = "TNR"; + pm_qos_class = <PM_QOS_TNR_THROUGHPUT>; + pm_qos_class_max = <PM_QOS_TNR_THROUGHPUT_MAX>; + ess_flag = <ESS_FLAG_TNR>; + dm-index = <DM_TNR>; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <67000 67000 67000 67000 664000 664000>; + /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */ + + /* governor data */ + governor = <SIMPLE_INTERACTIVE>; + + bts_update = "false"; + dfs_id = <ACPM_DVFS_TNR>; + }; + + devfreq_6: devfreq_mfc@17000070 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000070 0x0>; + devfreq_type = <DEVFREQ_MFC>; + devfreq_domain_name = "MFC"; + pm_qos_class = <PM_QOS_MFC_THROUGHPUT>; + pm_qos_class_max = <PM_QOS_MFC_THROUGHPUT_MAX>; + ess_flag = <ESS_FLAG_MFC>; + dm-index = <DM_MFC>; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <100000 100000 100000 100000 711000 711000>; + /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */ + + /* governor data */ + governor = <SIMPLE_INTERACTIVE>; + + bts_update = "false"; + dfs_id = <ACPM_DVFS_MFC>; + }; + + devfreq_7: devfreq_bo@17000080 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000080 0x0>; + devfreq_type = <DEVFREQ_BO>; + devfreq_domain_name = "BO"; + pm_qos_class = <PM_QOS_BO_THROUGHPUT>; + pm_qos_class_max = <PM_QOS_BO_THROUGHPUT_MAX>; + ess_flag = <ESS_FLAG_BO>; + dm-index = <DM_BO>; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <95000 95000 95000 95000 620000 620000>; + /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */ + + /* governor data */ + governor = <SIMPLE_INTERACTIVE>; + + bts_update = "false"; + dfs_id = <ACPM_DVFS_BO>; + }; + }; + + gs_governor_memlat: gs-governor-memlat { + compatible = "google,gs_governor_memlat"; + + primary_vote_config { + vote_name = "memlat"; + pm_qos_class = <PM_QOS_BUS_THROUGHPUT>; + }; + + governor_config { + gs_memlat_cl0 { + cpulist = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + ratio_ceil = <400>; + stall_floor = <0>; + cpuidle_state_depth_threshold = <2>; + + core-dev-table-latency = + /* CL0 MIF */ + < 10000 421000 >, + < 300001 546000 >, + < 574001 676000 >, + < 738001 845000 >, + < 930001 1014000 >, + < 1098001 1352000 >, + < 1197001 1539000 >, + < 1328001 1716000 >, + < 1598001 2028000 >, + < 1803001 2535000 >; + }; + gs_memlat_cl1 { + cpulist = <&cpu4>, <&cpu5>; + ratio_ceil = <2700>; + stall_floor = <0>; + cpuidle_state_depth_threshold = <2>; + + core-dev-table-latency = + /* CL1 MIF */ + < 10000 421000 >, + < 400001 546000 >, + < 553001 676000 >, + < 696001 845000 >, + < 799001 1014000 >, + < 1024001 1716000 >, + < 1491001 2028000 >, + < 1836001 2288000 >, + < 2130001 2730000 >; + }; + gs_memlat_cl2 { + cpulist = <&cpu6>, <&cpu7>; + ratio_ceil = <3200>; + stall_floor = <0>; + cpuidle_state_depth_threshold = <2>; + + core-dev-table-latency = + /* CL2 MIF */ + < 10000 845000 >, + < 100001 1014000 >, + < 851001 1352000 >, + < 1106001 1539000 >, + < 1277001 1716000 >, + < 1582001 2028000 >, + < 1826001 2288000 >, + < 2048001 2730000 >, + < 2252001 3172000 >; + }; + }; + }; + + gs_perf_mon { + compatible = "google,gs_perf_mon"; + param_ticks_per_counter_update = <2>; + client_update_backup_us = <10000>; + client_update_interval_us = <8000>; + gs_perf_cpu { + cpu0 { + cpu_idx = <0>; + pmu_events { + l3-cachemiss-ev = <0x002A>; + inst-ev = <0x0008>; + cyc-ev = <0x0011>; + }; + }; + cpu1 { + cpu_idx = <1>; + pmu_events { + l3-cachemiss-ev = <0x002A>; + inst-ev = <0x0008>; + cyc-ev = <0x0011>; + }; + }; + cpu2 { + cpu_idx = <2>; + pmu_events { + l3-cachemiss-ev = <0x002A>; + inst-ev = <0x0008>; + cyc-ev = <0x0011>; + }; + }; + cpu3 { + cpu_idx = <3>; + pmu_events { + l3-cachemiss-ev = <0x002A>; + inst-ev = <0x0008>; + cyc-ev = <0x0011>; + }; + }; + cpu4 { + cpu_idx = <4>; + pmu_events { + l3-cachemiss-ev = <0x002A>; + inst-ev = <0x0008>; + cyc-ev = <0x0011>; + }; + }; + cpu5 { + cpu_idx = <5>; + pmu_events { + l3-cachemiss-ev = <0x002A>; + inst-ev = <0x0008>; + cyc-ev = <0x0011>; + }; + }; + cpu6 { + cpu_idx = <6>; + pmu_events { + l3-cachemiss-ev = <0x002A>; + inst-ev = <0x0008>; + cyc-ev = <0x0011>; + }; + }; + cpu7 { + cpu_idx = <7>; + pmu_events { + l3-cachemiss-ev = <0x002A>; + inst-ev = <0x0008>; + cyc-ev = <0x0011>; + }; + }; + }; + }; + + gs_memlat_devfreq { + compatible = "memlat-devfreq-root"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mif_cpu0_mem_lat: devfreq_mif_cpu0_memlat@17000010 { + compatible = "memlat-devfreq"; + cpu = <0>; + devfreq_type = <DEVFREQ_MIF>; + devfreq_domain_name = "MIF"; + pm_qos_class = <PM_QOS_BUS_THROUGHPUT>; + pm_qos_class_max = <PM_QOS_BUS_THROUGHPUT_MAX>; + dm-index = <DM_MIF>; + clock-names = "DEVFREQ"; + polling_ms = <10>; + + /* governor data */ + governor = <MEM_LATENCY>; + dfs_id = <ACPM_DVFS_MIF>; + + }; + + mif_cpu1_mem_lat: devfreq_mif_cpu1_memlat@17000010 { + compatible = "memlat-devfreq"; + cpu = <1>; + devfreq_type = <DEVFREQ_MIF>; + devfreq_domain_name = "MIF"; + pm_qos_class = <PM_QOS_BUS_THROUGHPUT>; + pm_qos_class_max = <PM_QOS_BUS_THROUGHPUT_MAX>; + dm-index = <DM_MIF>; + clock-names = "DEVFREQ"; + polling_ms = <10>; + + /* governor data */ + governor = <MEM_LATENCY>; + dfs_id = <ACPM_DVFS_MIF>; + + }; + + mif_cpu2_mem_lat: devfreq_mif_cpu2_memlat@17000010 { + compatible = "memlat-devfreq"; + cpu = <2>; + devfreq_type = <DEVFREQ_MIF>; + devfreq_domain_name = "MIF"; + pm_qos_class = <PM_QOS_BUS_THROUGHPUT>; + pm_qos_class_max = <PM_QOS_BUS_THROUGHPUT_MAX>; + dm-index = <DM_MIF>; + clock-names = "DEVFREQ"; + polling_ms = <10>; + + /* governor data */ + governor = <MEM_LATENCY>; + dfs_id = <ACPM_DVFS_MIF>; + + }; + + mif_cpu3_mem_lat: devfreq_mif_cpu3_memlat@17000010 { + compatible = "memlat-devfreq"; + cpu = <3>; + devfreq_type = <DEVFREQ_MIF>; + devfreq_domain_name = "MIF"; + pm_qos_class = <PM_QOS_BUS_THROUGHPUT>; + pm_qos_class_max = <PM_QOS_BUS_THROUGHPUT_MAX>; + dm-index = <DM_MIF>; + clock-names = "DEVFREQ"; + polling_ms = <10>; + + /* governor data */ + governor = <MEM_LATENCY>; + dfs_id = <ACPM_DVFS_MIF>; + + }; + + + mif_cpu4_mem_lat: devfreq_mif_cpu4_memlat@17000010 { + compatible = "memlat-devfreq"; + cpu = <4>; + devfreq_type = <DEVFREQ_MIF>; + devfreq_domain_name = "MIF"; + pm_qos_class = <PM_QOS_BUS_THROUGHPUT>; + pm_qos_class_max = <PM_QOS_BUS_THROUGHPUT_MAX>; + dm-index = <DM_MIF>; + clock-names = "DEVFREQ"; + polling_ms = <10>; + + /* governor data */ + governor = <MEM_LATENCY>; + dfs_id = <ACPM_DVFS_MIF>; + + }; + + mif_cpu5_mem_lat: devfreq_mif_cpu5_memlat@17000010 { + compatible = "memlat-devfreq"; + cpu = <5>; + devfreq_type = <DEVFREQ_MIF>; + devfreq_domain_name = "MIF"; + pm_qos_class = <PM_QOS_BUS_THROUGHPUT>; + pm_qos_class_max = <PM_QOS_BUS_THROUGHPUT_MAX>; + dm-index = <DM_MIF>; + clock-names = "DEVFREQ"; + polling_ms = <10>; + + /* governor data */ + governor = <MEM_LATENCY>; + dfs_id = <ACPM_DVFS_MIF>; + + }; + + mif_cpu6_mem_lat: devfreq_mif_cpu6_memlat@17000010 { + compatible = "memlat-devfreq"; + cpu = <6>; + devfreq_type = <DEVFREQ_MIF>; + devfreq_domain_name = "MIF"; + pm_qos_class = <PM_QOS_BUS_THROUGHPUT>; + pm_qos_class_max = <PM_QOS_BUS_THROUGHPUT_MAX>; + dm-index = <DM_MIF>; + clock-names = "DEVFREQ"; + polling_ms = <10>; + + /* governor data */ + governor = <MEM_LATENCY>; + dfs_id = <ACPM_DVFS_MIF>; + + }; + + mif_cpu7_mem_lat: devfreq_mif_cpu7_memlat@17000010 { + compatible = "memlat-devfreq"; + cpu = <7>; + devfreq_type = <DEVFREQ_MIF>; + devfreq_domain_name = "MIF"; + pm_qos_class = <PM_QOS_BUS_THROUGHPUT>; + pm_qos_class_max = <PM_QOS_BUS_THROUGHPUT_MAX>; + dm-index = <DM_MIF>; + clock-names = "DEVFREQ"; + polling_ms = <10>; + + /* governor data */ + governor = <MEM_LATENCY>; + dfs_id = <ACPM_DVFS_MIF>; + + }; + }; + + cpu0_memlat_cpugrp: cpu0-cpugrp { + compatible = "arm-memlat-cpugrp"; + cpulist = <&cpu0>; + + cpu0_cpu_mif_latmon: cpu0-cpu-mif-latmon { + compatible = "arm-memlat-mon"; + cpulist = <&cpu0>; + target-dev = <&mif_cpu0_mem_lat>; + cachemiss-ev = <0x2A>; + core-dev-table = + < 300000 421000 >, + < 574000 546000 >, + < 738000 676000 >, + < 930000 845000 >, + < 1098000 1014000 >, + < 1197000 1352000 >, + < 1328000 1539000 >, + < 1598000 1716000 >, + < 1803000 2028000 >, + < 2024000 2535000 >; + }; + }; + + cpu1_memlat_cpugrp: cpu1-cpugrp { + compatible = "arm-memlat-cpugrp"; + cpulist = <&cpu1>; + + cpu1_cpu_mif_latmon: cpu1-cpu-mif-latmon { + compatible = "arm-memlat-mon"; + cpulist = <&cpu1>; + target-dev = <&mif_cpu1_mem_lat>; + cachemiss-ev = <0x2A>; + core-dev-table = + < 300000 421000 >, + < 574000 546000 >, + < 738000 676000 >, + < 930000 845000 >, + < 1098000 1014000 >, + < 1197000 1352000 >, + < 1328000 1539000 >, + < 1598000 1716000 >, + < 1803000 2028000 >, + < 2024000 2535000 >; + }; + }; + + cpu2_memlat_cpugrp: cpu2-cpugrp { + compatible = "arm-memlat-cpugrp"; + cpulist = <&cpu2>; + + cpu2_cpu_mif_latmon: cpu2-cpu-mif-latmon { + compatible = "arm-memlat-mon"; + cpulist = <&cpu2>; + target-dev = <&mif_cpu2_mem_lat>; + cachemiss-ev = <0x2A>; + core-dev-table = + < 300000 421000 >, + < 574000 546000 >, + < 738000 676000 >, + < 930000 845000 >, + < 1098000 1014000 >, + < 1197000 1352000 >, + < 1328000 1539000 >, + < 1598000 1716000 >, + < 1803000 2028000 >, + < 2024000 2535000 >; + }; + }; + + cpu3_memlat_cpugrp: cpu3-cpugrp { + compatible = "arm-memlat-cpugrp"; + cpulist = <&cpu3>; + + cpu3_cpu_mif_latmon: cpu3-cpu-mif-latmon { + compatible = "arm-memlat-mon"; + cpulist = <&cpu3>; + target-dev = <&mif_cpu3_mem_lat>; + cachemiss-ev = <0x2A>; + core-dev-table = + < 300000 421000 >, + < 574000 546000 >, + < 738000 676000 >, + < 930000 845000 >, + < 1098000 1014000 >, + < 1197000 1352000 >, + < 1328000 1539000 >, + < 1598000 1716000 >, + < 1803000 2028000 >, + < 2024000 2535000 >; + }; + }; + + + cpu4_memlat_cpugrp: cpu4-cpugrp { + compatible = "arm-memlat-cpugrp"; + cpulist = <&cpu4>; + + cpu4_cpu_mif_latmon: cpu4-cpu-mif-latmon { + compatible = "arm-memlat-mon"; + cpulist = <&cpu4>; + target-dev = <&mif_cpu4_mem_lat>; + cachemiss-ev = <0x2A>; + core-dev-table = + < 400000 421000 >, + < 553000 546000 >, + < 696000 676000 >, + < 799000 845000 >, + < 1024000 1014000 >, + < 1491000 1716000 >, + < 1836000 2028000 >, + < 2130000 2288000 >, + < 2253000 2730000 >; + }; + }; + + cpu5_memlat_cpugrp: cpu5-cpugrp { + compatible = "arm-memlat-cpugrp"; + cpulist = <&cpu5>; + + cpu5_cpu_mif_latmon: cpu5-cpu-mif-latmon { + compatible = "arm-memlat-mon"; + cpulist = <&cpu5>; + target-dev = <&mif_cpu5_mem_lat>; + cachemiss-ev = <0x2A>; + core-dev-table = + < 400000 421000 >, + < 553000 546000 >, + < 696000 676000 >, + < 799000 845000 >, + < 1024000 1014000 >, + < 1491000 1716000 >, + < 1836000 2028000 >, + < 2130000 2288000 >, + < 2253000 2730000 >; + }; + }; + + cpu6_memlat_cpugrp: cpu6-cpugrp { + compatible = "arm-memlat-cpugrp"; + cpulist = <&cpu6>; + + cpu6_cpu_mif_latmon: cpu6-cpu-mif-latmon { + compatible = "arm-memlat-mon"; + cpulist = <&cpu6>; + target-dev = <&mif_cpu6_mem_lat>; + cachemiss-ev = <0x2A>; + core-dev-table = + < 10000 421000 >, + < 100000 845000 >, + < 851000 1014000 >, + < 1106000 1352000 >, + < 1277000 1539000 >, + < 1582000 1716000 >, + < 1826000 2028000 >, + < 2048000 2288000 >, + < 2252000 2730000 >, + < 2507000 3172000 >; + }; + }; + + cpu7_memlat_cpugrp: cpu7-cpugrp { + compatible = "arm-memlat-cpugrp"; + cpulist = <&cpu7>; + + cpu7_cpu_mif_latmon: cpu7-cpu-mif-latmon { + compatible = "arm-memlat-mon"; + cpulist = <&cpu7>; + target-dev = <&mif_cpu7_mem_lat>; + cachemiss-ev = <0x2A>; + core-dev-table = + < 10000 421000 >, + < 100000 845000 >, + < 851000 1014000 >, + < 1106000 1352000 >, + < 1277000 1539000 >, + < 1582000 1716000 >, + < 1826000 2028000 >, + < 2048000 2288000 >, + < 2252000 2730000 >, + < 2507000 3172000 >; + }; + }; + + g2d: g2d@1C640000 { + compatible = "samsung,gs201-g2d"; + reg = <0x0 0x1C640000 0xA000>; + interrupts = <0 IRQ_G2D_G2D IRQ_TYPE_LEVEL_HIGH>; + samsung,iommu-group = <&iommu_group_g2d>; + iommus = <&sysmmu_g2d0>, <&sysmmu_g2d1>; + clocks = <&clock GATE_G2D>; + clock-names = "gate"; + samsung,tzmp; + hw_ppc = + /* sc_up none x1 x1/4 x1/9 x1/16 */ + <3800 3200 2100 2600 3300 3600 /* rgb32 non-rotated */ + 3500 3600 2100 2700 3300 3800 /* rgb32 rotated */ + 3700 3500 3600 4300 4300 3500 /* yuv2p non-rotated */ + 2600 2800 3200 3900 4300 3600 /* yuv2p rotated */ + 3600 2600 1400 900 1000 1000 /* sbwc non-rotated */ + 2600 2600 1400 900 1000 1000 /* sbwc rotated */ + 1600 3400 300 500 800 700 /*rgb afbc non-rotated*/ + 1400 3600 300 800 900 900 /*rgb afbc rotated*/ + 2900 2000 800 300 300 400 /*yuv afbc non-rotated*/ + 2600 2000 800 300 300 400 /*yuv afbc rotated*/ + 2800>; /* colorfill */ + + g2d_dvfs_table = <533000 711000 + 465000 400000 + 332000 332000 + 200000 200000 + 100000 100000 + >; + itmon,port = "G2D0", "G2D1"; + itmon,dest = "G2D"; + dvfs_mif = <DEVFREQ_MIF>; + dvfs_int = <DEVFREQ_INT>; + }; + + watchdog_cl0: watchdog_cl0@10060000 { + compatible = "google,gs201-cl0-wdt"; + reg = <0x0 0x10060000 0x100>; + interrupts = <GIC_SPI IRQ_WDT_CLUSTER0_MISC IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock OSCCLK>, <&clock GATE_WDT_CL0>; + clock-names = "rate_watchdog", "gate_watchdog"; + timeout-sec = <30>; + samsung,syscon-phandle = <&pmu_system_controller>; + index = <0>; /* if little cluster then index is 0*/ + }; + + watchdog_cl1: watchdog_cl1@10070000 { + compatible = "google,gs201-cl1-wdt"; + reg = <0x0 0x10070000 0x100>; + interrupts = <GIC_SPI IRQ_WDT_CLUSTER1_MISC IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock OSCCLK>, <&clock GATE_WDT_CL1>; + clock-names = "rate_watchdog", "gate_watchdog"; + timeout-sec = <30>; + samsung,syscon-phandle = <&pmu_system_controller>; + index = <1>; /* if little cluster then index is 0*/ + use_multistage_wdt; /* Use FIQ debug watchdog */ + }; + + acpm_tmu { + acpm-ipc-channel = <9>; + }; + + /* Secure Log */ + seclog { + compatible = "samsung,exynos-seclog"; + interrupts = <GIC_SPI INTREQ__SECURE_LOG IRQ_TYPE_LEVEL_HIGH>; + memory-region = <&seclog_mem>; + }; +};
diff --git a/gs201_defconfig b/gs201_defconfig new file mode 100644 index 0000000..e6a9c1b --- /dev/null +++ b/gs201_defconfig
@@ -0,0 +1,260 @@ +# In-tree kernel configs. Note that these configs are only applied to +# non-GKI modules. Make sure they're compatible with GKI. +CONFIG_LOG_BUF_SHIFT=22 +# CONFIG_MODULE_SIG_ALL is not set +CONFIG_CFG80211=m +CONFIG_NL80211_TESTMODE=y +# CONFIG_CFG80211_DEFAULT_PS is not set +# CONFIG_CFG80211_CRDA_SUPPORT is not set +CONFIG_MAC80211=m +CONFIG_EEPROM_AT24=m +CONFIG_CHR_DEV_SG=m +CONFIG_I2C_CHARDEV=m +CONFIG_SPI_SPIDEV=m +CONFIG_SOFT_WATCHDOG=m +CONFIG_ARM_DSU_PMU=m + +# private/google-modules/soc/gs/drivers/block/zram/Kconfig +CONFIG_ZRAM_GS=m +CONFIG_ZCOMP_CPU=m +CONFIG_ZCOMP_EH=m +CONFIG_ZRAM_GS_WRITEBACK=y + +# private/google-modules/soc/gs/drivers/bts/Kconfig +CONFIG_EXYNOS_BTS=m + +# private/google-modules/soc/gs/drivers/clk/gs/Kconfig +CONFIG_EXYNOS_GS_COMMON_CLK=m + +# private/google-modules/soc/gs/drivers/clocksource/Kconfig +CONFIG_CLKSRC_EXYNOS_MCT_GS=m + +# private/google-modules/soc/gs/drivers/cpufreq/Kconfig +CONFIG_ARM_EXYNOS_ACME=m + +# private/google-modules/soc/gs/drivers/devfreq-whi/google/Kconfig +CONFIG_ARM_EXYNOS_DEVFREQ=m +CONFIG_EXYNOS_ALT_DVFS=m + +# private/google-modules/soc/gs/drivers/dma-buf/heaps/Kconfig +CONFIG_DMABUF_SAMSUNG_HEAPS=m +CONFIG_DMABUF_HEAPS_SAMSUNG_CHUNK=y +CONFIG_DMABUF_HEAPS_SAMSUNG_CMA=y +CONFIG_DMABUF_HEAPS_SAMSUNG_CARVEOUT=y +CONFIG_DMABUF_HEAPS_SAMSUNG_SYSTEM=y + +# private/google-modules/soc/gs/drivers/dma/Kconfig +CONFIG_SAMSUNG_DMADEV=m + +# private/google-modules/soc/gs/drivers/i2c/busses/Kconfig +CONFIG_I2C_EXYNOS5_GS=m +CONFIG_I2C_ACPM=m + +# private/google-modules/soc/gs/drivers/iio/Kconfig +CONFIG_ODPM=m + +# private/google-modules/soc/gs/drivers/input/Kconfig +CONFIG_INPUT_KEYDEBUG=m +CONFIG_INPUT_STMVL53L1=m +CONFIG_GOODIX_FINGERPRINT=m +CONFIG_KEYBOARD_S2MPG12=m + +# private/google-modules/soc/gs/drivers/iommu/Kconfig +CONFIG_SAMSUNG_IOMMU=m +CONFIG_EXYNOS_PCIE_IOMMU=m +CONFIG_IOVAD_BEST_FIT_ALGO=m + +# private/google-modules/soc/gs/drivers/media/platform/Kconfig +CONFIG_VIDEO_EXYNOS_MFC=m +CONFIG_VIDEO_EXYNOS_SMFC=m + +# private/google-modules/soc/gs/drivers/mfd/Kconfig +CONFIG_MFD_S2MPG12=m +CONFIG_MFD_S2MPG13=m +CONFIG_MFD_S2MPG1X_GPIO=m +CONFIG_MFD_SLG51000=m +CONFIG_MFD_SLG51002=m + +# private/google-modules/soc/gs/drivers/misc/Kconfig +CONFIG_SUBSYSTEM_COREDUMP=m +CONFIG_SBB_MUX=m + +# private/google-modules/soc/gs/drivers/pci/controller/dwc-whi/Kconfig +CONFIG_PCI_EXYNOS_GS=m +CONFIG_PCI_EXYNOS_CAL_GS201=m + +# private/google-modules/soc/gs/drivers/performance/gs_perf_mon/Kconfig +CONFIG_GS_PERF_MON=m + +# private/google-modules/soc/gs/drivers/performance/lat_governors/Kconfig +CONFIG_GS_MEMLAT_GOVERNOR=m + +# private/google-modules/soc/gs/drivers/phy/Kconfig +CONFIG_PHY_EXYNOS_USBDRD=m +CONFIG_PHY_SAMSUNG_USB_GEN2_V4=y +CONFIG_PHY_EXYNOS_MIPI=m +CONFIG_PHY_EXYNOS_MIPI_DSIM=m + +# private/google-modules/soc/gs/drivers/pinctrl/Kconfig +CONFIG_PINCTRL_EXYNOS_GS=m +CONFIG_PINCTRL_SLG51000=m +CONFIG_PINCTRL_SLG51002=m + +# private/google-modules/soc/gs/drivers/power/Kconfig +CONFIG_DEBUG_REBOOT=m + +# private/google-modules/soc/gs/drivers/pwm/Kconfig +CONFIG_PWM_EXYNOS=m + +# private/google-modules/soc/gs/drivers/regulator/Kconfig +CONFIG_REGULATOR_S2MPG12=m +CONFIG_REGULATOR_S2MPG13=m +CONFIG_REGULATOR_SLG51000_GS=m +CONFIG_REGULATOR_SLG51002=m + +# private/google-modules/soc/gs/drivers/rtc/Kconfig +CONFIG_RTC_DRV_S2MPG12=m + +# private/google-modules/soc/gs/drivers/soc/google/Kconfig +CONFIG_SOC_GOOGLE=y +CONFIG_SOC_GS201=y +CONFIG_BOARD_CLOUDRIPPER=y +CONFIG_GS_CHIPID=m +CONFIG_EXYNOS_BCM_DBG=m +CONFIG_EXYNOS_BCM_DBG_PPMU=y +CONFIG_CAL_IF=m +CONFIG_EXYNOS_PMU_IF=m +CONFIG_EXYNOS_PD=m +CONFIG_EXYNOS_PD_DBG=m +CONFIG_EXYNOS_PM=m +CONFIG_EXYNOS_CPUPM=m +CONFIG_GS_ACPM=m +CONFIG_ACPM_FLEXPMU_DBG=m +CONFIG_ACPM_POWER_STATS=m +CONFIG_ACPM_MBOX_TEST=m +CONFIG_ACPM_DVFS=m +CONFIG_ECT=m +CONFIG_EXYNOS_DVFS_MANAGER=m +CONFIG_EXYNOS_PM_QOS=m +CONFIG_EXYNOS_CPUHP=m +CONFIG_SLC_PARTITION_MANAGER=m +CONFIG_GS_SLC_ACPM=m +CONFIG_SLC_PMON=y +CONFIG_PIXEL_STAT=m +CONFIG_EXYNOS_SECURE_LOG=m +CONFIG_EXYNOS_CONTENT_PATH_PROTECTION=m +CONFIG_GOOGLE_MODEMCTL=m +CONFIG_GSA=m +CONFIG_GSA_PKVM=m +CONFIG_GSA_GSC=m +CONFIG_DEBUG_SNAPSHOT=m +CONFIG_DEBUG_SNAPSHOT_DEBUG_KINFO=m +CONFIG_EXYNOS_EHLD=m +CONFIG_EXYNOS_DEBUG_TEST=m +CONFIG_PIXEL_DEBUG_TEST=m +CONFIG_EXYNOS_ITMON=m +CONFIG_EXYNOS_CORESIGHT=m +CONFIG_EXYNOS_ECC_HANDLER=m +CONFIG_EXYNOS_CORESIGHT_ETM=m +CONFIG_EXYNOS_CORESIGHT_ETF=y +CONFIG_EXYNOS_CORESIGHT_ETR=y +CONFIG_EXYNOS_ADV_TRACER=m +CONFIG_EXYNOS_ADV_TRACER_S2D=m +CONFIG_PIXEL_BOOT_METRICS=m +CONFIG_PIXEL_SUSPEND_DIAG=m +CONFIG_GS_SJTAG=m +CONFIG_ETM2DRAM=m +CONFIG_SMRA=m +CONFIG_VH_SYSTRACE=m +CONFIG_PIXEL_EM=m +CONFIG_PIXEL_METRICS=m +CONFIG_VH_FS=m +CONFIG_VH_MM=m +CONFIG_VH_CGROUP=m +CONFIG_VH_THERMAL=m +CONFIG_VH_SCHED=m +CONFIG_VH_SCHED_MAX_CPU_NR=8 +CONFIG_VH_PREEMPTIRQ_TRACEPOINTS=m +CONFIG_TICK_DRIVEN_LATGOV=y +CONFIG_HARDLOCKUP_DEBUG=m +CONFIG_HARDLOCKUP_WATCHDOG=m +CONFIG_DBGCORE_DUMP=m +CONFIG_SYSRQ_HOOK=m +CONFIG_PKVM_S2MPU=m +CONFIG_KERNEL_TOP=m + +# private/google-modules/soc/gs/drivers/spi/Kconfig +CONFIG_SPI_S3C64XX_GS=m + +# private/google-modules/soc/gs/drivers/thermal/Kconfig +CONFIG_GS_THERMAL_V3=m +CONFIG_EXYNOS_ACPM_THERMAL=m +CONFIG_EXYNOS_CPU_THERMAL=m +CONFIG_GPU_THERMAL=m +CONFIG_GSOC_PMIC_THERMAL=m + +# private/google-modules/soc/gs/drivers/tty/serial/Kconfig +CONFIG_SERIAL_EXYNOS=m + +# private/google-modules/soc/gs/drivers/ufs/Kconfig +CONFIG_SCSI_UFS_EXYNOS_GS=m +CONFIG_SCSI_UFS_CRYPTO_SW_KEYS_MODE=y +CONFIG_SCSI_UFS_PIXEL_FIPS140=m + +# private/google-modules/soc/gs/drivers/usb/Kconfig +CONFIG_USB_XHCI_EXYNOS=m +CONFIG_USB_DWC3_EXYNOS_GS=m +CONFIG_USB_CONFIGFS_F_DM=m +CONFIG_USB_CONFIGFS_F_ETR_MIU=m +CONFIG_TYPEC_COOLING_DEV=m +CONFIG_TYPEC_MAX77759=m +CONFIG_TYPEC_MAX77759_CONTAMINANT=m +CONFIG_TYPEC_MAX77779_CONTAMINANT=m + +# private/google-modules/soc/gs/drivers/video/Kconfig +CONFIG_EXYNOS_GRAPHICS_G2D=m + +# private/google-modules/soc/gs/drivers/video/backlight/Kconfig +CONFIG_BACKLIGHT_RT4539_GS=m + +# private/google-modules/soc/gs/drivers/watchdog/Kconfig +CONFIG_S3C2410_WATCHDOG_GS=m +CONFIG_S3C2410_SHUTDOWN_REBOOT=y + +# private/google-modules/bms/misc/Kconfig +CONFIG_GOOGLE_LOGBUFFER=m + +# private/google-modules/display/common/Kconfig +CONFIG_GS_DRM_PANEL_UNIFIED=m + +# private/google-modules/display/samsung/Kconfig +CONFIG_DRM_SAMSUNG=m +CONFIG_DRM_SAMSUNG_DP=y +CONFIG_DRM_SAMSUNG_DP_AUDIO=y + +# private/google-modules/display/samsung/panel/Kconfig +CONFIG_DRM_PANEL_GOOGLE_COMMON=m +CONFIG_DRM_PANEL_SAMSUNG_COMMON=m +CONFIG_DRM_PANEL_SAMSUNG_EMUL=m +CONFIG_DRM_PANEL_SAMSUNG_S6E3HC2=m +CONFIG_DRM_PANEL_SAMSUNG_S6E3FC3=m +CONFIG_DRM_PANEL_SAMSUNG_S6E3FC3_P10=m +CONFIG_DRM_PANEL_SAMSUNG_SOFEF01=m +CONFIG_DRM_PANEL_SAMSUNG_S6E3HC3=m +CONFIG_DRM_PANEL_SAMSUNG_S6E3HC3_C10=m +CONFIG_DRM_PANEL_SAMSUNG_S6E3HC4=m +CONFIG_DRM_PANEL_BOE_NT37290=m + +# private/google-modules/fingerprint/goodix/fps_touch_handler/Kconfig +CONFIG_FPS_TOUCH_HANDLER=m + +# private/google-modules/power/mitigation/Kconfig +CONFIG_GOOGLE_BCL=m + +# private/google-modules/power/reset/Kconfig +CONFIG_PIXEL_POWER_REBOOT=m + +# private/google-modules/trusty/drivers/trusty/Kconfig +CONFIG_TRUSTY=m +CONFIG_TRUSTY_DMA_BUF_FFA_TAG=y +CONFIG_TRUSTY_CRASH_IS_PANIC=y
diff --git a/insmod_cfg/init.insmod.cheetah.cfg b/insmod_cfg/init.insmod.cheetah.cfg new file mode 100644 index 0000000..b68c4c7 --- /dev/null +++ b/insmod_cfg/init.insmod.cheetah.cfg
@@ -0,0 +1,18 @@ +########################################################## +# init.insmod.cheetah.cfg # +# This file contains cheetah specific kernel modules # +# to load at init time by init.insmod.sh script # +########################################################## + +# Load device specific kernel modules +# Modules here will be loaded *after* all common modules +modprobe|bcmdhd4389.ko +modprobe|snd-soc-cs35l41-spi.ko +modprobe|syna_touch.ko +modprobe|cs40l26-i2c.ko +modprobe|snd-soc-cs40l26.ko + +# All device specific modules loaded +setprop|vendor.device.modules.ready +setprop|vendor.all.modules.ready +setprop|vendor.all.devices.ready
diff --git a/insmod_cfg/init.insmod.felix.cfg b/insmod_cfg/init.insmod.felix.cfg new file mode 100644 index 0000000..ce1274e --- /dev/null +++ b/insmod_cfg/init.insmod.felix.cfg
@@ -0,0 +1,19 @@ +########################################################## +# init.insmod.felix.cfg # +# This file contains felix specific kernel modules # +# to load at init time by init.insmod.sh script # + +# Load device specific kernel modules +# Modules here will be loaded *after* all common modules +modprobe|bcmdhd4389.ko +modprobe|snd-soc-cs35l41-i2c.ko +modprobe|fst2.ko +modprobe|ftm5.ko +modprobe|cs40l26-i2c.ko +modprobe|snd-soc-cs40l26.ko +modprobe|fpc1020_platform_tee.ko + +# All device specific modules loaded +setprop|vendor.device.modules.ready +setprop|vendor.all.modules.ready +setprop|vendor.all.devices.ready
diff --git a/insmod_cfg/init.insmod.lynx.cfg b/insmod_cfg/init.insmod.lynx.cfg new file mode 100644 index 0000000..f9a54de --- /dev/null +++ b/insmod_cfg/init.insmod.lynx.cfg
@@ -0,0 +1,23 @@ +########################################################## +# init.insmod.lynx.cfg # +# This file contains lynx specific kernel modules # +# to load at init time by init.insmod.sh script # +########################################################## + +# Load device specific kernel modules +# Modules here will be loaded *after* all common modules +modprobe|snd-soc-cs35l41-spi.ko +modprobe|goodix_brl_touch.ko +modprobe|focal_touch.ko +modprobe|cl_dsp.ko +modprobe|input-cs40l26-i2c.ko +modprobe|snd-soc-cs40l26.ko + +modprobe|wlan.ko +modprobe|google_wlan_mac.ko +modprobe|btpower.ko + +# All device specific modules loaded +setprop|vendor.device.modules.ready +setprop|vendor.all.modules.ready +setprop|vendor.all.devices.ready
diff --git a/insmod_cfg/init.insmod.panther.cfg b/insmod_cfg/init.insmod.panther.cfg new file mode 100644 index 0000000..56b6c68 --- /dev/null +++ b/insmod_cfg/init.insmod.panther.cfg
@@ -0,0 +1,18 @@ +########################################################## +# init.insmod.panther.cfg # +# This file contains panther specific kernel modules # +# to load at init time by init.insmod.sh script # +########################################################## + +# Load device specific kernel modules +# Modules here will be loaded *after* all common modules +modprobe|bcmdhd4389.ko +modprobe|snd-soc-cs35l41-spi.ko +modprobe|focal_touch.ko +modprobe|cs40l26-i2c.ko +modprobe|snd-soc-cs40l26.ko + +# All device specific modules loaded +setprop|vendor.device.modules.ready +setprop|vendor.all.modules.ready +setprop|vendor.all.devices.ready
diff --git a/insmod_cfg/init.insmod.tangorpro.cfg b/insmod_cfg/init.insmod.tangorpro.cfg new file mode 100644 index 0000000..4f43832 --- /dev/null +++ b/insmod_cfg/init.insmod.tangorpro.cfg
@@ -0,0 +1,18 @@ +########################################################## +# init.insmod.tangorpro.cfg # +# This file contains tangorpro specific kernel modules # +# to load at init time by init.insmod.sh script # +########################################################## + +# Load device specific kernel modules +# Modules here will be loaded *after* all common modules +modprobe|synadhd.ko +modprobe|snd-soc-cs35l41-spi.ko +modprobe|goog_usi_stylus.ko +modprobe|nvt_touch.ko +modprobe|fpc1020_platform_tee.ko + +# All device specific modules loaded +setprop|vendor.device.modules.ready +setprop|vendor.all.modules.ready +setprop|vendor.all.devices.ready
diff --git a/system_dlkm.props.gs201 b/system_dlkm.props.gs201 new file mode 100644 index 0000000..dfc4e19 --- /dev/null +++ b/system_dlkm.props.gs201
@@ -0,0 +1,9 @@ +fs_type=ext4 +use_dynamic_partition_size=true +ext_mkuserimg=mkuserimg_mke2fs +ext4_share_dup_blocks=true +extfs_rsv_pct=0 +journal_size=0 +partition_name=system_dlkm +mount_point=system_dlkm +selinux_fc=private/devices/google/common/sepolicy/system_dlkm_file_contexts
diff --git a/vendor_dlkm.blocklist.devices b/vendor_dlkm.blocklist.devices new file mode 100644 index 0000000..d94625f --- /dev/null +++ b/vendor_dlkm.blocklist.devices
@@ -0,0 +1,34 @@ +# WiFi, BT drivers; loaded per-device via insmod.sh +blocklist bcmdhd4389 +blocklist mhi +blocklist qmi_helpers +blocklist qrtr +blocklist qrtr_mhi +blocklist btpower + +# Only needed on lynx +blocklist cs40l26_i2c +blocklist goodix_brl_touch + +# Only needed on felix +blocklist ftm5 + +# Not needed for anyone? +blocklist sec_touch + +# Only needed on some pantah +blocklist syna_touch + +# Only needed on felix +blocklist fst2 + +# Only needed on tangorpro +blocklist goog_usi_stylus +blocklist nvt_touch +blocklist synadhd + +# Only needed on lynx, panther +blocklist focal_touch + +# Only needed on tangorpro, felix +blocklist fpc1020_platform_tee
diff --git a/vendor_dlkm.blocklist.gs201 b/vendor_dlkm.blocklist.gs201 new file mode 100644 index 0000000..f921afc --- /dev/null +++ b/vendor_dlkm.blocklist.gs201
@@ -0,0 +1,6 @@ +blocklist aoc_unit_test_dev +blocklist mali_kutf +blocklist mali_kutf_clk_rate_trace_test_portal +blocklist rt4539_bl +blocklist sscoredump_sample_test.ko +blocklist sscoredump_test.ko
diff --git a/vendor_dlkm.props.gs201 b/vendor_dlkm.props.gs201 new file mode 100644 index 0000000..19270e6 --- /dev/null +++ b/vendor_dlkm.props.gs201
@@ -0,0 +1,9 @@ +fs_type=ext4 +use_dynamic_partition_size=true +ext_mkuserimg=mkuserimg_mke2fs +ext4_share_dup_blocks=true +extfs_rsv_pct=0 +journal_size=0 +partition_name=vendor_dlkm +mount_point=vendor_dlkm +selinux_fc=private/devices/google/common/sepolicy/vendor_dlkm_file_contexts
diff --git a/vendor_ramdisk.modules.devices b/vendor_ramdisk.modules.devices new file mode 100644 index 0000000..b565d7f --- /dev/null +++ b/vendor_ramdisk.modules.devices
@@ -0,0 +1,40 @@ +extra/private/devices/google/felix/display/panel-samsung-ana6707-f10.ko +extra/private/devices/google/felix/display/panel-samsung-ea8182-f10.ko +extra/private/devices/google/lynx/display/panel-samsung-s6e3fc3-l10.ko +extra/private/devices/google/lynx/display/panel-samsung-s6e3fc5.ko +extra/private/devices/google/tangorpro/display/panel-boe-ts110f5mlg0.ko +extra/private/devices/google/tangorpro/display/panel-csot-ppa957db2d.ko +extra/private/devices/google/tangorpro/pogo/pogo_transport.ko +extra/private/google-modules/amplifiers/cs35l41/snd-soc-cs35l41.ko +extra/private/google-modules/amplifiers/cs35l41/snd-soc-cs35l41-spi.ko +extra/private/google-modules/amplifiers/cs35l45/cs35l45-cs-dsp.ko +extra/private/google-modules/amplifiers/cs35l45/snd-soc-cs35l45.ko +extra/private/google-modules/amplifiers/cs35l45/snd-soc-cs35l45-spi.ko +extra/private/google-modules/amplifiers/cs35l45/snd-soc-cs35l45-wm-adsp.ko +extra/private/google-modules/amplifiers/snd_soc_wm_adsp/snd-soc-wm-adsp.ko +extra/private/google-modules/bms/google_dock.ko +extra/private/google-modules/display/samsung/panel/panel-boe-nt37290.ko +extra/private/google-modules/display/samsung/panel/panel-samsung-s6e3fc3.ko +extra/private/google-modules/display/samsung/panel/panel-samsung-s6e3fc3-p10.ko +extra/private/google-modules/display/samsung/panel/panel-samsung-s6e3hc2.ko +extra/private/google-modules/display/samsung/panel/panel-samsung-s6e3hc3-c10.ko +extra/private/google-modules/display/samsung/panel/panel-samsung-s6e3hc3.ko +extra/private/google-modules/display/samsung/panel/panel-samsung-s6e3hc4.ko +extra/private/google-modules/display/samsung/panel/panel-samsung-sofef01.ko +extra/private/google-modules/gps/broadcom/bcm47765/bcm47765.ko +extra/private/google-modules/nfc/ese/st33spi.ko +extra/private/google-modules/nfc/ese/st54spi.ko +extra/private/google-modules/nfc/st21nfc.ko +extra/private/google-modules/radio/samsung/s5300/cpif.ko +extra/private/google-modules/radio/samsung/s5300/cpif_page.ko +extra/private/google-modules/radio/samsung/s5300/cp_thermal_zone.ko +extra/private/google-modules/radio/samsung/s5300/shm_ipc.ko +extra/private/google-modules/sensors/hall_sensor/hall_sensor.ko +extra/private/google-modules/soc/gs/drivers/video/backlight/rt4539_bl.ko +extra/private/google-modules/touch/common/heatmap.ko +extra/private/google-modules/touch/common/touch_bus_negotiator.ko +extra/private/google-modules/touch/common/touch_offload.ko +kernel/drivers/leds/leds-pwm.ko +kernel/drivers/regulator/rt4801-regulator.ko +kernel/drivers/regulator/tps65132-regulator.ko +kernel/drivers/video/backlight/lp855x_bl.ko
diff --git a/vendor_ramdisk.modules.gs201 b/vendor_ramdisk.modules.gs201 new file mode 100644 index 0000000..b1dff89 --- /dev/null +++ b/vendor_ramdisk.modules.gs201
@@ -0,0 +1,177 @@ +kernel/mm/zsmalloc.ko +kernel/drivers/gpu/drm/display/drm_display_helper.ko +kernel/drivers/misc/eeprom/at24.ko +kernel/drivers/scsi/sg.ko +kernel/drivers/spi/spidev.ko +kernel/drivers/i2c/i2c-dev.ko +kernel/drivers/watchdog/softdog.ko +kernel/drivers/perf/arm_dsu_pmu.ko +extra/private/google-modules/soc/gs/drivers/phy/samsung/phy-exynos-usbdrd-super.ko +extra/private/google-modules/soc/gs/drivers/phy/samsung/phy-exynos-mipi-dsim.ko +extra/private/google-modules/soc/gs/drivers/phy/samsung/phy-exynos-mipi.ko +extra/private/google-modules/soc/gs/drivers/pinctrl/gs/pinctrl-exynos-gs.ko +extra/private/google-modules/soc/gs/drivers/pci/controller/dwc-whi/pcie-exynos-gs.ko +extra/private/google-modules/soc/gs/drivers/pci/controller/dwc-whi/pcie-exynos-gs201-rc-cal.ko +extra/private/google-modules/soc/gs/drivers/clk/gs/clk_exynos_gs.ko +extra/private/google-modules/soc/gs/drivers/dma/pl330.ko +extra/private/google-modules/soc/gs/drivers/dma/samsung-dma.ko +extra/private/google-modules/soc/gs/drivers/soc/google/debug/dss.ko +extra/private/google-modules/soc/gs/drivers/soc/google/debug/debug-snapshot-debug-kinfo.ko +extra/private/google-modules/soc/gs/drivers/soc/google/debug/ehld.ko +extra/private/google-modules/soc/gs/drivers/soc/google/debug/exynos-debug-test.ko +extra/private/google-modules/soc/gs/drivers/soc/google/debug/pixel-debug-test.ko +extra/private/google-modules/soc/gs/drivers/soc/google/debug/itmon.ko +extra/private/google-modules/soc/gs/drivers/soc/google/debug/exynos-coresight.ko +extra/private/google-modules/soc/gs/drivers/soc/google/debug/exynos-ecc-handler.ko +extra/private/google-modules/soc/gs/drivers/soc/google/debug/exynos-coresight-etm.ko +extra/private/google-modules/soc/gs/drivers/soc/google/debug/exynos-adv-tracer.ko +extra/private/google-modules/soc/gs/drivers/soc/google/debug/exynos-adv-tracer-s2d.ko +extra/private/google-modules/soc/gs/drivers/soc/google/debug/pixel-boot-metrics.ko +extra/private/google-modules/soc/gs/drivers/soc/google/debug/pixel-suspend-diag.ko +extra/private/google-modules/soc/gs/drivers/soc/google/debug/sjtag-driver.ko +extra/private/google-modules/soc/gs/drivers/soc/google/debug/etm2dram.ko +extra/private/google-modules/soc/gs/drivers/soc/google/vh/kernel/sched/vh_sched.ko +extra/private/google-modules/soc/gs/drivers/soc/google/vh/kernel/sched/sched_tp.ko +extra/private/google-modules/soc/gs/drivers/soc/google/vh/kernel/sched/vh_preemptirq_long.ko +extra/private/google-modules/soc/gs/drivers/soc/google/vh/kernel/systrace.ko +extra/private/google-modules/soc/gs/drivers/soc/google/vh/kernel/fs/vh_fs.ko +extra/private/google-modules/soc/gs/drivers/soc/google/vh/kernel/mm/vh_mm.ko +extra/private/google-modules/soc/gs/drivers/soc/google/vh/kernel/cgroup/vh_cgroup.ko +extra/private/google-modules/soc/gs/drivers/soc/google/vh/kernel/pixel_em/pixel_em.ko +extra/private/google-modules/soc/gs/drivers/soc/google/vh/kernel/thermal/vh_thermal.ko +extra/private/google-modules/soc/gs/drivers/soc/google/vh/kernel/metrics/pixel_metrics.ko +extra/private/google-modules/soc/gs/drivers/soc/google/gs-chipid.ko +extra/private/google-modules/soc/gs/drivers/soc/google/cal-if/cmupmucal.ko +extra/private/google-modules/soc/gs/drivers/soc/google/exynos-pmu-if.ko +extra/private/google-modules/soc/gs/drivers/soc/google/exynos-cpuhp.ko +extra/private/google-modules/soc/gs/drivers/soc/google/exynos-pd.ko +extra/private/google-modules/soc/gs/drivers/soc/google/exynos-pd-dbg.ko +extra/private/google-modules/soc/gs/drivers/soc/google/exynos-pd_el3.ko +extra/private/google-modules/soc/gs/drivers/soc/google/exynos-pd_hsi0.ko +extra/private/google-modules/soc/gs/drivers/soc/google/exynos-pm.ko +extra/private/google-modules/soc/gs/drivers/soc/google/exynos-cpupm.ko +extra/private/google-modules/soc/gs/drivers/soc/google/ect_parser.ko +extra/private/google-modules/soc/gs/drivers/soc/google/acpm/gs_acpm.ko +extra/private/google-modules/soc/gs/drivers/soc/google/acpm/acpm_flexpmu_dbg.ko +extra/private/google-modules/soc/gs/drivers/soc/google/acpm/power_stats.ko +extra/private/google-modules/soc/gs/drivers/soc/google/acpm/acpm_mbox_test.ko +extra/private/google-modules/soc/gs/drivers/soc/google/exynos-dm.ko +extra/private/google-modules/soc/gs/drivers/soc/google/exynos_pm_qos.ko +extra/private/google-modules/soc/gs/drivers/soc/google/modemctl/google_modemctl.ko +extra/private/google-modules/soc/gs/drivers/soc/google/pt/slc_pt.ko +extra/private/google-modules/soc/gs/drivers/soc/google/pt/slc_dummy.ko +extra/private/google-modules/soc/gs/drivers/soc/google/pt/slc_acpm.ko +extra/private/google-modules/soc/gs/drivers/soc/google/pt/slc_pmon.ko +extra/private/google-modules/soc/gs/drivers/soc/google/gsa/gsa.ko +extra/private/google-modules/soc/gs/drivers/soc/google/gsa/gsa_gsc.ko +extra/private/google-modules/soc/gs/drivers/soc/google/bcm_dbg.ko +extra/private/google-modules/soc/gs/drivers/soc/google/exynos-bcm_dbg-dump.ko +extra/private/google-modules/soc/gs/drivers/soc/google/eh/eh.ko +extra/private/google-modules/soc/gs/drivers/soc/google/hardlockup-debug.ko +extra/private/google-modules/soc/gs/drivers/soc/google/hardlockup-watchdog.ko +extra/private/google-modules/soc/gs/drivers/soc/google/sysrq-hook.ko +extra/private/google-modules/soc/gs/drivers/soc/google/pixel_stat/pixel_stat_sysfs.ko +extra/private/google-modules/soc/gs/drivers/soc/google/pixel_stat/mm/pixel_stat_mm.ko +extra/private/google-modules/soc/gs/drivers/soc/google/dbgcore-dump.ko +extra/private/google-modules/soc/gs/drivers/soc/google/exynos-seclog.ko +extra/private/google-modules/soc/gs/drivers/soc/google/pkvm-s2mpu/pkvm-s2mpu/pkvm-s2mpu.ko +extra/private/google-modules/soc/gs/drivers/soc/google/kernel-top.ko +extra/private/google-modules/soc/gs/drivers/regulator/pmic_class.ko +extra/private/google-modules/soc/gs/drivers/regulator/s2mpg12-regulator.ko +extra/private/google-modules/soc/gs/drivers/regulator/s2mpg12-powermeter.ko +extra/private/google-modules/soc/gs/drivers/regulator/s2mpg13-regulator.ko +extra/private/google-modules/soc/gs/drivers/regulator/s2mpg13-powermeter.ko +extra/private/google-modules/soc/gs/drivers/tty/serial/exynos_tty.ko +extra/private/google-modules/soc/gs/drivers/iommu/samsung_iommu.ko +extra/private/google-modules/soc/gs/drivers/iommu/samsung-iommu-group.ko +extra/private/google-modules/soc/gs/drivers/iommu/samsung-secure-iova.ko +extra/private/google-modules/soc/gs/drivers/iommu/exynos-pcie-iommu.ko +extra/private/google-modules/soc/gs/drivers/gpu/exynos/g2d/g2d.ko +extra/private/google-modules/soc/gs/drivers/misc/sbb-mux/sbb-mux.ko +extra/private/google-modules/soc/gs/drivers/misc/sscoredump/sscoredump.ko +extra/private/google-modules/soc/gs/drivers/mfd/s2mpg1x-gpio.ko +extra/private/google-modules/soc/gs/drivers/mfd/s2mpg12-mfd.ko +extra/private/google-modules/soc/gs/drivers/mfd/s2mpg13-mfd.ko +extra/private/google-modules/soc/gs/drivers/dma-buf/heaps/samsung/samsung_dma_heap.ko +extra/private/google-modules/soc/gs/drivers/ufs/ufs-exynos-gs.ko +extra/private/google-modules/soc/gs/drivers/ufs/ufs-pixel-fips140.ko +extra/private/google-modules/soc/gs/drivers/spi/spi-s3c64xx.ko +extra/private/google-modules/soc/gs/drivers/usb/dwc3/dwc3-exynos-usb.ko +extra/private/google-modules/soc/gs/drivers/usb/host/xhci-exynos.ko +extra/private/google-modules/soc/gs/drivers/usb/gadget/function/usb_f_dm.ko +extra/private/google-modules/soc/gs/drivers/usb/gadget/function/usb_f_dm1.ko +extra/private/google-modules/soc/gs/drivers/usb/typec/tcpm/google/google_tcpci_shim.ko +extra/private/google-modules/soc/gs/drivers/usb/typec/tcpm/google/usb_psy.ko +extra/private/google-modules/soc/gs/drivers/usb/typec/tcpm/google/tcpci_max77759.ko +extra/private/google-modules/soc/gs/drivers/usb/typec/tcpm/google/max77759_helper.ko +extra/private/google-modules/soc/gs/drivers/usb/typec/tcpm/google/bc_max77759.ko +extra/private/google-modules/soc/gs/drivers/usb/typec/tcpm/google/max777x9_contaminant.ko +extra/private/google-modules/soc/gs/drivers/usb/typec/tcpm/google/max77759_contaminant.ko +extra/private/google-modules/soc/gs/drivers/usb/typec/tcpm/google/max77779_contaminant.ko +extra/private/google-modules/soc/gs/drivers/usb/typec/tcpm/google/usbc_cooling_dev.ko +extra/private/google-modules/soc/gs/drivers/input/keyboard/s2mpg12-key.ko +extra/private/google-modules/soc/gs/drivers/input/fingerprint/goodixfp.ko +extra/private/google-modules/soc/gs/drivers/input/keycombo.ko +extra/private/google-modules/soc/gs/drivers/input/keydebug.ko +extra/private/google-modules/soc/gs/drivers/rtc/rtc-s2mpg12.ko +extra/private/google-modules/soc/gs/drivers/i2c/busses/i2c-exynos5.ko +extra/private/google-modules/soc/gs/drivers/i2c/busses/i2c-acpm.ko +extra/private/google-modules/soc/gs/drivers/media/platform/exynos/mfc/exynos_mfc.ko +extra/private/google-modules/soc/gs/drivers/media/platform/exynos/smfc/smfc.ko +extra/private/google-modules/soc/gs/drivers/power/reset/debug-reboot.ko +extra/private/google-modules/soc/gs/drivers/thermal/samsung/gs_thermal.ko +extra/private/google-modules/soc/gs/drivers/thermal/samsung/gpu_cooling.ko +extra/private/google-modules/soc/gs/drivers/thermal/google/s2mpg13_spmic_thermal.ko +extra/private/google-modules/soc/gs/drivers/watchdog/s3c2410_wdt.ko +extra/private/google-modules/soc/gs/drivers/cpufreq/exynos-acme.ko +extra/private/google-modules/soc/gs/drivers/clocksource/exynos_mct.ko +extra/private/google-modules/soc/gs/drivers/devfreq-whi/google/exynos_devfreq.ko +extra/private/google-modules/soc/gs/drivers/performance/gs_perf_mon/gs_perf_mon.ko +extra/private/google-modules/soc/gs/drivers/performance/lat_governors/gs_governor_memlat.ko +extra/private/google-modules/soc/gs/drivers/performance/lat_governors/gs_governor_utils.ko +extra/private/google-modules/soc/gs/drivers/bts/bts.ko +extra/private/google-modules/soc/gs/drivers/block/zram/zram_gs.ko +extra/private/google-modules/soc/gs/drivers/block/zram/zcomp_cpu.ko +extra/private/google-modules/soc/gs/drivers/block/zram/zcomp_eh.ko +extra/private/google-modules/amplifiers/audiometrics/audiometrics.ko +extra/private/google-modules/aoc/mailbox-wc.ko +extra/private/google-modules/aoc/aoc_core.ko +extra/private/google-modules/aoc/aoc_char_dev.ko +extra/private/google-modules/aoc/aoc_control_dev.ko +extra/private/google-modules/aoc/aoc_channel_dev.ko +extra/private/google-modules/aoc/aoc_uwb_platform_drv.ko +extra/private/google-modules/aoc/aoc_uwb_service_dev.ko +extra/private/google-modules/aoc/aoc_tbn_service_dev.ko +extra/private/google-modules/aoc/alsa/aoc_alsa_dev.ko +extra/private/google-modules/aoc/alsa/aoc_alsa_dev_util.ko +extra/private/google-modules/aoc/usb/aoc_usb_driver.ko +extra/private/google-modules/bms/google-bms.ko +extra/private/google-modules/bms/google-battery.ko +extra/private/google-modules/bms/google-charger.ko +extra/private/google-modules/bms/google_dual_batt_gauge.ko +extra/private/google-modules/bms/google-cpm.ko +extra/private/google-modules/bms/max77729-pmic.ko +extra/private/google-modules/bms/max77729_uic.ko +extra/private/google-modules/bms/max77729_charger.ko +extra/private/google-modules/bms/max77759-charger.ko +extra/private/google-modules/bms/max77779-charger.ko +extra/private/google-modules/bms/p9221.ko +extra/private/google-modules/bms/pca9468.ko +extra/private/google-modules/bms/max1720x-battery.ko +extra/private/google-modules/bms/max77779-fg.ko +extra/private/google-modules/bms/max20339.ko +extra/private/google-modules/bms/max77779_pmic.ko +extra/private/google-modules/bms/misc/gvotable.ko +extra/private/google-modules/bms/misc/logbuffer.ko +extra/private/google-modules/display/common/gs_drm/gs-drm-connector.ko +extra/private/google-modules/display/samsung/panel/panel-samsung-drv.ko +extra/private/google-modules/display/samsung/panel/panel-samsung-emul.ko +extra/private/google-modules/display/samsung/exynos-drm.ko +extra/private/google-modules/display/samsung/exynos-drm-audio.ko +extra/private/google-modules/power/mitigation/google_bcl.ko +extra/private/google-modules/power/reset/pixel-reboot.ko +extra/private/google-modules/trusty/drivers/trusty/trusty-core.ko +extra/private/google-modules/trusty/drivers/trusty/trusty-log.ko +extra/private/google-modules/trusty/drivers/trusty/trusty-test.ko +extra/private/google-modules/trusty/drivers/trusty/trusty-virtio.ko +extra/private/google-modules/trusty/drivers/trusty/trusty-ipc.ko