blob: 0b61548d569bc11acf976a9db71c846242e683aa [file] [log] [blame]
/*
* OMAP3 Legacy clock data
*
* Copyright (C) 2014 Texas Instruments, Inc
* Tero Kristo (t-kristo@ti.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
#include "clock.h"
static struct ti_clk_fixed virt_12m_ck_data = {
.frequency = 12000000,
};
static struct ti_clk virt_12m_ck = {
.name = "virt_12m_ck",
.type = TI_CLK_FIXED,
.data = &virt_12m_ck_data,
};
static struct ti_clk_fixed virt_13m_ck_data = {
.frequency = 13000000,
};
static struct ti_clk virt_13m_ck = {
.name = "virt_13m_ck",
.type = TI_CLK_FIXED,
.data = &virt_13m_ck_data,
};
static struct ti_clk_fixed virt_19200000_ck_data = {
.frequency = 19200000,
};
static struct ti_clk virt_19200000_ck = {
.name = "virt_19200000_ck",
.type = TI_CLK_FIXED,
.data = &virt_19200000_ck_data,
};
static struct ti_clk_fixed virt_26000000_ck_data = {
.frequency = 26000000,
};
static struct ti_clk virt_26000000_ck = {
.name = "virt_26000000_ck",
.type = TI_CLK_FIXED,
.data = &virt_26000000_ck_data,
};
static struct ti_clk_fixed virt_38_4m_ck_data = {
.frequency = 38400000,
};
static struct ti_clk virt_38_4m_ck = {
.name = "virt_38_4m_ck",
.type = TI_CLK_FIXED,
.data = &virt_38_4m_ck_data,
};
static struct ti_clk_fixed virt_16_8m_ck_data = {
.frequency = 16800000,
};
static struct ti_clk virt_16_8m_ck = {
.name = "virt_16_8m_ck",
.type = TI_CLK_FIXED,
.data = &virt_16_8m_ck_data,
};
static const char *osc_sys_ck_parents[] = {
"virt_12m_ck",
"virt_13m_ck",
"virt_19200000_ck",
"virt_26000000_ck",
"virt_38_4m_ck",
"virt_16_8m_ck",
};
static struct ti_clk_mux osc_sys_ck_data = {
.num_parents = ARRAY_SIZE(osc_sys_ck_parents),
.reg = 0xd40,
.module = TI_CLKM_PRM,
.parents = osc_sys_ck_parents,
};
static struct ti_clk osc_sys_ck = {
.name = "osc_sys_ck",
.type = TI_CLK_MUX,
.data = &osc_sys_ck_data,
};
static struct ti_clk_divider sys_ck_data = {
.parent = "osc_sys_ck",
.bit_shift = 6,
.max_div = 3,
.reg = 0x1270,
.module = TI_CLKM_PRM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk sys_ck = {
.name = "sys_ck",
.type = TI_CLK_DIVIDER,
.data = &sys_ck_data,
};
static const char *dpll3_ck_parents[] = {
"sys_ck",
"sys_ck",
};
static struct ti_clk_dpll dpll3_ck_data = {
.num_parents = ARRAY_SIZE(dpll3_ck_parents),
.control_reg = 0xd00,
.idlest_reg = 0xd20,
.mult_div1_reg = 0xd40,
.autoidle_reg = 0xd30,
.module = TI_CLKM_CM,
.parents = dpll3_ck_parents,
.flags = CLKF_CORE,
.freqsel_mask = 0xf0,
.div1_mask = 0x7f00,
.idlest_mask = 0x1,
.auto_recal_bit = 0x3,
.max_divider = 0x80,
.min_divider = 0x1,
.recal_en_bit = 0x5,
.max_multiplier = 0x7ff,
.enable_mask = 0x7,
.mult_mask = 0x7ff0000,
.recal_st_bit = 0x5,
.autoidle_mask = 0x7,
};
static struct ti_clk dpll3_ck = {
.name = "dpll3_ck",
.clkdm_name = "dpll3_clkdm",
.type = TI_CLK_DPLL,
.data = &dpll3_ck_data,
};
static struct ti_clk_divider dpll3_m2_ck_data = {
.parent = "dpll3_ck",
.bit_shift = 27,
.max_div = 31,
.reg = 0xd40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll3_m2_ck = {
.name = "dpll3_m2_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll3_m2_ck_data,
};
static struct ti_clk_fixed_factor core_ck_data = {
.parent = "dpll3_m2_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk core_ck = {
.name = "core_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_ck_data,
};
static struct ti_clk_divider l3_ick_data = {
.parent = "core_ck",
.max_div = 3,
.reg = 0xa40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk l3_ick = {
.name = "l3_ick",
.type = TI_CLK_DIVIDER,
.data = &l3_ick_data,
};
static struct ti_clk_fixed_factor security_l3_ick_data = {
.parent = "l3_ick",
.div = 1,
.mult = 1,
};
static struct ti_clk security_l3_ick = {
.name = "security_l3_ick",
.type = TI_CLK_FIXED_FACTOR,
.data = &security_l3_ick_data,
};
static struct ti_clk_fixed_factor wkup_l4_ick_data = {
.parent = "sys_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk wkup_l4_ick = {
.name = "wkup_l4_ick",
.type = TI_CLK_FIXED_FACTOR,
.data = &wkup_l4_ick_data,
};
static struct ti_clk_gate usim_ick_data = {
.parent = "wkup_l4_ick",
.bit_shift = 9,
.reg = 0xc10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk usim_ick = {
.name = "usim_ick",
.clkdm_name = "wkup_clkdm",
.type = TI_CLK_GATE,
.data = &usim_ick_data,
};
static struct ti_clk_gate dss2_alwon_fck_data = {
.parent = "sys_ck",
.bit_shift = 1,
.reg = 0xe00,
.module = TI_CLKM_CM,
};
static struct ti_clk dss2_alwon_fck = {
.name = "dss2_alwon_fck",
.clkdm_name = "dss_clkdm",
.type = TI_CLK_GATE,
.data = &dss2_alwon_fck_data,
};
static struct ti_clk_divider l4_ick_data = {
.parent = "l3_ick",
.bit_shift = 2,
.max_div = 3,
.reg = 0xa40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk l4_ick = {
.name = "l4_ick",
.type = TI_CLK_DIVIDER,
.data = &l4_ick_data,
};
static struct ti_clk_fixed_factor core_l4_ick_data = {
.parent = "l4_ick",
.div = 1,
.mult = 1,
};
static struct ti_clk core_l4_ick = {
.name = "core_l4_ick",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_l4_ick_data,
};
static struct ti_clk_gate mmchs2_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 25,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mmchs2_ick = {
.name = "mmchs2_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mmchs2_ick_data,
};
static const char *dpll4_ck_parents[] = {
"sys_ck",
"sys_ck",
};
static struct ti_clk_dpll dpll4_ck_data = {
.num_parents = ARRAY_SIZE(dpll4_ck_parents),
.control_reg = 0xd00,
.idlest_reg = 0xd20,
.mult_div1_reg = 0xd44,
.autoidle_reg = 0xd30,
.module = TI_CLKM_CM,
.parents = dpll4_ck_parents,
.flags = CLKF_PER,
.freqsel_mask = 0xf00000,
.modes = 0x82,
.div1_mask = 0x7f,
.idlest_mask = 0x2,
.auto_recal_bit = 0x13,
.max_divider = 0x80,
.min_divider = 0x1,
.recal_en_bit = 0x6,
.max_multiplier = 0x7ff,
.enable_mask = 0x70000,
.mult_mask = 0x7ff00,
.recal_st_bit = 0x6,
.autoidle_mask = 0x38,
};
static struct ti_clk dpll4_ck = {
.name = "dpll4_ck",
.clkdm_name = "dpll4_clkdm",
.type = TI_CLK_DPLL,
.data = &dpll4_ck_data,
};
static struct ti_clk_divider dpll4_m2_ck_data = {
.parent = "dpll4_ck",
.max_div = 63,
.reg = 0xd48,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll4_m2_ck = {
.name = "dpll4_m2_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll4_m2_ck_data,
};
static struct ti_clk_fixed_factor dpll4_m2x2_mul_ck_data = {
.parent = "dpll4_m2_ck",
.div = 1,
.mult = 2,
};
static struct ti_clk dpll4_m2x2_mul_ck = {
.name = "dpll4_m2x2_mul_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll4_m2x2_mul_ck_data,
};
static struct ti_clk_gate dpll4_m2x2_ck_data = {
.parent = "dpll4_m2x2_mul_ck",
.bit_shift = 0x1b,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll4_m2x2_ck = {
.name = "dpll4_m2x2_ck",
.type = TI_CLK_GATE,
.data = &dpll4_m2x2_ck_data,
};
static struct ti_clk_fixed_factor omap_96m_alwon_fck_data = {
.parent = "dpll4_m2x2_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk omap_96m_alwon_fck = {
.name = "omap_96m_alwon_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &omap_96m_alwon_fck_data,
};
static struct ti_clk_fixed_factor cm_96m_fck_data = {
.parent = "omap_96m_alwon_fck",
.div = 1,
.mult = 1,
};
static struct ti_clk cm_96m_fck = {
.name = "cm_96m_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &cm_96m_fck_data,
};
static const char *omap_96m_fck_parents[] = {
"cm_96m_fck",
"sys_ck",
};
static struct ti_clk_mux omap_96m_fck_data = {
.bit_shift = 6,
.num_parents = ARRAY_SIZE(omap_96m_fck_parents),
.reg = 0xd40,
.module = TI_CLKM_CM,
.parents = omap_96m_fck_parents,
};
static struct ti_clk omap_96m_fck = {
.name = "omap_96m_fck",
.type = TI_CLK_MUX,
.data = &omap_96m_fck_data,
};
static struct ti_clk_fixed_factor core_96m_fck_data = {
.parent = "omap_96m_fck",
.div = 1,
.mult = 1,
};
static struct ti_clk core_96m_fck = {
.name = "core_96m_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_96m_fck_data,
};
static struct ti_clk_gate mspro_fck_data = {
.parent = "core_96m_fck",
.bit_shift = 23,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk mspro_fck = {
.name = "mspro_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mspro_fck_data,
};
static struct ti_clk_gate dss_ick_3430es2_data = {
.parent = "l4_ick",
.bit_shift = 0,
.reg = 0xe10,
.module = TI_CLKM_CM,
.flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk dss_ick_3430es2 = {
.name = "dss_ick",
.clkdm_name = "dss_clkdm",
.type = TI_CLK_GATE,
.data = &dss_ick_3430es2_data,
};
static struct ti_clk_gate uart4_ick_am35xx_data = {
.parent = "core_l4_ick",
.bit_shift = 23,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk uart4_ick_am35xx = {
.name = "uart4_ick_am35xx",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &uart4_ick_am35xx_data,
};
static struct ti_clk_fixed_factor security_l4_ick2_data = {
.parent = "l4_ick",
.div = 1,
.mult = 1,
};
static struct ti_clk security_l4_ick2 = {
.name = "security_l4_ick2",
.type = TI_CLK_FIXED_FACTOR,
.data = &security_l4_ick2_data,
};
static struct ti_clk_gate aes1_ick_data = {
.parent = "security_l4_ick2",
.bit_shift = 3,
.reg = 0xa14,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk aes1_ick = {
.name = "aes1_ick",
.type = TI_CLK_GATE,
.data = &aes1_ick_data,
};
static const char *dpll5_ck_parents[] = {
"sys_ck",
"sys_ck",
};
static struct ti_clk_dpll dpll5_ck_data = {
.num_parents = ARRAY_SIZE(dpll5_ck_parents),
.control_reg = 0xd04,
.idlest_reg = 0xd24,
.mult_div1_reg = 0xd4c,
.autoidle_reg = 0xd34,
.module = TI_CLKM_CM,
.parents = dpll5_ck_parents,
.freqsel_mask = 0xf0,
.modes = 0x82,
.div1_mask = 0x7f,
.idlest_mask = 0x1,
.auto_recal_bit = 0x3,
.max_divider = 0x80,
.min_divider = 0x1,
.recal_en_bit = 0x19,
.max_multiplier = 0x7ff,
.enable_mask = 0x7,
.mult_mask = 0x7ff00,
.recal_st_bit = 0x19,
.autoidle_mask = 0x7,
};
static struct ti_clk dpll5_ck = {
.name = "dpll5_ck",
.clkdm_name = "dpll5_clkdm",
.type = TI_CLK_DPLL,
.data = &dpll5_ck_data,
};
static struct ti_clk_divider dpll5_m2_ck_data = {
.parent = "dpll5_ck",
.max_div = 31,
.reg = 0xd50,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll5_m2_ck = {
.name = "dpll5_m2_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll5_m2_ck_data,
};
static struct ti_clk_gate usbhost_120m_fck_data = {
.parent = "dpll5_m2_ck",
.bit_shift = 1,
.reg = 0x1400,
.module = TI_CLKM_CM,
};
static struct ti_clk usbhost_120m_fck = {
.name = "usbhost_120m_fck",
.clkdm_name = "usbhost_clkdm",
.type = TI_CLK_GATE,
.data = &usbhost_120m_fck_data,
};
static struct ti_clk_fixed_factor cm_96m_d2_fck_data = {
.parent = "cm_96m_fck",
.div = 2,
.mult = 1,
};
static struct ti_clk cm_96m_d2_fck = {
.name = "cm_96m_d2_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &cm_96m_d2_fck_data,
};
static struct ti_clk_fixed sys_altclk_data = {
.frequency = 0x0,
};
static struct ti_clk sys_altclk = {
.name = "sys_altclk",
.type = TI_CLK_FIXED,
.data = &sys_altclk_data,
};
static const char *omap_48m_fck_parents[] = {
"cm_96m_d2_fck",
"sys_altclk",
};
static struct ti_clk_mux omap_48m_fck_data = {
.bit_shift = 3,
.num_parents = ARRAY_SIZE(omap_48m_fck_parents),
.reg = 0xd40,
.module = TI_CLKM_CM,
.parents = omap_48m_fck_parents,
};
static struct ti_clk omap_48m_fck = {
.name = "omap_48m_fck",
.type = TI_CLK_MUX,
.data = &omap_48m_fck_data,
};
static struct ti_clk_fixed_factor core_48m_fck_data = {
.parent = "omap_48m_fck",
.div = 1,
.mult = 1,
};
static struct ti_clk core_48m_fck = {
.name = "core_48m_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_48m_fck_data,
};
static struct ti_clk_fixed mcbsp_clks_data = {
.frequency = 0x0,
};
static struct ti_clk mcbsp_clks = {
.name = "mcbsp_clks",
.type = TI_CLK_FIXED,
.data = &mcbsp_clks_data,
};
static struct ti_clk_gate mcbsp2_gate_fck_data = {
.parent = "mcbsp_clks",
.bit_shift = 0,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static struct ti_clk_fixed_factor per_96m_fck_data = {
.parent = "omap_96m_alwon_fck",
.div = 1,
.mult = 1,
};
static struct ti_clk per_96m_fck = {
.name = "per_96m_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &per_96m_fck_data,
};
static const char *mcbsp2_mux_fck_parents[] = {
"per_96m_fck",
"mcbsp_clks",
};
static struct ti_clk_mux mcbsp2_mux_fck_data = {
.bit_shift = 6,
.num_parents = ARRAY_SIZE(mcbsp2_mux_fck_parents),
.reg = 0x274,
.module = TI_CLKM_SCRM,
.parents = mcbsp2_mux_fck_parents,
};
static struct ti_clk_composite mcbsp2_fck_data = {
.mux = &mcbsp2_mux_fck_data,
.gate = &mcbsp2_gate_fck_data,
};
static struct ti_clk mcbsp2_fck = {
.name = "mcbsp2_fck",
.type = TI_CLK_COMPOSITE,
.data = &mcbsp2_fck_data,
};
static struct ti_clk_fixed_factor dpll3_m2x2_ck_data = {
.parent = "dpll3_m2_ck",
.div = 1,
.mult = 2,
};
static struct ti_clk dpll3_m2x2_ck = {
.name = "dpll3_m2x2_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll3_m2x2_ck_data,
};
static struct ti_clk_fixed_factor corex2_fck_data = {
.parent = "dpll3_m2x2_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk corex2_fck = {
.name = "corex2_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &corex2_fck_data,
};
static struct ti_clk_gate ssi_ssr_gate_fck_3430es1_data = {
.parent = "corex2_fck",
.bit_shift = 0,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_NO_WAIT,
};
static int ssi_ssr_div_fck_3430es1_divs[] = {
0,
1,
2,
3,
4,
0,
6,
0,
8,
};
static struct ti_clk_divider ssi_ssr_div_fck_3430es1_data = {
.num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es1_divs),
.parent = "corex2_fck",
.bit_shift = 8,
.dividers = ssi_ssr_div_fck_3430es1_divs,
.reg = 0xa40,
.module = TI_CLKM_CM,
};
static struct ti_clk_composite ssi_ssr_fck_3430es1_data = {
.gate = &ssi_ssr_gate_fck_3430es1_data,
.divider = &ssi_ssr_div_fck_3430es1_data,
};
static struct ti_clk ssi_ssr_fck_3430es1 = {
.name = "ssi_ssr_fck",
.type = TI_CLK_COMPOSITE,
.data = &ssi_ssr_fck_3430es1_data,
};
static struct ti_clk_fixed_factor ssi_sst_fck_3430es1_data = {
.parent = "ssi_ssr_fck",
.div = 2,
.mult = 1,
};
static struct ti_clk ssi_sst_fck_3430es1 = {
.name = "ssi_sst_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &ssi_sst_fck_3430es1_data,
};
static struct ti_clk_fixed omap_32k_fck_data = {
.frequency = 32768,
};
static struct ti_clk omap_32k_fck = {
.name = "omap_32k_fck",
.type = TI_CLK_FIXED,
.data = &omap_32k_fck_data,
};
static struct ti_clk_fixed_factor per_32k_alwon_fck_data = {
.parent = "omap_32k_fck",
.div = 1,
.mult = 1,
};
static struct ti_clk per_32k_alwon_fck = {
.name = "per_32k_alwon_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &per_32k_alwon_fck_data,
};
static struct ti_clk_gate gpio5_dbck_data = {
.parent = "per_32k_alwon_fck",
.bit_shift = 16,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static struct ti_clk gpio5_dbck = {
.name = "gpio5_dbck",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpio5_dbck_data,
};
static struct ti_clk_gate gpt1_ick_data = {
.parent = "wkup_l4_ick",
.bit_shift = 0,
.reg = 0xc10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt1_ick = {
.name = "gpt1_ick",
.clkdm_name = "wkup_clkdm",
.type = TI_CLK_GATE,
.data = &gpt1_ick_data,
};
static struct ti_clk_gate mcspi3_fck_data = {
.parent = "core_48m_fck",
.bit_shift = 20,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk mcspi3_fck = {
.name = "mcspi3_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mcspi3_fck_data,
};
static struct ti_clk_gate gpt2_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 3,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static const char *gpt2_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt2_mux_fck_data = {
.num_parents = ARRAY_SIZE(gpt2_mux_fck_parents),
.reg = 0x1040,
.module = TI_CLKM_CM,
.parents = gpt2_mux_fck_parents,
};
static struct ti_clk_composite gpt2_fck_data = {
.mux = &gpt2_mux_fck_data,
.gate = &gpt2_gate_fck_data,
};
static struct ti_clk gpt2_fck = {
.name = "gpt2_fck",
.type = TI_CLK_COMPOSITE,
.data = &gpt2_fck_data,
};
static struct ti_clk_gate gpt10_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 11,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt10_ick = {
.name = "gpt10_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &gpt10_ick_data,
};
static struct ti_clk_gate uart2_fck_data = {
.parent = "core_48m_fck",
.bit_shift = 14,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk uart2_fck = {
.name = "uart2_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &uart2_fck_data,
};
static struct ti_clk_fixed_factor sr_l4_ick_data = {
.parent = "l4_ick",
.div = 1,
.mult = 1,
};
static struct ti_clk sr_l4_ick = {
.name = "sr_l4_ick",
.type = TI_CLK_FIXED_FACTOR,
.data = &sr_l4_ick_data,
};
static struct ti_clk_fixed_factor omap_96m_d8_fck_data = {
.parent = "omap_96m_fck",
.div = 8,
.mult = 1,
};
static struct ti_clk omap_96m_d8_fck = {
.name = "omap_96m_d8_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &omap_96m_d8_fck_data,
};
static struct ti_clk_divider dpll4_m5_ck_data = {
.parent = "dpll4_ck",
.max_div = 63,
.reg = 0xf40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll4_m5_ck = {
.name = "dpll4_m5_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll4_m5_ck_data,
};
static struct ti_clk_fixed_factor dpll4_m5x2_mul_ck_data = {
.parent = "dpll4_m5_ck",
.div = 1,
.mult = 2,
.flags = CLKF_SET_RATE_PARENT,
};
static struct ti_clk dpll4_m5x2_mul_ck = {
.name = "dpll4_m5x2_mul_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll4_m5x2_mul_ck_data,
};
static struct ti_clk_gate dpll4_m5x2_ck_data = {
.parent = "dpll4_m5x2_mul_ck",
.bit_shift = 0x1e,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll4_m5x2_ck = {
.name = "dpll4_m5x2_ck",
.type = TI_CLK_GATE,
.data = &dpll4_m5x2_ck_data,
};
static struct ti_clk_gate cam_mclk_data = {
.parent = "dpll4_m5x2_ck",
.bit_shift = 0,
.reg = 0xf00,
.module = TI_CLKM_CM,
.flags = CLKF_SET_RATE_PARENT,
};
static struct ti_clk cam_mclk = {
.name = "cam_mclk",
.type = TI_CLK_GATE,
.data = &cam_mclk_data,
};
static struct ti_clk_gate mcbsp3_gate_fck_data = {
.parent = "mcbsp_clks",
.bit_shift = 1,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static const char *mcbsp3_mux_fck_parents[] = {
"per_96m_fck",
"mcbsp_clks",
};
static struct ti_clk_mux mcbsp3_mux_fck_data = {
.num_parents = ARRAY_SIZE(mcbsp3_mux_fck_parents),
.reg = 0x2d8,
.module = TI_CLKM_SCRM,
.parents = mcbsp3_mux_fck_parents,
};
static struct ti_clk_composite mcbsp3_fck_data = {
.mux = &mcbsp3_mux_fck_data,
.gate = &mcbsp3_gate_fck_data,
};
static struct ti_clk mcbsp3_fck = {
.name = "mcbsp3_fck",
.type = TI_CLK_COMPOSITE,
.data = &mcbsp3_fck_data,
};
static struct ti_clk_gate csi2_96m_fck_data = {
.parent = "core_96m_fck",
.bit_shift = 1,
.reg = 0xf00,
.module = TI_CLKM_CM,
};
static struct ti_clk csi2_96m_fck = {
.name = "csi2_96m_fck",
.clkdm_name = "cam_clkdm",
.type = TI_CLK_GATE,
.data = &csi2_96m_fck_data,
};
static struct ti_clk_gate gpt9_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 10,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static const char *gpt9_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt9_mux_fck_data = {
.bit_shift = 7,
.num_parents = ARRAY_SIZE(gpt9_mux_fck_parents),
.reg = 0x1040,
.module = TI_CLKM_CM,
.parents = gpt9_mux_fck_parents,
};
static struct ti_clk_composite gpt9_fck_data = {
.mux = &gpt9_mux_fck_data,
.gate = &gpt9_gate_fck_data,
};
static struct ti_clk gpt9_fck = {
.name = "gpt9_fck",
.type = TI_CLK_COMPOSITE,
.data = &gpt9_fck_data,
};
static struct ti_clk_divider dpll3_m3_ck_data = {
.parent = "dpll3_ck",
.bit_shift = 16,
.max_div = 31,
.reg = 0x1140,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll3_m3_ck = {
.name = "dpll3_m3_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll3_m3_ck_data,
};
static struct ti_clk_fixed_factor dpll3_m3x2_mul_ck_data = {
.parent = "dpll3_m3_ck",
.div = 1,
.mult = 2,
};
static struct ti_clk dpll3_m3x2_mul_ck = {
.name = "dpll3_m3x2_mul_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll3_m3x2_mul_ck_data,
};
static struct ti_clk_gate sr2_fck_data = {
.parent = "sys_ck",
.bit_shift = 7,
.reg = 0xc00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk sr2_fck = {
.name = "sr2_fck",
.clkdm_name = "wkup_clkdm",
.type = TI_CLK_GATE,
.data = &sr2_fck_data,
};
static struct ti_clk_fixed pclk_ck_data = {
.frequency = 27000000,
};
static struct ti_clk pclk_ck = {
.name = "pclk_ck",
.type = TI_CLK_FIXED,
.data = &pclk_ck_data,
};
static struct ti_clk_gate wdt2_ick_data = {
.parent = "wkup_l4_ick",
.bit_shift = 5,
.reg = 0xc10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk wdt2_ick = {
.name = "wdt2_ick",
.clkdm_name = "wkup_clkdm",
.type = TI_CLK_GATE,
.data = &wdt2_ick_data,
};
static struct ti_clk_fixed_factor core_l3_ick_data = {
.parent = "l3_ick",
.div = 1,
.mult = 1,
};
static struct ti_clk core_l3_ick = {
.name = "core_l3_ick",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_l3_ick_data,
};
static struct ti_clk_gate mcspi4_fck_data = {
.parent = "core_48m_fck",
.bit_shift = 21,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk mcspi4_fck = {
.name = "mcspi4_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mcspi4_fck_data,
};
static struct ti_clk_fixed_factor per_48m_fck_data = {
.parent = "omap_48m_fck",
.div = 1,
.mult = 1,
};
static struct ti_clk per_48m_fck = {
.name = "per_48m_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &per_48m_fck_data,
};
static struct ti_clk_gate uart4_fck_data = {
.parent = "per_48m_fck",
.bit_shift = 18,
.reg = 0x1000,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk uart4_fck = {
.name = "uart4_fck",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &uart4_fck_data,
};
static struct ti_clk_fixed_factor omap_96m_d10_fck_data = {
.parent = "omap_96m_fck",
.div = 10,
.mult = 1,
};
static struct ti_clk omap_96m_d10_fck = {
.name = "omap_96m_d10_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &omap_96m_d10_fck_data,
};
static struct ti_clk_gate usim_gate_fck_data = {
.parent = "omap_96m_fck",
.bit_shift = 9,
.reg = 0xc00,
.module = TI_CLKM_CM,
};
static struct ti_clk_fixed_factor per_l4_ick_data = {
.parent = "l4_ick",
.div = 1,
.mult = 1,
};
static struct ti_clk per_l4_ick = {
.name = "per_l4_ick",
.type = TI_CLK_FIXED_FACTOR,
.data = &per_l4_ick_data,
};
static struct ti_clk_gate gpt5_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 6,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt5_ick = {
.name = "gpt5_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpt5_ick_data,
};
static struct ti_clk_gate mcspi2_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 19,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mcspi2_ick = {
.name = "mcspi2_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mcspi2_ick_data,
};
static struct ti_clk_fixed_factor ssi_l4_ick_data = {
.parent = "l4_ick",
.div = 1,
.mult = 1,
};
static struct ti_clk ssi_l4_ick = {
.name = "ssi_l4_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_FIXED_FACTOR,
.data = &ssi_l4_ick_data,
};
static struct ti_clk_gate ssi_ick_3430es1_data = {
.parent = "ssi_l4_ick",
.bit_shift = 0,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
};
static struct ti_clk ssi_ick_3430es1 = {
.name = "ssi_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &ssi_ick_3430es1_data,
};
static struct ti_clk_gate i2c2_fck_data = {
.parent = "core_96m_fck",
.bit_shift = 16,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk i2c2_fck = {
.name = "i2c2_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &i2c2_fck_data,
};
static struct ti_clk_divider dpll1_fck_data = {
.parent = "core_ck",
.bit_shift = 19,
.max_div = 7,
.reg = 0x940,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll1_fck = {
.name = "dpll1_fck",
.type = TI_CLK_DIVIDER,
.data = &dpll1_fck_data,
};
static const char *dpll1_ck_parents[] = {
"sys_ck",
"dpll1_fck",
};
static struct ti_clk_dpll dpll1_ck_data = {
.num_parents = ARRAY_SIZE(dpll1_ck_parents),
.control_reg = 0x904,
.idlest_reg = 0x924,
.mult_div1_reg = 0x940,
.autoidle_reg = 0x934,
.module = TI_CLKM_CM,
.parents = dpll1_ck_parents,
.freqsel_mask = 0xf0,
.modes = 0xa0,
.div1_mask = 0x7f,
.idlest_mask = 0x1,
.auto_recal_bit = 0x3,
.max_divider = 0x80,
.min_divider = 0x1,
.recal_en_bit = 0x7,
.max_multiplier = 0x7ff,
.enable_mask = 0x7,
.mult_mask = 0x7ff00,
.recal_st_bit = 0x7,
.autoidle_mask = 0x7,
};
static struct ti_clk dpll1_ck = {
.name = "dpll1_ck",
.clkdm_name = "dpll1_clkdm",
.type = TI_CLK_DPLL,
.data = &dpll1_ck_data,
};
static struct ti_clk_fixed secure_32k_fck_data = {
.frequency = 32768,
};
static struct ti_clk secure_32k_fck = {
.name = "secure_32k_fck",
.type = TI_CLK_FIXED,
.data = &secure_32k_fck_data,
};
static struct ti_clk_gate gpio5_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 16,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpio5_ick = {
.name = "gpio5_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpio5_ick_data,
};
static struct ti_clk_divider dpll4_m4_ck_data = {
.parent = "dpll4_ck",
.max_div = 32,
.reg = 0xe40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll4_m4_ck = {
.name = "dpll4_m4_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll4_m4_ck_data,
};
static struct ti_clk_fixed_factor dpll4_m4x2_mul_ck_data = {
.parent = "dpll4_m4_ck",
.div = 1,
.mult = 2,
.flags = CLKF_SET_RATE_PARENT,
};
static struct ti_clk dpll4_m4x2_mul_ck = {
.name = "dpll4_m4x2_mul_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll4_m4x2_mul_ck_data,
};
static struct ti_clk_gate dpll4_m4x2_ck_data = {
.parent = "dpll4_m4x2_mul_ck",
.bit_shift = 0x1d,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll4_m4x2_ck = {
.name = "dpll4_m4x2_ck",
.type = TI_CLK_GATE,
.data = &dpll4_m4x2_ck_data,
};
static struct ti_clk_gate dss1_alwon_fck_3430es2_data = {
.parent = "dpll4_m4x2_ck",
.bit_shift = 0,
.reg = 0xe00,
.module = TI_CLKM_CM,
.flags = CLKF_DSS | CLKF_SET_RATE_PARENT,
};
static struct ti_clk dss1_alwon_fck_3430es2 = {
.name = "dss1_alwon_fck",
.clkdm_name = "dss_clkdm",
.type = TI_CLK_GATE,
.data = &dss1_alwon_fck_3430es2_data,
};
static struct ti_clk_gate uart3_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 11,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk uart3_ick = {
.name = "uart3_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &uart3_ick_data,
};
static struct ti_clk_divider dpll4_m3_ck_data = {
.parent = "dpll4_ck",
.bit_shift = 8,
.max_div = 32,
.reg = 0xe40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll4_m3_ck = {
.name = "dpll4_m3_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll4_m3_ck_data,
};
static struct ti_clk_gate mcbsp3_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 1,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mcbsp3_ick = {
.name = "mcbsp3_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &mcbsp3_ick_data,
};
static struct ti_clk_gate gpio3_dbck_data = {
.parent = "per_32k_alwon_fck",
.bit_shift = 14,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static struct ti_clk gpio3_dbck = {
.name = "gpio3_dbck",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpio3_dbck_data,
};
static struct ti_clk_gate fac_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 8,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk fac_ick = {
.name = "fac_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &fac_ick_data,
};
static struct ti_clk_gate clkout2_src_gate_ck_data = {
.parent = "core_ck",
.bit_shift = 7,
.reg = 0xd70,
.module = TI_CLKM_CM,
.flags = CLKF_NO_WAIT,
};
static struct ti_clk_fixed_factor dpll4_m3x2_mul_ck_data = {
.parent = "dpll4_m3_ck",
.div = 1,
.mult = 2,
};
static struct ti_clk dpll4_m3x2_mul_ck = {
.name = "dpll4_m3x2_mul_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll4_m3x2_mul_ck_data,
};
static struct ti_clk_gate dpll4_m3x2_ck_data = {
.parent = "dpll4_m3x2_mul_ck",
.bit_shift = 0x1c,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll4_m3x2_ck = {
.name = "dpll4_m3x2_ck",
.type = TI_CLK_GATE,
.data = &dpll4_m3x2_ck_data,
};
static const char *omap_54m_fck_parents[] = {
"dpll4_m3x2_ck",
"sys_altclk",
};
static struct ti_clk_mux omap_54m_fck_data = {
.bit_shift = 5,
.num_parents = ARRAY_SIZE(omap_54m_fck_parents),
.reg = 0xd40,
.module = TI_CLKM_CM,
.parents = omap_54m_fck_parents,
};
static struct ti_clk omap_54m_fck = {
.name = "omap_54m_fck",
.type = TI_CLK_MUX,
.data = &omap_54m_fck_data,
};
static const char *clkout2_src_mux_ck_parents[] = {
"core_ck",
"sys_ck",
"cm_96m_fck",
"omap_54m_fck",
};
static struct ti_clk_mux clkout2_src_mux_ck_data = {
.num_parents = ARRAY_SIZE(clkout2_src_mux_ck_parents),
.reg = 0xd70,
.module = TI_CLKM_CM,
.parents = clkout2_src_mux_ck_parents,
};
static struct ti_clk_composite clkout2_src_ck_data = {
.mux = &clkout2_src_mux_ck_data,
.gate = &clkout2_src_gate_ck_data,
};
static struct ti_clk clkout2_src_ck = {
.name = "clkout2_src_ck",
.type = TI_CLK_COMPOSITE,
.data = &clkout2_src_ck_data,
};
static struct ti_clk_gate i2c1_fck_data = {
.parent = "core_96m_fck",
.bit_shift = 15,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk i2c1_fck = {
.name = "i2c1_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &i2c1_fck_data,
};
static struct ti_clk_gate wdt3_fck_data = {
.parent = "per_32k_alwon_fck",
.bit_shift = 12,
.reg = 0x1000,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk wdt3_fck = {
.name = "wdt3_fck",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &wdt3_fck_data,
};
static struct ti_clk_gate gpt7_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 8,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static const char *gpt7_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt7_mux_fck_data = {
.bit_shift = 5,
.num_parents = ARRAY_SIZE(gpt7_mux_fck_parents),
.reg = 0x1040,
.module = TI_CLKM_CM,
.parents = gpt7_mux_fck_parents,
};
static struct ti_clk_composite gpt7_fck_data = {
.mux = &gpt7_mux_fck_data,
.gate = &gpt7_gate_fck_data,
};
static struct ti_clk gpt7_fck = {
.name = "gpt7_fck",
.type = TI_CLK_COMPOSITE,
.data = &gpt7_fck_data,
};
static struct ti_clk_gate usb_l4_gate_ick_data = {
.parent = "l4_ick",
.bit_shift = 5,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_INTERFACE,
};
static struct ti_clk_divider usb_l4_div_ick_data = {
.parent = "l4_ick",
.bit_shift = 4,
.max_div = 1,
.reg = 0xa40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk_composite usb_l4_ick_data = {
.gate = &usb_l4_gate_ick_data,
.divider = &usb_l4_div_ick_data,
};
static struct ti_clk usb_l4_ick = {
.name = "usb_l4_ick",
.type = TI_CLK_COMPOSITE,
.data = &usb_l4_ick_data,
};
static struct ti_clk_gate uart4_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 18,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk uart4_ick = {
.name = "uart4_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &uart4_ick_data,
};
static struct ti_clk_fixed dummy_ck_data = {
.frequency = 0,
};
static struct ti_clk dummy_ck = {
.name = "dummy_ck",
.type = TI_CLK_FIXED,
.data = &dummy_ck_data,
};
static const char *gpt3_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt3_mux_fck_data = {
.bit_shift = 1,
.num_parents = ARRAY_SIZE(gpt3_mux_fck_parents),
.reg = 0x1040,
.module = TI_CLKM_CM,
.parents = gpt3_mux_fck_parents,
};
static struct ti_clk_gate gpt9_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 10,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt9_ick = {
.name = "gpt9_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpt9_ick_data,
};
static struct ti_clk_gate gpt10_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 11,
.reg = 0xa00,
.module = TI_CLKM_CM,
};
static struct ti_clk_gate dss_ick_3430es1_data = {
.parent = "l4_ick",
.bit_shift = 0,
.reg = 0xe10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
};
static struct ti_clk dss_ick_3430es1 = {
.name = "dss_ick",
.clkdm_name = "dss_clkdm",
.type = TI_CLK_GATE,
.data = &dss_ick_3430es1_data,
};
static struct ti_clk_gate gpt11_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 12,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt11_ick = {
.name = "gpt11_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &gpt11_ick_data,
};
static struct ti_clk_divider dpll2_fck_data = {
.parent = "core_ck",
.bit_shift = 19,
.max_div = 7,
.reg = 0x40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll2_fck = {
.name = "dpll2_fck",
.type = TI_CLK_DIVIDER,
.data = &dpll2_fck_data,
};
static struct ti_clk_gate uart1_fck_data = {
.parent = "core_48m_fck",
.bit_shift = 13,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk uart1_fck = {
.name = "uart1_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &uart1_fck_data,
};
static struct ti_clk_gate hsotgusb_ick_3430es1_data = {
.parent = "core_l3_ick",
.bit_shift = 4,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
};
static struct ti_clk hsotgusb_ick_3430es1 = {
.name = "hsotgusb_ick_3430es1",
.clkdm_name = "core_l3_clkdm",
.type = TI_CLK_GATE,
.data = &hsotgusb_ick_3430es1_data,
};
static struct ti_clk_gate gpio2_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 13,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpio2_ick = {
.name = "gpio2_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpio2_ick_data,
};
static struct ti_clk_gate mmchs1_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 24,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mmchs1_ick = {
.name = "mmchs1_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mmchs1_ick_data,
};
static struct ti_clk_gate modem_fck_data = {
.parent = "sys_ck",
.bit_shift = 31,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk modem_fck = {
.name = "modem_fck",
.clkdm_name = "d2d_clkdm",
.type = TI_CLK_GATE,
.data = &modem_fck_data,
};
static struct ti_clk_gate mcbsp4_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 2,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mcbsp4_ick = {
.name = "mcbsp4_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &mcbsp4_ick_data,
};
static struct ti_clk_gate gpio1_ick_data = {
.parent = "wkup_l4_ick",
.bit_shift = 3,
.reg = 0xc10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpio1_ick = {
.name = "gpio1_ick",
.clkdm_name = "wkup_clkdm",
.type = TI_CLK_GATE,
.data = &gpio1_ick_data,
};
static const char *gpt6_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt6_mux_fck_data = {
.bit_shift = 4,
.num_parents = ARRAY_SIZE(gpt6_mux_fck_parents),
.reg = 0x1040,
.module = TI_CLKM_CM,
.parents = gpt6_mux_fck_parents,
};
static struct ti_clk_fixed_factor dpll1_x2_ck_data = {
.parent = "dpll1_ck",
.div = 1,
.mult = 2,
};
static struct ti_clk dpll1_x2_ck = {
.name = "dpll1_x2_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll1_x2_ck_data,
};
static struct ti_clk_divider dpll1_x2m2_ck_data = {
.parent = "dpll1_x2_ck",
.max_div = 31,
.reg = 0x944,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll1_x2m2_ck = {
.name = "dpll1_x2m2_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll1_x2m2_ck_data,
};
static struct ti_clk_fixed_factor mpu_ck_data = {
.parent = "dpll1_x2m2_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk mpu_ck = {
.name = "mpu_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &mpu_ck_data,
};
static struct ti_clk_divider arm_fck_data = {
.parent = "mpu_ck",
.max_div = 2,
.reg = 0x924,
.module = TI_CLKM_CM,
};
static struct ti_clk arm_fck = {
.name = "arm_fck",
.type = TI_CLK_DIVIDER,
.data = &arm_fck_data,
};
static struct ti_clk_fixed_factor core_d3_ck_data = {
.parent = "core_ck",
.div = 3,
.mult = 1,
};
static struct ti_clk core_d3_ck = {
.name = "core_d3_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_d3_ck_data,
};
static struct ti_clk_gate gpt11_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 12,
.reg = 0xa00,
.module = TI_CLKM_CM,
};
static const char *gpt11_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt11_mux_fck_data = {
.bit_shift = 7,
.num_parents = ARRAY_SIZE(gpt11_mux_fck_parents),
.reg = 0xa40,
.module = TI_CLKM_CM,
.parents = gpt11_mux_fck_parents,
};
static struct ti_clk_composite gpt11_fck_data = {
.mux = &gpt11_mux_fck_data,
.gate = &gpt11_gate_fck_data,
};
static struct ti_clk gpt11_fck = {
.name = "gpt11_fck",
.type = TI_CLK_COMPOSITE,
.data = &gpt11_fck_data,
};
static struct ti_clk_fixed_factor core_d6_ck_data = {
.parent = "core_ck",
.div = 6,
.mult = 1,
};
static struct ti_clk core_d6_ck = {
.name = "core_d6_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_d6_ck_data,
};
static struct ti_clk_gate uart4_fck_am35xx_data = {
.parent = "core_48m_fck",
.bit_shift = 23,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk uart4_fck_am35xx = {
.name = "uart4_fck_am35xx",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &uart4_fck_am35xx_data,
};
static struct ti_clk_gate dpll3_m3x2_ck_data = {
.parent = "dpll3_m3x2_mul_ck",
.bit_shift = 0xc,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll3_m3x2_ck = {
.name = "dpll3_m3x2_ck",
.type = TI_CLK_GATE,
.data = &dpll3_m3x2_ck_data,
};
static struct ti_clk_fixed_factor emu_core_alwon_ck_data = {
.parent = "dpll3_m3x2_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk emu_core_alwon_ck = {
.name = "emu_core_alwon_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &emu_core_alwon_ck_data,
};
static struct ti_clk_divider dpll4_m6_ck_data = {
.parent = "dpll4_ck",
.bit_shift = 24,
.max_div = 63,
.reg = 0x1140,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll4_m6_ck = {
.name = "dpll4_m6_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll4_m6_ck_data,
};
static struct ti_clk_fixed_factor dpll4_m6x2_mul_ck_data = {
.parent = "dpll4_m6_ck",
.div = 1,
.mult = 2,
};
static struct ti_clk dpll4_m6x2_mul_ck = {
.name = "dpll4_m6x2_mul_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll4_m6x2_mul_ck_data,
};
static struct ti_clk_gate dpll4_m6x2_ck_data = {
.parent = "dpll4_m6x2_mul_ck",
.bit_shift = 0x1f,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll4_m6x2_ck = {
.name = "dpll4_m6x2_ck",
.type = TI_CLK_GATE,
.data = &dpll4_m6x2_ck_data,
};
static struct ti_clk_fixed_factor emu_per_alwon_ck_data = {
.parent = "dpll4_m6x2_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk emu_per_alwon_ck = {
.name = "emu_per_alwon_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &emu_per_alwon_ck_data,
};
static struct ti_clk_fixed_factor emu_mpu_alwon_ck_data = {
.parent = "mpu_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk emu_mpu_alwon_ck = {
.name = "emu_mpu_alwon_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &emu_mpu_alwon_ck_data,
};
static const char *emu_src_mux_ck_parents[] = {
"sys_ck",
"emu_core_alwon_ck",
"emu_per_alwon_ck",
"emu_mpu_alwon_ck",
};
static struct ti_clk_mux emu_src_mux_ck_data = {
.num_parents = ARRAY_SIZE(emu_src_mux_ck_parents),
.reg = 0x1140,
.module = TI_CLKM_CM,
.parents = emu_src_mux_ck_parents,
};
static struct ti_clk emu_src_mux_ck = {
.name = "emu_src_mux_ck",
.type = TI_CLK_MUX,
.data = &emu_src_mux_ck_data,
};
static struct ti_clk_gate emu_src_ck_data = {
.parent = "emu_src_mux_ck",
.flags = CLKF_CLKDM,
};
static struct ti_clk emu_src_ck = {
.name = "emu_src_ck",
.clkdm_name = "emu_clkdm",
.type = TI_CLK_GATE,
.data = &emu_src_ck_data,
};
static struct ti_clk_divider atclk_fck_data = {
.parent = "emu_src_ck",
.bit_shift = 4,
.max_div = 3,
.reg = 0x1140,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk atclk_fck = {
.name = "atclk_fck",
.type = TI_CLK_DIVIDER,
.data = &atclk_fck_data,
};
static struct ti_clk_gate ipss_ick_data = {
.parent = "core_l3_ick",
.bit_shift = 4,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_AM35XX | CLKF_INTERFACE,
};
static struct ti_clk ipss_ick = {
.name = "ipss_ick",
.clkdm_name = "core_l3_clkdm",
.type = TI_CLK_GATE,
.data = &ipss_ick_data,
};
static struct ti_clk_gate emac_ick_data = {
.parent = "ipss_ick",
.bit_shift = 1,
.reg = 0x59c,
.module = TI_CLKM_SCRM,
.flags = CLKF_AM35XX,
};
static struct ti_clk emac_ick = {
.name = "emac_ick",
.clkdm_name = "core_l3_clkdm",
.type = TI_CLK_GATE,
.data = &emac_ick_data,
};
static struct ti_clk_gate vpfe_ick_data = {
.parent = "ipss_ick",
.bit_shift = 2,
.reg = 0x59c,
.module = TI_CLKM_SCRM,
.flags = CLKF_AM35XX,
};
static struct ti_clk vpfe_ick = {
.name = "vpfe_ick",
.clkdm_name = "core_l3_clkdm",
.type = TI_CLK_GATE,
.data = &vpfe_ick_data,
};
static const char *dpll2_ck_parents[] = {
"sys_ck",
"dpll2_fck",
};
static struct ti_clk_dpll dpll2_ck_data = {
.num_parents = ARRAY_SIZE(dpll2_ck_parents),
.control_reg = 0x4,
.idlest_reg = 0x24,
.mult_div1_reg = 0x40,
.autoidle_reg = 0x34,
.module = TI_CLKM_CM,
.parents = dpll2_ck_parents,
.freqsel_mask = 0xf0,
.modes = 0xa2,
.div1_mask = 0x7f,
.idlest_mask = 0x1,
.auto_recal_bit = 0x3,
.max_divider = 0x80,
.min_divider = 0x1,
.recal_en_bit = 0x8,
.max_multiplier = 0x7ff,
.enable_mask = 0x7,
.mult_mask = 0x7ff00,
.recal_st_bit = 0x8,
.autoidle_mask = 0x7,
};
static struct ti_clk dpll2_ck = {
.name = "dpll2_ck",
.clkdm_name = "dpll2_clkdm",
.type = TI_CLK_DPLL,
.data = &dpll2_ck_data,
};
static struct ti_clk_divider dpll2_m2_ck_data = {
.parent = "dpll2_ck",
.max_div = 31,
.reg = 0x44,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk dpll2_m2_ck = {
.name = "dpll2_m2_ck",
.type = TI_CLK_DIVIDER,
.data = &dpll2_m2_ck_data,
};
static const char *mcbsp4_mux_fck_parents[] = {
"per_96m_fck",
"mcbsp_clks",
};
static struct ti_clk_mux mcbsp4_mux_fck_data = {
.bit_shift = 2,
.num_parents = ARRAY_SIZE(mcbsp4_mux_fck_parents),
.reg = 0x2d8,
.module = TI_CLKM_SCRM,
.parents = mcbsp4_mux_fck_parents,
};
static const char *mcbsp1_mux_fck_parents[] = {
"core_96m_fck",
"mcbsp_clks",
};
static struct ti_clk_mux mcbsp1_mux_fck_data = {
.bit_shift = 2,
.num_parents = ARRAY_SIZE(mcbsp1_mux_fck_parents),
.reg = 0x274,
.module = TI_CLKM_SCRM,
.parents = mcbsp1_mux_fck_parents,
};
static struct ti_clk_gate gpt8_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 9,
.reg = 0x1000,
.module = TI_CLKM_CM,
};
static struct ti_clk_gate gpt8_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 9,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt8_ick = {
.name = "gpt8_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpt8_ick_data,
};
static const char *gpt10_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt10_mux_fck_data = {
.bit_shift = 6,
.num_parents = ARRAY_SIZE(gpt10_mux_fck_parents),
.reg = 0xa40,
.module = TI_CLKM_CM,
.parents = gpt10_mux_fck_parents,
};
static struct ti_clk_gate mmchs3_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 30,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mmchs3_ick = {
.name = "mmchs3_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mmchs3_ick_data,
};
static struct ti_clk_gate gpio3_ick_data = {
.parent = "per_l4_ick",
.bit_shift = 14,
.reg = 0x1010,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpio3_ick = {
.name = "gpio3_ick",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &gpio3_ick_data,
};
static const char *traceclk_src_fck_parents[] = {
"sys_ck",
"emu_core_alwon_ck",
"emu_per_alwon_ck",
"emu_mpu_alwon_ck",
};
static struct ti_clk_mux traceclk_src_fck_data = {
.bit_shift = 2,
.num_parents = ARRAY_SIZE(traceclk_src_fck_parents),
.reg = 0x1140,
.module = TI_CLKM_CM,
.parents = traceclk_src_fck_parents,
};
static struct ti_clk traceclk_src_fck = {
.name = "traceclk_src_fck",
.type = TI_CLK_MUX,
.data = &traceclk_src_fck_data,
};
static struct ti_clk_divider traceclk_fck_data = {
.parent = "traceclk_src_fck",
.bit_shift = 11,
.max_div = 7,
.reg = 0x1140,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk traceclk_fck = {
.name = "traceclk_fck",
.type = TI_CLK_DIVIDER,
.data = &traceclk_fck_data,
};
static struct ti_clk_gate mcbsp5_gate_fck_data = {
.parent = "mcbsp_clks",
.bit_shift = 10,
.reg = 0xa00,
.module = TI_CLKM_CM,
};
static struct ti_clk_gate sad2d_ick_data = {
.parent = "l3_ick",
.bit_shift = 3,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk sad2d_ick = {
.name = "sad2d_ick",
.clkdm_name = "d2d_clkdm",
.type = TI_CLK_GATE,
.data = &sad2d_ick_data,
};
static const char *gpt1_mux_fck_parents[] = {
"omap_32k_fck",
"sys_ck",
};
static struct ti_clk_mux gpt1_mux_fck_data = {
.num_parents = ARRAY_SIZE(gpt1_mux_fck_parents),
.reg = 0xc40,
.module = TI_CLKM_CM,
.parents = gpt1_mux_fck_parents,
};
static struct ti_clk_gate hecc_ck_data = {
.parent = "sys_ck",
.bit_shift = 3,
.reg = 0x59c,
.module = TI_CLKM_SCRM,
.flags = CLKF_AM35XX,
};
static struct ti_clk hecc_ck = {
.name = "hecc_ck",
.clkdm_name = "core_l3_clkdm",
.type = TI_CLK_GATE,
.data = &hecc_ck_data,
};
static struct ti_clk_gate gpt1_gate_fck_data = {
.parent = "sys_ck",
.bit_shift = 0,
.reg = 0xc00,
.module = TI_CLKM_CM,
};
static struct ti_clk_composite gpt1_fck_data = {
.mux = &gpt1_mux_fck_data,
.gate = &gpt1_gate_fck_data,
};
static struct ti_clk gpt1_fck = {
.name = "gpt1_fck",
.type = TI_CLK_COMPOSITE,
.data = &gpt1_fck_data,
};
static struct ti_clk_gate dpll4_m2x2_ck_omap36xx_data = {
.parent = "dpll4_m2x2_mul_ck",
.bit_shift = 0x1b,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll4_m2x2_ck_omap36xx = {
.name = "dpll4_m2x2_ck",
.type = TI_CLK_GATE,
.data = &dpll4_m2x2_ck_omap36xx_data,
.patch = &dpll4_m2x2_ck,
};
static struct ti_clk_divider gfx_l3_fck_data = {
.parent = "l3_ick",
.max_div = 7,
.reg = 0xb40,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk gfx_l3_fck = {
.name = "gfx_l3_fck",
.type = TI_CLK_DIVIDER,
.data = &gfx_l3_fck_data,
};
static struct ti_clk_gate gfx_cg1_ck_data = {
.parent = "gfx_l3_fck",
.bit_shift = 1,
.reg = 0xb00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk gfx_cg1_ck = {
.name = "gfx_cg1_ck",
.clkdm_name = "gfx_3430es1_clkdm",
.type = TI_CLK_GATE,
.data = &gfx_cg1_ck_data,
};
static struct ti_clk_gate mailboxes_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 7,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk mailboxes_ick = {
.name = "mailboxes_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mailboxes_ick_data,
};
static struct ti_clk_gate sha11_ick_data = {
.parent = "security_l4_ick2",
.bit_shift = 1,
.reg = 0xa14,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk sha11_ick = {
.name = "sha11_ick",
.type = TI_CLK_GATE,
.data = &sha11_ick_data,
};
static struct ti_clk_gate hsotgusb_ick_am35xx_data = {
.parent = "ipss_ick",
.bit_shift = 0,
.reg = 0x59c,
.module = TI_CLKM_SCRM,
.flags = CLKF_AM35XX,
};
static struct ti_clk hsotgusb_ick_am35xx = {
.name = "hsotgusb_ick_am35xx",
.clkdm_name = "core_l3_clkdm",
.type = TI_CLK_GATE,
.data = &hsotgusb_ick_am35xx_data,
};
static struct ti_clk_gate mmchs3_fck_data = {
.parent = "core_96m_fck",
.bit_shift = 30,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk mmchs3_fck = {
.name = "mmchs3_fck",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &mmchs3_fck_data,
};
static struct ti_clk_divider pclk_fck_data = {
.parent = "emu_src_ck",
.bit_shift = 8,
.max_div = 7,
.reg = 0x1140,
.module = TI_CLKM_CM,
.flags = CLKF_INDEX_STARTS_AT_ONE,
};
static struct ti_clk pclk_fck = {
.name = "pclk_fck",
.type = TI_CLK_DIVIDER,
.data = &pclk_fck_data,
};
static const char *dpll4_ck_omap36xx_parents[] = {
"sys_ck",
"sys_ck",
};
static struct ti_clk_dpll dpll4_ck_omap36xx_data = {
.num_parents = ARRAY_SIZE(dpll4_ck_omap36xx_parents),
.control_reg = 0xd00,
.idlest_reg = 0xd20,
.mult_div1_reg = 0xd44,
.autoidle_reg = 0xd30,
.module = TI_CLKM_CM,
.parents = dpll4_ck_omap36xx_parents,
.modes = 0x82,
.div1_mask = 0x7f,
.idlest_mask = 0x2,
.auto_recal_bit = 0x13,
.max_divider = 0x80,
.min_divider = 0x1,
.recal_en_bit = 0x6,
.max_multiplier = 0xfff,
.enable_mask = 0x70000,
.mult_mask = 0xfff00,
.recal_st_bit = 0x6,
.autoidle_mask = 0x38,
.sddiv_mask = 0xff000000,
.dco_mask = 0xe00000,
.flags = CLKF_PER | CLKF_J_TYPE,
};
static struct ti_clk dpll4_ck_omap36xx = {
.name = "dpll4_ck",
.type = TI_CLK_DPLL,
.data = &dpll4_ck_omap36xx_data,
.patch = &dpll4_ck,
};
static struct ti_clk_gate uart3_fck_data = {
.parent = "per_48m_fck",
.bit_shift = 11,
.reg = 0x1000,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk uart3_fck = {
.name = "uart3_fck",
.clkdm_name = "per_clkdm",
.type = TI_CLK_GATE,
.data = &uart3_fck_data,
};
static struct ti_clk_fixed_factor wkup_32k_fck_data = {
.parent = "omap_32k_fck",
.div = 1,
.mult = 1,
};
static struct ti_clk wkup_32k_fck = {
.name = "wkup_32k_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &wkup_32k_fck_data,
};
static struct ti_clk_gate sys_clkout1_data = {
.parent = "osc_sys_ck",
.bit_shift = 7,
.reg = 0xd70,
.module = TI_CLKM_PRM,
};
static struct ti_clk sys_clkout1 = {
.name = "sys_clkout1",
.type = TI_CLK_GATE,
.data = &sys_clkout1_data,
};
static struct ti_clk_fixed_factor gpmc_fck_data = {
.parent = "core_l3_ick",
.div = 1,
.mult = 1,
};
static struct ti_clk gpmc_fck = {
.name = "gpmc_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &gpmc_fck_data,
};
static struct ti_clk_fixed_factor dpll5_m2_d20_ck_data = {
.parent = "dpll5_m2_ck",
.div = 20,
.mult = 1,
};
static struct ti_clk dpll5_m2_d20_ck = {
.name = "dpll5_m2_d20_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &dpll5_m2_d20_ck_data,
};
static struct ti_clk_gate dpll4_m5x2_ck_omap36xx_data = {
.parent = "dpll4_m5x2_mul_ck",
.bit_shift = 0x1e,
.reg = 0xd00,
.module = TI_CLKM_CM,
.flags = CLKF_HSDIV | CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE,
};
static struct ti_clk dpll4_m5x2_ck_omap36xx = {
.name = "dpll4_m5x2_ck",
.type = TI_CLK_GATE,
.data = &dpll4_m5x2_ck_omap36xx_data,
.patch = &dpll4_m5x2_ck,
};
static struct ti_clk_gate ssi_ssr_gate_fck_3430es2_data = {
.parent = "corex2_fck",
.bit_shift = 0,
.reg = 0xa00,
.module = TI_CLKM_CM,
.flags = CLKF_NO_WAIT,
};
static struct ti_clk_gate uart1_ick_data = {
.parent = "core_l4_ick",
.bit_shift = 13,
.reg = 0xa10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk uart1_ick = {
.name = "uart1_ick",
.clkdm_name = "core_l4_clkdm",
.type = TI_CLK_GATE,
.data = &uart1_ick_data,
};
static struct ti_clk_gate iva2_ck_data = {
.parent = "dpll2_m2_ck",
.bit_shift = 0,
.reg = 0x0,
.module = TI_CLKM_CM,
.flags = CLKF_WAIT,
};
static struct ti_clk iva2_ck = {
.name = "iva2_ck",
.clkdm_name = "iva2_clkdm",
.type = TI_CLK_GATE,
.data = &iva2_ck_data,
};
static struct ti_clk_gate pka_ick_data = {
.parent = "security_l3_ick",
.bit_shift = 4,
.reg = 0xa14,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk pka_ick = {
.name = "pka_ick",
.type = TI_CLK_GATE,
.data = &pka_ick_data,
};
static struct ti_clk_gate gpt12_ick_data = {
.parent = "wkup_l4_ick",
.bit_shift = 1,
.reg = 0xc10,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk gpt12_ick = {
.name = "gpt12_ick",
.clkdm_name = "wkup_clkdm",
.type = TI_CLK_GATE,
.data = &gpt12_ick_data,
};
static const char *mcbsp5_mux_fck_parents[] = {
"core_96m_fck",
"mcbsp_clks",
};
static struct ti_clk_mux mcbsp5_mux_fck_data = {
.bit_shift = 4,
.num_parents = ARRAY_SIZE(mcbsp5_mux_fck_parents),
.reg = 0x2d8,
.module = TI_CLKM_SCRM,
.parents = mcbsp5_mux_fck_parents,
};
static struct ti_clk_composite mcbsp5_fck_data = {
.mux = &mcbsp5_mux_fck_data,
.gate = &mcbsp5_gate_fck_data,
};
static struct ti_clk mcbsp5_fck = {
.name = "mcbsp5_fck",
.type = TI_CLK_COMPOSITE,
.data = &mcbsp5_fck_data,
};
static struct ti_clk_gate usbhost_48m_fck_data = {
.parent = "omap_48m_fck",
.bit_shift = 0,
.reg = 0x1400,
.module = TI_CLKM_CM,
.flags = CLKF_DSS,
};
static struct ti_clk usbhost_48m_fck = {
.name = "usbhost_48m_fck",
.clkdm_name = "usbhost_clkdm",
.type = TI_CLK_GATE,
.data = &usbhost_48m_fck_data,
};
static struct ti_clk_gate des1_ick_data = {
.parent = "security_l4_ick2",
.bit_shift = 0,
.reg = 0xa14,
.module = TI_CLKM_CM,
.flags = CLKF_OMAP3 | CLKF_INTERFACE,
};
static struct ti_clk des1_ick = {
.name = "des1_ick",
.type = TI_CLK_GATE,
.data = &des1_ick_data,
};
static struct ti_clk_gate sgx_gate_fck_data = {
.parent = "core_ck",
.bit_shift = 1,
.reg = 0xb00,
.module = TI_CLKM_CM,
};
static struct ti_clk_fixed_factor core_d4_ck_data = {
.parent = "core_ck",
.div = 4,
.mult = 1,
};
static struct ti_clk core_d4_ck = {
.name = "core_d4_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_d4_ck_data,
};
static struct ti_clk_fixed_factor omap_192m_alwon_fck_data = {
.parent = "dpll4_m2x2_ck",
.div = 1,
.mult = 1,
};
static struct ti_clk omap_192m_alwon_fck = {
.name = "omap_192m_alwon_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &omap_192m_alwon_fck_data,
};
static struct ti_clk_fixed_factor core_d2_ck_data = {
.parent = "core_ck",
.div = 2,
.mult = 1,
};
static struct ti_clk core_d2_ck = {
.name = "core_d2_ck",
.type = TI_CLK_FIXED_FACTOR,
.data = &core_d2_ck_data,
};
static struct ti_clk_fixed_factor corex2_d3_fck_data = {
.parent = "corex2_fck",
.div = 3,
.mult = 1,
};
static struct ti_clk corex2_d3_fck = {
.name = "corex2_d3_fck",
.type = TI_CLK_FIXED_FACTOR,
.data = &corex2_d3_fck_data,
};
static struct ti_clk_fixed_factor corex2_d5_fck_data = {
.parent = "corex2_fck",
.div = 5,
.mult = 1,
};
static struct ti_clk corex2_d5_fck = {
.name = "corex2_d5_fck",