arch/arm64/include/asm/sysreg.h - kernel/common.git - Git at Google

 /*
  * Macros for accessing system registers with older binutils.
  *
  * Copyright (C) 2014 ARM Ltd.
  * Author: Catalin Marinas <catalin.marinas@arm.com>
  *
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */

 #ifndef __ASM_SYSREG_H
 #define __ASM_SYSREG_H

 #include <asm/opcodes.h>

 /*
  * ARMv8 ARM reserves the following encoding for system registers:
  * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
  *  C5.2, version:ARM DDI 0487A.f)
  *	[20-19] : Op0
  *	[18-16] : Op1
  *	[15-12] : CRn
  *	[11-8]  : CRm
  *	[7-5]   : Op2
  */
 #define sys_reg(op0, op1, crn, crm, op2) \
 	((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))

 #define SYS_MIDR_EL1			sys_reg(3, 0, 0, 0, 0)
 #define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)
 #define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)

 #define SYS_ID_PFR0_EL1			sys_reg(3, 0, 0, 1, 0)
 #define SYS_ID_PFR1_EL1			sys_reg(3, 0, 0, 1, 1)
 #define SYS_ID_DFR0_EL1			sys_reg(3, 0, 0, 1, 2)
 #define SYS_ID_MMFR0_EL1		sys_reg(3, 0, 0, 1, 4)
 #define SYS_ID_MMFR1_EL1		sys_reg(3, 0, 0, 1, 5)
 #define SYS_ID_MMFR2_EL1		sys_reg(3, 0, 0, 1, 6)
 #define SYS_ID_MMFR3_EL1		sys_reg(3, 0, 0, 1, 7)

 #define SYS_ID_ISAR0_EL1		sys_reg(3, 0, 0, 2, 0)
 #define SYS_ID_ISAR1_EL1		sys_reg(3, 0, 0, 2, 1)
 #define SYS_ID_ISAR2_EL1		sys_reg(3, 0, 0, 2, 2)
 #define SYS_ID_ISAR3_EL1		sys_reg(3, 0, 0, 2, 3)
 #define SYS_ID_ISAR4_EL1		sys_reg(3, 0, 0, 2, 4)
 #define SYS_ID_ISAR5_EL1		sys_reg(3, 0, 0, 2, 5)
 #define SYS_ID_MMFR4_EL1		sys_reg(3, 0, 0, 2, 6)

 #define SYS_MVFR0_EL1			sys_reg(3, 0, 0, 3, 0)
 #define SYS_MVFR1_EL1			sys_reg(3, 0, 0, 3, 1)
 #define SYS_MVFR2_EL1			sys_reg(3, 0, 0, 3, 2)

 #define SYS_ID_AA64PFR0_EL1		sys_reg(3, 0, 0, 4, 0)
 #define SYS_ID_AA64PFR1_EL1		sys_reg(3, 0, 0, 4, 1)

 #define SYS_ID_AA64DFR0_EL1		sys_reg(3, 0, 0, 5, 0)
 #define SYS_ID_AA64DFR1_EL1		sys_reg(3, 0, 0, 5, 1)

 #define SYS_ID_AA64ISAR0_EL1		sys_reg(3, 0, 0, 6, 0)
 #define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)

 #define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
 #define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)

 #define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)
 #define SYS_CTR_EL0			sys_reg(3, 3, 0, 0, 1)
 #define SYS_DCZID_EL0			sys_reg(3, 3, 0, 0, 7)

 #define REG_PSTATE_PAN_IMM		sys_reg(0, 0, 4, 0, 4)

 #define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 | REG_PSTATE_PAN_IMM |\
 				     (!!x)<<8 | 0x1f)

 /* SCTLR_EL1 */
 #define SCTLR_EL1_CP15BEN	(0x1 << 5)
 #define SCTLR_EL1_SED		(0x1 << 8)
 #define SCTLR_EL1_SPAN		(0x1 << 23)


 /* id_aa64isar0 */
 #define ID_AA64ISAR0_RDM_SHIFT		28
 #define ID_AA64ISAR0_ATOMICS_SHIFT	20
 #define ID_AA64ISAR0_CRC32_SHIFT	16
 #define ID_AA64ISAR0_SHA2_SHIFT		12
 #define ID_AA64ISAR0_SHA1_SHIFT		8
 #define ID_AA64ISAR0_AES_SHIFT		4

 /* id_aa64pfr0 */
 #define ID_AA64PFR0_GIC_SHIFT		24
 #define ID_AA64PFR0_ASIMD_SHIFT		20
 #define ID_AA64PFR0_FP_SHIFT		16
 #define ID_AA64PFR0_EL3_SHIFT		12
 #define ID_AA64PFR0_EL2_SHIFT		8
 #define ID_AA64PFR0_EL1_SHIFT		4
 #define ID_AA64PFR0_EL0_SHIFT		0

 #define ID_AA64PFR0_FP_NI		0xf
 #define ID_AA64PFR0_FP_SUPPORTED	0x0
 #define ID_AA64PFR0_ASIMD_NI		0xf
 #define ID_AA64PFR0_ASIMD_SUPPORTED	0x0
 #define ID_AA64PFR0_EL1_64BIT_ONLY	0x1
 #define ID_AA64PFR0_EL0_64BIT_ONLY	0x1
 #define ID_AA64PFR0_EL0_32BIT_64BIT	0x2

 /* id_aa64mmfr0 */
 #define ID_AA64MMFR0_TGRAN4_SHIFT	28
 #define ID_AA64MMFR0_TGRAN64_SHIFT	24
 #define ID_AA64MMFR0_TGRAN16_SHIFT	20
 #define ID_AA64MMFR0_BIGENDEL0_SHIFT	16
 #define ID_AA64MMFR0_SNSMEM_SHIFT	12
 #define ID_AA64MMFR0_BIGENDEL_SHIFT	8
 #define ID_AA64MMFR0_ASID_SHIFT		4
 #define ID_AA64MMFR0_PARANGE_SHIFT	0

 #define ID_AA64MMFR0_TGRAN4_NI		0xf
 #define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0
 #define ID_AA64MMFR0_TGRAN64_NI		0xf
 #define ID_AA64MMFR0_TGRAN64_SUPPORTED	0x0
 #define ID_AA64MMFR0_TGRAN16_NI		0x0
 #define ID_AA64MMFR0_TGRAN16_SUPPORTED	0x1

 /* id_aa64mmfr1 */
 #define ID_AA64MMFR1_PAN_SHIFT		20
 #define ID_AA64MMFR1_LOR_SHIFT		16
 #define ID_AA64MMFR1_HPD_SHIFT		12
 #define ID_AA64MMFR1_VHE_SHIFT		8
 #define ID_AA64MMFR1_VMIDBITS_SHIFT	4
 #define ID_AA64MMFR1_HADBS_SHIFT	0

 /* id_aa64dfr0 */
 #define ID_AA64DFR0_CTX_CMPS_SHIFT	28
 #define ID_AA64DFR0_WRPS_SHIFT		20
 #define ID_AA64DFR0_BRPS_SHIFT		12
 #define ID_AA64DFR0_PMUVER_SHIFT	8
 #define ID_AA64DFR0_TRACEVER_SHIFT	4
 #define ID_AA64DFR0_DEBUGVER_SHIFT	0

 #define ID_ISAR5_RDM_SHIFT		24
 #define ID_ISAR5_CRC32_SHIFT		16
 #define ID_ISAR5_SHA2_SHIFT		12
 #define ID_ISAR5_SHA1_SHIFT		8
 #define ID_ISAR5_AES_SHIFT		4
 #define ID_ISAR5_SEVL_SHIFT		0

 #define MVFR0_FPROUND_SHIFT		28
 #define MVFR0_FPSHVEC_SHIFT		24
 #define MVFR0_FPSQRT_SHIFT		20
 #define MVFR0_FPDIVIDE_SHIFT		16
 #define MVFR0_FPTRAP_SHIFT		12
 #define MVFR0_FPDP_SHIFT		8
 #define MVFR0_FPSP_SHIFT		4
 #define MVFR0_SIMD_SHIFT		0

 #define MVFR1_SIMDFMAC_SHIFT		28
 #define MVFR1_FPHP_SHIFT		24
 #define MVFR1_SIMDHP_SHIFT		20
 #define MVFR1_SIMDSP_SHIFT		16
 #define MVFR1_SIMDINT_SHIFT		12
 #define MVFR1_SIMDLS_SHIFT		8
 #define MVFR1_FPDNAN_SHIFT		4
 #define MVFR1_FPFTZ_SHIFT		0


 #define ID_AA64MMFR0_TGRAN4_SHIFT	28
 #define ID_AA64MMFR0_TGRAN64_SHIFT	24
 #define ID_AA64MMFR0_TGRAN16_SHIFT	20

 #define ID_AA64MMFR0_TGRAN4_NI		0xf
 #define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0
 #define ID_AA64MMFR0_TGRAN64_NI		0xf
 #define ID_AA64MMFR0_TGRAN64_SUPPORTED	0x0
 #define ID_AA64MMFR0_TGRAN16_NI		0x0
 #define ID_AA64MMFR0_TGRAN16_SUPPORTED	0x1

 #if defined(CONFIG_ARM64_4K_PAGES)
 #define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN4_SHIFT
 #define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN4_SUPPORTED
 #elif defined(CONFIG_ARM64_16K_PAGES)
 #define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN16_SHIFT
 #define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN16_SUPPORTED
 #elif defined(CONFIG_ARM64_64K_PAGES)
 #define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN64_SHIFT
 #define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN64_SUPPORTED
 #endif

 #ifdef __ASSEMBLY__

 	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
 	.equ	__reg_num_x\num, \num
 	.endr
 	.equ	__reg_num_xzr, 31

 	.macro	mrs_s, rt, sreg
 	.inst	0xd5200000|(\sreg)|(__reg_num_\rt)
 	.endm

 	.macro	msr_s, sreg, rt
 	.inst	0xd5000000|(\sreg)|(__reg_num_\rt)
 	.endm

 #else

 asm(
 "	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
 "	.equ	__reg_num_x\\num, \\num\n"
 "	.endr\n"
 "	.equ	__reg_num_xzr, 31\n"
 "\n"
 "	.macro	mrs_s, rt, sreg\n"
 "	.inst	0xd5200000|(\\sreg)|(__reg_num_\\rt)\n"
 "	.endm\n"
 "\n"
 "	.macro	msr_s, sreg, rt\n"
 "	.inst	0xd5000000|(\\sreg)|(__reg_num_\\rt)\n"
 "	.endm\n"
 );

 static inline void config_sctlr_el1(u32 clear, u32 set)
 {
 	u32 val;

 	asm volatile("mrs %0, sctlr_el1" : "=r" (val));
 	val &= ~clear;
 	val |= set;
 	asm volatile("msr sctlr_el1, %0" : : "r" (val));
 }
 #endif

 #endif	/* __ASM_SYSREG_H */
	/*
	* Macros for accessing system registers with older binutils.
	*
	* Copyright (C) 2014 ARM Ltd.
	* Author: Catalin Marinas <catalin.marinas@arm.com>
	*
	* This program is free software: you can redistribute it and/or modify
	* it under the terms of the GNU General Public License version 2 as
	* published by the Free Software Foundation.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* You should have received a copy of the GNU General Public License
	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	*/

	#ifndef __ASM_SYSREG_H
	#define __ASM_SYSREG_H

	#include <asm/opcodes.h>

	/*
	* ARMv8 ARM reserves the following encoding for system registers:
	* (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
	* C5.2, version:ARM DDI 0487A.f)
	* [20-19] : Op0
	* [18-16] : Op1
	* [15-12] : CRn
	* [11-8] : CRm
	* [7-5] : Op2
	*/
	#define sys_reg(op0, op1, crn, crm, op2) \
	((((op0)&3)<<19)\|((op1)<<16)\|((crn)<<12)\|((crm)<<8)\|((op2)<<5))

	#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
	#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
	#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)

	#define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
	#define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
	#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
	#define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
	#define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
	#define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
	#define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)

	#define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
	#define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
	#define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
	#define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
	#define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
	#define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
	#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)

	#define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
	#define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
	#define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)

	#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
	#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)

	#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
	#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)

	#define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
	#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)

	#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
	#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)

	#define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
	#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
	#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)

	#define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)

	#define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 \| REG_PSTATE_PAN_IMM \|\
	(!!x)<<8 \| 0x1f)

	/* SCTLR_EL1 */
	#define SCTLR_EL1_CP15BEN (0x1 << 5)
	#define SCTLR_EL1_SED (0x1 << 8)
	#define SCTLR_EL1_SPAN (0x1 << 23)


	/* id_aa64isar0 */
	#define ID_AA64ISAR0_RDM_SHIFT 28
	#define ID_AA64ISAR0_ATOMICS_SHIFT 20
	#define ID_AA64ISAR0_CRC32_SHIFT 16
	#define ID_AA64ISAR0_SHA2_SHIFT 12
	#define ID_AA64ISAR0_SHA1_SHIFT 8
	#define ID_AA64ISAR0_AES_SHIFT 4

	/* id_aa64pfr0 */
	#define ID_AA64PFR0_GIC_SHIFT 24
	#define ID_AA64PFR0_ASIMD_SHIFT 20
	#define ID_AA64PFR0_FP_SHIFT 16
	#define ID_AA64PFR0_EL3_SHIFT 12
	#define ID_AA64PFR0_EL2_SHIFT 8
	#define ID_AA64PFR0_EL1_SHIFT 4
	#define ID_AA64PFR0_EL0_SHIFT 0

	#define ID_AA64PFR0_FP_NI 0xf
	#define ID_AA64PFR0_FP_SUPPORTED 0x0
	#define ID_AA64PFR0_ASIMD_NI 0xf
	#define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
	#define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
	#define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
	#define ID_AA64PFR0_EL0_32BIT_64BIT 0x2

	/* id_aa64mmfr0 */
	#define ID_AA64MMFR0_TGRAN4_SHIFT 28
	#define ID_AA64MMFR0_TGRAN64_SHIFT 24
	#define ID_AA64MMFR0_TGRAN16_SHIFT 20
	#define ID_AA64MMFR0_BIGENDEL0_SHIFT 16
	#define ID_AA64MMFR0_SNSMEM_SHIFT 12
	#define ID_AA64MMFR0_BIGENDEL_SHIFT 8
	#define ID_AA64MMFR0_ASID_SHIFT 4
	#define ID_AA64MMFR0_PARANGE_SHIFT 0

	#define ID_AA64MMFR0_TGRAN4_NI 0xf
	#define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
	#define ID_AA64MMFR0_TGRAN64_NI 0xf
	#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
	#define ID_AA64MMFR0_TGRAN16_NI 0x0
	#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1

	/* id_aa64mmfr1 */
	#define ID_AA64MMFR1_PAN_SHIFT 20
	#define ID_AA64MMFR1_LOR_SHIFT 16
	#define ID_AA64MMFR1_HPD_SHIFT 12
	#define ID_AA64MMFR1_VHE_SHIFT 8
	#define ID_AA64MMFR1_VMIDBITS_SHIFT 4
	#define ID_AA64MMFR1_HADBS_SHIFT 0

	/* id_aa64dfr0 */
	#define ID_AA64DFR0_CTX_CMPS_SHIFT 28
	#define ID_AA64DFR0_WRPS_SHIFT 20
	#define ID_AA64DFR0_BRPS_SHIFT 12
	#define ID_AA64DFR0_PMUVER_SHIFT 8
	#define ID_AA64DFR0_TRACEVER_SHIFT 4
	#define ID_AA64DFR0_DEBUGVER_SHIFT 0

	#define ID_ISAR5_RDM_SHIFT 24
	#define ID_ISAR5_CRC32_SHIFT 16
	#define ID_ISAR5_SHA2_SHIFT 12
	#define ID_ISAR5_SHA1_SHIFT 8
	#define ID_ISAR5_AES_SHIFT 4
	#define ID_ISAR5_SEVL_SHIFT 0

	#define MVFR0_FPROUND_SHIFT 28
	#define MVFR0_FPSHVEC_SHIFT 24
	#define MVFR0_FPSQRT_SHIFT 20
	#define MVFR0_FPDIVIDE_SHIFT 16
	#define MVFR0_FPTRAP_SHIFT 12
	#define MVFR0_FPDP_SHIFT 8
	#define MVFR0_FPSP_SHIFT 4
	#define MVFR0_SIMD_SHIFT 0

	#define MVFR1_SIMDFMAC_SHIFT 28
	#define MVFR1_FPHP_SHIFT 24
	#define MVFR1_SIMDHP_SHIFT 20
	#define MVFR1_SIMDSP_SHIFT 16
	#define MVFR1_SIMDINT_SHIFT 12
	#define MVFR1_SIMDLS_SHIFT 8
	#define MVFR1_FPDNAN_SHIFT 4
	#define MVFR1_FPFTZ_SHIFT 0


	#define ID_AA64MMFR0_TGRAN4_SHIFT 28
	#define ID_AA64MMFR0_TGRAN64_SHIFT 24
	#define ID_AA64MMFR0_TGRAN16_SHIFT 20

	#define ID_AA64MMFR0_TGRAN4_NI 0xf
	#define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
	#define ID_AA64MMFR0_TGRAN64_NI 0xf
	#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
	#define ID_AA64MMFR0_TGRAN16_NI 0x0
	#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1

	#if defined(CONFIG_ARM64_4K_PAGES)
	#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
	#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
	#elif defined(CONFIG_ARM64_16K_PAGES)
	#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
	#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
	#elif defined(CONFIG_ARM64_64K_PAGES)
	#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
	#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
	#endif

	#ifdef __ASSEMBLY__

	.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
	.equ __reg_num_x\num, \num
	.endr
	.equ __reg_num_xzr, 31

	.macro mrs_s, rt, sreg
	.inst 0xd5200000\|(\sreg)\|(__reg_num_\rt)
	.endm

	.macro msr_s, sreg, rt
	.inst 0xd5000000\|(\sreg)\|(__reg_num_\rt)
	.endm

	#else

	asm(
	" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
	" .equ __reg_num_x\\num, \\num\n"
	" .endr\n"
	" .equ __reg_num_xzr, 31\n"
	"\n"
	" .macro mrs_s, rt, sreg\n"
	" .inst 0xd5200000\|(\\sreg)\|(__reg_num_\\rt)\n"
	" .endm\n"
	"\n"
	" .macro msr_s, sreg, rt\n"
	" .inst 0xd5000000\|(\\sreg)\|(__reg_num_\\rt)\n"
	" .endm\n"
	);

	static inline void config_sctlr_el1(u32 clear, u32 set)
	{
	u32 val;

	asm volatile("mrs %0, sctlr_el1" : "=r" (val));
	val &= ~clear;
	val \|= set;
	asm volatile("msr sctlr_el1, %0" : : "r" (val));
	}
	#endif

	#endif /* __ASM_SYSREG_H */