// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier PXs2 SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "socionext,uniphier-pxs2";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
			#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
			#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
			#cooling-cells = <2>;
		};
	};

	cpu_opp: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			clock-latency-ns = <300>;
		};
		opp-150000000 {
			opp-hz = /bits/ 64 <150000000>;
			clock-latency-ns = <300>;
		};
		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			clock-latency-ns = <300>;
		};
		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			clock-latency-ns = <300>;
		};
		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			clock-latency-ns = <300>;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			clock-latency-ns = <300>;
		};
		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			clock-latency-ns = <300>;
		};
		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			clock-latency-ns = <300>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	clocks {
		refclk: ref {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};

		arm_timer_clk: arm-timer {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};

	thermal-zones {
		cpu-thermal {
			polling-delay-passive = <250>;	/* 250ms */
			polling-delay = <1000>;		/* 1000ms */
			thermal-sensors = <&pvtctl>;

			trips {
				cpu_crit: cpu-crit {
					temperature = <95000>;	/* 95C */
					hysteresis = <2000>;
					type = "critical";
				};
				cpu_alert: cpu-alert {
					temperature = <85000>;	/* 85C */
					hysteresis = <2000>;
					type = "passive";
				};
			};

			cooling-maps {
				map {
					trip = <&cpu_alert>;
					cooling-device = <&cpu0
					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;

		l2: l2-cache@500c0000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
			      <0x506c0000 0x400>;
			interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
			cache-unified;
			cache-size = <(1280 * 1024)>;
			cache-sets = <512>;
			cache-line-size = <128>;
			cache-level = <2>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&peri_clk 0>;
			resets = <&peri_rst 0>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&peri_clk 1>;
			resets = <&peri_rst 1>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&peri_clk 2>;
			resets = <&peri_rst 2>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <0 177 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&peri_clk 3>;
			resets = <&peri_rst 3>;
		};

		gpio: gpio@55000000 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000000 0x200>;
			interrupt-parent = <&aidet>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 0>,
				      <&pinctrl 96 0 0>;
			gpio-ranges-group-names = "gpio_range0",
						  "gpio_range1";
			ngpios = <232>;
			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
						     <21 217 3>;
		};

		audio@56000000 {
			compatible = "socionext,uniphier-pxs2-aio";
			reg = <0x56000000 0x80000>;
			interrupts = <0 144 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_ain1>,
				    <&pinctrl_ain2>,
				    <&pinctrl_ainiec1>,
				    <&pinctrl_aout2>,
				    <&pinctrl_aout3>,
				    <&pinctrl_aoutiec1>,
				    <&pinctrl_aoutiec2>;
			clock-names = "aio";
			clocks = <&sys_clk 40>;
			reset-names = "aio";
			resets = <&sys_rst 40>;
			#sound-dai-cells = <1>;
			socionext,syscon = <&soc_glue>;

			i2s_port0: port@0 {
				i2s_hdmi: endpoint {
				};
			};

			i2s_port1: port@1 {
				i2s_line: endpoint {
				};
			};

			i2s_port2: port@2 {
				i2s_aux: endpoint {
				};
			};

			spdif_port0: port@3 {
				spdif_hiecout1: endpoint {
				};
			};

			spdif_port1: port@4 {
				spdif_iecout1: endpoint {
				};
			};

			comp_spdif_port0: port@5 {
				comp_spdif_hiecout1: endpoint {
				};
			};

			comp_spdif_port1: port@6 {
				comp_spdif_iecout1: endpoint {
				};
			};
		};

		i2c0: i2c@58780000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58780000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 41 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&peri_clk 4>;
			resets = <&peri_rst 4>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58781000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58781000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 42 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&peri_clk 5>;
			resets = <&peri_rst 5>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58782000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58782000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 43 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c2>;
			clocks = <&peri_clk 6>;
			resets = <&peri_rst 6>;
			clock-frequency = <100000>;
		};

		i2c3: i2c@58783000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58783000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 44 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			clocks = <&peri_clk 7>;
			resets = <&peri_rst 7>;
			clock-frequency = <100000>;
		};

		/* chip-internal connection for DMD */
		i2c4: i2c@58784000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58784000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 45 4>;
			clocks = <&peri_clk 8>;
			resets = <&peri_rst 8>;
			clock-frequency = <400000>;
		};

		/* chip-internal connection for STM */
		i2c5: i2c@58785000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58785000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 25 4>;
			clocks = <&peri_clk 9>;
			resets = <&peri_rst 9>;
			clock-frequency = <400000>;
		};

		/* chip-internal connection for HDMI */
		i2c6: i2c@58786000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58786000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 26 4>;
			clocks = <&peri_clk 10>;
			resets = <&peri_rst 10>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59801000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		sdctrl@59810000 {
			compatible = "socionext,uniphier-pxs2-sdctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x400>;

			sd_clk: clock {
				compatible = "socionext,uniphier-pxs2-sd-clock";
				#clock-cells = <1>;
			};

			sd_rst: reset {
				compatible = "socionext,uniphier-pxs2-sd-reset";
				#reset-cells = <1>;
			};
		};

		perictrl@59820000 {
			compatible = "socionext,uniphier-pxs2-perictrl",
				     "simple-mfd", "syscon";
			reg = <0x59820000 0x200>;

			peri_clk: clock {
				compatible = "socionext,uniphier-pxs2-peri-clock";
				#clock-cells = <1>;
			};

			peri_rst: reset {
				compatible = "socionext,uniphier-pxs2-peri-reset";
				#reset-cells = <1>;
			};
		};

		soc_glue: soc-glue@5f800000 {
			compatible = "socionext,uniphier-pxs2-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-pxs2-pinctrl";
			};
		};

		soc-glue@5f900000 {
			compatible = "socionext,uniphier-pxs2-soc-glue-debug",
				     "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x5f900000 0x2000>;

			efuse@100 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x100 0x28>;
			};

			efuse@200 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x200 0x58>;
			};
		};

		aidet: aidet@5fc20000 {
			compatible = "socionext,uniphier-pxs2-aidet";
			reg = <0x5fc20000 0x200>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		timer@60000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x60000200 0x20>;
			interrupts = <1 11 0xf04>;
			clocks = <&arm_timer_clk>;
		};

		timer@60000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x60000600 0x20>;
			interrupts = <1 13 0xf04>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@60001000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0x60001000 0x1000>,
			      <0x60000100 0x100>;
			#interrupt-cells = <3>;
			interrupt-controller;
		};

		sysctrl@61840000 {
			compatible = "socionext,uniphier-pxs2-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0x61840000 0x10000>;

			sys_clk: clock {
				compatible = "socionext,uniphier-pxs2-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset {
				compatible = "socionext,uniphier-pxs2-reset";
				#reset-cells = <1>;
			};

			pvtctl: pvtctl {
				compatible = "socionext,uniphier-pxs2-thermal";
				interrupts = <0 3 4>;
				#thermal-sensor-cells = <0>;
				socionext,tmod-calibration = <0x0f86 0x6844>;
			};
		};

		eth: ethernet@65000000 {
			compatible = "socionext,uniphier-pxs2-ave4";
			status = "disabled";
			reg = <0x65000000 0x8500>;
			interrupts = <0 66 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_ether_rgmii>;
			clock-names = "ether";
			clocks = <&sys_clk 6>;
			reset-names = "ether";
			resets = <&sys_rst 6>;
			phy-mode = "rgmii";
			local-mac-address = [00 00 00 00 00 00];
			socionext,syscon-phy-mode = <&soc_glue 0>;

			mdio: mdio {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		nand: nand@68000000 {
			compatible = "socionext,uniphier-denali-nand-v5b";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			interrupts = <0 65 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand2cs>;
			clocks = <&sys_clk 2>;
			resets = <&sys_rst 2>;
		};
	};
};

#include "uniphier-pinctrl.dtsi"