OMAP4+: Correct the dpll lock sequence

The recommended sequence to update the frequencies for
different dplls are core, mpu, iva. Currently though
core dpll is configured first locking is done
only with the emif freq update mechanism. So the sequence
is mpu, core. Change this so that the core dpll is locked
first and only the post dividers are changed by freq update
procedure later.

Change-Id: I06a7fccd3e33905193d1c24b62e6b1e1ac8e44ef
Signed-off-by: R Sricharan <>
Signed-off-by: Mike J. Chen <>
3 files changed