| /* |
| * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are met: |
| * |
| * Redistributions of source code must retain the above copyright notice, this |
| * list of conditions and the following disclaimer. |
| * |
| * Redistributions in binary form must reproduce the above copyright notice, |
| * this list of conditions and the following disclaimer in the documentation |
| * and/or other materials provided with the distribution. |
| * |
| * Neither the name of ARM nor the names of its contributors may be used |
| * to endorse or promote products derived from this software without specific |
| * prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| * POSSIBILITY OF SUCH DAMAGE. |
| */ |
| |
| #include <arch.h> |
| #include <arch_helpers.h> |
| #include <arm_gic.h> |
| #include <assert.h> |
| #include <bl_common.h> |
| #include <bl31.h> |
| #include <console.h> |
| #include <mmio.h> |
| #include <platform.h> |
| #include <stddef.h> |
| #include "drivers/pwrc/fvp_pwrc.h" |
| #include "fvp_def.h" |
| #include "fvp_private.h" |
| |
| /******************************************************************************* |
| * Declarations of linker defined symbols which will help us find the layout |
| * of trusted SRAM |
| ******************************************************************************/ |
| extern unsigned long __RO_START__; |
| extern unsigned long __RO_END__; |
| extern unsigned long __BL31_END__; |
| |
| #if USE_COHERENT_MEM |
| extern unsigned long __COHERENT_RAM_START__; |
| extern unsigned long __COHERENT_RAM_END__; |
| #endif |
| |
| /* |
| * The next 3 constants identify the extents of the code, RO data region and the |
| * limit of the BL3-1 image. These addresses are used by the MMU setup code and |
| * therefore they must be page-aligned. It is the responsibility of the linker |
| * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols |
| * refer to page-aligned addresses. |
| */ |
| #define BL31_RO_BASE (unsigned long)(&__RO_START__) |
| #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) |
| #define BL31_END (unsigned long)(&__BL31_END__) |
| |
| #if USE_COHERENT_MEM |
| /* |
| * The next 2 constants identify the extents of the coherent memory region. |
| * These addresses are used by the MMU setup code and therefore they must be |
| * page-aligned. It is the responsibility of the linker script to ensure that |
| * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols |
| * refer to page-aligned addresses. |
| */ |
| #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) |
| #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) |
| #endif |
| |
| #if RESET_TO_BL31 |
| static entry_point_info_t bl32_image_ep_info; |
| static entry_point_info_t bl33_image_ep_info; |
| #else |
| /******************************************************************************* |
| * Reference to structure which holds the arguments that have been passed to |
| * BL31 from BL2. |
| ******************************************************************************/ |
| static bl31_params_t *bl2_to_bl31_params; |
| #endif |
| |
| /******************************************************************************* |
| * Return a pointer to the 'entry_point_info' structure of the next image for the |
| * security state specified. BL33 corresponds to the non-secure image type |
| * while BL32 corresponds to the secure image type. A NULL pointer is returned |
| * if the image does not exist. |
| ******************************************************************************/ |
| entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) |
| { |
| #if RESET_TO_BL31 |
| assert(sec_state_is_valid(type)); |
| |
| if (type == NON_SECURE) |
| return &bl33_image_ep_info; |
| else |
| return &bl32_image_ep_info; |
| #else |
| entry_point_info_t *next_image_info; |
| |
| assert(sec_state_is_valid(type)); |
| |
| next_image_info = (type == NON_SECURE) ? |
| bl2_to_bl31_params->bl33_ep_info : |
| bl2_to_bl31_params->bl32_ep_info; |
| |
| /* None of the images on this platform can have 0x0 as the entrypoint */ |
| if (next_image_info->pc) |
| return next_image_info; |
| else |
| return NULL; |
| #endif |
| } |
| |
| /******************************************************************************* |
| * Return a pointer to the 'image_info' structure of the next image for the |
| * security state specified. BL33 corresponds to the non-secure image type |
| * while BL32 corresponds to the secure image type. A NULL pointer is returned |
| * if the image does not exist. |
| ******************************************************************************/ |
| image_info_t *bl31_plat_get_next_image_image_info(uint32_t type) |
| { |
| #if RESET_TO_BL31 |
| assert(sec_state_is_valid(type)); |
| |
| if (type == NON_SECURE) |
| return NULL; |
| else |
| return NULL; |
| #else |
| image_info_t *next_image_info; |
| |
| assert(sec_state_is_valid(type)); |
| |
| next_image_info = (type == NON_SECURE) ? |
| bl2_to_bl31_params->bl33_image_info : |
| bl2_to_bl31_params->bl32_image_info; |
| |
| /* None of the images on this platform can have size 0x0 */ |
| if (next_image_info->image_size) |
| return next_image_info; |
| else |
| return NULL; |
| #endif |
| } |
| |
| |
| |
| /******************************************************************************* |
| * Perform any BL31 specific platform actions. Here is an opportunity to copy |
| * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they |
| * are lost (potentially). This needs to be done before the MMU is initialized |
| * so that the memory layout can be used while creating page tables. On the FVP |
| * we know that BL2 has populated the parameters in secure DRAM. So we just use |
| * the reference passed in 'from_bl2' instead of copying. The 'data' parameter |
| * is not used since all the information is contained in 'from_bl2'. Also, BL2 |
| * has flushed this information to memory, so we are guaranteed to pick up good |
| * data |
| ******************************************************************************/ |
| void bl31_early_platform_setup(bl31_params_t *from_bl2, |
| void *plat_params_from_bl2) |
| { |
| /* Initialize the console to provide early debug support */ |
| console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); |
| |
| /* Initialize the platform config for future decision making */ |
| fvp_config_setup(); |
| |
| #if RESET_TO_BL31 |
| /* There are no parameters from BL2 if BL31 is a reset vector */ |
| assert(from_bl2 == NULL); |
| assert(plat_params_from_bl2 == NULL); |
| |
| /* |
| * Do initial security configuration to allow DRAM/device access. On |
| * Base FVP only DRAM security is programmable (via TrustZone), but |
| * other platforms might have more programmable security devices |
| * present. |
| */ |
| fvp_security_setup(); |
| |
| /* Populate entry point information for BL3-2 and BL3-3 */ |
| SET_PARAM_HEAD(&bl32_image_ep_info, |
| PARAM_EP, |
| VERSION_1, |
| 0); |
| SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); |
| bl32_image_ep_info.pc = BL32_BASE; |
| bl32_image_ep_info.spsr = fvp_get_spsr_for_bl32_entry(); |
| |
| SET_PARAM_HEAD(&bl33_image_ep_info, |
| PARAM_EP, |
| VERSION_1, |
| 0); |
| /* |
| * Tell BL31 where the non-trusted software image |
| * is located and the entry state information |
| */ |
| bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); |
| bl33_image_ep_info.spsr = fvp_get_spsr_for_bl33_entry(); |
| SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); |
| |
| #else |
| /* Check params passed from BL2 should not be NULL, |
| * We are not checking plat_params_from_bl2 as NULL as we are not |
| * using it on FVP |
| */ |
| assert(from_bl2 != NULL); |
| assert(from_bl2->h.type == PARAM_BL31); |
| assert(from_bl2->h.version >= VERSION_1); |
| |
| bl2_to_bl31_params = from_bl2; |
| assert(((unsigned long)plat_params_from_bl2) == FVP_BL31_PLAT_PARAM_VAL); |
| #endif |
| } |
| |
| /******************************************************************************* |
| * Initialize the gic, configure the CLCD and zero out variables needed by the |
| * secondaries to boot up correctly. |
| ******************************************************************************/ |
| void bl31_platform_setup(void) |
| { |
| unsigned int reg_val; |
| |
| /* Initialize the gic cpu and distributor interfaces */ |
| fvp_gic_init(); |
| arm_gic_setup(); |
| |
| /* |
| * TODO: Configure the CLCD before handing control to |
| * linux. Need to see if a separate driver is needed |
| * instead. |
| */ |
| mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGDATA, 0); |
| mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL, |
| (1ull << 31) | (1 << 30) | (7 << 20) | (0 << 16)); |
| |
| /* Enable and initialize the System level generic timer */ |
| mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); |
| |
| /* Allow access to the System counter timer module */ |
| reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); |
| reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); |
| reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); |
| mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val); |
| mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val); |
| |
| reg_val = (1 << CNTNSAR_NS_SHIFT(0)) | (1 << CNTNSAR_NS_SHIFT(1)); |
| mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val); |
| |
| /* Intialize the power controller */ |
| fvp_pwrc_setup(); |
| |
| /* Topologies are best known to the platform. */ |
| fvp_setup_topology(); |
| } |
| |
| /******************************************************************************* |
| * Perform the very early platform specific architectural setup here. At the |
| * moment this is only intializes the mmu in a quick and dirty way. |
| ******************************************************************************/ |
| void bl31_plat_arch_setup(void) |
| { |
| fvp_cci_init(); |
| #if RESET_TO_BL31 |
| fvp_cci_enable(); |
| #endif |
| fvp_configure_mmu_el3(BL31_RO_BASE, |
| (BL31_END - BL31_RO_BASE), |
| BL31_RO_BASE, |
| BL31_RO_LIMIT |
| #if USE_COHERENT_MEM |
| , BL31_COHERENT_RAM_BASE, |
| BL31_COHERENT_RAM_LIMIT |
| #endif |
| ); |
| } |
