| /* |
| * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are met: |
| * |
| * Redistributions of source code must retain the above copyright notice, this |
| * list of conditions and the following disclaimer. |
| * |
| * Redistributions in binary form must reproduce the above copyright notice, |
| * this list of conditions and the following disclaimer in the documentation |
| * and/or other materials provided with the distribution. |
| * |
| * Neither the name of ARM nor the names of its contributors may be used |
| * to endorse or promote products derived from this software without specific |
| * prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| * POSSIBILITY OF SUCH DAMAGE. |
| */ |
| |
| #include <arch.h> |
| #include <asm_macros.S> |
| #include <bl_common.h> |
| |
| .globl bl31_entrypoint |
| |
| |
| /* ----------------------------------------------------- |
| * bl31_entrypoint() is the cold boot entrypoint, |
| * executed only by the primary cpu. |
| * ----------------------------------------------------- |
| */ |
| |
| func bl31_entrypoint |
| /* --------------------------------------------------------------- |
| * Preceding bootloader has populated x0 with a pointer to a |
| * 'bl31_params' structure & x1 with a pointer to platform |
| * specific structure |
| * --------------------------------------------------------------- |
| */ |
| #if !RESET_TO_BL31 |
| mov x20, x0 |
| mov x21, x1 |
| #else |
| /* --------------------------------------------- |
| * Set the CPU endianness before doing anything |
| * that might involve memory reads or writes. |
| * --------------------------------------------- |
| */ |
| mrs x0, sctlr_el3 |
| bic x0, x0, #SCTLR_EE_BIT |
| msr sctlr_el3, x0 |
| isb |
| #endif |
| |
| /* --------------------------------------------- |
| * When RESET_TO_BL31 is true, perform any |
| * processor specific actions upon reset e.g. |
| * cache, tlb invalidations, errata workarounds |
| * etc. |
| * When RESET_TO_BL31 is false, perform any |
| * processor specific actions which undo or are |
| * in addition to the actions performed by the |
| * reset handler in the Boot ROM (BL1). |
| * --------------------------------------------- |
| */ |
| bl reset_handler |
| |
| /* --------------------------------------------- |
| * Enable the instruction cache, stack pointer |
| * and data access alignment checks |
| * --------------------------------------------- |
| */ |
| mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) |
| mrs x0, sctlr_el3 |
| orr x0, x0, x1 |
| msr sctlr_el3, x0 |
| isb |
| |
| /* --------------------------------------------- |
| * Initialise cpu_data early to enable crash |
| * reporting to have access to crash stack. |
| * Since crash reporting depends on cpu_data to |
| * report the unhandled exception, not |
| * doing so can lead to recursive exceptions due |
| * to a NULL TPIDR_EL3 |
| * --------------------------------------------- |
| */ |
| bl init_cpu_data_ptr |
| |
| /* --------------------------------------------- |
| * Set the exception vector. |
| * --------------------------------------------- |
| */ |
| adr x1, runtime_exceptions |
| msr vbar_el3, x1 |
| isb |
| |
| /* --------------------------------------------- |
| * Enable the SError interrupt now that the |
| * exception vectors have been setup. |
| * --------------------------------------------- |
| */ |
| msr daifclr, #DAIF_ABT_BIT |
| |
| /* --------------------------------------------------------------------- |
| * The initial state of the Architectural feature trap register |
| * (CPTR_EL3) is unknown and it must be set to a known state. All |
| * feature traps are disabled. Some bits in this register are marked as |
| * Reserved and should not be modified. |
| * |
| * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 |
| * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. |
| * CPTR_EL3.TTA: This causes access to the Trace functionality to trap |
| * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register |
| * access to trace functionality is not supported, this bit is RES0. |
| * CPTR_EL3.TFP: This causes instructions that access the registers |
| * associated with Floating Point and Advanced SIMD execution to trap |
| * to EL3 when executed from any exception level, unless trapped to EL1 |
| * or EL2. |
| * --------------------------------------------------------------------- |
| */ |
| mrs x1, cptr_el3 |
| bic w1, w1, #TCPAC_BIT |
| bic w1, w1, #TTA_BIT |
| bic w1, w1, #TFP_BIT |
| msr cptr_el3, x1 |
| |
| #if RESET_TO_BL31 |
| /* ------------------------------------------------------- |
| * Will not return from this macro if it is a warm boot. |
| * ------------------------------------------------------- |
| */ |
| wait_for_entrypoint |
| bl platform_mem_init |
| #endif |
| |
| /* --------------------------------------------- |
| * Zero out NOBITS sections. There are 2 of them: |
| * - the .bss section; |
| * - the coherent memory section. |
| * --------------------------------------------- |
| */ |
| ldr x0, =__BSS_START__ |
| ldr x1, =__BSS_SIZE__ |
| bl zeromem16 |
| |
| #if USE_COHERENT_MEM |
| ldr x0, =__COHERENT_RAM_START__ |
| ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ |
| bl zeromem16 |
| #endif |
| |
| /* --------------------------------------------- |
| * Initialize the cpu_ops pointer. |
| * --------------------------------------------- |
| */ |
| bl init_cpu_ops |
| |
| /* --------------------------------------------- |
| * Use SP_EL0 for the C runtime stack. |
| * --------------------------------------------- |
| */ |
| msr spsel, #0 |
| |
| /* -------------------------------------------- |
| * Allocate a stack whose memory will be marked |
| * as Normal-IS-WBWA when the MMU is enabled. |
| * There is no risk of reading stale stack |
| * memory after enabling the MMU as only the |
| * primary cpu is running at the moment. |
| * -------------------------------------------- |
| */ |
| mrs x0, mpidr_el1 |
| bl platform_set_stack |
| |
| /* --------------------------------------------- |
| * Perform platform specific early arch. setup |
| * --------------------------------------------- |
| */ |
| #if RESET_TO_BL31 |
| mov x0, 0 |
| mov x1, 0 |
| #else |
| mov x0, x20 |
| mov x1, x21 |
| #endif |
| |
| bl bl31_early_platform_setup |
| bl bl31_plat_arch_setup |
| |
| /* --------------------------------------------- |
| * Jump to main function. |
| * --------------------------------------------- |
| */ |
| bl bl31_main |
| |
| b el3_exit |
