rockchip: rk3399: fix PMU_CRU_GATEDIS_CON0 setting error
As rk3399 TRM1.1 document show, when set PMU_CRU_GATEDIS_CON0/1
register, it need set the write_mask bit (bit16 ~ bit31), but as
we test, it not need it. So need to correct the setting way, otherwise
it will set wrong value to this register.
Signed-off-by: Lin Huang <hl@rock-chips.com>
diff --git a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c
index 66f3a19..47bd3e3 100644
--- a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c
+++ b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c
@@ -52,9 +52,8 @@
BITS_WITH_WMASK((M0_BINCODE_BASE >> 28) & 0xf,
0xf, 0));
- /* gating disable for M0 */
- mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0,
- BITS_WITH_WMASK(0x3, 0x3, 0));
+ /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */
+ mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02);
/*
* To switch the parent to xin24M and div == 1,
