Hisilicon/Serdes: add support for D05
Modify OemGetSerdesParam interface to support D05, for it has 2 sockets
on the board, and each socket has 2 IO super clusters. The interface
is modified to support getting serdes parameter for both IO super clusters
(denoted as A and B) on each socket.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Peicong Li <lipeicong@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c
index a0e3de3..62e4b7f 100644
--- a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c
@@ -73,9 +73,10 @@
)
{
EFI_STATUS Status;
- serdes_param_t sSerdesParam;
+ serdes_param_t SerdesParamA;
+ serdes_param_t SerdesParamB;
- Status = OemGetSerdesParam (&sSerdesParam);
+ Status = OemGetSerdesParam (&SerdesParamA, &SerdesParamB, 0);
if(EFI_ERROR(Status))
{
DEBUG((EFI_D_ERROR, "[%a]:[%dL] OemGetSerdesParam failed %r\n", __FUNCTION__, __LINE__, Status));
@@ -85,8 +86,8 @@
//
// PCIE0
//
- if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data) && sSerdesParam.hilink1_mode == EM_HILINK1_PCIE0_8LANE)
- {
+ if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data)
+ && SerdesParamA.hilink1_mode == EM_HILINK1_PCIE0_8LANE) {
InputData->CurrentUsage = SlotUsageAvailable;
}
@@ -95,8 +96,7 @@
//
if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie1Data)
{
- if (sSerdesParam.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE)
- {
+ if (SerdesParamA.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) {
InputData->SlotDataBusWidth = SlotDataBusWidth4X;
}
}
@@ -106,13 +106,10 @@
//
if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie2Data)
{
- if (sSerdesParam.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE)
- {
+ if (SerdesParamA.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) {
InputData->SlotDataBusWidth = SlotDataBusWidth4X;
InputData->CurrentUsage = SlotUsageAvailable;
- }
- else if (sSerdesParam.hilink2_mode == EM_HILINK2_PCIE2_8LANE)
- {
+ } else if (SerdesParamA.hilink2_mode == EM_HILINK2_PCIE2_8LANE) {
InputData->CurrentUsage = SlotUsageAvailable;
}
}
@@ -120,8 +117,8 @@
//
// PCIE3
//
- if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data) && sSerdesParam.hilink5_mode == EM_HILINK5_PCIE3_4LANE)
- {
+ if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data)
+ && SerdesParamA.hilink5_mode == EM_HILINK5_PCIE3_4LANE) {
InputData->CurrentUsage = SlotUsageAvailable;
}
}
diff --git a/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h
index 700d40e..3bd5a0f 100755
--- a/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h
+++ b/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h
@@ -82,7 +82,7 @@
UINT32 DsCfg;
} SERDES_POLARITY_INVERT;
-EFI_STATUS OemGetSerdesParam (serdes_param_t *Param);
+EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId);
extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[];
extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[];
UINT32 GetEthType(UINT8 EthChannel);
diff --git a/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h
index 070934b..b6c7e20 100644
--- a/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h
+++ b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h
@@ -76,7 +76,7 @@
} SERDES_POLARITY_INVERT;
-EFI_STATUS OemGetSerdesParam (serdes_param_t *Param);
+EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId);
extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[];
extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[];
UINT32 GetEthType(UINT8 EthChannel);
diff --git a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c
index d4aa84a..7526644 100644
--- a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c
+++ b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c
@@ -59,15 +59,14 @@
.hilink5_mode = EM_HILINK5_SAS1_4LANE,
};
-EFI_STATUS OemGetSerdesParam (serdes_param_t *Param)
+EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId)
{
- if (NULL == Param)
- {
- DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
+ if (ParamA == NULL) {
+ DEBUG((DEBUG_ERROR, "[%a]:[%dL] ParamA == NULL!\n", __FUNCTION__, __LINE__));
return EFI_INVALID_PARAMETER;
}
- (VOID) CopyMem(Param, &gSerdesParam, sizeof(*Param));
+ (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA));
return EFI_SUCCESS;
}
diff --git a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c
index 23c55e1..a54e76f 100644
--- a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c
+++ b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c
@@ -75,15 +75,14 @@
.use_ssc = 0,
};
-EFI_STATUS OemGetSerdesParam (serdes_param_t *Param)
+EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId)
{
- if (NULL == Param)
- {
+ if (ParamA == NULL) {
DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
return EFI_INVALID_PARAMETER;
}
- (VOID) CopyMem(Param, &gSerdesParam, sizeof(*Param));
+ (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA));
return EFI_SUCCESS;
}
