| commit | 331135f3107c33f9537ba2de8922104e3c6322be | [log] [tgz] |
|---|---|---|
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | Wed Sep 14 13:46:40 2016 +0100 |
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | Mon Sep 19 18:45:47 2016 +0100 |
| tree | 375aa0e7b39f98241a0acb16e5cfe1e0ee1d32ce | |
| parent | d078b3a2ed8d48774718838590c211d724a02989 [diff] |
Platforms/AMD/Styx: correct PCIe bus and I/O ranges in DSDT Change the PCIe bus range in the DSDT from [0x0 .. 0xf] to [0x00 .. 0x7f], which aligns it with the DT descripton. Also fix the I/O window: its range should be listed without taking the translation into account. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Graeme Gregory <graeme.gregory@linaro.org>