| commit | 0ce014a8b60d7cced27a310b547f22b536621fe0 | [log] [tgz] |
|---|---|---|
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | Tue Dec 06 12:51:41 2016 +0000 |
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | Wed Dec 07 09:48:40 2016 +0000 |
| tree | ca2f3db3a74152f1a5c33de17d73d7866c1c07c6 | |
| parent | 242d1f50d8fb9c159385b26870cef616cafd7736 [diff] |
Platforms/AMD/Styx: rename SATA PCDs for symmetry To match the port 1 counterparts, rename PcdSataCtrlAxiSlvPort to PcdSata0CtrlAxiSlvPort and PcdSataPortCount to PcdSata0PortCount. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>