| ## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn54x) |
| ## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn54x) |
| |
| ############################################################################### |
| # Application options |
| # Logging Levels |
| # NXPLOG_DEFAULT_LOGLEVEL 0x01 |
| # ANDROID_LOG_DEBUG 0x03 |
| # ANDROID_LOG_WARN 0x02 |
| # ANDROID_LOG_ERROR 0x01 |
| # ANDROID_LOG_SILENT 0x00 |
| # |
| NXPLOG_EXTNS_LOGLEVEL=0x01 |
| NXPLOG_NCIHAL_LOGLEVEL=0x01 |
| NXPLOG_NCIX_LOGLEVEL=0x01 |
| NXPLOG_NCIR_LOGLEVEL=0x01 |
| NXPLOG_FWDNLD_LOGLEVEL=0x01 |
| NXPLOG_TML_LOGLEVEL=0x01 |
| |
| ############################################################################### |
| # Extension for Mifare reader enable |
| # 0x00 - Disabled |
| # 0x01 - Enabled |
| MIFARE_READER_ENABLE=0x01 |
| |
| ############################################################################### |
| # File location for Firmware |
| #FW_STORAGE="/vendor/firmware/libpn548_fw.so" |
| |
| ############################################################################### |
| # System clock source selection configuration |
| # CLK_SRC_XTAL - 0x01 |
| # CLK_SRC_PLL - 0x02 |
| NXP_SYS_CLK_SRC_SEL=0x01 |
| |
| ############################################################################### |
| # System clock frequency selection configuration for PLL |
| # CLK_FREQ_13MHZ - 0x01 |
| # CLK_FREQ_19_2MHZ - 0x02 |
| # CLK_FREQ_24MHZ - 0x03 |
| # CLK_FREQ_26MHZ - 0x04 |
| # CLK_FREQ_38_4MHZ - 0x05 |
| # CLK_FREQ_52MHZ - 0x06 |
| NXP_SYS_CLK_FREQ_SEL=0x02 |
| |
| ############################################################################### |
| # The timeout value to be used for clock request acknowledgment |
| # min value = 0x01 to max = 0x1A |
| NXP_SYS_CLOCK_TO_CFG=0x1A |
| |
| ############################################################################### |
| # NXP TVDD configurations settings |
| # Allow NFCC to configure External TVDD, There are currently three |
| #configurations (1, 2 and 3) are supported, out of them only one can be |
| #supported. |
| NXP_EXT_TVDD_CFG=0x03 |
| |
| ############################################################################### |
| # NXP proprietary settings |
| NXP_ACT_PROP_EXTN={2F, 02, 00} |
| |
| ############################################################################### |
| # NFC forum profile settings |
| NXP_NFC_PROFILE_EXTN={20, 02, 05, 01, A0, 44, 01, 00} |
| |
| ############################################################################### |
| # Standby enable settings |
| # 0x00 - Disabled |
| # 0x01 - Enabled |
| NXP_CORE_STANDBY={2F, 00, 01, 01} |
| |
| # *** ALMSL(NO BOOSTER) FW VERSION = 10.01.17 *** |
| ############################################################################### |
| # NXP RF configuration ALM/PLM settings |
| # This section needs to be updated with the correct values based on the platform |
| # New Features were added since FW10.1.13 |
| # A0, 0D, 06, 70, 44, A3, 90, 03, 00, RF_CLIF_CFG_BR_212_T_RXA CLIF_ANA_RX_REG |
| # A0, 0D, 06, 74, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXA CLIF_ANA_RX_REG |
| # A0, 0D, 06, 8E, 44, 12, 90, 03, 00, RF_CLIF_CFG_BR_212_T_RXF CLIF_ANA_RX_REG |
| # A0, 0D, 06, 94, 44, 12, 90, 03, 00, RF_CLIF_CFG_BR_424_T_RXF CLIF_ANA_RX_REG |
| # A0, 0D, 03, 24, 41, 40, RF_CLIF_CFG_TECHNO_T_TXA_P CLIF_ANA_TX_CLK_CONTROL_REG |
| # A0, 0D, 06, 24, 42, 00, 02, FF, FF, RF_CLIF_CFG_TECHNO_T_TXA_P CLIF_ANA_TX_AMPLITUDE_REG |
| # A0, 0D, 03, 28, 41, 40, RF_CLIF_CFG_TECHNO_T_TXB CLIF_ANA_TX_CLK_CONTROL_REG |
| # A0, 0D, 06, 28, 42, 00, 02, FF, FF, RF_CLIF_CFG_TECHNO_T_TXB CLIF_ANA_TX_AMPLITUDE_REG |
| # A0, 0D, 03, 8A, 41, 40, RF_CLIF_CFG_BR_212_T_TXF_P CLIF_ANA_TX_CLK_CONTROL_REG |
| # A0, 0D, 03, 90, 41, 40, RF_CLIF_CFG_BR_424_T_TXF_P CLIF_ANA_TX_CLK_CONTROL_REG |
| |
| # legacy RF parameters. |
| # A0, 0D, 03, 06, 37, 08, RF_CLIF_CFG_TARGET CLIF_TX_CONTROL_REG |
| # A0, 0D, 06, 32, 42, F8, 20, FF, FF, RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_AMPLITUDE_REG |
| # A0, 0D, 06, 06, 42, 00, 03, F2, F4, RF_CLIF_CFG_TARGET CLIF_ANA_TX_AMPLITUDE_REG |
| # A0, 0D, 06, 32, 4A, 33, 07, 00, 1C, RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG |
| # A0, 1D, 11, 55, ... CLK_MAN_Power ON |
| # A0, 1E, 11, 1D, ... CLK_MAN_Power OFF |
| # A0, 0D, 04, 06, 03, 00, 71, RF_CLIF_CFG_TARGET CLIF_TRANSCEIVE_CONTROL_REG |
| # A0, 0D, 03, 00, 40, 05 RF_CLIF_CFG_BOOT CLIF_ANA_NFCLD_REG |
| # A0, 0D, 06, 9A, 42, 00, 00, FF, FF, RF_CLIF_CFG_GTM_FELICA CLIF_ANA_TX_AMPLITUDE_REG |
| ############################################################################################################## |
| ############################################################################################################## |
| # Please be noticed that below registers has to be set as same value !!!!! |
| # x value should be set to 0x0 |
| # y value should be set as same value. |
| # A0, 0D, 06, 06, 42, 00, 0x, Fy, F3, |
| # A0, 0D, 06, 24, 42, 00, 0x, Fy, F3, |
| # A0, 0D, 06, 98, 42, 00, 0x, Fy, F3, |
| # A0, 0D, 06, 9A, 42, 00, 0x, Fy, F3, |
| ############################################################################################################## |
| ############################################################################################################## |
| |
| NXP_RF_CONF_BLK_1={ 20, 02, AF, 12, |
| A0, 0D, 06, 04, 35, F4, 02, FF, 03, |
| A0, 0D, 03, 06, 37, 08, |
| A0, 0D, 06, 34, 2D, 24, 37, 0C, 00, |
| A0, 0D, 04, 34, 44, 22, 00, |
| A0, 0D, 06, 32, 42, F8, 20, FF, FF, |
| A0, 0D, 06, 06, 42, 00, 00, F1, F1, |
| A0, 0D, 06, 24, 42, 00, 00, F1, F1, |
| A0, 0D, 06, 98, 42, 00, 00, F1, F1, |
| A0, 0D, 06, 9A, 42, 00, 00, F1, F1, |
| A0, 0D, 06, 32, 4A, 33, 07, 00, 1C, |
| A0, 1D, 11, 54, 33, 14, 17, 00, AA, 85, 00, 80, 55, 2A, 04, 00, 63, 00, 00, 00, |
| A0, 1E, 11, 1C, 13, 14, 14, 00, 6F, 97, 00, 00, 00, 10, 04, 00, 63, 02, 00, 00, |
| A0, 0D, 06, 06, 03, 00, 71, 00, 20, |
| A0, 0D, 03, 00, 40, 05, |
| A0, 0D, 06, 56, 2D, 05, 9F, 0C, 00, |
| A0, 0D, 04, 56, 44, 22, 00, |
| A0, 0D, 06, 54, 42, 88, 30, FF, FF, |
| A0, 0D, 06, 44, 42, 88, 20, FF, FF |
| } |
| |
| |
| # Core configuration extensions |
| # It includes |
| # A002 - Clock Request |
| # 0x00 - Disabled |
| # 0x01 - Enabled |
| # A003 - Clock Selection |
| # Please refer to User Manual |
| # A004 - Clock Time Out |
| # Defined in ms |
| # A00E - Load Modulation Mode |
| # 0x00 - PLM |
| # 0x01 - ALM |
| # A012 - SWP interface 2 configuration |
| # 0x00 - SWP |
| # 0x02 - DWP |
| # Please refer to User Manual |
| # A040-A043 - Ultra Low Power Tag Detector |
| # Please refer to Application Note of ULPTD |
| # A05E - Jewel Reader |
| # Please refer to User Manual |
| # A0CD - SWP S1 line behavior |
| # Defined S1 High time out during Activation sequence |
| # A0EC - SWP1 interface |
| # 0x00 - Disabled |
| # 0x01 - Enabled |
| # A0ED - SWP2 interface |
| # 0x00 - Disabled |
| # 0x01 - Enabled |
| NXP_CORE_CONF_EXTN={20, 02, 49, 11, |
| A0, 02, 01, 01, |
| A0, 03, 01, 08, |
| A0, 04, 01, 0A, |
| A0, 06, 01, 01, |
| A0, 80, 02, B0, 04, |
| A0, 11, 04, 14, B8, 0B, 14, |
| A0, 5E, 01, 01, |
| A0, CD, 01, 0F, |
| A0, EC, 01, 00, |
| A0, ED, 01, 00, |
| A0, CB, 01, 0F, |
| A0, CE, 01, 7F, |
| A0, 40, 01, 01, |
| A0, 41, 01, 03, |
| A0, 42, 01, 19, |
| A0, 43, 01, 03, |
| A0, F2, 01, 00 |
| } |
| |
| NXP_EXT_TVDD_CFG_3={20, 02, 0B, 02, |
| A0, 0E, 03, 52, 64, 0A, |
| A0, 66, 01, 01 |
| } |
| |
| ############################################################################### |
| # To enable i2c fragmentation set i2c fragmentation enable 0x01 to disable set to 0x00 |
| NXP_I2C_FRAGMENTATION_ENABLED=0x00 |
| |
| ############################################################################### |
| # Core configuration settings |
| NXP_CORE_CONF={ 20, 02, 2B, 0D, |
| 28, 01, 00, |
| 21, 01, 00, |
| 30, 01, 08, |
| 31, 01, 03, |
| 33, 04, 01, 02, 03, 04, |
| 54, 01, 06, |
| 50, 01, 00, |
| 5B, 01, 00, |
| 60, 01, 0E, |
| 80, 01, 01, |
| 81, 01, 01, |
| 82, 01, 0E, |
| 18, 01, 01 |
| } |
| |
| ############################################################################### |
| # Mifare Classic Key settings |
| #NXP_CORE_MFCKEY_SETTING={20, 02, 25,04, A0, 51, 06, A0, A1, A2, A3, A4, A5, |
| # A0, 52, 06, D3, F7, D3, F7, D3, F7, |
| # A0, 53, 06, FF, FF, FF, FF, FF, FF, |
| # A0, 54, 06, 00, 00, 00, 00, 00, 00} |
| |
| ############################################################################### |
| # Default SE Options |
| # No secure element 0x00 |
| # eSE 0x01 |
| # UICC 0x02 |
| NXP_DEFAULT_SE=0x03 |
| |
| ############################################################################### |
| #Enable SWP full power mode when phone is power off |
| NXP_SWP_FULL_PWR_ON=0x00 |
| |
| ############################################################################### |
| #### Select the CHIP #### |
| #PN547C2 0x01 |
| #PN65T 0x02 |
| #PN548AD 0x03 |
| #PN66T 0x04 |
| NXP_NFC_CHIP=0x03 |
| |
| ############################################################################### |
| # CE when Screen state is locked |
| # Disable 0x00 |
| # Enable 0x01 |
| NXP_CE_ROUTE_STRICT_DISABLE=0x01 |
| |
| NXP_DEFAULT_NFCEE_TIMEOUT=0x06 |
| |
| ############################################################################### |
| #Timeout in secs |
| NXP_SWP_RD_START_TIMEOUT=0x0A |
| |
| ############################################################################### |
| #Timeout in secs |
| NXP_SWP_RD_TAG_OP_TIMEOUT=0x01 |
| |
| ############################################################################### |
| #Set the default AID route Location : |
| #This settings will be used when application does not set this parameter |
| # host 0x00 |
| # eSE 0x01 |
| # UICC 0x02 |
| DEFAULT_AID_ROUTE=0x00 |
| |
| ############################################################################### |
| #Set the Mifare Desfire route Location : |
| #This settings will be used when application does not set this parameter |
| # host 0x00 |
| # eSE 0x01 |
| # UICC 0x02 |
| DEFAULT_DESFIRE_ROUTE=0x02 |
| |
| ############################################################################### |
| #Set the Mifare CLT route Location : |
| #This settings will be used when application does not set this parameter |
| # host 0x00 |
| # eSE 0x01 |
| # UICC 0x02 |
| DEFAULT_MIFARE_CLT_ROUTE=0x02 |
| |
| ############################################################################### |
| # AID Matching platform options |
| # AID_MATCHING_L 0x01 |
| # AID_MATCHING_K 0x02 |
| AID_MATCHING_PLATFORM=0x01 |
| |
