UPSTREAM: ASoC: rockchip: i2s: change bclk and lrck according to sample rates
This patch sets the dividers autonomously.
when i2s works on master mode, and sample rates changed. We need to change
bclk and lrck at the same time for cpu internal side.
As the input source clock to the module is MCLK_I2S,
and by the divider of the module, the clock generator generates
SCLK and LRCK to transmitter and receiver.
Bug: 25923642
Patchset: I2S block needed to adjust it's divider settings for these
different frequencies.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org torvalds/linux.git master
commit 2458c37779ddb91b4109949d86f5a5e193ba415b)
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I91073f0a2252d965cd425c7240db3a024dc055ab
1 file changed
